WO2016003049A1 - Light emitting element and lighting system including same - Google Patents

Light emitting element and lighting system including same Download PDF

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Publication number
WO2016003049A1
WO2016003049A1 PCT/KR2015/002544 KR2015002544W WO2016003049A1 WO 2016003049 A1 WO2016003049 A1 WO 2016003049A1 KR 2015002544 W KR2015002544 W KR 2015002544W WO 2016003049 A1 WO2016003049 A1 WO 2016003049A1
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WO
WIPO (PCT)
Prior art keywords
layer
hole injection
injection layer
disposed
light emitting
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PCT/KR2015/002544
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French (fr)
Korean (ko)
Inventor
최광용
장정훈
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엘지이노텍 주식회사
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Publication of WO2016003049A1 publication Critical patent/WO2016003049A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure

Definitions

  • the embodiment relates to a light emitting device for improving light efficiency.
  • a light emitting device is a compound semiconductor having a characteristic in which electrical energy is converted into light energy.
  • the light emitting device may be formed of compound semiconductors such as group III and group V on the periodic table, and various colors may be adjusted by adjusting the composition ratio of the compound semiconductor. Implementation is possible.
  • the n-layer electrons and the p-layer holes combine to emit energy corresponding to the bandgap energy of the conduction band and the valence band. Is mainly emitted in the form of heat or light, and emits light in the form of light emitting elements.
  • nitride semiconductors are receiving great attention in the field of optical devices and high power electronic devices due to their high thermal stability and wide bandgap energy.
  • blue light emitting devices, green light emitting devices, and ultraviolet light emitting devices using nitride semiconductors are commercially used and widely used.
  • Conventional nitride semiconductors are formed by sequentially stacking a first conductive semiconductor layer of GaN material, an active layer and a second conductive semiconductor layer on a substrate, and smoothly flow holes between the active layer and the second conductive semiconductor layer.
  • a hole injection layer for forming is formed.
  • the hole injection layer is mainly formed of a single layer doped with Mg, a problem occurs in that the output Po and the light efficiency measurement voltage VF1 fall in the long wavelength region.
  • an embodiment is to provide a light emitting device for improving the light efficiency and an illumination system having the same.
  • a light emitting device includes a substrate, a first conductive semiconductor layer disposed on the substrate, an active layer disposed on the first conductive semiconductor layer, and on the active layer A second conductive semiconductor layer disposed, a first hole injection layer disposed between the active layer and the second conductive semiconductor layer and undoped, and a second doped p-type dopant disposed on the first hole injection layer It may include a hole injection layer including a hole injection layer.
  • the embodiment has the effect of improving the output voltage and the light efficiency measurement voltage while maintaining the operating voltage by forming a layer in which the p-type dopant is removed in the hole injection layer.
  • the hole injection layer is formed so that the first hole injection layer and the second hole injection layer are paired, thereby reducing the lattice mismatch of the upper and lower layers.
  • the embodiment further includes an InN layer in the hole injection layer, thereby preventing the p-type dopant from diffusing into the active layer.
  • the embodiment further improves the hole injection efficiency by further disposing a GaN layer having a lower p-type dopant concentration of the lowermost layer of the hole injection layer.
  • FIG. 1 is a cross-sectional view of a light emitting device according to a first embodiment.
  • FIG. 2 is a cross-sectional view illustrating a hole injection layer of the light emitting device according to the first embodiment.
  • 3 to 6 are graphs showing the Mg doping method of the hole injection layer according to the first embodiment.
  • FIG. 7 is a graph showing Po of the light emitting device according to the first embodiment.
  • FIG 8 is a graph illustrating VF1 of the light emitting device according to the first embodiment.
  • FIG 9 is a graph showing VF3 of the light emitting device according to the first embodiment.
  • FIG. 10 is a sectional view showing a light emitting device according to the second embodiment.
  • FIG. 11 is a cross-sectional view illustrating a hole injection layer of a light emitting device according to a second embodiment.
  • FIG. 12 is a sectional view showing a light emitting device according to the third embodiment.
  • 13 and 14 are cross-sectional views illustrating a hole injection layer of the light emitting device according to the third embodiment.
  • 15 is a sectional view showing a light emitting device according to the fourth embodiment.
  • 16 is a cross-sectional view illustrating a hole injection layer of a light emitting device according to a fourth embodiment.
  • 17 is a cross-sectional view illustrating a package of a light emitting device with a light emitting device according to embodiments.
  • 18 to 20 are exploded perspective views showing embodiments of a lighting system having a light emitting device according to the embodiments.
  • FIG. 1 is a cross-sectional view illustrating a light emitting device according to a first embodiment
  • FIG. 2 is a cross-sectional view showing a hole injection layer of a light emitting device according to a first embodiment
  • FIGS. 3 to 6 are hole injections according to a first embodiment.
  • FIG. 7 is a graph showing Po of the light emitting device according to the first embodiment
  • FIG. 8 is a graph showing VF1 of the light emitting device according to the first embodiment
  • the light emitting device includes a substrate 110, a buffer layer 181 disposed on the substrate, and a strain control layer 183 disposed on the buffer layer 181.
  • a first conductive semiconductor layer 120 disposed on the strain control layer 183, a current spreading layer 185 disposed on the first conductive semiconductor layer 120, and the current spreading layer
  • the active layer 130 disposed on the active layer 130, the hole injection layer 140 disposed on the active layer 130, the electron blocking layer 187 disposed on the hole injection layer 140, and the electrons.
  • the second conductive semiconductor layer 150 disposed on the blocking layer 187, the light transmissive electrode layer 189 disposed on the second conductive semiconductor layer 150, and the first conductive semiconductor layer 120.
  • the first electrode 160 is disposed on the first electrode 160
  • the second electrode 170 is disposed on the transparent electrode layer 189.
  • the substrate 110 may be formed of a material having excellent thermal conductivity, and may be a conductive substrate or an insulating substrate.
  • the substrate 110 may use at least one of sapphire (Al 2 O 3 ), SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, and Ga 2 0 3 .
  • a buffer layer 181 may be disposed on the substrate 110.
  • the buffer layer 181 serves to alleviate the lattice mismatch between the material of the light emitting structure and the substrate 110.
  • the buffer layer 181 may include a group III-V compound semiconductor.
  • the buffer layer 181 may be formed of a material including Al.
  • the buffer layer 120 may be formed of at least one of AlN, AlGaN, InAlGaN, and AlInN.
  • a strain control layer 183 may be disposed on the buffer layer 181.
  • the first conductivity type semiconductor layer 120 may be disposed on the strain control layer 183.
  • the first conductivity-type semiconductor layer 120 may include, for example, an n-type semiconductor layer.
  • the first conductivity type semiconductor layer 120 may be implemented as a compound semiconductor.
  • the first conductivity type semiconductor layer 120 may be implemented as, for example, a group II-VI compound semiconductor or a group III-V compound semiconductor.
  • the first conductivity type semiconductor layer 120 is formed of a semiconductor material having a composition formula of In x Al y Ga 1 -x- y N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1). Can be.
  • the first conductivity type semiconductor layer 120 may be selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and the like.
  • N-type dopants such as Se and Te may be doped.
  • the current diffusion layer 185 may be disposed on the first conductivity type semiconductor layer 120.
  • the current diffusion layer 185 may increase light efficiency by improving internal quantum efficiency, and may be an undoped gallium nitride layer.
  • An electron injection layer (not shown) may be further formed on the current diffusion layer 185.
  • the electron injection layer may be a conductive gallium nitride layer.
  • the n-type doping element is doped at a concentration of 6.0x10 18 atoms / cm 3 to 3.0x10 19 atoms / cm 3 , thereby enabling efficient electron injection.
  • the active layer 130 may be disposed on the current spreading layer 185.
  • the active layer 130 In the active layer 130, electrons (or holes) injected through the first conductive semiconductor layer 120 and holes (or electrons) injected through the second conductive semiconductor layer 150 meet each other, and thus, the active layer is formed.
  • the layer emits light due to a band gap difference of an energy band according to the forming material of 130.
  • the active layer 130 may be formed of any one of a single well structure, a multiple well structure, a quantum dot structure, or a quantum line structure, but is not limited thereto.
  • the active layer 130 may be implemented with a compound semiconductor.
  • the active layer 130 may be implemented as, for example, a group II-VI or group III-V compound semiconductor.
  • the active layer 130 may be formed of, for example, a semiconductor material having a composition formula of In x Al y Ga 1 -x- y N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1). have.
  • the active layer 130 may be implemented by stacking a plurality of well layers and a plurality of barrier layers, for example, an InGaN well layer / GaN barrier layer. Can be implemented in cycles.
  • the hole injection layer 140 may be disposed on the active layer 130.
  • the hole injection layer 140 may increase the light emission efficiency by effectively moving holes to the center of the light emitting layer.
  • the hole injection layer 140 may include a first hole injection layer 141 and a second hole injection layer 143.
  • the first hole injection layer 141 may be an undoped layer.
  • the second hole injection layer 143 may be a layer doped with a p-type dopant.
  • the hole injection layer 140 will be described in detail later with reference to the drawings.
  • An electron blocking layer EBL 187 may be disposed on the hole injection layer 140.
  • the electron blocking layer 187 serves as electron blocking and cladding of the active layer, thereby improving luminous efficiency.
  • the electron blocking layer 187 may be formed of an Al x In y Ga (1-xy) N (0 ⁇ x ⁇ 1,0 ⁇ y ⁇ 1) based semiconductor, and may be higher than the energy band gap of the active layer 130. It may have an energy band gap, and may be formed to a thickness of about 100 kPa to about 600 kPa, but is not limited thereto.
  • the electron blocking layer 187 may be formed of Al z Ga (1-z) N / GaN (0 ⁇ z ⁇ 1) superlattice.
  • the second conductivity type semiconductor layer 150 may be disposed on the electron blocking layer 187.
  • the second conductivity-type semiconductor layer 150 may be implemented with, for example, a p-type semiconductor layer.
  • the second conductivity-type semiconductor layer 150 may be implemented as a compound semiconductor.
  • the second conductivity-type semiconductor layer 150 may be implemented as a group II-VI compound semiconductor or a group III-V compound semiconductor.
  • the second conductive type semiconductor layer 150 is a semiconductor material having a compositional formula of In x Al y Ga 1 -x- y N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) Can be implemented.
  • the second conductive semiconductor layer 150 may be selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and the like, and may include Mg, Zn, Ca, P-type dopants such as Sr and Be may be doped.
  • the first conductive semiconductor layer 120 may include a p-type semiconductor layer
  • the second conductive semiconductor layer 150 may include an n-type semiconductor layer.
  • a semiconductor layer including an n-type or p-type semiconductor layer may be further formed below the second conductive semiconductor layer 150. Accordingly, the light emitting structure may have at least one of np, pn, npn, and pnp junction structures.
  • Doping concentrations of impurities in the first conductive semiconductor layer 120 and the second conductive semiconductor layer 150 may be uniformly or non-uniformly formed. That is, the structure of the light emitting structure may be formed in various ways, but is not limited thereto.
  • the light transmissive electrode layer 189 may be disposed on the second conductive semiconductor layer 150.
  • the translucent electrode layer 189 may stack a single metal, a metal alloy, a metal oxide, or the like in multiple layers so as to efficiently inject carriers.
  • the light transmissive electrode layer 189 may be formed of a material having excellent electrical contact with a semiconductor.
  • the light transmissive electrode layer 189 may be indium tin oxide (ITO), indium zinc oxide (IZO), or indium zinc tin oxide (IZTO).
  • IAZO Indium aluminum zinc oxide
  • IGZO indium gallium zinc oxide
  • IGTO indium gallium tin oxide
  • ATO antimony tin oxide
  • GZO gallium zinc oxide
  • IZO Nitride AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au, and Ni / IrOx / Au / ITO, Ag, Ni, Cr , Ti, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf may be formed including at least one, and is not limited to these materials.
  • the second electrode 170 is formed on the light transmissive electrode layer 189, and the first electrode 160 is formed on the first conductive semiconductor layer 120 having a portion of the upper portion exposed.
  • the first electrode 160 and the second electrode 170 for example, Cr, Ti, Ag, Ni, RH, Pd, Ir, Ru, Mg, Zn, Pt, Cu, Au. It may be formed of a metal or an alloy containing any one of Hf. Thereafter, the first electrode 160 and the second electrode 170 are finally connected to each other, thereby manufacturing the light emitting device.
  • the hole injection layer 140 may include a first hole injection layer 141 and a second hole injection layer 143.
  • a first hole injection layer 141 can be a layer of undoped In x Al y Ga 1 -x- y N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • the second hole injection layer 143 can be a layer of p-type dopant of In x Al y Ga 1 -x- y N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1) doped .
  • the p-type dopant may include Mg, Zn, Ca, Sr, Be.
  • the composition of Al in the first hole injection layer 141 and the second hole injection layer 143 may be 25% to 35%, and more specifically, 30%. When the composition of Al is 25% or less or 35% or more, the output voltage Po decreases.
  • the total thickness T11 of the hole injection layer 140 may be 15 ⁇ m to 25 ⁇ m, and more specifically, 20 ⁇ m to be formed. Can be.
  • the thickness T12 of the first hole injection layer 141 may be smaller than the thickness T13 of the second hole injection layer 143.
  • the thickness T12 of the first hole injection layer 141 may be the same as the thickness T13 of the second hole injection layer 143.
  • the ratio of the thickness T12 of the first hole injection layer 141 and the thickness T13 of the second hole injection layer 143 may be 1: 1 to 1: 3.
  • the concentration of the p-type dopant is decreased, so that the output voltage Po in the long wavelength region is obtained.
  • the light efficiency measuring voltage VF1 has an improvement effect, a problem arises in that the operating voltage VF3 becomes high. Therefore, when the ratio of the thickness T12 of the first hole injection layer 141 and the thickness T13 of the second hole injection layer 143 is 1: 1, as shown in Table 1, in the long wavelength region, The output voltage Po and the light efficiency measurement voltage VF1 may obtain an improvement effect, from which the thickness T12 of the first hole injection layer 141 and the thickness T13 of the second hole injection layer 143 may be obtained. When the ratio is 1: 1 to 1: 3, the improvement effect of the output voltage Po and the light efficiency measurement voltage VF1 may be maximized.
  • the p-type dopant of the second hole injection layer 143 for example, the concentration of Mg may be 1E18 to 3E20. As described above, the concentration of Mg is a concentration value for optimizing the output voltage Po and the light efficiency measurement voltage VF1 in the long wavelength region.
  • the p-type dopant may be formed to have a uniform concentration value along the thickness direction of the second hole injection layer 143.
  • the p-type dopant may be supplied at a uniform concentration in the thickness direction of the second hole injection layer 143.
  • the p-type dopant may be continuously supplied to the second hole injection layer 143 while the target concentration value Ta, that is, 1E18 to 3E20 is maintained.
  • the p-type dopant may be supplied at a uniform concentration in the thickness direction of the second hole injection layer 143, and the p-type dopant may be repeatedly supplied at a predetermined time.
  • the p-type dopant may be formed to increase the concentration value along the thickness direction of the second hole injection layer 143.
  • the p-type dopant may be supplied while sequentially increasing the concentration in the thickness direction of the second hole injection layer 143.
  • the p-type dopant may be supplied at a concentration value Tb higher than the target target concentration value Ta to adjust the p-type dopant concentration value of the second hole injection layer 143 to 1E18 to 3E20.
  • the p-type dopant is supplied while increasing the concentration in the thickness direction of the second hole injection layer 143 sequentially, and the p-type dopant may be repeatedly supplied at a predetermined time.
  • the hole injection layer structure according to the embodiment has a long wavelength region ( As shown to A), it can be seen that the output voltage Po is improved compared to the conventional hole injection layer R structure.
  • the hole injection layer 140 structure according to the embodiment is increased by about 20 mW by 4% on average.
  • the structure of the hole injection layer 140 according to the embodiment It can be seen that toward the long wavelength region A, the light efficiency voltage VF1 is improved.
  • the hole injection layer 140 includes the second hole injection layer including the p-type dopant even if the first hole injection layer from which the p-type dopant is removed exists, thereby operating voltage. It can be seen that (VF3) was kept stable.
  • the hole injection layer 140 of the two-layer structure according to the embodiment improves the output voltage Po and the light efficiency measurement voltage VF1 while maintaining the operating voltage VF3. It can be seen that there is an effect of improving the efficiency.
  • FIG. 10 is a sectional view showing a light emitting device according to the second embodiment
  • FIG. 11 is a sectional view showing a hole injection layer of the light emitting device according to the second embodiment.
  • the light emitting device includes a substrate 210, a buffer layer 281 disposed on the substrate 210, and a strain control layer 283 disposed on the buffer layer 281.
  • a first conductive semiconductor layer 220 disposed on the strain control layer 283, a current spreading layer 285 disposed on the first conductive semiconductor layer 220, and the current spreading layer
  • the active layer 230 disposed on the 285, the hole injection layer 240 disposed on the active layer 230, the electron blocking layer 287 disposed on the hole injection layer 240, and the electrons.
  • the second conductive semiconductor layer 250 disposed on the blocking layer 287, the transmissive electrode layer 289 disposed on the second conductive semiconductor layer 250, and the first conductive semiconductor layer 220.
  • the first electrode 260 is disposed on the second electrode 260, and the second electrode 270 is disposed on the transparent electrode layer 289.
  • the configuration except for the hole injection layer 240 is the same as the configuration of the light emitting device according to the first embodiment and thus will be omitted.
  • the hole injection layer 240 may include a first hole injection layer 241, a second hole injection layer 243, a third hole injection layer 245, and a fourth hole injection layer 247. It may include.
  • the first hole injection layer 241 and the third hole injection layer 245 may be undoped InAlGaN layer.
  • the second hole injection layer 243 and the fourth hole injection layer 247 may be an InAlGaN layer doped with a p-type dopant.
  • the thickness T21 of the hole injection layer 240 may be 15 mm to 25 mm.
  • the thickness of the first hole injection layer 241 may be the same as the thickness of the third hole injection layer 245.
  • the thickness of the second hole injection layer 243 may be the same as the thickness of the fourth hole injection layer 247.
  • the ratio of the thicknesses of the first hole injection layer 241 and the second hole injection layer 243 may be 1: 1 to 1: 3.
  • the ratio of the thicknesses of the third hole injection layer 245 and the fourth hole injection layer 247 may be 1: 1 to 1: 3.
  • the p-type dopant of the second hole injection layer 243 and the fourth hole injection layer 247 for example, the concentration of Mg may be 1E18 to 3E20.
  • a plurality of hole injection layers 240 are formed such that the first hole injection layer and the second hole injection layer are paired, thereby alleviating the lattice mismatch between the layers. It has an effect.
  • FIGS. 13 and 14 are cross-sectional views illustrating a hole injection layer of a light emitting device according to a third embodiment.
  • the light emitting device includes a substrate 310, a buffer layer 381 disposed on the substrate 310, and a strain control layer 383 disposed on the buffer layer 381.
  • a first conductive semiconductor layer 320 disposed on the strain control layer 383, a current spreading layer 385 disposed on the first conductive semiconductor layer 320, and the current spreading layer
  • the active layer 330 disposed on the 385, the hole injection layer 340 disposed on the active layer 330, the electron blocking layer 387 disposed on the hole injection layer 340, and the electrons.
  • the second conductive semiconductor layer 350 disposed on the blocking layer 387, the transparent electrode layer 389 disposed on the second conductive semiconductor layer 350, and the first conductive semiconductor layer 320.
  • the first electrode 360 is disposed on the first electrode 360, and the second electrode 370 is disposed on the light transmissive electrode layer 389.
  • the configuration except for the hole injection layer 340 is the same as the configuration of the light emitting device according to the first embodiment and will be omitted.
  • the hole injection layer 340 includes a first hole injection layer 341 and a second hole injection layer 343 and the first hole injection layer disposed on the first hole injection layer 341.
  • the third hole injection layer 345 may be disposed between the layer 341 and the second hole injection layer 343.
  • the first hole injection layer 341 may be an undoped InAlGaN layer.
  • the second hole injection layer 343 may be an InAlGaN layer doped with a p-type dopant.
  • the p-type dopant of the second hole injection layer 343, for example, the concentration of Mg may be 1E18 to 3E20.
  • the third hole injection layer 345 may include InN.
  • the third hole injection layer 345 serves to prevent the p-type dopant included in the second hole injection layer 343 from diffusing into the active layer 330. That is, the third hole injection layer 345 uses In to prevent diffusion of Mg, which is a p-type dopant.
  • the hole injection layer 340 may have a thickness of 15 mm to 25 mm.
  • the ratio of the thicknesses of the first hole injection layer 341 and the second hole injection layer 343 may be 1: 1 to 1: 3.
  • the thickness of the third hole injection layer 345 may be formed to be 5 ⁇ or less.
  • the sum of the thicknesses of the first hole injection layer 341 and the third hole injection layer 345 is preferably smaller than the thickness of the second hole injection layer 343.
  • the concentration of the p-type dopant decreases and the output voltage in the long wavelength region is reduced.
  • the Po and the light efficiency measurement voltage VF1 have an improvement effect, a problem arises in that the operating voltage VF3 is increased.
  • the hole injection layer 340 may include the second hole injection layer 343 and the second hole injection layer 343 disposed on the first hole injection layer 341 and the first hole injection layer 341.
  • the first hole injection layer 341 may include a third hole injection layer 345 disposed under the hole injection layer 341.
  • the third hole injection layer 345 may include InN.
  • the third hole injection layer 345 serves to prevent the p-type dopant included in the second hole injection layer 343 from diffusing into the active layer 330. That is, the third hole injection layer 345 uses In to prevent diffusion of Mg, which is a p-type dopant.
  • FIG. 15 is a cross-sectional view illustrating a light emitting device according to a fourth embodiment
  • FIG. 16 is a cross-sectional view illustrating a hole injection layer of a light emitting device according to a fourth embodiment.
  • the light emitting device includes a substrate 410, a buffer layer 481 disposed on the substrate 410, and a strain control layer 483 disposed on the buffer layer 481.
  • a first conductivity type semiconductor layer 420 disposed on the strain control layer 483, a current diffusion layer 485 disposed on the first conductivity type semiconductor layer 420, and the current diffusion layer
  • the second conductive semiconductor layer 450 disposed on the blocking layer 481, the transparent electrode layer 489 disposed on the second conductive semiconductor layer 450, and the first conductive semiconductor layer 420.
  • the first electrode 460 is disposed on the second electrode 460, and the second electrode 470 is disposed on the light transmissive electrode layer 489.
  • the configuration except for the hole injection layer 440 is the same as the configuration of the light emitting device according to the first embodiment and thus will be omitted.
  • the hole injection layer 440 includes a first hole injection layer 441 and a second hole injection layer 443 disposed on the first hole injection layer 441, and a first hole injection layer. It may include a third hole injection layer 445 disposed below the layer 441.
  • the first hole injection layer 441 may be an undoped InAlGaN layer.
  • the second hole injection layer 443 may be an InAlGaN layer doped with a p-type dopant.
  • the p-type dopant of the second hole injection layer 443, for example, the concentration of Mg may be 1E18 to 3E20.
  • the third hole injection layer 445 may include GaN, InGaN, AlGaN, InAlGaN.
  • the third hole injection layer 445 may include a p-type dopant.
  • the p-type dopant included in the third hole injection layer 445 may have a concentration value of 1/2 or less of the second hole injection layer 443.
  • the third hole injection layer 445 may improve the output voltage and the light efficiency voltage by minimizing the diffusion of Mg into the active layer 430 by lowering the concentration of the p-type dopant. At the same time, since the third hole injection layer 445 is formed of GaN, InGaN, AlGaN, or InAlGaN, the hole injection efficiency can be further improved.
  • 17 is a cross-sectional view illustrating a package of a light emitting device with a light emitting device according to embodiments.
  • the light emitting device package 500 includes a package body 505, a third electrode layer 513 and a fourth electrode layer 514 disposed on the package body 505, and The light emitting device 100 disposed on the package body 505 and electrically connected to the third electrode layer 513 and the fourth electrode layer 514, and the molding member 530 surrounding the light emitting device 100. Included.
  • the package body 505 may include a silicon material, a synthetic resin material, or a metal material, and an inclined surface may be formed on a circumference of the light emitting device 100.
  • the third electrode layer 513 and the fourth electrode layer 514 are electrically separated from each other, and serve to provide power to the light emitting device 100.
  • the third electrode layer 513 and the fourth electrode layer 514 may serve to increase light efficiency by reflecting the light generated from the light emitting device 100, and generated from the light emitting device 100. It may also serve to release heat to the outside.
  • the light emitting device 100 may be disposed on the package body 505 or on the third electrode layer 513 or the fourth electrode layer 514.
  • the light emitting device 100 may be electrically connected to the third electrode layer 513 and / or the fourth electrode layer 514 by any one of a wire method, a flip chip method, or a die bonding method. In the embodiment, the light emitting device 100 is electrically connected to the first electrode layer 513 and the second electrode layer 514 through wires, respectively, but is not limited thereto.
  • the molding member 530 may surround the light emitting device 100 to protect the light emitting device 100.
  • the molding member 530 may include a phosphor 532 to change the wavelength of light emitted from the light emitting device 100.
  • 18 to 20 are exploded perspective views showing embodiments of a lighting system having a light emitting device according to the embodiments.
  • the lighting apparatus includes a cover 2100, a light source module 2200, a heat radiator 2400, a power supply 2600, an inner case 2700, and a socket 2800. It may include. In addition, the lighting apparatus according to the embodiment may further include any one or more of the member 2300 and the holder 2500.
  • the light source module 2200 may include a light emitting device 100 or a light emitting device package 200 according to the present invention.
  • the cover 2100 may have a shape of a bulb or hemisphere, may be hollow, and may be provided in an open shape.
  • the cover 2100 may be optically coupled to the light source module 2200.
  • the cover 2100 may diffuse, scatter or excite the light provided from the light source module 2200.
  • the cover 2100 may be a kind of optical member.
  • the cover 2100 may be coupled to the heat sink 2400.
  • the cover 2100 may have a coupling part coupled to the heat sink 2400.
  • An inner surface of the cover 2100 may be coated with a milky paint.
  • the milky paint may include a diffuser to diffuse light.
  • the surface roughness of the inner surface of the cover 2100 may be greater than the surface roughness of the outer surface of the cover 2100. This is for the light from the light source module 2200 to be sufficiently scattered and diffused to be emitted to the outside.
  • the cover 2100 may be made of glass, plastic, polypropylene (PP), polyethylene (PE), polycarbonate (PC), or the like.
  • polycarbonate is excellent in light resistance, heat resistance, and strength.
  • the cover 2100 may be transparent and opaque so that the light source module 2200 is visible from the outside.
  • the cover 2100 may be formed through blow molding.
  • the light source module 2200 may be disposed on one surface of the heat sink 2400. Thus, heat from the light source module 2200 is conducted to the heat sink 2400.
  • the light source module 2200 may include a light source unit 2210, a connection plate 2230, and a connector 2250.
  • the member 2300 is disposed on an upper surface of the heat dissipator 2400 and has a plurality of light source parts 2210 and guide grooves 2310 into which the connector 2250 is inserted.
  • the guide groove 2310 corresponds to the board and the connector 2250 of the light source unit 2210.
  • the surface of the member 2300 may be coated or coated with a light reflective material.
  • the surface of the member 2300 may be coated or coated with a white paint.
  • the member 2300 is reflected on the inner surface of the cover 2100 to reflect the light returned to the light source module 2200 side again toward the cover 2100. Therefore, it is possible to improve the light efficiency of the lighting apparatus according to the embodiment.
  • the member 2300 may be made of an insulating material, for example.
  • the connection plate 2230 of the light source module 2200 may include an electrically conductive material. Therefore, electrical contact may be made between the radiator 2400 and the connection plate 2230.
  • the member 2300 may be formed of an insulating material to block an electrical short between the connection plate 2230 and the radiator 2400.
  • the radiator 2400 receives heat from the light source module 2200 and heat from the power supply unit 2600 to radiate heat.
  • the holder 2500 may block the accommodating groove 2719 of the insulating portion 2710 of the inner case 2700. Therefore, the power supply unit 2600 accommodated in the insulating unit 2710 of the inner case 2700 is sealed.
  • the holder 2500 has a guide protrusion 2510.
  • the guide protrusion 2510 has a hole through which the protrusion 2610 of the power supply unit 2600 passes.
  • the power supply unit 2600 processes or converts an electrical signal provided from the outside to provide the light source module 2200.
  • the power supply unit 2600 is accommodated in the accommodating groove 2725 of the inner case 2700, and is sealed in the inner case 2700 by the holder 2500.
  • the power supply unit 2600 may include a protrusion 2610, a guide unit 2630, a base 2650, and an extension unit 2670.
  • the guide part 2630 has a shape protruding outward from one side of the base 2650.
  • the guide part 2630 may be inserted into the holder 2500.
  • a plurality of parts may be disposed on one surface of the base 2650.
  • the plurality of components may include, for example, a DC converter for converting AC power provided from an external power source into DC power, a driving chip for controlling the driving of the light source module 2200, and an ESD for protecting the light source module 2200. (ElectroStatic discharge) protection element and the like, but may not be limited thereto.
  • the extension part 2670 has a shape protruding outward from the other side of the base 2650.
  • the extension part 2670 is inserted into the connection part 2750 of the inner case 2700 and receives an electrical signal from the outside.
  • the extension part 2670 may be provided to be equal to or smaller than the width of the connection part 2750 of the inner case 2700.
  • Each end of the "+ wire” and the “-wire” may be electrically connected to the extension 2670, and the other end of the "+ wire” and the "-wire” may be electrically connected to the socket 2800. .
  • the inner case 2700 may include a molding unit together with the power supply unit 2600 therein.
  • the molding part is a part where the molding liquid is hardened, so that the power supply part 2600 can be fixed inside the inner case 2700.
  • the lighting apparatus may include a cover 3100, a light source unit 3200, a radiator 3300, a circuit unit 3400, an inner case 3500, and a socket 3600.
  • the light source unit 3200 may include a light emitting device or a light emitting device package according to the embodiment.
  • the cover 3100 has a bulb shape and is hollow.
  • the cover 3100 has an opening 3110.
  • the light source 3200 and the member 3350 may be inserted through the opening 3110.
  • the cover 3100 may be coupled to the radiator 3300 and may surround the light source unit 3200 and the member 3350. By combining the cover 3100 and the radiator 3300, the light source 3200 and the member 3350 may be blocked from the outside.
  • the cover 3100 and the radiator 3300 may be coupled to each other through an adhesive, and may be coupled in various ways such as a rotation coupling method and a hook coupling method.
  • the rotation coupling method is a method in which a screw thread of the cover 3100 is coupled to a screw groove of the heat sink 3300, and the cover 3100 and the heat sink 3300 are coupled by the rotation of the cover 3100.
  • the hook coupling method is a method in which the jaw of the cover 3100 is fitted into the groove of the heat sink 3300 and the cover 3100 and the heat sink 3300 are coupled to each other.
  • the cover 3100 is optically coupled to the light source 3200.
  • the cover 3100 may diffuse, scatter, or excite light from the light emitting device 3230 of the light source unit 3200.
  • the cover 3100 may be a kind of optical member.
  • the cover 3100 may have a phosphor on the inside / outside or inside to excite the light from the light source unit 3200.
  • An inner surface of the cover 3100 may be coated with a milky paint.
  • the milky white paint may include a diffusion material for diffusing light.
  • the surface roughness of the inner surface of the cover 3100 may be greater than the surface roughness of the outer surface of the cover 3100. This is to sufficiently scatter and diffuse the light from the light source unit 3200.
  • the cover 3100 may be made of glass, plastic, polypropylene (PP), polyethylene (PE), polycarbonate (PC), or the like. Here, polycarbonate is excellent in light resistance, heat resistance, and strength.
  • the cover 3100 may be a transparent material that can be seen by the light source unit 3200 and the member 3350 from the outside, or may be an invisible opaque material.
  • the cover 3100 may be formed through, for example, blow molding.
  • the light source unit 3200 may be disposed on the member 3350 of the radiator 3300 and may be disposed in plural. Specifically, the light source 3200 may be disposed on one or more side surfaces of the plurality of side surfaces of the member 3350. In addition, the light source 3200 may be disposed at an upper end of the side of the member 3350.
  • the light source unit 3200 may be disposed on three side surfaces of six side surfaces of the member 3350. However, the present invention is not limited thereto, and the light source unit 3200 may be disposed on all side surfaces of the member 3350.
  • the light source 3200 may include a substrate 3210 and a light emitting device 3230. The light emitting device 3230 may be disposed on one surface of the substrate 3210.
  • the substrate 3210 has a rectangular plate shape, but is not limited thereto and may have various shapes.
  • the substrate 3210 may have a circular or polygonal plate shape.
  • the substrate 3210 may be a circuit pattern printed on an insulator.
  • a printed circuit board (PCB), a metal core PCB, a flexible PCB, a ceramic PCB, and the like may be printed. It may include.
  • COB Chips On Board
  • the substrate 3210 may be formed of a material that efficiently reflects light, or may be formed of a color that reflects light efficiently, for example, white, silver, or the like.
  • the substrate 3210 may be electrically connected to the circuit unit 3400 accommodated in the radiator 3300.
  • the substrate 3210 and the circuit unit 3400 may be connected by, for example, a wire.
  • a wire may pass through the radiator 3300 to connect the substrate 3210 and the circuit unit 3400.
  • the light emitting device 3230 may be a light emitting diode chip emitting red, green, or blue light or a light emitting diode chip emitting UV.
  • the LED chip may be a horizontal type or a vertical type, and the LED chip may emit blue, red, yellow, or green. Can be.
  • the light emitting device 3230 may have a phosphor.
  • the phosphor may be one or more of a Garnet-based (YAG, TAG), a silicate (Silicate), a nitride (Nitride) and an oxynitride (oxyxyride).
  • the phosphor may be one or more of a yellow phosphor, a green phosphor, and a red phosphor.
  • the radiator 3300 may be coupled to the cover 3100 to radiate heat from the light source unit 3200.
  • the radiator 3300 has a predetermined volume and includes an upper surface 3310 and a side surface 3330.
  • a member 3350 may be disposed on the top surface 3310 of the heat sink 3300.
  • An upper surface 3310 of the heat sink 3300 may be coupled to the cover 3100.
  • the top surface 3310 of the heat sink 3300 may have a shape corresponding to the opening 3110 of the cover 3100.
  • a plurality of heat sink fins 3370 may be disposed on the side surface 3330 of the heat sink 3300.
  • the heat radiating fins 3370 may extend outward from the side surface 3330 of the heat sink 3300 or may be connected to the side surface 3330.
  • the heat dissipation fins 3370 may improve heat dissipation efficiency by widening a heat dissipation area of the heat dissipator 3300.
  • the side surface 3330 may not include the heat dissipation fins 3370.
  • the member 3350 may be disposed on an upper surface 3310 of the heat sink 3300.
  • the member 3350 may be integrated with the top surface 3310 or may be coupled to the top surface 3310.
  • the member 3350 may be a polygonal pillar.
  • the member 3350 may be a hexagonal pillar.
  • the member 3350 of the hexagonal column has a top side and a bottom side and six sides.
  • the member 3350 may be a circular pillar or an elliptical pillar as well as a polygonal pillar.
  • the substrate 3210 of the light source unit 3200 may be a flexible substrate.
  • the light source unit 3200 may be disposed on six side surfaces of the member 3350.
  • the light source unit 3200 may be disposed on all six side surfaces, or the light source unit 3200 may be disposed on some of the six side surfaces. In FIG. 16, the light source unit 3200 is disposed on three side surfaces of the six side surfaces.
  • the substrate 3210 is disposed on the side surface of the member 3350. Side surfaces of the member 3350 may be substantially perpendicular to the top surface 3310 of the heat sink 3300. Accordingly, the substrate 3210 and the top surface 3310 of the heat sink 3300 may be substantially perpendicular to each other.
  • the material of the member 3350 may be a material having thermal conductivity. This is for receiving heat generated from the light source unit 3200 quickly.
  • the material of the member 3350 may be, for example, aluminum (Al), nickel (Ni), copper (Cu), magnesium (Mg), silver (Ag), tin (Sn), or an alloy of the metals.
  • the member 3350 may be formed of a thermally conductive plastic having thermal conductivity. Thermally conductive plastics are lighter than metals and have the advantage of having unidirectional thermal conductivity.
  • the circuit unit 3400 receives power from the outside and converts the received power to match the light source unit 3200.
  • the circuit unit 3400 supplies the converted power to the light source unit 3200.
  • the circuit unit 3400 may be disposed on the heat sink 3300.
  • the circuit unit 3400 may be accommodated in the inner case 3500 and may be accommodated in the radiator 3300 together with the inner case 3500.
  • the circuit unit 3400 may include a circuit board 3410 and a plurality of components 3430 mounted on the circuit board 3410.
  • the circuit board 3410 has a circular plate shape, but is not limited thereto and may have various shapes.
  • the circuit board 3410 may have an oval or polygonal plate shape.
  • the circuit board 3410 may have a circuit pattern printed on an insulator.
  • the circuit board 3410 is electrically connected to the substrate 3210 of the light source unit 3200.
  • the electrical connection between the circuit board 3410 and the substrate 3210 may be connected through, for example, a wire.
  • a wire may be disposed in the heat sink 3300 to connect the circuit board 3410 and the board 3210.
  • the plurality of components 3430 may include, for example, a DC converter for converting an AC power provided from an external power source into a DC power source, a driving chip for controlling the driving of the light source unit 3200, and the protection of the light source unit 3200. Electrostatic discharge (ESD) protection element and the like.
  • ESD Electrostatic discharge
  • the inner case 3500 accommodates the circuit unit 3400 therein.
  • the inner case 3500 may have an accommodating part 3510 for accommodating the circuit part 3400.
  • the accommodating part 3510 may have a cylindrical shape.
  • the shape of the accommodating part 3510 may vary depending on the shape of the heat sink 3300.
  • the inner case 3500 may be accommodated in the heat sink 3300.
  • the accommodating part 3510 of the inner case 3500 may be accommodated in an accommodating part formed on a lower surface of the heat sink 3300.
  • the inner case 3500 may be coupled to the socket 3600.
  • the inner case 3500 may have a connection part 3530 that is coupled to the socket 3600.
  • the connection part 3530 may have a thread structure corresponding to the screw groove structure of the socket 3600.
  • the inner case 3500 is an insulator. Therefore, an electrical short circuit between the circuit part 3400 and the heat sink 3300 is prevented.
  • the inner case 3500 may be formed of plastic or resin.
  • the socket 3600 may be coupled to the inner case 3500.
  • the socket 3600 may be coupled to the connection part 3530 of the inner case 3500.
  • the socket 3600 may have a structure such as a conventional conventional incandescent bulb.
  • the circuit unit 3400 and the socket 3600 are electrically connected to each other. Electrical connection between the circuit unit 3400 and the socket 3600 may be connected through a wire. Therefore, when external power is applied to the socket 3600, the external power may be transferred to the circuit unit 3400.
  • the socket 3600 may have a screw groove structure corresponding to the screw structure of the connection part 3550.
  • the lighting apparatus for example, the backlight unit includes a light guide plate 1210, a light emitting module unit 1240 for providing light to the light guide plate 1210, and a reflective member 1220 under the light guide plate 1210. ) And a bottom cover 1230 for accommodating the light guide plate 1210, the light emitting module unit 1240, and the reflective member 1220, but is not limited thereto.
  • the light guide plate 1210 serves to surface light by diffusing light.
  • the light guide plate 1210 is made of a transparent material, for example, an acrylic resin series such as polymethyl metaacrylate (PMMA), polyethylene terephthlate (PET), polycarbonate (PC), cycloolefin copolymer (COC), and polyethylene naphthalate (PEN). It may include one of the resins.
  • PMMA polymethyl metaacrylate
  • PET polyethylene terephthlate
  • PC polycarbonate
  • COC cycloolefin copolymer
  • PEN polyethylene naphthalate
  • the light emitting module unit 1240 provides light to at least one side of the light guide plate 1210 and ultimately serves as a light source of a display device in which the backlight unit is disposed.
  • the light emitting module unit 1240 may be in contact with the light guide plate 1210, but is not limited thereto.
  • the light emitting module unit 1240 includes a substrate 1242 and a plurality of light emitting device packages 200 mounted on the substrate 1242, wherein the substrate 1242 is connected to the light guide plate 1210. It may be encountered, but is not limited thereto.
  • the substrate 1242 may be a printed circuit board (PCB) including a circuit pattern (not shown).
  • PCB printed circuit board
  • the substrate 1242 may include not only a general PCB but also a metal core PCB (MCPCB, Metal Core PCB), a flexible PCB (FPCB, Flexible PCB), and the like, but is not limited thereto.
  • the plurality of light emitting device packages 200 may be mounted on the substrate 1242 such that a light emitting surface on which light is emitted is spaced apart from the light guide plate 1210 by a predetermined distance.
  • the reflective member 1220 may be formed under the light guide plate 1210.
  • the reflective member 1220 may improve the luminance of the backlight unit by reflecting the light incident on the lower surface of the light guide plate 1210 upward.
  • the reflective member 1220 may be formed of, for example, PET, PC, or PVC resin, but is not limited thereto.
  • the bottom cover 1230 may accommodate the light guide plate 1210, the light emitting module unit 1240, the reflective member 1220, and the like. To this end, the bottom cover 1230 may be formed in a box shape having an upper surface opened, but is not limited thereto.
  • the bottom cover 1230 may be formed of a metal material or a resin material, and may be manufactured using a process such as press molding or extrusion molding.
  • the embodiment can improve the reliability of the light emitting device.

Abstract

A light emitting element according to an embodiment comprises: a substrate; a first buffer layer disposed on the substrate; a second buffer layer that is disposed on the first buffer layer and contains Al; a first conductive type semiconductor layer disposed on the second buffer layer; an active layer disposed on the first conductive type semiconductor layer; and a second conductive type semiconductor layer disposed on the active layer, wherein the second buffer layer includes a first layer and a second layer that are horizontally arranged, in which case the first layer has a gradually increasing Al ratio toward the first conductive type semiconductor layer, and the second layer has a gradually decreasing Al ratio toward the first conductive type semiconductor layer. In the embodiment, the first layer that has a linearly increasing Al ratio and the second layer that has a linearly decreasing Al ratio are horizontally arranged in the buffer layer, which makes it possible to effectively control strain caused by lattice mismatch and a difference in a coefficient of thermal expansion between the substrate and the first conductive type semiconductor layer.

Description

발광소자 및 이를 구비하는 조명 시스템Light emitting device and lighting system having same
실시예는 광 효율을 향상시키기 위한 발광소자에 관한 것이다.The embodiment relates to a light emitting device for improving light efficiency.
일반적으로, 발광소자(Light Emitting Device)는 전기에너지가 빛 에너지로 변환되는 특성의 화합물 반도체로서, 주기율표상에서 Ⅲ족과 Ⅴ족 등의 화합물 반도체로 생성될 수 있고 화합물 반도체의 조성비를 조절함으로써 다양한 색상구현이 가능하다.In general, a light emitting device is a compound semiconductor having a characteristic in which electrical energy is converted into light energy. The light emitting device may be formed of compound semiconductors such as group III and group V on the periodic table, and various colors may be adjusted by adjusting the composition ratio of the compound semiconductor. Implementation is possible.
발광소자는 순방향전압 인가 시 n층의 전자와 p층의 정공(hole)이 결합하여 전도대(Conduction band)와 가전대(Valance band)의 밴드갭 에너지에 해당하는 만큼의 에너지를 발산하는데, 이 에너지는 주로 열이나 빛의 형태로 방출되며, 빛의 형태로 발산되면 발광소자가 되는 것이다. 예를 들어, 질화물 반도체는 높은 열적 안정성과 폭넓은 밴드갭 에너지에 의해 광소자 및 고출력 전자소자 개발 분야에서 큰 관심을 받고 있다. 특히, 질화물 반도체를 이용한 청색(Blue) 발광소자, 녹색(Green) 발광소자, 자외선(UV) 발광소자 등은 상용화되어 널리 사용되고 있다.When the forward voltage is applied, the n-layer electrons and the p-layer holes combine to emit energy corresponding to the bandgap energy of the conduction band and the valence band. Is mainly emitted in the form of heat or light, and emits light in the form of light emitting elements. For example, nitride semiconductors are receiving great attention in the field of optical devices and high power electronic devices due to their high thermal stability and wide bandgap energy. In particular, blue light emitting devices, green light emitting devices, and ultraviolet light emitting devices using nitride semiconductors are commercially used and widely used.
종래 질화물 반도체는 기판 상에 GaN 재질의 제1 도전형 반도체층과, 활성층과 제2 도전형 반도체층이 순차적으로 적층되어 형성되며, 활성층과 제2 도전형 반도체층 사이에는 정공의 흐름을 원활하게 하기 위한 정공 주입층이 형성된다.Conventional nitride semiconductors are formed by sequentially stacking a first conductive semiconductor layer of GaN material, an active layer and a second conductive semiconductor layer on a substrate, and smoothly flow holes between the active layer and the second conductive semiconductor layer. A hole injection layer for forming is formed.
정공 주입층은 주로 Mg를 도핑한 단일층으로 형성하고 있으나, 장파장 영역에서 출력(Po) 및 광 효율 측정 전압(VF1)이 떨어지는 문제점이 발생된다.Although the hole injection layer is mainly formed of a single layer doped with Mg, a problem occurs in that the output Po and the light efficiency measurement voltage VF1 fall in the long wavelength region.
상기와 같은 문제점을 해결하기 위해, 실시예는 광 효율을 향상시키기 위한 발광소자 및 이를 구비하는 조명 시스템을 제공하는 것을 그 목적으로 한다.In order to solve the above problems, an embodiment is to provide a light emitting device for improving the light efficiency and an illumination system having the same.
상술한 목적을 달성하기 위하여, 실시예에 따른 발광소자는 기판과, 상기 기판 상에 배치된 제1 도전형 반도체층과, 상기 제1 도전형 반도체층 상에 배치된 활성층과, 상기 활성층 상에 배치된 제2 도전형 반도체층과, 상기 활성층과 제2 도전형 반도체층 사이에 배치되어 언도프된 제1 정공주입층과, 제1 정공주입층 상에 배치되어 p형 도펀트가 도핑된 제2 정공주입층을 포함하는 정공 주입층을 포함할 수 있다.In order to achieve the above object, a light emitting device according to an embodiment includes a substrate, a first conductive semiconductor layer disposed on the substrate, an active layer disposed on the first conductive semiconductor layer, and on the active layer A second conductive semiconductor layer disposed, a first hole injection layer disposed between the active layer and the second conductive semiconductor layer and undoped, and a second doped p-type dopant disposed on the first hole injection layer It may include a hole injection layer including a hole injection layer.
실시예는 정공 주입층에 p형 도펀트가 제거된 층을 형성함으로써, 동작 전압을 유지한 상태에서 출력 전압 및 광 효율 측정 전압을 개선시킬 수 있는 효과가 있다.The embodiment has the effect of improving the output voltage and the light efficiency measurement voltage while maintaining the operating voltage by forming a layer in which the p-type dopant is removed in the hole injection layer.
또한, 실시예는 정공 주입층을 제1 정공주입층 및 제2 정공주입층이 쌍을 이루도록 형성함으로써, 상하층의 격자 불일치를 완화시켜줄 수 있는 효과가 있다.In addition, in the embodiment, the hole injection layer is formed so that the first hole injection layer and the second hole injection layer are paired, thereby reducing the lattice mismatch of the upper and lower layers.
또한, 실시예는 정공 주입층에 InN층을 더 포함시킴으로써, p형 도펀트가 활성층으로 확산되는 것을 방지할 수 있는 효과가 있다.In addition, the embodiment further includes an InN layer in the hole injection layer, thereby preventing the p-type dopant from diffusing into the active layer.
또한, 실시예는 정공 주입층의 가장 하부층의 p형 도펀트 농도를 낮은 GaN층을 더 배치함으로써, 정공 주입 효율을 향상시킬 수 있는 효과가 있다.In addition, the embodiment further improves the hole injection efficiency by further disposing a GaN layer having a lower p-type dopant concentration of the lowermost layer of the hole injection layer.
도 1은 제1 실시예에 따른 발광소자를 나타낸 단면도이다.1 is a cross-sectional view of a light emitting device according to a first embodiment.
도 2는 제1 실시예에 따른 발광소자의 정공 주입층을 나타낸 단면도이다.2 is a cross-sectional view illustrating a hole injection layer of the light emitting device according to the first embodiment.
도 3 내지 도 6은 제1 실시예에 따른 정공 주입층의 Mg 도핑 방법을 나타낸 그래프이다.3 to 6 are graphs showing the Mg doping method of the hole injection layer according to the first embodiment.
도 7은 제1 실시예에 따른 발광소자의 Po을 나타낸 그래프이다.7 is a graph showing Po of the light emitting device according to the first embodiment.
도 8은 제1 실시예에 따른 발광소자의 VF1를 나타낸 그래프이다.8 is a graph illustrating VF1 of the light emitting device according to the first embodiment.
도 9는 제1 실시예에 따른 발광소자의 VF3를 나타낸 그래프이다.9 is a graph showing VF3 of the light emitting device according to the first embodiment.
도 10은 제2 실시예에 따른 발광소자를 나타낸 단면도이다.10 is a sectional view showing a light emitting device according to the second embodiment.
도 11은 제2 실시예에 따른 발광소자의 정공 주입층을 나타낸 단면도이다.11 is a cross-sectional view illustrating a hole injection layer of a light emitting device according to a second embodiment.
도 12는 제3 실시예에 따른 발광소자를 나타낸 단면도이다.12 is a sectional view showing a light emitting device according to the third embodiment.
도 13 및 도 14는 제3 실시예에 따른 발광소자의 정공 주입층을 나타낸 단면도이다.13 and 14 are cross-sectional views illustrating a hole injection layer of the light emitting device according to the third embodiment.
도 15는 제4 실시예에 따른 발광소자를 나타낸 단면도이다.15 is a sectional view showing a light emitting device according to the fourth embodiment.
도 16은 제4 실시예에 따른 발광소자의 정공 주입층을 나타낸 단면도이다.16 is a cross-sectional view illustrating a hole injection layer of a light emitting device according to a fourth embodiment.
도 17은 실시예들에 따른 발광소자가 구비된 발광소자의 패키지를 나타낸 단면도이다.17 is a cross-sectional view illustrating a package of a light emitting device with a light emitting device according to embodiments.
도 18 내지 도 20은 실시예들에 따른 발광소자가 구비된 조명시스템의 실시예들을 나타낸 분해 사시도이다.18 to 20 are exploded perspective views showing embodiments of a lighting system having a light emitting device according to the embodiments.
이하, 도면을 참조하여 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.
도 1은 제1 실시예에 따른 발광소자를 나타낸 단면도이고, 도 2는 제1 실시예에 따른 발광소자의 정공 주입층을 나타낸 단면도이고, 도 3 내지 도 6은 제1 실시예에 따른 정공 주입층의 Mg 도핑 방법을 나타낸 그래프이고, 도 7은 제1 실시예에 따른 발광소자의 Po을 나타낸 그래프이고, 도 8은 제1 실시예에 따른 발광소자의 VF1를 나타낸 그래프이고, 도 9는 제1 실시예에 따른 발광소자의 VF3를 나타낸 그래프이다.1 is a cross-sectional view illustrating a light emitting device according to a first embodiment, FIG. 2 is a cross-sectional view showing a hole injection layer of a light emitting device according to a first embodiment, and FIGS. 3 to 6 are hole injections according to a first embodiment. FIG. 7 is a graph showing Po of the light emitting device according to the first embodiment, FIG. 8 is a graph showing VF1 of the light emitting device according to the first embodiment, and FIG. A graph showing VF3 of the light emitting device according to the embodiment.
도 1 및 도 2를 참조하면, 제1 실시예에 따른 발광소자는 기판(110)과, 상기 기판 상에 배치된 버퍼층(181)과, 상기 버퍼층(181) 상에 배치된 스트레인 제어층(183)과, 상기 스트레인 제어층(183) 상에 배치된 제1 도전형 반도체층(120)과, 상기 제1 도전형 반도체층(120) 상에 배치된 전류 확산층(185)과, 상기 전류 확산층(185) 상에 배치된 활성층(130)과, 상기 활성층(130) 상에 배치된 정공 주입층(140)과, 상기 정공 주입층(140) 상에 배치된 전자 차단층(187)과, 상기 전자 차단층(187) 상에 배치된 제2 도전형 반도체층(150)과, 상기 제2 도전형 반도체층(150) 상에 배치된 투광성 전극층(189)과, 상기 제1 도전형 반도체층(120) 상에 배치된 제1 전극(160)과, 상기 투광성 전극층(189) 상에 배치된 제2 전극(170)을 포함한다.1 and 2, the light emitting device according to the first embodiment includes a substrate 110, a buffer layer 181 disposed on the substrate, and a strain control layer 183 disposed on the buffer layer 181. ), A first conductive semiconductor layer 120 disposed on the strain control layer 183, a current spreading layer 185 disposed on the first conductive semiconductor layer 120, and the current spreading layer ( The active layer 130 disposed on the active layer 130, the hole injection layer 140 disposed on the active layer 130, the electron blocking layer 187 disposed on the hole injection layer 140, and the electrons. The second conductive semiconductor layer 150 disposed on the blocking layer 187, the light transmissive electrode layer 189 disposed on the second conductive semiconductor layer 150, and the first conductive semiconductor layer 120. The first electrode 160 is disposed on the first electrode 160, and the second electrode 170 is disposed on the transparent electrode layer 189.
기판(110)은 열전도성이 뛰어난 물질로 형성될 수 있으며, 전도성 기판 또는 절연성 기판일 수 있다. 예를 들어, 상기 기판(110)은 사파이어(Al2O3), SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, and Ga203 중 적어도 하나를 사용할 수 있다.The substrate 110 may be formed of a material having excellent thermal conductivity, and may be a conductive substrate or an insulating substrate. For example, the substrate 110 may use at least one of sapphire (Al 2 O 3 ), SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, and Ga 2 0 3 .
상기 기판(110) 상에는 버퍼층(181)이 배치될 수 있다. 버퍼층(181)은 상기 발광구조물의 재료와 기판(110)의 격자 불일치를 완화시켜 주는 역할을 한다. 버퍼층(181)으로는 3족-5족 화합물 반도체를 포함할 수 있다. 버퍼층(181)은 Al을 포함하는 재질로 형성될 수 있다. 버퍼층(120)은 AlN, AlGaN, InAlGaN, AlInN 중 적어도 하나로 형성될 수 있다. 상기 버퍼층(181) 상에는 스트레인 제어층(183)이 배치될 수 있다. A buffer layer 181 may be disposed on the substrate 110. The buffer layer 181 serves to alleviate the lattice mismatch between the material of the light emitting structure and the substrate 110. The buffer layer 181 may include a group III-V compound semiconductor. The buffer layer 181 may be formed of a material including Al. The buffer layer 120 may be formed of at least one of AlN, AlGaN, InAlGaN, and AlInN. A strain control layer 183 may be disposed on the buffer layer 181.
상기 스트레인 제어층(183) 상에는 제1 도전형 반도체층(120)이 배치될 수 있다.The first conductivity type semiconductor layer 120 may be disposed on the strain control layer 183.
제1 도전형 반도체층(120)은 예를 들어, n형 반도체층을 포함할 수 있다. 상기 제1 도전형 반도체층(120)은 화합물 반도체로 구현될 수 있다. 상기 제1 도전형 반도체층(120)은 예로서 II족-VI족 화합물 반도체 또는 III족-V족 화합물 반도체로 구현될 수 있다. The first conductivity-type semiconductor layer 120 may include, for example, an n-type semiconductor layer. The first conductivity type semiconductor layer 120 may be implemented as a compound semiconductor. The first conductivity type semiconductor layer 120 may be implemented as, for example, a group II-VI compound semiconductor or a group III-V compound semiconductor.
제1 도전형 반도체층(120)은 InxAlyGa1 -x- yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1)의 조성식을 갖는 반도체 재료로 구현될 수 있다. 상기 제1 도전형 반도체층(120)은, 예를 들어 GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP 등에서 선택될 수 있으며, Si, Ge, Sn, Se, Te 등의 n형 도펀트가 도핑될 수 있다. The first conductivity type semiconductor layer 120 is formed of a semiconductor material having a composition formula of In x Al y Ga 1 -x- y N (0≤x≤1, 0≤y≤1, 0≤x + y≤1). Can be. The first conductivity type semiconductor layer 120 may be selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and the like. N-type dopants such as Se and Te may be doped.
상기 제1 도전형 반도체층(120) 상에는 전류 확산층(185)이 배치될 수 있다.The current diffusion layer 185 may be disposed on the first conductivity type semiconductor layer 120.
전류 확산층(185)은 내부 양자 효율을 향상시켜 광 효율을 증대시킬 수 있으며, 언도프트 질화갈륨층(undoped GaN layer)일 수 있다. 전류 확산층(185) 상에는 전자 주입층(미도시)이 더 형성될 수도 있다. 상기 전자 주입층은 도전형 질화갈륨층일 수 있다. 예를 들어, 상기 전자 주입층은 n형 도핑원소가 6.0x1018atoms/cm3~3.0x1019atoms/cm3의 농도로 도핑 됨으로써 효율적으로 전자주입을 할 수 있다.The current diffusion layer 185 may increase light efficiency by improving internal quantum efficiency, and may be an undoped gallium nitride layer. An electron injection layer (not shown) may be further formed on the current diffusion layer 185. The electron injection layer may be a conductive gallium nitride layer. For example, in the electron injection layer, the n-type doping element is doped at a concentration of 6.0x10 18 atoms / cm 3 to 3.0x10 19 atoms / cm 3 , thereby enabling efficient electron injection.
상기 전류 확산층(185) 상에는 활성층(130)이 배치될 수 있다.The active layer 130 may be disposed on the current spreading layer 185.
활성층(130)은 상기 제1 도전형 반도체층(120)을 통해서 주입되는 전자(또는 정공)와 상기 제2 도전형 반도체층(150)을 통해서 주입되는 정공(또는 전자)이 서로 만나서, 상기 활성층(130)의 형성 물질에 따른 에너지 밴드(Energy Band)의 밴드갭(Band Gap) 차이에 의해서 빛을 방출하는 층이다. 상기 활성층(130)은 단일 우물 구조, 다중 우물 구조, 양자점 구조 또는 양자선 구조 중 어느 하나로 형성될 수 있으나, 이에 한정되는 것은 아니다.In the active layer 130, electrons (or holes) injected through the first conductive semiconductor layer 120 and holes (or electrons) injected through the second conductive semiconductor layer 150 meet each other, and thus, the active layer is formed. The layer emits light due to a band gap difference of an energy band according to the forming material of 130. The active layer 130 may be formed of any one of a single well structure, a multiple well structure, a quantum dot structure, or a quantum line structure, but is not limited thereto.
상기 활성층(130)은 화합물 반도체로 구현될 수 있다. 상기 활성층(130)은 예로서 II족-VI족 또는 III족-V족 화합물 반도체로 구현될 수 있다. 상기 활성층(130)은 예로서 InxAlyGa1 -x- yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1)의 조성식을 갖는 반도체 재료로 구현될 수 있다. 상기 활성층(130)이 상기 다중 우물 구조로 구현된 경우, 상기 활성층(130)은 복수의 우물층과 복수의 장벽층이 적층되어 구현될 수 있으며, 예를 들어, InGaN 우물층/GaN 장벽층의 주기로 구현될 수 있다.The active layer 130 may be implemented with a compound semiconductor. The active layer 130 may be implemented as, for example, a group II-VI or group III-V compound semiconductor. The active layer 130 may be formed of, for example, a semiconductor material having a composition formula of In x Al y Ga 1 -x- y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). have. When the active layer 130 is implemented as the multi-well structure, the active layer 130 may be implemented by stacking a plurality of well layers and a plurality of barrier layers, for example, an InGaN well layer / GaN barrier layer. Can be implemented in cycles.
상기 활성층(130) 상에는 정공 주입층(140)이 배치될 수 있다. The hole injection layer 140 may be disposed on the active layer 130.
정공 주입층(140)은 정공을 발광층의 중심부로 효과적으로 이동시켜 발광 효율을 증가시킬 수 있다. 정공 주입층(140)은 제1 정공주입층(141)과 제2 정공주입층(143)을 포함할 수 있다. 제1 정공주입층(141)은 언도프 층일 수 있다. 제2 정공주입층(143)은 p형 도펀트가 도핑된 층일 수 있다. 정공 주입층(140)에 대해서는 이후 도면을 참조하여 상세히 설명하기로 한다.The hole injection layer 140 may increase the light emission efficiency by effectively moving holes to the center of the light emitting layer. The hole injection layer 140 may include a first hole injection layer 141 and a second hole injection layer 143. The first hole injection layer 141 may be an undoped layer. The second hole injection layer 143 may be a layer doped with a p-type dopant. The hole injection layer 140 will be described in detail later with reference to the drawings.
상기 정공 주입층(140) 상에는 전자 차단층(EBL,187)이 배치될 수 있다.An electron blocking layer EBL 187 may be disposed on the hole injection layer 140.
전자 차단층(187)은 전자 차단(electron blocking) 및 활성층의 클래딩(MQW cladding) 역할을 하며, 이로 인해 발광 효율을 향상시킬 수 있다. 전자 차단층(187)은 AlxInyGa(1-x-y)N(0≤x≤1,0≤y≤1)계 반도체로 형성될 수 있으며, 상기 활성층(130)의 에너지 밴드 갭보다는 높은 에너지 밴드 갭을 가질 수 있으며, 약 100Å~ 약 600Å의 두께로 형성될 수 있으나 이에 한정되는 것은 아니다. 이와 달리, 상기 전자 차단층(187)은 AlzGa(1-z)N/GaN(0≤z≤1) 초격자(superlattice)로 형성될 수 있다.The electron blocking layer 187 serves as electron blocking and cladding of the active layer, thereby improving luminous efficiency. The electron blocking layer 187 may be formed of an Al x In y Ga (1-xy) N (0 ≦ x ≦ 1,0 ≦ y ≦ 1) based semiconductor, and may be higher than the energy band gap of the active layer 130. It may have an energy band gap, and may be formed to a thickness of about 100 kPa to about 600 kPa, but is not limited thereto. Alternatively, the electron blocking layer 187 may be formed of Al z Ga (1-z) N / GaN (0 ≦ z ≦ 1) superlattice.
상기 전자 차단층(187) 상에는 제2 도전형 반도체층(150)이 배치될 수 있다.The second conductivity type semiconductor layer 150 may be disposed on the electron blocking layer 187.
상기 제2 도전형 반도체층(150)은 예를 들어, p형 반도체층으로 구현될 수 있다. 상기 제2 도전형 반도체층(150)은 화합물 반도체로 구현될 수 있다. 상기 제2 도전형 반도체층(150)은 예로서 II족-VI족 화합물 반도체 또는 III족-V족 화합물 반도체로 구현될 수 있다.The second conductivity-type semiconductor layer 150 may be implemented with, for example, a p-type semiconductor layer. The second conductivity-type semiconductor layer 150 may be implemented as a compound semiconductor. For example, the second conductivity-type semiconductor layer 150 may be implemented as a group II-VI compound semiconductor or a group III-V compound semiconductor.
상기 제2 도전형 반도체층(150)은 InxAlyGa1 -x- yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1)의 조성식을 갖는 반도체 재료로 구현될 수 있다. 상기 제2 도전형 반도체층(150)은, 예를 들어 GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP 등에서 선택될 수 있으며, Mg, Zn, Ca, Sr, Be 등의 p형 도펀트가 도핑될 수 있다.The second conductive type semiconductor layer 150 is a semiconductor material having a compositional formula of In x Al y Ga 1 -x- y N (0≤x≤1, 0≤y≤1, 0≤x + y≤1) Can be implemented. The second conductive semiconductor layer 150 may be selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and the like, and may include Mg, Zn, Ca, P-type dopants such as Sr and Be may be doped.
상기 제1 도전형 반도체층(120)이 p형 반도체층을 포함하고 상기 제2 도전형 반도체층(150)이 n형 반도체층을 포함할 수도 있다. 또한, 상기 제2 도전형 반도체층(150) 아래에는 n형 또는 p형 반도체층을 포함하는 반도체층이 더 형성될 수도 있다. 이에 따라, 상기 발광 구조물은 np, pn, npn, pnp 접합 구조 중 적어도 어느 하나를 가질 수 있다. The first conductive semiconductor layer 120 may include a p-type semiconductor layer, and the second conductive semiconductor layer 150 may include an n-type semiconductor layer. In addition, a semiconductor layer including an n-type or p-type semiconductor layer may be further formed below the second conductive semiconductor layer 150. Accordingly, the light emitting structure may have at least one of np, pn, npn, and pnp junction structures.
상기 제1 도전형 반도체층(120) 및 상기 제2 도전형 반도체층(150) 내의 불순물의 도핑 농도는 균일 또는 불균일하게 형성될 수 있다. 즉, 상기 발광 구조물의 구조는 다양하게 형성될 수 있으며, 이에 대해 한정하지는 않는다.Doping concentrations of impurities in the first conductive semiconductor layer 120 and the second conductive semiconductor layer 150 may be uniformly or non-uniformly formed. That is, the structure of the light emitting structure may be formed in various ways, but is not limited thereto.
제2 도전형 반도체층(150) 상에는 투광성 전극층(189)이 배치될 수 있다.The light transmissive electrode layer 189 may be disposed on the second conductive semiconductor layer 150.
투광성 전극층(189)은 캐리어 주입을 효율적으로 할 수 있도록 단일 금속 또는 금속합금, 금속 산화물 등을 다중으로 적층할 수도 있다. 예컨대, 투광성 전극층(189)은 반도체와 전기적인 접촉이 우수한 물질로 형성될 수 있으며, 투광성 전극층(189)으로는 ITO(indium tin oxide), IZO(indium zinc oxide), IZTO(indium zinc tin oxide), IAZO(indium aluminum zinc oxide), IGZO(indium gallium zinc oxide), IGTO(indium gallium tin oxide), AZO(aluminum zinc oxide), ATO(antimony tin oxide), GZO(gallium zinc oxide), IZON(IZO Nitride), AGZO(Al-Ga ZnO), IGZO(In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx/ITO, Ni/IrOx/Au, 및 Ni/IrOx/Au/ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf 중 적어도 하나를 포함하여 형성될 수 있으며, 이러한 재료에 한정되는 않는다.The translucent electrode layer 189 may stack a single metal, a metal alloy, a metal oxide, or the like in multiple layers so as to efficiently inject carriers. For example, the light transmissive electrode layer 189 may be formed of a material having excellent electrical contact with a semiconductor. The light transmissive electrode layer 189 may be indium tin oxide (ITO), indium zinc oxide (IZO), or indium zinc tin oxide (IZTO). , Indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IZO Nitride ), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx / ITO, Ni / IrOx / Au, and Ni / IrOx / Au / ITO, Ag, Ni, Cr , Ti, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf may be formed including at least one, and is not limited to these materials.
투광성 전극층(189) 상에는 제2 전극(170)이 형성되며, 상부 일부가 노출된 제1 도전형 반도체층(120) 상에는 제1 전극(160)이 형성된다. 제1 전극(160) 및 제2 전극(170)으로는 예컨대, Cr, Ti, Ag, Ni, RH, Pd, Ir, Ru, Mg, Zn, Pt, Cu, Au. Hf 중 어느 하나를 포함하는 금속 또는 합금으로 형성될 수 있다. 이후, 최종적으로 제1 전극(160) 및 제2 전극(170)이 서로 연결됨으로써 발광 소자의 제작이 완료될 수 있다.The second electrode 170 is formed on the light transmissive electrode layer 189, and the first electrode 160 is formed on the first conductive semiconductor layer 120 having a portion of the upper portion exposed. As the first electrode 160 and the second electrode 170, for example, Cr, Ti, Ag, Ni, RH, Pd, Ir, Ru, Mg, Zn, Pt, Cu, Au. It may be formed of a metal or an alloy containing any one of Hf. Thereafter, the first electrode 160 and the second electrode 170 are finally connected to each other, thereby manufacturing the light emitting device.
한편, 도 2에 도시된 바와 같이, 제1 실시예에 따른 정공 주입층(140)은 제1 정공주입층(141)과, 제2 정공주입층(143)을 포함할 수 있다.As shown in FIG. 2, the hole injection layer 140 according to the first embodiment may include a first hole injection layer 141 and a second hole injection layer 143.
제1 정공주입층(141)은 언도프된 InxAlyGa1 -x- yN (0<x≤1, 0<y≤1, 0<x+y≤1)층일 수 있다. 제2 정공주입층(143)은 p형 도펀트가 도핑된 InxAlyGa1 -x- yN (0<x≤1, 0<y≤1, 0<x+y≤1)층일 수 있다. p형 도펀트는 Mg, Zn, Ca, Sr, Be를 포함할 수 있다. 제1 정공주입층(141) 및 제2 정공주입층(143)의 Al의 조성은 25% 내지 35%일 수 있으며, 더욱 상세하게는 30%일 수 있다. Al의 조성이 25% 이하이거나 35% 이상이 되면, 출력 전압(Po)이 감소하게 된다.A first hole injection layer 141 can be a layer of undoped In x Al y Ga 1 -x- y N (0 <x≤1, 0 <y≤1, 0 <x + y≤1). The second hole injection layer 143 can be a layer of p-type dopant of In x Al y Ga 1 -x- y N (0 <x≤1, 0 <y≤1, 0 <x + y≤1) doped . The p-type dopant may include Mg, Zn, Ca, Sr, Be. The composition of Al in the first hole injection layer 141 and the second hole injection layer 143 may be 25% to 35%, and more specifically, 30%. When the composition of Al is 25% or less or 35% or more, the output voltage Po decreases.
정공 주입층(140) 예컨대, 제1 정공주입층(141) 및 제2 정공주입층(143)의 총 두께(T11)는 15Å 내지 25Å일 수 있으며, 더욱 상세하게는 20Å의 두께를 가지도록 형성될 수 있다. 제1 정공주입층(141)의 두께(T12)는 제2 정공주입층(143)의 두께(T13)보다 작을 수 있다. 이와 다르게, 제1 정공주입층(141)의 두께(T12)는 제2 정공주입층(143)의 두께(T13)와 동일할 수 있다. 제1 정공주입층(141)의 두께(T12)와 제2 정공주입층(143)의 두께(T13)의 비는 1:1 내지 1:3일 수 있다.For example, the total thickness T11 of the hole injection layer 140, for example, the first hole injection layer 141 and the second hole injection layer 143, may be 15 μm to 25 μm, and more specifically, 20 μm to be formed. Can be. The thickness T12 of the first hole injection layer 141 may be smaller than the thickness T13 of the second hole injection layer 143. Alternatively, the thickness T12 of the first hole injection layer 141 may be the same as the thickness T13 of the second hole injection layer 143. The ratio of the thickness T12 of the first hole injection layer 141 and the thickness T13 of the second hole injection layer 143 may be 1: 1 to 1: 3.
제2 정공주입층(143)의 두께(T13)가 제1 정공주입층(141)의 두께(T12)보다 얇게 형성될 경우, p형 도펀트의 농도가 작아져 장파장 영역에서의 출력 전압(Po) 및 광 효율 측정 전압(VF1)은 개선 효과가 있으나, 동작 전압(VF3)이 높아지게 되는 문제점이 발생된다. 따라서, 제1 정공주입층(141)의 두께(T12)와 제2 정공주입층(143)의 두께(T13)의 비는 1:1일 경우, 표 1에서 도시된 바와 같이, 장파장 영역에서의 출력 전압(Po) 및 광 효율 측정 전압(VF1)은 개선 효과를 얻을 수 있으며, 이로부터 제1 정공주입층(141)의 두께(T12)와 제2 정공주입층(143)의 두께(T13)의 비는 1:1 내지 1:3일 경우, 출력 전압(Po) 및 광 효율 측정 전압(VF1)은 개선 효과는 극대화될 수 있다.When the thickness T13 of the second hole injection layer 143 is formed to be thinner than the thickness T12 of the first hole injection layer 141, the concentration of the p-type dopant is decreased, so that the output voltage Po in the long wavelength region is obtained. Although the light efficiency measuring voltage VF1 has an improvement effect, a problem arises in that the operating voltage VF3 becomes high. Therefore, when the ratio of the thickness T12 of the first hole injection layer 141 and the thickness T13 of the second hole injection layer 143 is 1: 1, as shown in Table 1, in the long wavelength region, The output voltage Po and the light efficiency measurement voltage VF1 may obtain an improvement effect, from which the thickness T12 of the first hole injection layer 141 and the thickness T13 of the second hole injection layer 143 may be obtained. When the ratio is 1: 1 to 1: 3, the improvement effect of the output voltage Po and the light efficiency measurement voltage VF1 may be maximized.
표 1
Run 정보 저전류 특성
NO Purpose Epi구조 Ir Vr Vf1 Vf2-5V -10uV 0.1uV 0.1uV Vf3 Po350mA 350mA
1 Dual Peak LED Repeat S0738 0.002 20.7 1.94 2.1587% 66% 93% 94% 2.97 493.099% 78%
2 2step pQ test Based on S0876 0.002 20.7 1.88 2.0992% 79% 86% 89% 3.00 438.9100% 69%
Run 정보 수율 파장
NO Purpose Epi구조 Prober 초기 SCR후 Target SCR인식 양품 양품 양품 Reject Wd Wp350mA 350mA
1 Dual Peak LED Repeat S0738 466 301 235 68 66100% 65% 50% 15% 14% 443.6 438.822% 97%
2 2step pQ test Based on S0876 435 334 287 253 47100% 77% 66% 58% 11% 448.5 445.384% 100%
Table 1
Run Information Low current characteristic
NO Purpose Epi structure Ir Vr Vf1 Vf2-5V -10uV 0.1uV 0.1uV Vf3 Po350mA 350mA
One Dual Peak LED Repeat S0738 0.002 20.7 1.94 2.1587% 66% 93% 94% 2.97 493.099% 78%
2 2step pQ test Based on S0876 0.002 20.7 1.88 2.0992% 79% 86% 89% 3.00 438.9 100% 69%
Run Information yield wavelength
NO Purpose Epi structure Target SCR Recognition Good Good Good Good Reject after Prober initial SCR Wd Wp350mA 350mA
One Dual Peak LED Repeat S0738 466 301 235 68 66 100% 65% 50% 15% 14% 443.6 438.822% 97%
2 2step pQ test Based on S0876 435 334 287 253 47 100% 77% 66% 58% 11% 448.5 445.384% 100%
제2 정공주입층(143)의 p형 도펀트 예컨대, Mg의 농도는 1E18 내지 3E20일 수 있다. 이러한 Mg의 농도는 앞서 설명한 바와 같이, 장파장 영역에서의 출력 전압(Po) 및 광 효율 측정 전압(VF1)을 최적화하기 위한 농도값이다.The p-type dopant of the second hole injection layer 143, for example, the concentration of Mg may be 1E18 to 3E20. As described above, the concentration of Mg is a concentration value for optimizing the output voltage Po and the light efficiency measurement voltage VF1 in the long wavelength region.
p형 도펀트는 제2 정공주입층(143)의 두께 방향을 따라 균일한 농도값을 가지도록 형성될 수 있다. The p-type dopant may be formed to have a uniform concentration value along the thickness direction of the second hole injection layer 143.
도 3에 도시된 바와 같이, p형 도펀트는 제2 정공주입층(143)의 두께 방향으로 균일한 농도로 공급할 수 있다. 예컨대, 제2 정공주입층(143)에는 타겟 농도값(Ta) 즉, 1E18 내지 3E20이 유지된 상태에서 p형 도펀트를 연속적으로 공급할 수 있다.As shown in FIG. 3, the p-type dopant may be supplied at a uniform concentration in the thickness direction of the second hole injection layer 143. For example, the p-type dopant may be continuously supplied to the second hole injection layer 143 while the target concentration value Ta, that is, 1E18 to 3E20 is maintained.
이와 다르게, 도 4에 도시된 바와 같이, p형 도펀트는 제2 정공주입층(143)의 두께 방향으로 균일한 농도로 공급하되, p형 도펀트를 일정 시간을 두고 반복적으로 공급할 수 있다.Alternatively, as shown in FIG. 4, the p-type dopant may be supplied at a uniform concentration in the thickness direction of the second hole injection layer 143, and the p-type dopant may be repeatedly supplied at a predetermined time.
p형 도펀트는 제2 정공주입층(143)의 두께 방향을 따라 농도값이 커지도록 형성될 수 있다.The p-type dopant may be formed to increase the concentration value along the thickness direction of the second hole injection layer 143.
도 5에 도시된 바와 같이, p형 도펀트는 제2 정공주입층(143)의 두께 방향으로 순차적으로 농도를 높이면서 공급할 수 있다. 여기서, 제2 정공주입층(143)의 p형 도펀트 농도값을 1E18 내지 3E20로 맞추기 위해 목표한 타겟 농도값(Ta) 보다 높은 농도값(Tb)으로 p형 도펀트를 공급할 수 있다.As shown in FIG. 5, the p-type dopant may be supplied while sequentially increasing the concentration in the thickness direction of the second hole injection layer 143. Here, the p-type dopant may be supplied at a concentration value Tb higher than the target target concentration value Ta to adjust the p-type dopant concentration value of the second hole injection layer 143 to 1E18 to 3E20.
이와 다르게, 도 6에 도시된 바와 같이, p형 도펀트는 제2 정공주입층(143)의 두께 방향으로 순차적으로 농도를 높이면서 공급하되, p형 도펀트를 일정 시간을 두고 반복적으로 공급할 수 있다.Alternatively, as shown in FIG. 6, the p-type dopant is supplied while increasing the concentration in the thickness direction of the second hole injection layer 143 sequentially, and the p-type dopant may be repeatedly supplied at a predetermined time.
도 7에 도시된 바와 같이, 실시예에 따른 정공 주입층(140)과 종래 정공 주입층(R)과의 출력 전압(Po)을 살펴보게 되면, 실시예에 따른 정공 주입층 구조는 장파장 영역(A)으로 갈수록 출력 전압(Po)이 종래 정공 주입층(R) 구조에 비해 개선됨을 알 수 있다. 예컨대, 실시예에 따른 정공 주입층(140) 구조는 평균적으로 4%의 상승 약 20mW의 상승됨을 알 수 있다.As shown in FIG. 7, when the output voltage Po between the hole injection layer 140 and the conventional hole injection layer R according to the embodiment is described, the hole injection layer structure according to the embodiment has a long wavelength region ( As shown to A), it can be seen that the output voltage Po is improved compared to the conventional hole injection layer R structure. For example, it can be seen that the hole injection layer 140 structure according to the embodiment is increased by about 20 mW by 4% on average.
도 8에 도시된 바와 같이, 실시예에 따른 정공 주입층(140)과 종래 정공 주입층(R)의 광 효율 전압(VF1)을 살펴보게 되면, 실시예에 따른 정공 주입층(140) 구조는 장파장 영역(A)으로 갈수록 광 효율 전압(VF1)이 개선된을 알 수 있다.As shown in FIG. 8, when looking at the light efficiency voltage VF1 of the hole injection layer 140 and the conventional hole injection layer R according to the embodiment, the structure of the hole injection layer 140 according to the embodiment It can be seen that toward the long wavelength region A, the light efficiency voltage VF1 is improved.
도 9에 도시된 바와 같이, 실시예에 따른 정공 주입층(140)은 p형 도펀트가 제거된 제1 정공주입층이 존재하더라도 p형 도펀트가 포함된 제2 정공주입층을 포함함으로써, 동작전압(VF3)은 안정적으로 유지된 것을 알 수 있다.As shown in FIG. 9, the hole injection layer 140 according to the embodiment includes the second hole injection layer including the p-type dopant even if the first hole injection layer from which the p-type dopant is removed exists, thereby operating voltage. It can be seen that (VF3) was kept stable.
도 7 내지 도 9에서 도시된 바와 같이, 실시예에 따른 2층 구조의 정공 주입층(140)은 동작 전압(VF3)을 유지시키면서도 출력전압(Po) 및 광효율측정전압(VF1)을 개선시켜 광 효율을 향상시키는 효과가 있음을 알 수 있다.As shown in FIGS. 7 to 9, the hole injection layer 140 of the two-layer structure according to the embodiment improves the output voltage Po and the light efficiency measurement voltage VF1 while maintaining the operating voltage VF3. It can be seen that there is an effect of improving the efficiency.
도 10은 제2 실시예에 따른 발광소자를 나타낸 단면도이고, 도 11은 제2 실시예에 따른 발광소자의 정공 주입층을 나타낸 단면도이다.10 is a sectional view showing a light emitting device according to the second embodiment, and FIG. 11 is a sectional view showing a hole injection layer of the light emitting device according to the second embodiment.
도 10을 참조하면, 제2 실시예에 따른 발광소자는 기판(210)과, 상기 기판(210) 상에 배치된 버퍼층(281)과, 상기 버퍼층(281) 상에 배치된 스트레인 제어층(283)과, 상기 스트레인 제어층(283) 상에 배치된 제1 도전형 반도체층(220)과, 상기 제1 도전형 반도체층(220) 상에 배치된 전류 확산층(285)과, 상기 전류 확산층(285) 상에 배치된 활성층(230)과, 상기 활성층(230) 상에 배치된 정공 주입층(240)과, 상기 정공 주입층(240) 상에 배치된 전자 차단층(287)과, 상기 전자 차단층(287) 상에 배치된 제2 도전형 반도체층(250)과, 상기 제2 도전형 반도체층(250) 상에 배치된 투광성 전극층(289)과, 상기 제1 도전형 반도체층(220) 상에 배치된 제1 전극(260)과, 상기 투광성 전극층(289) 상에 배치된 제2 전극(270)을 포함한다. 여기서, 정공 주입층(240)을 제외한 구성은 제1 실시예에 따른 발광소자의 구성과 동일하므로 생략한다.Referring to FIG. 10, the light emitting device according to the second embodiment includes a substrate 210, a buffer layer 281 disposed on the substrate 210, and a strain control layer 283 disposed on the buffer layer 281. ), A first conductive semiconductor layer 220 disposed on the strain control layer 283, a current spreading layer 285 disposed on the first conductive semiconductor layer 220, and the current spreading layer ( The active layer 230 disposed on the 285, the hole injection layer 240 disposed on the active layer 230, the electron blocking layer 287 disposed on the hole injection layer 240, and the electrons. The second conductive semiconductor layer 250 disposed on the blocking layer 287, the transmissive electrode layer 289 disposed on the second conductive semiconductor layer 250, and the first conductive semiconductor layer 220. The first electrode 260 is disposed on the second electrode 260, and the second electrode 270 is disposed on the transparent electrode layer 289. Here, the configuration except for the hole injection layer 240 is the same as the configuration of the light emitting device according to the first embodiment and thus will be omitted.
도 11에 도시된 바와 같이, 정공 주입층(240)은 제1 정공주입층(241)과 제2 정공주입층(243)과 제3 정공주입층(245)과 제4 정공주입층(247)을 포함할 수 있다. 제1 정공주입층(241) 및 제3 정공주입층(245)은 언도프된 InAlGaN층일 수 있다. 제2 정공주입층(243) 및 제4 정공주입층(247)은 p형 도펀트가 도핑된 InAlGaN층일 수 있다.As illustrated in FIG. 11, the hole injection layer 240 may include a first hole injection layer 241, a second hole injection layer 243, a third hole injection layer 245, and a fourth hole injection layer 247. It may include. The first hole injection layer 241 and the third hole injection layer 245 may be undoped InAlGaN layer. The second hole injection layer 243 and the fourth hole injection layer 247 may be an InAlGaN layer doped with a p-type dopant.
정공 주입층(240)의 두께(T21)는 15Å 내지 25Å일 수 있다. 제1 정공주입층(241)의 두께는 제3 정공주입층(245)의 두께와 동일할 수 있다. 제2 정공주입층(243)의 두께는 제4 정공주입층(247)의 두께와 동일할 수 있다. 제1 정공주입층(241)과 제2 정공주입층(243)의 두께의 비는 1:1 내지 1:3일 수 있다. 이와 대응되도록 제3 정공주입층(245)과 제4 정공주입층(247)의 두께의 비는 1:1 내지 1:3일 수 있다.The thickness T21 of the hole injection layer 240 may be 15 mm to 25 mm. The thickness of the first hole injection layer 241 may be the same as the thickness of the third hole injection layer 245. The thickness of the second hole injection layer 243 may be the same as the thickness of the fourth hole injection layer 247. The ratio of the thicknesses of the first hole injection layer 241 and the second hole injection layer 243 may be 1: 1 to 1: 3. Correspondingly, the ratio of the thicknesses of the third hole injection layer 245 and the fourth hole injection layer 247 may be 1: 1 to 1: 3.
제2 정공주입층(243) 및 제4 정공주입층(247)의 p형 도펀트 예컨대, Mg의 농도는 1E18 내지 3E20일 수 있다.The p-type dopant of the second hole injection layer 243 and the fourth hole injection layer 247, for example, the concentration of Mg may be 1E18 to 3E20.
상기와 같이, 제2 실시예에 따른 발광소자는 정공 주입층(240)이 제1 정공주입층과 제2 정공주입층이 쌍을 이루도록 다수개가 형성됨으로써, 각 층 사이의 격자 불일치를 완화시킬 수 있는 효과가 있다.As described above, in the light emitting device according to the second embodiment, a plurality of hole injection layers 240 are formed such that the first hole injection layer and the second hole injection layer are paired, thereby alleviating the lattice mismatch between the layers. It has an effect.
도 12는 제3 실시예에 따른 발광소자를 나타낸 단면도이고, 도 13 및 도 14는 제3 실시예에 따른 발광소자의 정공 주입층을 나타낸 단면도이다.12 is a cross-sectional view illustrating a light emitting device according to a third embodiment, and FIGS. 13 and 14 are cross-sectional views illustrating a hole injection layer of a light emitting device according to a third embodiment.
도 12를 참조하면, 제3 실시예에 따른 발광소자는 기판(310)과, 상기 기판(310) 상에 배치된 버퍼층(381)과, 상기 버퍼층(381) 상에 배치된 스트레인 제어층(383)과, 상기 스트레인 제어층(383) 상에 배치된 제1 도전형 반도체층(320)과, 상기 제1 도전형 반도체층(320) 상에 배치된 전류 확산층(385)과, 상기 전류 확산층(385) 상에 배치된 활성층(330)과, 상기 활성층(330) 상에 배치된 정공 주입층(340)과, 상기 정공 주입층(340) 상에 배치된 전자 차단층(387)과, 상기 전자 차단층(387) 상에 배치된 제2 도전형 반도체층(350)과, 상기 제2 도전형 반도체층(350) 상에 배치된 투광성 전극층(389)과, 상기 제1 도전형 반도체층(320) 상에 배치된 제1 전극(360)과, 상기 투광성 전극층(389) 상에 배치된 제2 전극(370)을 포함한다. 여기서, 정공 주입층(340)을 제외한 구성은 제1 실시예에 따른 발광소자의 구성과 동일하므로 생략한다.Referring to FIG. 12, the light emitting device according to the third embodiment includes a substrate 310, a buffer layer 381 disposed on the substrate 310, and a strain control layer 383 disposed on the buffer layer 381. ), A first conductive semiconductor layer 320 disposed on the strain control layer 383, a current spreading layer 385 disposed on the first conductive semiconductor layer 320, and the current spreading layer ( The active layer 330 disposed on the 385, the hole injection layer 340 disposed on the active layer 330, the electron blocking layer 387 disposed on the hole injection layer 340, and the electrons. The second conductive semiconductor layer 350 disposed on the blocking layer 387, the transparent electrode layer 389 disposed on the second conductive semiconductor layer 350, and the first conductive semiconductor layer 320. The first electrode 360 is disposed on the first electrode 360, and the second electrode 370 is disposed on the light transmissive electrode layer 389. Here, the configuration except for the hole injection layer 340 is the same as the configuration of the light emitting device according to the first embodiment and will be omitted.
도 13에 도시된 바와 같이, 정공 주입층(340)은 제1 정공주입층(341)과 제1 정공주입층(341) 상에 배치된 제2 정공주입층(343)과 상기 제1 정공주입층(341)과 제2 정공주입층(343) 사이에 배치된 제3 정공주입층(345)을 포함할 수 있다.As shown in FIG. 13, the hole injection layer 340 includes a first hole injection layer 341 and a second hole injection layer 343 and the first hole injection layer disposed on the first hole injection layer 341. The third hole injection layer 345 may be disposed between the layer 341 and the second hole injection layer 343.
제1 정공주입층(341)은 언도프 InAlGaN층일 수 있다. 제2 정공주입층(343)은 p형 도펀트가 도핑된 InAlGaN층일 수 있다. 제2 정공주입층(343)의 p형 도펀트 예컨대, Mg의 농도는 1E18 내지 3E20일 수 있다.The first hole injection layer 341 may be an undoped InAlGaN layer. The second hole injection layer 343 may be an InAlGaN layer doped with a p-type dopant. The p-type dopant of the second hole injection layer 343, for example, the concentration of Mg may be 1E18 to 3E20.
제3 정공주입층(345)은 InN을 포함할 수 있다. 제3 정공주입층(345)은 제2 정공주입층(343)에 포함된 p형 도펀트가 활성층(330)으로 확산되는 것을 방지하는 역할을 한다. 즉, 제3 정공주입층(345)은 In을 이용함으로써, p형 도펀트인 Mg의 확산을 방지할 수 있게 된다.The third hole injection layer 345 may include InN. The third hole injection layer 345 serves to prevent the p-type dopant included in the second hole injection layer 343 from diffusing into the active layer 330. That is, the third hole injection layer 345 uses In to prevent diffusion of Mg, which is a p-type dopant.
정공 주입층(340)의 두께는 15Å 내지 25Å일 수 있다. 제1 정공주입층(341)과 제2 정공주입층(343)의 두께의 비는 1:1 내지 1:3일 수 있다. 제3 정공주입층(345)의 두께는 5Å 이하로 형성될 수 있다. 제1 정공주입층(341)과 제3 정공주입층(345)의 두께의 합은 제2 정공주입층(343)의 두께보다 작은 것이 바람직하다. The hole injection layer 340 may have a thickness of 15 mm to 25 mm. The ratio of the thicknesses of the first hole injection layer 341 and the second hole injection layer 343 may be 1: 1 to 1: 3. The thickness of the third hole injection layer 345 may be formed to be 5 Å or less. The sum of the thicknesses of the first hole injection layer 341 and the third hole injection layer 345 is preferably smaller than the thickness of the second hole injection layer 343.
제1 정공주입층(341)과 제3 정공주입층(345)의 두께의 합이 제2 정공주입층(343)의 두께보다 클 경우, p형 도펀트의 농도가 작아져 장파장 영역에서의 출력 전압(Po) 및 광 효율 측정 전압(VF1)은 개선 효과가 있으나, 동작전압(VF3) 높아지게 되는 문제점이 발생된다.When the sum of the thicknesses of the first hole injection layer 341 and the third hole injection layer 345 is greater than the thickness of the second hole injection layer 343, the concentration of the p-type dopant decreases and the output voltage in the long wavelength region is reduced. Although the Po and the light efficiency measurement voltage VF1 have an improvement effect, a problem arises in that the operating voltage VF3 is increased.
이와 다르게, 도 14에 도시된 바와 같이, 정공 주입층(340)은 제1 정공주입층(341)과 제1 정공주입층(341) 상에 배치된 제2 정공주입층(343)과 상기 제1 정공주입층(341)의 아래에 배치된 제3 정공주입층(345)을 포함할 수 있다.Alternatively, as shown in FIG. 14, the hole injection layer 340 may include the second hole injection layer 343 and the second hole injection layer 343 disposed on the first hole injection layer 341 and the first hole injection layer 341. The first hole injection layer 341 may include a third hole injection layer 345 disposed under the hole injection layer 341.
제3 정공주입층(345)은 InN을 포함할 수 있다. 제3 정공주입층(345)은 제2 정공주입층(343)에 포함된 p형 도펀트가 활성층(330)으로 확산되는 것을 방지하는 역할을 한다. 즉, 제3 정공주입층(345)은 In을 이용함으로써, p형 도펀트인 Mg의 확산을 방지할 수 있게 된다.The third hole injection layer 345 may include InN. The third hole injection layer 345 serves to prevent the p-type dopant included in the second hole injection layer 343 from diffusing into the active layer 330. That is, the third hole injection layer 345 uses In to prevent diffusion of Mg, which is a p-type dopant.
도 15는 제4 실시예에 따른 발광소자를 나타낸 단면도이고, 도 16은 제4 실시예에 따른 발광소자의 정공 주입층을 나타낸 단면도이다.15 is a cross-sectional view illustrating a light emitting device according to a fourth embodiment, and FIG. 16 is a cross-sectional view illustrating a hole injection layer of a light emitting device according to a fourth embodiment.
도 15를 참조하면, 제4 실시예에 따른 발광소자는 기판(410)과, 상기 기판(410) 상에 배치된 버퍼층(481)과, 상기 버퍼층(481) 상에 배치된 스트레인 제어층(483)과, 상기 스트레인 제어층(483) 상에 배치된 제1 도전형 반도체층(420)과, 상기 제1 도전형 반도체층(420) 상에 배치된 전류 확산층(485)과, 상기 전류 확산층(485) 상에 배치된 활성층(430)과, 상기 활성층(430) 상에 배치된 정공 주입층(440)과, 상기 정공 주입층(440) 상에 배치된 전자 차단층(481)과, 상기 전자 차단층(481) 상에 배치된 제2 도전형 반도체층(450)과, 상기 제2 도전형 반도체층(450) 상에 배치된 투광성 전극층(489)과, 상기 제1 도전형 반도체층(420) 상에 배치된 제1 전극(460)과, 상기 투광성 전극층(489) 상에 배치된 제2 전극(470)을 포함한다. 여기서, 정공 주입층(440)을 제외한 구성은 제1 실시예에 따른 발광소자의 구성과 동일하므로 생략한다.Referring to FIG. 15, the light emitting device according to the fourth embodiment includes a substrate 410, a buffer layer 481 disposed on the substrate 410, and a strain control layer 483 disposed on the buffer layer 481. ), A first conductivity type semiconductor layer 420 disposed on the strain control layer 483, a current diffusion layer 485 disposed on the first conductivity type semiconductor layer 420, and the current diffusion layer ( An active layer 430 disposed on the 485, a hole injection layer 440 disposed on the active layer 430, an electron blocking layer 481 disposed on the hole injection layer 440, and the electrons The second conductive semiconductor layer 450 disposed on the blocking layer 481, the transparent electrode layer 489 disposed on the second conductive semiconductor layer 450, and the first conductive semiconductor layer 420. The first electrode 460 is disposed on the second electrode 460, and the second electrode 470 is disposed on the light transmissive electrode layer 489. Here, the configuration except for the hole injection layer 440 is the same as the configuration of the light emitting device according to the first embodiment and thus will be omitted.
도 16에 도시된 바와 같이, 정공 주입층(440)은 제1 정공주입층(441)과 제1 정공주입층(441) 상에 배치된 제2 정공주입층(443)과, 제1 정공주입층(441)의 아래에 배치된 제3 정공주입층(445)을 포함할 수 있다.As shown in FIG. 16, the hole injection layer 440 includes a first hole injection layer 441 and a second hole injection layer 443 disposed on the first hole injection layer 441, and a first hole injection layer. It may include a third hole injection layer 445 disposed below the layer 441.
제1 정공주입층(441)은 언도프 InAlGaN층일 수 있다. 제2 정공주입층(443)은 p형 도펀트가 도핑된 InAlGaN층일 수 있다. 제2 정공주입층(443)의 p형 도펀트 예컨대, Mg의 농도는 1E18 내지 3E20일 수 있다.The first hole injection layer 441 may be an undoped InAlGaN layer. The second hole injection layer 443 may be an InAlGaN layer doped with a p-type dopant. The p-type dopant of the second hole injection layer 443, for example, the concentration of Mg may be 1E18 to 3E20.
제3 정공주입층(445)은 GaN, InGaN, AlGaN, InAlGaN을 포함할 수 있다. 제3 정공주입층(445)은 p형 도펀트를 포함할 수 있다. 제3 정공주입층(445)에 포함된 p형 도펀트는 제2 정공주입층(443)의 1/2 이하의 농도값을 가질 수 있다.The third hole injection layer 445 may include GaN, InGaN, AlGaN, InAlGaN. The third hole injection layer 445 may include a p-type dopant. The p-type dopant included in the third hole injection layer 445 may have a concentration value of 1/2 or less of the second hole injection layer 443.
제3 정공주입층(445)은 p형 도펀트의 농도를 낮춤으로써 활성층(430)에 Mg가 확산되는 것을 최소화하여 출력 전압 및 광 효율 전압을 개선할 수 있게 된다. 이와 동시에, 제3 정공주입층(445)은 GaN, InGaN, AlGaN, InAlGaN 재질로 형성함으로써, 정공의 주입 효율을 더욱 향상시킬 수 있게 된다.The third hole injection layer 445 may improve the output voltage and the light efficiency voltage by minimizing the diffusion of Mg into the active layer 430 by lowering the concentration of the p-type dopant. At the same time, since the third hole injection layer 445 is formed of GaN, InGaN, AlGaN, or InAlGaN, the hole injection efficiency can be further improved.
도 17은 실시예들에 따른 발광소자가 구비된 발광소자의 패키지를 나타낸 단면도이다.17 is a cross-sectional view illustrating a package of a light emitting device with a light emitting device according to embodiments.
도 17에 도시된 바와 같이, 발광 소자 패키지(500)는 패키지 몸체부(505)와, 상기 패키지 몸체부(505) 상에 배치된 제3 전극층(513) 및 제4 전극층(514)과, 상기 패키지 몸체부(505) 상에 배치되어 상기 제3 전극층(513) 및 제4 전극층(514)과 전기적으로 연결되는 발광 소자(100)와, 상기 발광 소자(100)를 포위하는 몰딩부재(530)가 포함된다.As shown in FIG. 17, the light emitting device package 500 includes a package body 505, a third electrode layer 513 and a fourth electrode layer 514 disposed on the package body 505, and The light emitting device 100 disposed on the package body 505 and electrically connected to the third electrode layer 513 and the fourth electrode layer 514, and the molding member 530 surrounding the light emitting device 100. Included.
상기 패키지 몸체부(505)는 실리콘 재질, 합성수지 재질, 또는 금속 재질을 포함하여 형성될 수 있으며, 상기 발광 소자(100)의 주상에 경사면이 형성될 수 있다.The package body 505 may include a silicon material, a synthetic resin material, or a metal material, and an inclined surface may be formed on a circumference of the light emitting device 100.
상기 제3 전극층(513) 및 제4 전극층(514)은 서로 전기적으로 분리되며, 상기 발광 소자(100)에 전원을 제공하는 역할을 한다. 또한, 상기 제3 전극층(513) 및 제4 전극층(514)은 상기 발광 소자(100)에서 발생된 빛을 반사시켜 광 효율을 증가시키는 역할을 할 수 있으며, 상기 발광 소자(100)에서 발생된 열을 외부로 배출시키는 역할을 할 수도 있다.The third electrode layer 513 and the fourth electrode layer 514 are electrically separated from each other, and serve to provide power to the light emitting device 100. In addition, the third electrode layer 513 and the fourth electrode layer 514 may serve to increase light efficiency by reflecting the light generated from the light emitting device 100, and generated from the light emitting device 100. It may also serve to release heat to the outside.
상기 발광 소자(100)는 상기 패키지 몸체부(505) 상에 배치되거나 상기 제3 전극층(513) 또는 제4 전극층(514) 상에 배치될 수 있다.The light emitting device 100 may be disposed on the package body 505 or on the third electrode layer 513 or the fourth electrode layer 514.
상기 발광 소자(100)는 상기 제3 전극층(513) 및/또는 제4 전극층(514)과 와이어 방식, 플립칩 방식 또는 다이 본딩 방식 중 어느 하나에 의해 전기적으로 연결될 수도 있다. 실시예에서는 상기 발광 소자(100)가 상기 제1 전극층(513) 및 제2 전극층(514)과 각각 와이어를 통해 전기적으로 연결된 것이 예시되어 있으나 이에 한정되는 것은 아니다.The light emitting device 100 may be electrically connected to the third electrode layer 513 and / or the fourth electrode layer 514 by any one of a wire method, a flip chip method, or a die bonding method. In the embodiment, the light emitting device 100 is electrically connected to the first electrode layer 513 and the second electrode layer 514 through wires, respectively, but is not limited thereto.
상기 몰딩부재(530)는 상기 발광 소자(100)를 포위하여 상기 발광 소자(100)를 보호할 수 있다. 또한, 상기 몰딩부재(530)에는 형광체(532)가 포함되어 상기 발광 소자(100)에서 방출된 광의 파장을 변화시킬 수 있다.The molding member 530 may surround the light emitting device 100 to protect the light emitting device 100. In addition, the molding member 530 may include a phosphor 532 to change the wavelength of light emitted from the light emitting device 100.
도 18 내지 도 20은 실시예들에 따른 발광소자가 구비된 조명시스템의 실시예들을 나타낸 분해 사시도이다.18 to 20 are exploded perspective views showing embodiments of a lighting system having a light emitting device according to the embodiments.
도 18에 도시된 바와 같이, 실시예에 따른 조명 장치는 커버(2100), 광원 모듈(2200), 방열체(2400), 전원 제공부(2600), 내부 케이스(2700), 소켓(2800)을 포함할 수 있다. 또한, 실시 예에 따른 조명 장치는 부재(2300)와 홀더(2500) 중 어느 하나 이상을 더 포함할 수 있다. 상기 광원 모듈(2200)은 본 발명에 따른 발광소자(100) 또는 발광소자 패키지(200)를 포함할 수 있다.As shown in FIG. 18, the lighting apparatus according to the embodiment includes a cover 2100, a light source module 2200, a heat radiator 2400, a power supply 2600, an inner case 2700, and a socket 2800. It may include. In addition, the lighting apparatus according to the embodiment may further include any one or more of the member 2300 and the holder 2500. The light source module 2200 may include a light emitting device 100 or a light emitting device package 200 according to the present invention.
예컨대, 상기 커버(2100)는 벌브(bulb) 또는 반구의 형상을 가지며, 속이 비어 있고, 일 부분이 개구된 형상으로 제공될 수 있다. 상기 커버(2100)는 상기 광원 모듈(2200)과 광학적으로 결합될 수 있다. 예를 들어, 상기 커버(2100)는 상기 광원 모듈(2200)로부터 제공되는 빛을 확산, 산란 또는 여기 시킬 수 있다. 상기 커버(2100)는 일종의 광학 부재일 수 있다. 상기 커버(2100)는 상기 방열체(2400)와 결합될 수 있다. 상기 커버(2100)는 상기 방열체(2400)와 결합하는 결합부를 가질 수 있다.For example, the cover 2100 may have a shape of a bulb or hemisphere, may be hollow, and may be provided in an open shape. The cover 2100 may be optically coupled to the light source module 2200. For example, the cover 2100 may diffuse, scatter or excite the light provided from the light source module 2200. The cover 2100 may be a kind of optical member. The cover 2100 may be coupled to the heat sink 2400. The cover 2100 may have a coupling part coupled to the heat sink 2400.
상기 커버(2100)의 내면에는 유백색 도료가 코팅될 수 있다. 유백색의 도료는 빛을 확산시키는 확산재를 포함할 수 있다. 상기 커버(2100)의 내면의 표면 거칠기는 상기 커버(2100)의 외면의 표면 거칠기보다 크게 형성될 수 있다. 이는 상기 광원 모듈(2200)로부터의 빛이 충분히 산란 및 확산되어 외부로 방출시키기 위함이다. An inner surface of the cover 2100 may be coated with a milky paint. The milky paint may include a diffuser to diffuse light. The surface roughness of the inner surface of the cover 2100 may be greater than the surface roughness of the outer surface of the cover 2100. This is for the light from the light source module 2200 to be sufficiently scattered and diffused to be emitted to the outside.
상기 커버(2100)의 재질은 유리(glass), 플라스틱, 폴리프로필렌(PP), 폴리에틸렌(PE), 폴리카보네이트(PC) 등일 수 있다. 여기서, 폴리카보네이트는 내광성, 내열성, 강도가 뛰어나다. 상기 커버(2100)는 외부에서 상기 광원 모듈(2200)이 보이도록 투명할 수 있고, 불투명할 수 있다. 상기 커버(2100)는 블로우(blow) 성형을 통해 형성될 수 있다.The cover 2100 may be made of glass, plastic, polypropylene (PP), polyethylene (PE), polycarbonate (PC), or the like. Here, polycarbonate is excellent in light resistance, heat resistance, and strength. The cover 2100 may be transparent and opaque so that the light source module 2200 is visible from the outside. The cover 2100 may be formed through blow molding.
상기 광원 모듈(2200)은 상기 방열체(2400)의 일 면에 배치될 수 있다. 따라서, 상기 광원 모듈(2200)로부터의 열은 상기 방열체(2400)로 전도된다. 상기 광원 모듈(2200)은 광원부(2210), 연결 플레이트(2230), 커넥터(2250)를 포함할 수 있다.The light source module 2200 may be disposed on one surface of the heat sink 2400. Thus, heat from the light source module 2200 is conducted to the heat sink 2400. The light source module 2200 may include a light source unit 2210, a connection plate 2230, and a connector 2250.
상기 부재(2300)는 상기 방열체(2400)의 상면 상에 배치되고, 복수의 광원부(2210)들과 커넥터(2250)이 삽입되는 가이드홈(2310)들을 갖는다. 상기 가이드홈(2310)은 상기 광원부(2210)의 기판 및 커넥터(2250)와 대응된다.The member 2300 is disposed on an upper surface of the heat dissipator 2400 and has a plurality of light source parts 2210 and guide grooves 2310 into which the connector 2250 is inserted. The guide groove 2310 corresponds to the board and the connector 2250 of the light source unit 2210.
상기 부재(2300)의 표면은 빛 반사 물질로 도포 또는 코팅된 것일 수 있다. 예를 들면, 상기 부재(2300)의 표면은 백색의 도료로 도포 또는 코팅된 것일 수 있다. 이러한 상기 부재(2300)는 상기 커버(2100)의 내면에 반사되어 상기 광원 모듈(2200)측 방향으로 되돌아오는 빛을 다시 상기 커버(2100) 방향으로 반사한다. 따라서, 실시 예에 따른 조명 장치의 광 효율을 향상시킬 수 있다.The surface of the member 2300 may be coated or coated with a light reflective material. For example, the surface of the member 2300 may be coated or coated with a white paint. The member 2300 is reflected on the inner surface of the cover 2100 to reflect the light returned to the light source module 2200 side again toward the cover 2100. Therefore, it is possible to improve the light efficiency of the lighting apparatus according to the embodiment.
상기 부재(2300)는 예로서 절연 물질로 이루어질 수 있다. 상기 광원 모듈(2200)의 연결 플레이트(2230)는 전기 전도성의 물질을 포함할 수 있다. 따라서, 상기 방열체(2400)와 상기 연결 플레이트(2230) 사이에 전기적인 접촉이 이루어질 수 있다. 상기 부재(2300)는 절연 물질로 구성되어 상기 연결 플레이트(2230)와 상기 방열체(2400)의 전기적 단락을 차단할 수 있다. 상기 방열체(2400)는 상기 광원 모듈(2200)로부터의 열과 상기 전원 제공부(2600)로부터의 열을 전달받아 방열한다.The member 2300 may be made of an insulating material, for example. The connection plate 2230 of the light source module 2200 may include an electrically conductive material. Therefore, electrical contact may be made between the radiator 2400 and the connection plate 2230. The member 2300 may be formed of an insulating material to block an electrical short between the connection plate 2230 and the radiator 2400. The radiator 2400 receives heat from the light source module 2200 and heat from the power supply unit 2600 to radiate heat.
상기 홀더(2500)는 내부 케이스(2700)의 절연부(2710)의 수납홈(2719)를 막는다. 따라서, 상기 내부 케이스(2700)의 상기 절연부(2710)에 수납되는 상기 전원 제공부(2600)는 밀폐된다. 상기 홀더(2500)는 가이드 돌출부(2510)를 갖는다. 상기 가이드 돌출부(2510)는 상기 전원 제공부(2600)의 돌출부(2610)가 관통하는 홀을 갖는다.The holder 2500 may block the accommodating groove 2719 of the insulating portion 2710 of the inner case 2700. Therefore, the power supply unit 2600 accommodated in the insulating unit 2710 of the inner case 2700 is sealed. The holder 2500 has a guide protrusion 2510. The guide protrusion 2510 has a hole through which the protrusion 2610 of the power supply unit 2600 passes.
상기 전원 제공부(2600)는 외부로부터 제공받은 전기적 신호를 처리 또는 변환하여 상기 광원 모듈(2200)로 제공한다. 상기 전원 제공부(2600)는 상기 내부 케이스(2700)의 수납홈(2719)에 수납되고, 상기 홀더(2500)에 의해 상기 내부 케이스(2700)의 내부에 밀폐된다.The power supply unit 2600 processes or converts an electrical signal provided from the outside to provide the light source module 2200. The power supply unit 2600 is accommodated in the accommodating groove 2725 of the inner case 2700, and is sealed in the inner case 2700 by the holder 2500.
상기 전원 제공부(2600)는 돌출부(2610), 가이드부(2630), 베이스(2650), 연장부(2670)를 포함할 수 있다.The power supply unit 2600 may include a protrusion 2610, a guide unit 2630, a base 2650, and an extension unit 2670.
상기 가이드부(2630)는 상기 베이스(2650)의 일 측에서 외부로 돌출된 형상을 갖는다. 상기 가이드부(2630)는 상기 홀더(2500)에 삽입될 수 있다. 상기 베이스(2650)의 일 면 상에 다수의 부품이 배치될 수 있다. 다수의 부품은 예를 들어, 외부 전원으로부터 제공되는 교류 전원을 직류 전원으로 변환하는 직류변환장치, 상기 광원 모듈(2200)의 구동을 제어하는 구동칩, 상기 광원 모듈(2200)을 보호하기 위한 ESD(ElectroStatic discharge) 보호 소자 등을 포함할 수 있으나 이에 대해 한정하지는 않는다.The guide part 2630 has a shape protruding outward from one side of the base 2650. The guide part 2630 may be inserted into the holder 2500. A plurality of parts may be disposed on one surface of the base 2650. The plurality of components may include, for example, a DC converter for converting AC power provided from an external power source into DC power, a driving chip for controlling the driving of the light source module 2200, and an ESD for protecting the light source module 2200. (ElectroStatic discharge) protection element and the like, but may not be limited thereto.
상기 연장부(2670)는 상기 베이스(2650)의 다른 일 측에서 외부로 돌출된 형상을 갖는다. 상기 연장부(2670)는 상기 내부 케이스(2700)의 연결부(2750) 내부에 삽입되고, 외부로부터의 전기적 신호를 제공받는다. 예컨대, 상기 연장부(2670)는 상기 내부 케이스(2700)의 연결부(2750)의 폭과 같거나 작게 제공될 수 있다. 상기 연장부(2670)에는 "+ 전선"과 "- 전선"의 각 일 단이 전기적으로 연결되고, "+ 전선"과 "- 전선"의 다른 일 단은 소켓(2800)에 전기적으로 연결될 수 있다.The extension part 2670 has a shape protruding outward from the other side of the base 2650. The extension part 2670 is inserted into the connection part 2750 of the inner case 2700 and receives an electrical signal from the outside. For example, the extension part 2670 may be provided to be equal to or smaller than the width of the connection part 2750 of the inner case 2700. Each end of the "+ wire" and the "-wire" may be electrically connected to the extension 2670, and the other end of the "+ wire" and the "-wire" may be electrically connected to the socket 2800. .
상기 내부 케이스(2700)는 내부에 상기 전원 제공부(2600)와 함께 몰딩부를 포함할 수 있다. 몰딩부는 몰딩 액체가 굳어진 부분으로서, 상기 전원 제공부(2600)가 상기 내부 케이스(2700) 내부에 고정될 수 있도록 한다.The inner case 2700 may include a molding unit together with the power supply unit 2600 therein. The molding part is a part where the molding liquid is hardened, so that the power supply part 2600 can be fixed inside the inner case 2700.
도 19에 도시된 바와 같이, 실시예에 따른 조명 장치는 커버(3100), 광원부(3200), 방열체(3300), 회로부(3400), 내부 케이스(3500), 소켓(3600)을 포함할 수 있다. 상기 광원부(3200)는 실시 예에 따른 발광소자 또는 발광소자 패키지를 포함할 수 있다. As shown in FIG. 19, the lighting apparatus according to the embodiment may include a cover 3100, a light source unit 3200, a radiator 3300, a circuit unit 3400, an inner case 3500, and a socket 3600. have. The light source unit 3200 may include a light emitting device or a light emitting device package according to the embodiment.
상기 커버(3100)는 벌브(bulb) 형상을 가지며, 속이 비어 있다. 상기 커버(3100)는 개구(3110)를 갖는다. 상기 개구(3110)를 통해 상기 광원부(3200)와 부재(3350)가 삽입될 수 있다. The cover 3100 has a bulb shape and is hollow. The cover 3100 has an opening 3110. The light source 3200 and the member 3350 may be inserted through the opening 3110.
상기 커버(3100)는 상기 방열체(3300)와 결합하고, 상기 광원부(3200)와 상기 부재(3350)를 둘러쌀 수 있다. 상기 커버(3100)와 상기 방열체(3300)의 결합에 의해, 상기 광원부(3200)와 상기 부재(3350)는 외부와 차단될 수 있다. 상기 커버(3100)와 상기 방열체(3300)의 결합은 접착제를 통해 결합할 수도 있고, 회전 결합 방식 및 후크 결합 방식 등 다양한 방식으로 결합할 수 있다. 회전 결합 방식은 상기 방열체(3300)의 나사홈에 상기 커버(3100)의 나사선이 결합하는 방식으로서 상기 커버(3100)의 회전에 의해 상기 커버(3100)와 상기 방열체(3300)가 결합하는 방식이고, 후크 결합 방식은 상기 커버(3100)의 턱이 상기 방열체(3300)의 홈에 끼워져 상기 커버(3100)와 상기 방열체(3300)가 결합하는 방식이다.The cover 3100 may be coupled to the radiator 3300 and may surround the light source unit 3200 and the member 3350. By combining the cover 3100 and the radiator 3300, the light source 3200 and the member 3350 may be blocked from the outside. The cover 3100 and the radiator 3300 may be coupled to each other through an adhesive, and may be coupled in various ways such as a rotation coupling method and a hook coupling method. The rotation coupling method is a method in which a screw thread of the cover 3100 is coupled to a screw groove of the heat sink 3300, and the cover 3100 and the heat sink 3300 are coupled by the rotation of the cover 3100. The hook coupling method is a method in which the jaw of the cover 3100 is fitted into the groove of the heat sink 3300 and the cover 3100 and the heat sink 3300 are coupled to each other.
상기 커버(3100)는 상기 광원부(3200)와 광학적으로 결합한다. 구체적으로 상기 커버(3100)는 상기 광원부(3200)의 발광 소자(3230)로부터의 광을 확산, 산란 또는 여기시킬 수 있다. 상기 커버(3100)는 일종의 광학 부재일 수 있다. 여기서, 상기 커버(3100)는 상기 광원부(3200)로부터의 광을 여기시키기 위해, 내/외면 또는 내부에 형광체를 가질 수 있다. The cover 3100 is optically coupled to the light source 3200. In detail, the cover 3100 may diffuse, scatter, or excite light from the light emitting device 3230 of the light source unit 3200. The cover 3100 may be a kind of optical member. Here, the cover 3100 may have a phosphor on the inside / outside or inside to excite the light from the light source unit 3200.
상기 커버(3100)의 내면에는 유백색 도료가 코팅될 수 있다. 여기서, 유백색 도료는 빛을 확산시키는 확산재를 포함할 수 있다. 상기 커버(3100)의 내면의 표면 거칠기는 상기 커버(3100)의 외면의 표면 거칠기보다 클 수 있다. 이는 상기 광원부(3200)로부터의 광을 충분히 산란 및 확산시키기 위함이다.An inner surface of the cover 3100 may be coated with a milky paint. Here, the milky white paint may include a diffusion material for diffusing light. The surface roughness of the inner surface of the cover 3100 may be greater than the surface roughness of the outer surface of the cover 3100. This is to sufficiently scatter and diffuse the light from the light source unit 3200.
상기 커버(3100)의 재질은 유리(glass), 플라스틱, 폴리프로필렌(PP), 폴리에틸렌(PE), 폴리카보네이트(PC) 등일 수 있다. 여기서, 폴리카보네이트는 내광성, 내열성, 강도가 뛰어나다. 상기 커버(3100)는 외부에서 상기 광원부(3200)와 상기 부재(3350)가 보일 수 있는 투명한 재질일 수 있고, 보이지 않는 불투명한 재질일 수 있다. 상기 커버(3100)는 예컨대 블로우(blow) 성형을 통해 형성될 수 있다.The cover 3100 may be made of glass, plastic, polypropylene (PP), polyethylene (PE), polycarbonate (PC), or the like. Here, polycarbonate is excellent in light resistance, heat resistance, and strength. The cover 3100 may be a transparent material that can be seen by the light source unit 3200 and the member 3350 from the outside, or may be an invisible opaque material. The cover 3100 may be formed through, for example, blow molding.
상기 광원부(3200)는 상기 방열체(3300)의 부재(3350)에 배치되고, 복수로 배치될 수 있다. 구체적으로, 상기 광원부(3200)는 상기 부재(3350)의 복수의 측면들 중 하나 이상의 측면에 배치될 수 있다. 그리고, 상기 광원부(3200)는 상기 부재(3350)의 측면에서도 상단부에 배치될 수 있다.The light source unit 3200 may be disposed on the member 3350 of the radiator 3300 and may be disposed in plural. Specifically, the light source 3200 may be disposed on one or more side surfaces of the plurality of side surfaces of the member 3350. In addition, the light source 3200 may be disposed at an upper end of the side of the member 3350.
상기 광원부(3200)는 상기 부재(3350)의 6 개의 측면들 중 3 개의 측면들에 배치될 수 있다. 그러나 이에 한정하는 것은 아니고, 상기 광원부(3200)는 상기 부재(3350)의 모든 측면들에 배치될 수 있다. 상기 광원부(3200)는 기판(3210)과 발광 소자(3230)를 포함할 수 있다. 상기 발광 소자(3230)는 기판(3210)의 일 면 상에 배치될 수 있다. The light source unit 3200 may be disposed on three side surfaces of six side surfaces of the member 3350. However, the present invention is not limited thereto, and the light source unit 3200 may be disposed on all side surfaces of the member 3350. The light source 3200 may include a substrate 3210 and a light emitting device 3230. The light emitting device 3230 may be disposed on one surface of the substrate 3210.
상기 기판(3210)은 사각형의 판 형상을 갖지만, 이에 한정되지 않고 다양한 형태를 가질 수 있다. 예를 들면, 상기 기판(3210)은 원형 또는 다각형의 판 형상일 수 있다. 상기 기판(3210)은 절연체에 회로 패턴이 인쇄된 것일 수 있으며, 예를 들어, 일반 인쇄회로기판(PCB: Printed Circuit Board), 메탈 코아(Metal Core) PCB, 연성(Flexible) PCB, 세라믹 PCB 등을 포함할 수 있다. 또한, 인쇄회로기판 상에 패키지 하지 않은 LED 칩을 직접 본딩할 수 있는 COB(Chips On Board) 타입을 사용할 수 있다. 또한, 상기 기판(3210)은 광을 효율적으로 반사하는 재질로 형성되거나, 표면이 광을 효율적으로 반사하는 컬러, 예를 들어 백색, 은색 등으로 형성될 수 있다. 상기 기판(3210)은 상기 방열체(3300)에 수납되는 상기 회로부(3400)와 전기적으로 연결될 수 있다. 상기 기판(3210)과 상기 회로부(3400)는 예로서 와이어(wire)를 통해 연결될 수 있다. 와이어는 상기 방열체(3300)를 관통하여 상기 기판(3210)과 상기 회로부(3400)를 연결시킬 수 있다.The substrate 3210 has a rectangular plate shape, but is not limited thereto and may have various shapes. For example, the substrate 3210 may have a circular or polygonal plate shape. The substrate 3210 may be a circuit pattern printed on an insulator. For example, a printed circuit board (PCB), a metal core PCB, a flexible PCB, a ceramic PCB, and the like may be printed. It may include. In addition, it is possible to use a Chips On Board (COB) type that can directly bond the LED chip unpacked on the printed circuit board. In addition, the substrate 3210 may be formed of a material that efficiently reflects light, or may be formed of a color that reflects light efficiently, for example, white, silver, or the like. The substrate 3210 may be electrically connected to the circuit unit 3400 accommodated in the radiator 3300. The substrate 3210 and the circuit unit 3400 may be connected by, for example, a wire. A wire may pass through the radiator 3300 to connect the substrate 3210 and the circuit unit 3400.
상기 발광 소자(3230)는 적색, 녹색, 청색의 광을 방출하는 발광 다이오드 칩이거나 UV를 방출하는 발광 다이오드 칩일 수 있다. 여기서, 발광 다이오드 칩은 수평형(Lateral Type) 또는 수직형(Vertical Type)일 수 있고, 발광 다이오드 칩은 청색(Blue), 적색(Red), 황색(Yellow), 또는 녹색(Green)을 발산할 수 있다.The light emitting device 3230 may be a light emitting diode chip emitting red, green, or blue light or a light emitting diode chip emitting UV. The LED chip may be a horizontal type or a vertical type, and the LED chip may emit blue, red, yellow, or green. Can be.
상기 발광 소자(3230)는 형광체를 가질 수 있다. 형광체는 가넷(Garnet)계(YAG, TAG), 실리케이드(Silicate)계, 나이트라이드(Nitride)계 및 옥시나이트라이드(Oxynitride)계 중 어느 하나 이상일 수 있다. 또는 형광체는 황색 형광체, 녹색 형광체 및 적색 형광체 중 어느 하나 이상일 수 있다.The light emitting device 3230 may have a phosphor. The phosphor may be one or more of a Garnet-based (YAG, TAG), a silicate (Silicate), a nitride (Nitride) and an oxynitride (oxyxyride). Alternatively, the phosphor may be one or more of a yellow phosphor, a green phosphor, and a red phosphor.
상기 방열체(3300)는 상기 커버(3100)와 결합하고, 상기 광원부(3200)로부터의 열을 방열할 수 있다. 상기 방열체(3300)는 소정의 체적을 가지며, 상면(3310), 측면(3330)을 포함한다. 상기 방열체(3300)의 상면(3310)에는 부재(3350)가 배치될 수 있다. 상기 방열체(3300)의 상면(3310)은 상기 커버(3100)와 결합할 수 있다. 상기 방열체(3300)의 상면(3310)은 상기 커버(3100)의 개구(3110)와 대응되는 형상을 가질 수 있다.The radiator 3300 may be coupled to the cover 3100 to radiate heat from the light source unit 3200. The radiator 3300 has a predetermined volume and includes an upper surface 3310 and a side surface 3330. A member 3350 may be disposed on the top surface 3310 of the heat sink 3300. An upper surface 3310 of the heat sink 3300 may be coupled to the cover 3100. The top surface 3310 of the heat sink 3300 may have a shape corresponding to the opening 3110 of the cover 3100.
상기 방열체(3300)의 측면(3330)에는 복수의 방열핀(3370)이 배치될 수 있다. 상기 방열핀(3370)은 상기 방열체(3300)의 측면(3330)에서 외측으로 연장된 것이거나 측면(3330)에 연결된 것일 수 있다. 상기 방열핀(3370)은 상기 방열체(3300)의 방열 면적을 넓혀 방열 효율을 향상시킬 수 있다. 여기서, 측면(3330)은 상기 방열핀(3370)을 포함하지 않을 수도 있다.A plurality of heat sink fins 3370 may be disposed on the side surface 3330 of the heat sink 3300. The heat radiating fins 3370 may extend outward from the side surface 3330 of the heat sink 3300 or may be connected to the side surface 3330. The heat dissipation fins 3370 may improve heat dissipation efficiency by widening a heat dissipation area of the heat dissipator 3300. Here, the side surface 3330 may not include the heat dissipation fins 3370.
상기 부재(3350)는 상기 방열체(3300)의 상면(3310)에 배치될 수 있다. 상기 부재(3350)는 상면(3310)과 일체일 수도 있고, 상면(3310)에 결합된 것일 수 있다. 상기 부재(3350)는 다각 기둥일 수 있다. 구체적으로, 상기 부재(3350)는 육각 기둥일 수 있다. 육각 기둥의 부재(3350)는 윗면과 밑면 그리고 6 개의 측면들을 갖는다. 여기서, 상기 부재(3350)는 다각 기둥뿐만 아니라 원 기둥 또는 타원 기둥일 수 있다. 상기 부재(3350)가 원 기둥 또는 타원 기둥일 경우, 상기 광원부(3200)의 상기 기판(3210)은 연성 기판일 수 있다.The member 3350 may be disposed on an upper surface 3310 of the heat sink 3300. The member 3350 may be integrated with the top surface 3310 or may be coupled to the top surface 3310. The member 3350 may be a polygonal pillar. Specifically, the member 3350 may be a hexagonal pillar. The member 3350 of the hexagonal column has a top side and a bottom side and six sides. Here, the member 3350 may be a circular pillar or an elliptical pillar as well as a polygonal pillar. When the member 3350 is a circular pillar or an elliptic pillar, the substrate 3210 of the light source unit 3200 may be a flexible substrate.
상기 부재(3350)의 6 개의 측면에는 상기 광원부(3200)가 배치될 수 있다. 6 개의 측면 모두에 상기 광원부(3200)가 배치될 수도 있고, 6 개의 측면들 중 몇 개의 측면들에 상기 광원부(3200)가 배치될 수도 있다. 도 16에서는 6 개의 측면들 중 3 개의 측면들에 상기 광원부(3200)가 배치되어 있다. The light source unit 3200 may be disposed on six side surfaces of the member 3350. The light source unit 3200 may be disposed on all six side surfaces, or the light source unit 3200 may be disposed on some of the six side surfaces. In FIG. 16, the light source unit 3200 is disposed on three side surfaces of the six side surfaces.
상기 부재(3350)의 측면에는 상기 기판(3210)이 배치된다. 상기 부재(3350)의 측면은 상기 방열체(3300)의 상면(3310)과 실질적으로 수직을 이룰 수 있다. 따라서, 상기 기판(3210)과 상기 방열체(3300)의 상면(3310)은 실질적으로 수직을 이룰 수 있다. The substrate 3210 is disposed on the side surface of the member 3350. Side surfaces of the member 3350 may be substantially perpendicular to the top surface 3310 of the heat sink 3300. Accordingly, the substrate 3210 and the top surface 3310 of the heat sink 3300 may be substantially perpendicular to each other.
상기 부재(3350)의 재질은 열 전도성을 갖는 재질일 수 있다. 이는 상기 광원부(3200)로부터 발생되는 열을 빠르게 전달받기 위함이다. 상기 부재(3350)의 재질로서는 예를 들면, 알루미늄(Al), 니켈(Ni), 구리(Cu), 마그네슘(Mg), 은(Ag), 주석(Sn) 등과 상기 금속들의 합금일 수 있다. 또는 상기 부재(3350)는 열 전도성을 갖는 열 전도성 플라스틱으로 형성될 수 있다. 열 전도성 플라스틱은 금속보다 무게가 가볍고, 단방향성의 열 전도성을 갖는 이점이 있다.The material of the member 3350 may be a material having thermal conductivity. This is for receiving heat generated from the light source unit 3200 quickly. The material of the member 3350 may be, for example, aluminum (Al), nickel (Ni), copper (Cu), magnesium (Mg), silver (Ag), tin (Sn), or an alloy of the metals. Alternatively, the member 3350 may be formed of a thermally conductive plastic having thermal conductivity. Thermally conductive plastics are lighter than metals and have the advantage of having unidirectional thermal conductivity.
상기 회로부(3400)는 외부로부터 전원을 제공받고, 제공받은 전원을 상기 광원부(3200)에 맞게 변환한다. 상기 회로부(3400)는 변환된 전원을 상기 광원부(3200)로 공급한다. 상기 회로부(3400)는 상기 방열체(3300)에 배치될 수 있다. 구체적으로, 상기 회로부(3400)는 상기 내부 케이스(3500)에 수납되고, 상기 내부 케이스(3500)와 함께 상기 방열체(3300)에 수납될 수 있다. 상기 회로부(3400)는 회로 기판(3410)과 상기 회로 기판(3410) 상에 탑재되는 다수의 부품(3430)을 포함할 수 있다. The circuit unit 3400 receives power from the outside and converts the received power to match the light source unit 3200. The circuit unit 3400 supplies the converted power to the light source unit 3200. The circuit unit 3400 may be disposed on the heat sink 3300. In detail, the circuit unit 3400 may be accommodated in the inner case 3500 and may be accommodated in the radiator 3300 together with the inner case 3500. The circuit unit 3400 may include a circuit board 3410 and a plurality of components 3430 mounted on the circuit board 3410.
상기 회로 기판(3410)은 원형의 판 형상을 갖지만, 이에 한정되지 않고 다양한 형태를 가질 수 있다. 예를 들면, 상기 회로 기판(3410)은 타원형 또는 다각형의 판 형상일 수 있다. 이러한 회로 기판(3410)은 절연체에 회로 패턴이 인쇄된 것일 수 있다. The circuit board 3410 has a circular plate shape, but is not limited thereto and may have various shapes. For example, the circuit board 3410 may have an oval or polygonal plate shape. The circuit board 3410 may have a circuit pattern printed on an insulator.
상기 회로 기판(3410)은 상기 광원부(3200)의 기판(3210)과 전기적으로 연결된다. 상기 회로 기판(3410)과 상기 기판(3210)의 전기적 연결은 예로서 와이어(wire)를 통해 연결될 수 있다. 와이어는 상기 방열체(3300)의 내부에 배치되어 상기 회로 기판(3410)과 상기 기판(3210)을 연결할 수 있다. The circuit board 3410 is electrically connected to the substrate 3210 of the light source unit 3200. The electrical connection between the circuit board 3410 and the substrate 3210 may be connected through, for example, a wire. A wire may be disposed in the heat sink 3300 to connect the circuit board 3410 and the board 3210.
다수의 부품(3430)은 예를 들어, 외부 전원으로부터 제공되는 교류 전원을 직류 전원으로 변환하는 직류변환장치, 상기 광원부(3200)의 구동을 제어하는 구동칩, 상기 광원부(3200)를 보호하기 위한 ESD(ElectroStatic discharge) 보호 소자 등을 포함할 수 있다.The plurality of components 3430 may include, for example, a DC converter for converting an AC power provided from an external power source into a DC power source, a driving chip for controlling the driving of the light source unit 3200, and the protection of the light source unit 3200. Electrostatic discharge (ESD) protection element and the like.
상기 내부 케이스(3500)는 내부에 상기 회로부(3400)를 수납한다. 상기 내부 케이스(3500)는 상기 회로부(3400)를 수납하기 위해 수납부(3510)를 가질 수 있다. The inner case 3500 accommodates the circuit unit 3400 therein. The inner case 3500 may have an accommodating part 3510 for accommodating the circuit part 3400.
상기 수납부(3510)는 예로서 원통 형상을 가질 수 있다. 상기 수납부(3510)의 형상은 상기 방열체(3300)의 형상에 따라 달라질 수 있다. 상기 내부 케이스(3500)는 상기 방열체(3300)에 수납될 수 있다. 상기 내부 케이스(3500)의 수납부(3510)는 상기 방열체(3300)의 하면에 형성된 수납부에 수납될 수 있다. For example, the accommodating part 3510 may have a cylindrical shape. The shape of the accommodating part 3510 may vary depending on the shape of the heat sink 3300. The inner case 3500 may be accommodated in the heat sink 3300. The accommodating part 3510 of the inner case 3500 may be accommodated in an accommodating part formed on a lower surface of the heat sink 3300.
상기 내부 케이스(3500)는 상기 소켓(3600)과 결합될 수 있다. 상기 내부 케이스(3500)는 상기 소켓(3600)과 결합하는 연결부(3530)를 가질 수 있다. 상기 연결부(3530)는 상기 소켓(3600)의 나사홈 구조와 대응되는 나사산 구조를 가질 수 있다. 상기 내부 케이스(3500)는 부도체이다. 따라서, 상기 회로부(3400)와 상기 방열체(3300) 사이의 전기적 단락을 막는다. 예로서 상기 내부 케이스(3500)는 플라스틱 또는 수지 재질로 형성될 수 있다.The inner case 3500 may be coupled to the socket 3600. The inner case 3500 may have a connection part 3530 that is coupled to the socket 3600. The connection part 3530 may have a thread structure corresponding to the screw groove structure of the socket 3600. The inner case 3500 is an insulator. Therefore, an electrical short circuit between the circuit part 3400 and the heat sink 3300 is prevented. For example, the inner case 3500 may be formed of plastic or resin.
상기 소켓(3600)은 상기 내부 케이스(3500)와 결합될 수 있다. 구체적으로, 상기 소켓(3600)은 상기 내부 케이스(3500)의 연결부(3530)와 결합될 수 있다. 상기 소켓(3600)은 종래 재래식 백열 전구와 같은 구조를 가질 수 있다. 상기 회로부(3400)와 상기 소켓(3600)은 전기적으로 연결된다. 상기 회로부(3400)와 상기 소켓(3600)의 전기적 연결은 와이어(wire)를 통해 연결될 수 있다. 따라서, 상기 소켓(3600)에 외부 전원이 인가되면, 외부 전원은 상기 회로부(3400)로 전달될 수 있다. 상기 소켓(3600)은 상기 연결부(3550)의 나사선 구조과 대응되는 나사홈 구조를 가질 수 있다.The socket 3600 may be coupled to the inner case 3500. In detail, the socket 3600 may be coupled to the connection part 3530 of the inner case 3500. The socket 3600 may have a structure such as a conventional conventional incandescent bulb. The circuit unit 3400 and the socket 3600 are electrically connected to each other. Electrical connection between the circuit unit 3400 and the socket 3600 may be connected through a wire. Therefore, when external power is applied to the socket 3600, the external power may be transferred to the circuit unit 3400. The socket 3600 may have a screw groove structure corresponding to the screw structure of the connection part 3550.
도 20에 도시된 바와 같이, 조명장치 예컨대, 백라이트 유닛은 도광판(1210)과, 상기 도광판(1210)에 빛을 제공하는 발광모듈부(1240)와, 상기 도광판(1210) 아래에 반사 부재(1220)와, 상기 도광판(1210), 발광모듈부(1240) 및 반사 부재(1220)를 수납하는 바텀 커버(1230)를 포함할 수 있으나 이에 한정되지 않는다.As shown in FIG. 20, the lighting apparatus, for example, the backlight unit includes a light guide plate 1210, a light emitting module unit 1240 for providing light to the light guide plate 1210, and a reflective member 1220 under the light guide plate 1210. ) And a bottom cover 1230 for accommodating the light guide plate 1210, the light emitting module unit 1240, and the reflective member 1220, but is not limited thereto.
상기 도광판(1210)은 빛을 확산시켜 면광원화 시키는 역할을 한다. 상기 도광판(1210)은 투명한 재질로 이루어지며, 예를 들어, PMMA(polymethyl metaacrylate)와 같은 아크릴 수지 계열, PET(polyethylene terephthlate), PC(poly carbonate), COC(cycloolefin copolymer) 및 PEN(polyethylene naphthalate) 수지 중 하나를 포함할 수 있다. The light guide plate 1210 serves to surface light by diffusing light. The light guide plate 1210 is made of a transparent material, for example, an acrylic resin series such as polymethyl metaacrylate (PMMA), polyethylene terephthlate (PET), polycarbonate (PC), cycloolefin copolymer (COC), and polyethylene naphthalate (PEN). It may include one of the resins.
상기 발광모듈부(1240)은 상기 도광판(1210)의 적어도 일 측면에 빛을 제공하며, 궁극적으로는 상기 백라이트 유닛이 배치되는 디스플레이 장치의 광원으로써 작용하게 된다.The light emitting module unit 1240 provides light to at least one side of the light guide plate 1210 and ultimately serves as a light source of a display device in which the backlight unit is disposed.
상기 발광모듈부(1240)은 상기 도광판(1210)과 접할 수 있으나 이에 한정되지 않는). 구체적으로는, 상기 발광모듈부(1240)은 기판(1242)과, 상기 기판(1242)에 탑재된 다수의 발광소자 패키지(200)를 포함하는데, 상기 기판(1242)이 상기 도광판(1210)과 접할 수 있으나 이에 한정되지 않는다.The light emitting module unit 1240 may be in contact with the light guide plate 1210, but is not limited thereto. Specifically, the light emitting module unit 1240 includes a substrate 1242 and a plurality of light emitting device packages 200 mounted on the substrate 1242, wherein the substrate 1242 is connected to the light guide plate 1210. It may be encountered, but is not limited thereto.
상기 기판(1242)은 회로패턴(미도시)을 포함하는 인쇄회로기판(PCB, Printed Circuit Board)일 수 있다. 다만, 상기 기판(1242)은 일반 PCB 뿐 아니라, 메탈 코어 PCB(MCPCB, Metal Core PCB), 연성 PCB(FPCB, Flexible PCB) 등을 포함할 수도 있으며, 이에 대해 한정하지는 않는다.The substrate 1242 may be a printed circuit board (PCB) including a circuit pattern (not shown). However, the substrate 1242 may include not only a general PCB but also a metal core PCB (MCPCB, Metal Core PCB), a flexible PCB (FPCB, Flexible PCB), and the like, but is not limited thereto.
그리고, 상기 다수의 발광소자 패키지(200)는 상기 기판(1242) 상에 빛이 방출되는 발광면이 상기 도광판(1210)과 소정 거리 이격되도록 탑재될 수 있다.The plurality of light emitting device packages 200 may be mounted on the substrate 1242 such that a light emitting surface on which light is emitted is spaced apart from the light guide plate 1210 by a predetermined distance.
상기 도광판(1210) 아래에는 상기 반사 부재(1220)가 형성될 수 있다. 상기 반사 부재(1220)는 상기 도광판(1210)의 하면으로 입사된 빛을 반사시켜 위로 향하게 함으로써, 상기 백라이트 유닛의 휘도를 향상시킬 수 있다. 상기 반사 부재(1220)는 예를 들어, PET, PC, PVC 레진 등으로 형성될 수 있으나, 이에 대해 한정하지는 않는다.The reflective member 1220 may be formed under the light guide plate 1210. The reflective member 1220 may improve the luminance of the backlight unit by reflecting the light incident on the lower surface of the light guide plate 1210 upward. The reflective member 1220 may be formed of, for example, PET, PC, or PVC resin, but is not limited thereto.
상기 바텀 커버(1230)는 상기 도광판(1210), 발광모듈부(1240) 및 반사 부재(1220) 등을 수납할 수 있다. 이를 위해, 상기 바텀 커버(1230)는 상면이 개구된 박스(box) 형상으로 형성될 수 있으나, 이에 대해 한정하지는 않는다.The bottom cover 1230 may accommodate the light guide plate 1210, the light emitting module unit 1240, the reflective member 1220, and the like. To this end, the bottom cover 1230 may be formed in a box shape having an upper surface opened, but is not limited thereto.
상기 바텀 커버(1230)는 금속 재질 또는 수지 재질로 형성될 수 있으며, 프레스 성형 또는 압출 성형 등의 공정을 이용하여 제조될 수 있다.The bottom cover 1230 may be formed of a metal material or a resin material, and may be manufactured using a process such as press molding or extrusion molding.
상기에서는 도면 및 실시예를 참조하여 설명하였지만, 해당 기술 분야의 숙련된 당업자는 하기의 특허청구범위에 기재된 실시예의 기술적 사상으로부터 벗어나지 않는 범위 내에서 실시예는 다양하게 수정 및 변경시킬 수 있음은 이해할 수 있을 것이다.Although described above with reference to the drawings and embodiments, those skilled in the art will understand that the embodiments can be variously modified and changed without departing from the spirit of the embodiments described in the claims below. Could be.
실시예는 발광 소자의 신뢰성을 개선시켜 줄 수 있다.The embodiment can improve the reliability of the light emitting device.

Claims (20)

  1. 기판;Board;
    상기 기판 상에 배치된 제1 도전형 반도체층;A first conductivity type semiconductor layer disposed on the substrate;
    상기 제1 도전형 반도체층 상에 배치된 활성층;An active layer disposed on the first conductivity type semiconductor layer;
    상기 활성층 상에 배치된 제2 도전형 반도체층; 및A second conductivity type semiconductor layer disposed on the active layer; And
    상기 활성층과 제2 도전형 반도체층 사이에 배치되어 언도프된 제1 정공주입층과, 제1 정공주입층 상에 배치되어 p형 도펀트가 도핑된 제2 정공주입층을 포함하는 정공 주입층;A hole injection layer including a first hole injection layer disposed between the active layer and the second conductive semiconductor layer and undoped, and a second hole injection layer disposed on the first hole injection layer and doped with a p-type dopant;
    을 포함하는 발광소자.Light emitting device comprising a.
  2. 제 1 항에 있어서,The method of claim 1,
    상기 p형 도펀트는 Mg, Zn, Ca, Sr, Be를 포함하는 발광소자.The p-type dopant is Mg, Zn, Ca, Sr, Be comprising a light emitting device.
  3. 제 2 항에 있어서,The method of claim 2,
    상기 제1 정공주입층 및 제2 정공주입층은 InxAlyGa1 -x- yN (0<x≤1, 0<y≤1, 0<x+y≤1)을 포함하는 발광소자.A light emitting device including the first hole injection layer and the second hole injection layer is In x Al y Ga 1 -x- y N (0 <x≤1, 0 <y≤1, 0 <x + y≤1) .
  4. 제 3 항에 있어서,The method of claim 3, wherein
    상기 정공 주입층의 두께는 15Å 내지 25Å인 발광소자.The hole injection layer has a thickness of 15 kHz to 25 kHz.
  5. 제 4 항에 있어서,The method of claim 4, wherein
    상기 제1 정공주입층의 두께와 제2 정공주입층의 두께의 비는 1:1 내지 1:3인 발광소자.The ratio of the thickness of the first hole injection layer and the thickness of the second hole injection layer is 1: 1 to 1: 3.
  6. 제 1 항에 있어서,The method of claim 1,
    상기 p형 도펀트 농도는 1E18 내지 3E20 인 발광소자.The p-type dopant concentration is 1E18 to 3E20 light emitting device.
  7. 제 6 항에 있어서,The method of claim 6,
    상기 제2 정공주입층의 p형 도펀트는 두께 방향으로 동일한 농도값을 가지는 발광소자.The p-type dopant of the second hole injection layer has the same concentration value in the thickness direction.
  8. 제 6 항에 있어서,The method of claim 6,
    상기 제2 정공주입층의 p형 도펀트는 두께 방향으로 갈수록 농도값이 커지는 발광소자.The p-type dopant of the second hole injection layer is a light emitting device that the concentration value increases in the thickness direction.
  9. 제 1 항에 있어서,The method of claim 1,
    상기 정공 주입층 상에는 제1 및 제2 정공주입층이 쌍을 이루어 다수개가 배치되는 발광소자.A light emitting device in which a plurality of first and second hole injection layers are arranged in pairs on the hole injection layer.
  10. 제 1 항에 있어서,The method of claim 1,
    상기 정공 주입층은 InN을 포함하는 제3 정공주입층을 더 포함하는 발광소자.The hole injection layer further comprises a third hole injection layer including InN.
  11. 제 10 항에 있어서,The method of claim 10,
    상기 제3 정공주입층은 제1 정공주입층과 제2 정공주입층 사이에 배치되는 발광소자.The third hole injection layer is a light emitting device disposed between the first hole injection layer and the second hole injection layer.
  12. 제 10 항에 있어서,The method of claim 10,
    상기 제3 정공주입층은 활성층과 제1 정공주입층 사이에 배치되는 발광소자.The third hole injection layer is disposed between the active layer and the first hole injection layer.
  13. 제 10 항에 있어서,The method of claim 10,
    상기 제3 정공주입층의 두께는 5Å 이하인 발광소자.The third hole injection layer has a thickness of 5 Å or less.
  14. 제 1 항에 있어서,The method of claim 1,
    상기 정공 주입층은 p형 도펀트 농도가 제2 정공주입층의 1/2 이하인 제3 정공주입층을 더 포함하는 발광소자.The hole injection layer further comprises a third hole injection layer having a p-type dopant concentration of 1/2 or less of the second hole injection layer.
  15. 제 14 항에 있어서,The method of claim 14,
    상기 제3 정공주입층은 활성층과 제1 정공주입층 사이에 배치되는 발광소자.The third hole injection layer is disposed between the active layer and the first hole injection layer.
  16. 제 15 항에 있어서,The method of claim 15,
    상기 제3 정공주입층은 GaN, InGaN, AlGaN, InAlGaN을 포함하는 발광소자.The third hole injection layer includes a GaN, InGaN, AlGaN, InAlGaN.
  17. 제 1 항에 있어서,The method of claim 1,
    상기 기판과 상기 제1 도전형 반도체층 사이에 배치된 버퍼층 및 스트레인 제어층을 더 포함하는 발광소자.And a buffer layer and a strain control layer disposed between the substrate and the first conductive semiconductor layer.
  18. 제 1 항에 있어서,The method of claim 1,
    상기 제1 도전형 반도체층과 상기 활성층 사이에 배치된 전류 확산층을 더 포함하는 발광소자.And a current spreading layer disposed between the first conductive semiconductor layer and the active layer.
  19. 제 1 항에 있어서,The method of claim 1,
    상기 제2 도전형 반도체층 상에 배치된 투광성 전극층을 더 포함하는 발광소자.The light emitting device further comprising a translucent electrode layer disposed on the second conductive semiconductor layer.
  20. 제 1 항 내지 제 19 항 중 어느 한 항의 발광소자를 포함하는 조명 시스템.20. An illumination system comprising the light emitting device of any one of claims 1-19.
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KR20130094451A (en) * 2012-02-16 2013-08-26 엘지디스플레이 주식회사 Nitride semiconductor light emitting device and method for fabricating the same
KR20140052173A (en) * 2012-10-22 2014-05-07 일진엘이디(주) Nitride semiconductor light emitting device with excellent lightness and esd protection

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