WO2015197971A1

WO2015197971A1 - Methods and devices for error corrector coding and decoding, and corresponding computer program

Info

Publication number: WO2015197971A1
Application number: PCT/FR2015/051680
Authority: WO
Inventors: Jean-Claude Carlach
Original assignee: Orange
Priority date: 2014-06-24
Filing date: 2015-06-23
Publication date: 2015-12-30
Also published as: FR3022651A1

Abstract

The invention relates to a device for coding by belief propagation on a multi-stage Tanner graph. According to the invention, such a coding device comprises: - two first-level permutation stages, of which a first stage (231) connected to input variables and to internal variables associated with a first second-level coding stage (221), and a second stage (232) connected to output variables and to internal variables associated with a second second-level coding stage (222), and - a first-level coding stage (21) connected on the one hand to the first first-level permutation stage and on the other hand to the second first-level permutation stage, each coding stage comprising at least two base coding modules each implementing a base code.

Description

Methods and devices for error correction coding and decoding, and corresponding computer program.

1. Field of the invention

The field of the invention is that of coding and decoding data, implementing an error correction code.

More specifically, the invention proposes a new source data coding technique, delivering coded data packets or a coded data stream, intended to be transmitted over a transmission channel (for example of the wireless, optical or electrical), or stored in a physical medium. The invention also relates to a corresponding decoding technique, in particular for correcting transmission errors inherent in the transmission channel, and in particular erase-type errors.

The invention finds particular applications in the following fields:

the transmission of information by wired electrical telecommunications, as in the ADSL or optical standards, on optical fibers or in free space;

the transmission of information in space and wireless terrestrial radio communications ("wireless"), as in the digital television systems DTT, DAB digital radio, GSM or U-MTS telephony, WiFi radio network, and also in future communications systems, such as future DVB, 4G, LTE standards, "Future Internet", or in communications between vehicles, objects or communicating machines ...;

information source compression and decompression;

the generation and detection of so-called scrambling sequences in CDMA systems;

storing information in magnetic, optical, mechanical or electrical mass memories for constituting hard disks, or RAMs of computers, or memory sticks with a USB type interface ...;

correcting information during calculations in an integrated circuit of a microprocessor or in a computer;

etc.

2. Prior Art

Numerous coding techniques allow the correction of transmission errors (at decoding) by generating redundancy data from source data.

Thus, an error correction code is conventionally defined by:

a length n, corresponding to the output data of the encoder (code word of length n formed of k source data and (n - k) redundancy data), a number of bits or useful information symbols k, corresponding to the input data of the encoder, also called source data, and

a minimum distance d _min .

The minimum distance of a code d _mjn is the minimum distance between two codewords. It allows to determine the maximum number of errors that the code can correct in a code word. The performance of the code is defined by R = k / n

For example, a Hamming code (8, 4, 4) is a code of length n = 8, taking as input k = 4 useful information symbols, of minimum distance d _mjn = 4, and of output 1/2.

In European Patent EP 1 101 288, J.C. Carlach and C. Vervoux have presented a technique for constructing quasi-optimal codes, designated by the term "Cortex codes". Such codes are constructed using a plurality of coding stages, each implementing a plurality of simple basic coding modules, and patching stages between two coding stages. Such a technique makes it possible to construct auto-dual type-1 and tye-11 codes, according to the parity of the number of stages.

A disadvantage of such a technique is that it requires a large number of coding stages to obtain codes of great minimum distances d _min with respect to the length n of a code word.

In general, the minimum distance d _mjn is therefore not optimal for these lengths n and k, ie the minimum distance is not as close as possible to a terminal for which the code allows to detect the maximum number of errors (Hamming terminal or "Sphere-Packing Bound", such as d _min / n≤ 0.22 for an auto-dual code of k

yield - = 1/2) or the Gilbert-Varshamov bound (such as d _min / n "0.11 for a k

self-dual code of yield - = 1/2).

However, the greater the minimum distance d _mjn , the better the error correction code, since it makes it possible to detect (d _min - 1) erroneous symbols and to correct [(d _min - 1) / 2J (where the operator [.J denotes the integer part).

However, the current Cortex code decoders do not function optimally as soon as the number of coding stages used to construct the Cortex code exceeds a number of three coding stages. This is mainly due to the fact that the intermediate variables (internal state variables) between the coding stages are not transmitted and therefore do not have any likelihood values or prior probabilities with which to initialize them, especially when the implementation at decoding of a propagation probability algorithm (in English "Belief Propagation" or BP).

This difficulty in decoding Cortex codes built using more than three stages of coding makes the use of longer Cortex codes problematic, having to have more coding stages to achieve much greater minimum distances. However, a higher number of coding stages makes it possible to obtain codes offering significant practical error correction capabilities.

There is therefore a need for a new error-correcting coding technique, making it possible to generate codewords having large minimum distances, and which can be decoded simply.

3. Presentation of the invention

The invention proposes a new solution that does not have all of these disadvantages of the prior art, in the form of an error correction coding device, capable of implementing a global error correction code associating redundancy data to source data, the global correction code being capable of being represented by a generating matrix comprising, in its systematic form, an identity matrix and a matrix for passing the source data to the invertible redundancy data.

According to the invention, the coding device comprises:

two stages of first-level permutation, of which:

a first stage of first-level permutation connected, as input, on the one hand to input variables associated with a first set of source and / or redundancy data, and on the other hand to internal variables associated with input data and output data of a first level second-level coding stage, and

a second stage of first-level permutation connected, on the output, on the one hand to output variables associated with a second set of source and / or redundancy data, and on the other hand to internal variables associated with data. input and output data of a second second-level coding stage,

the first set and the second set forming a code word,

a first level coding stage connected firstly to the variables associated with the output data of the first level switching stage and secondly to the variables associated with the input data of the second level of first level permutation,

each coding stage comprising at least two basic coding modules each implementing a basic code that can be represented by a generator matrix comprising, in its systematic form, an identity matrix and an input data passage matrix to the invertible output data. In other words, according to the invention the coding device comprises:

a first level coding stage and

two stages of first-level permutation, of which:

a first level switching stage connected on one side to input variables associated with a first set of said source and / or redundancy data, and to internal variables associated with input data and data; outputting a second level coding stage, and on the other side to said first level coding stage,

a second first-level permutation stage connected on one side to output variables associated with a second set of said source and / or redundancy data, and to internal variables associated with input data and output data; a second level of second level coding, and on the other side to said first level coding stage,

said first set and said second set forming a code word, and each coding stage comprising at least two basic coding modules each implementing a basic code capable of being represented by a generating matrix comprising, in its systematic form , an identity matrix and an input data pass matrix to the invertible output data.

The invention thus proposes a new error-correcting coding device, the particular structure of which makes it possible to construct an efficient overall code with a large minimum distance, even if the number of coding stages is small (for example three coding stages). ).

As a result, the code words obtained by using a global code thus constructed can be decoded by using the current Cortex code decoders, based on efficient "Belief Propagation" iterative decoding, or a decoder according to the invention.

According to the invention, it is considered that the matrix of passage of the source data to the redundancy data is invertible. No other constraint is imposed on the error correction code, and in particular on the length of this code or the length of the cycles. It can therefore be considered that the error correction code implemented is quasi-random.

In particular, the proposed coder makes it possible to construct a global self-dual code with a large minimum distance regardless of the length of the code, and in particular for a rather short code (of the order of n <1000). The invention thus makes decoding easier and more efficient than the techniques of the prior art, in particular for codes having short lengths and / or short cycles.

To do this, at least three coding stages are considered, each comprising at least two basic coding modules operating independently, each basic coding module implementing a basic code. Only the first level coding stage is connected to input variables and output variables corresponding to the source data and the redundancy data after permutation. The other coding stages are connected only to internal variables, which are state variables, not transmitted to the decoder. The structure is therefore recursive and closed.

In particular, the basic codes belong to the group comprising:

a Hamming code;

an identity code;

a Golay code;

a simple repetition code;

For example, a base code is a Hamming code (8.4.4), or a code defined on a quaternary alphabet TL \, or a Golay code (24, 12, 8) ....

It is advantageous to choose a basic code having a large minimum distance. Thus, the basic codes have the property of implementing auto-dual codes. This self-duality property allows for optimal decoding with reduced decoding complexity.

It guarantees in particular a coding efficiency equal to 1/2.

According to one particular characteristic of the invention, the coding device comprises at least two stages of permutation of q-th level, with q an integer greater than or equal to 2, including: a first level of permutation of q-th level connected, as input, to internal variables associated with the input data and the output data of a first (q + 1) -th level coding stage, and, at the output, to internal variables associated with the input data and the output data of a first level q-th level coding stage;

a second stage of permutation of q-th level connected, at the input, to internal variables associated with the input data and the output data of a second stage of coding of q-th level and, at the output, with variables internal data associated with the input data and the output data of a second coding stage of (q + 1) -th level. According to an exemplary embodiment, each basic coding module of the i-th level coding stage (s) comprises c inputs and c outputs, and each permutation stage of i-th level This level implements a permutation of the c-cyclic type, with i and c being integers greater than or equal to 1. In particular, c is equal to 4.

A permutation of c-cyclic type is a permutation according to which the same permutation pattern is applied for each block of length c.

In particular, such block cyclic permutations are easy to implement. The use of c-cyclic permutations makes it possible in particular to minimize the number of memory access operations (read / write), and to avoid memory access conflict problems.

For example, such a permutation of c-cyclic type is written in the form:

with, for conditions, that D = {Δο, Δ- ^ ..., Δ ^ _! ) a set of integer parameters such as:

the parameters (Δ ₀ , A ₁ ..., A _{C - 1} ) must take at least three different values, or if the parameters (at ₀ , A ₁ ..., Δ _ε _ ₁ ) take only two values different, then each of the two values is at least twice in the set.

According to another exemplary embodiment, each i-th level permutation stage implements an affine permutation, with i an integer greater than or equal to 1.

According to a specific aspect of the invention, the i-th level coding stage (s) each comprise at least two local permutation modules, each local permutation module permutating the internal variables obtained at the output of a basic coding module .

Such local permutations make it possible in particular to obtain basic code words having good minimum distances.

According to a particular characteristic, the coding device has a symmetrical structure.

Thus, the two levels of q-th level coding are located on either side of the first level coding stage (q≥2), and include the same number of inputs and outputs.

In the same way, the two (ql) -th level permutation stages, each inserted between one of the (ql) -th level coding stages and one of the q-th level coding stages, are symmetrical. For example, if π _{0 is} the permutation inserted between the first second level coding stage and the first level coding stage, then the inserted permutation between the second second level coding stage and the first level coding stage, denoted π-L, will be such that π ₁ = π ₀ ^_1 .

In particular, a symmetry between the source data and the redundancy data makes it possible to design "Belief-Propagation" type algorithms faster to converge, because working on pairs (χ _{ί (} ) for i = 0.1, .. ., k- 1.

According to a particular characteristic of the invention, the number of internal variables is twice the number of variables associated with the source data.

According to a particular embodiment, all basic coding modules implement an identical basic code.

Thus, the coding device according to the invention is simplified by the use of basic coding modules implementing identical basic codes.

According to a particular aspect of the invention, the device comprises a zero forcing module, setting to zero at least one of the source data and / or at least one of the redundancy data.

This "forcing" to zero of certain data makes it possible in particular to obtain, in a very flexible manner, yield codes different from ½ and whose minimum distances remain good, even when the yield tends to 1. Similarly, it is possible to construct quasi-optimal codes with yields tending toward zero. Indeed, the data forced to zero at the time of the coding represent on the reception of the information null perfect non-noisy.

It is also possible to obtain a yield different from ½ by using a non-symmetrical structure.

In particular, the set of coding and permutation stages form a Tanner graph whose inputs are the input variables associated with the first set of source and / or redundancy data, and the outputs are the associated output variables. the second set of source and / or redundancy data.

For example, the two coding stages of (q + 1) -th level and the two stages of permutation of q-th level are symmetrical to each other with respect to the middle axis of the Tanner graph.

In another embodiment, the invention relates to an error correction coding method, capable of implementing a global error correction code associating redundancy data with source data, the global correction code being capable of be represented by a generator matrix comprising, in its systematic form, an identity matrix and a matrix for passing the source data to the invertible redundancy data.

According to the invention, such a coding method implements:

two steps of first-level permutation, including: a first step of first-level permutation receiving, on the input side, on the one hand a first set of source and / or redundancy data, and on the other hand input data and output data obtained from a first step of second level coding, and

a second step of first-level permutation outputting on the one hand a second set of source and / or redundancy data, and on the other hand input data and output data obtained from a second level of second level coding,

the first set and the second set forming a code word, and

a first level encoding step receiving the output data of the first first level permutation step and outputting input data to the second first level permutation step,

each coding step implementing at least two basic coding modules each implementing a basic code that can be represented by a generating matrix comprising, in its systematic form, an identity matrix and a data transmission matrix; input to the invertible output data.

Such a method may in particular be implemented by an error correction coding device as described above. This method may of course include the various characteristics relating to the coding device according to the invention, which can be combined or taken in isolation. Thus, the features and advantages of this method are the same as those of the coding device, and are not detailed further.

In particular, each step advantageously corresponds to a stage of the structure of the corresponding coding device, and can be implemented in the form of an integrated circuit, or in an electronic component of the microprocessor type. This structure allows an easier understanding of the invention. However, the method of the invention can be implemented in any other suitable form, and especially in essentially software form, one or more processors performing the corresponding processing.

The invention also relates to an error correction decoding device, able to retrieve source data from a received code word, the source data having been coded by a global error correction code associating redundancy data. to the source data, the global correction code being capable of being represented by a generating matrix comprising, in its systematic form, an identity matrix and a matrix for passing the source data to the invertible redundancy data.

According to the invention, such a decoding device comprises:

two stages of first-level permutation, of which: a first stage of first-level permutation connected, as input, on the one hand to input variables associated with a first set of source and / or redundancy data, and on the other hand to internal variables associated with input data and output data of a second level decoding first stage, and

a second stage of first-level permutation connected, on the output, on the one hand to output variables associated with a second set of source and / or redundancy data, and on the other hand to internal variables associated with data. input and output data of a second second level decoding stage,

the first set and the second set forming the code word, and

a first-level decoding stage connected firstly to the variables associated with the output data of the first first-level permutation stage and secondly to the variables associated with the input data of the second-level first-level permutation stage,

each decoding stage comprising at least two basic decoding modules each implementing a basic code that may be represented by a generating matrix comprising, in its systematic form, an identity matrix and an input data passage matrix to the invertible output data.

Such a decoding device has a similar structure to that of the coding device described above. It therefore has the same characteristics as the coding device according to the invention, which can be combined or taken in isolation.

In particular, such a device can be used to decode code words obtained from the coding device described above.

In another embodiment, the invention relates to an error correction decoding method capable of retrieving source data from a received code word, the source data having been coded by a global error correction code. associating redundancy data with the source data, the global correction code being capable of being represented by a generating matrix comprising, in its systematic form, an identity matrix and a matrix for passing the source data to the invertible redundancy data.

According to the invention, such a decoding method implements:

two steps of first-level permutation, including:

a first step of first-level permutation receiving, as input, on the one hand a first set of source and / or redundancy data, and on the other hand part of the input data and output data obtained from a first second level decoding step, and

a second step of first-level permutation outputting on the one hand a second set of source and / or redundancy data, and on the other hand input data and output data obtained from a second level of second level decoding,

the first set and the second set forming the code word, and

a first level decoding step receiving the output data of the first first level permutation step and outputting input data to the second first level permutation step,

each decoding step implementing at least two basic decoding modules, each implementing a basic code that can be represented by a generating matrix comprising, in its systematic form, an identity matrix and a data transmission matrix; input to the invertible output data.

Such a method may in particular be implemented by an error correction decoding device as described above. This method may of course include the various features relating to the error correction decoding device according to the invention, which can be combined or taken separately. Thus, the features and advantages of this method are the same as those of the error correction decoding device, and are not detailed further.

In particular, each step advantageously corresponds to a stage of the structure of the corresponding decoding device; and can be implemented as an integrated circuit, or in an electronic component of the microprocessor type. This structure allows an easier understanding of the invention. However, the method of the invention can be implemented in any other suitable form, and especially in essentially software form, one or more processors performing the corresponding processing.

Thus, the invention also relates to one or more computer programs comprising instructions for implementing an encoding method and / or a decoding method when the program or programs are executed by a processor. Such programs can be stored on a storage medium.

Finally, the invention relates to a device capable of implementing the corresponding coding and decoding operations.

4. List of figures

Other characteristics and advantages of the invention will appear more clearly on reading the following description of a particular embodiment, given as a simple illustrative and nonlimiting example, and appended drawings, among which:

Figure 1 shows the main steps implemented by a coding method according to one embodiment of the invention;

FIG. 2 illustrates the structure of an encoder and / or decoder with three stages of (de) coding according to one embodiment of the invention;

FIG. 3 presents the main steps implemented by a decoding method according to one embodiment of the invention;

FIG. 4 illustrates the structure of an encoder and / or decoder with seven stages of (de) coding according to one embodiment of the invention;

FIGS. 5A and 5B show an example of construction and use of the Golay code (24, 12, 8) according to one embodiment of the invention;

FIGS. 6A and 6B show an example of construction and use of a type II auto-dual code (72,36,12) according to one embodiment of the invention.

5. Description of an embodiment of the invention

5.1 General principle

The general principle of the invention is based on a particular structure of an error correction code, based on an alternation of coding stages and permutation stages.

In particular, the proposed coding structure makes it possible to construct auto-dual error correcting codes with only three coding stages and a minimum number of "hidden" (ie non-transmitted) internal variables, also called intermediate or variable variables. state, and having great minimum distances. In particular, it provides a practical solution to best protect small packets of information (n <1000 bits) from the noise and interference inherent in any transmission channel. It also simplifies decoding, because of the small number of coding stages used.

In particular, it is recalled that among the coding techniques allowing the correction of transmission errors, turbo codes and LDPC codes (in English "Low-Density Parity Check") have very good performances in terms of correction of errors. errors for codes of great length n, with n of the order of a few thousand bits at least (n> 1000). In contrast, turbo codes and LDPC codes have lower performance for shorter codes.

The proposed solution makes it possible to obtain efficient codes that are quite short (/ i <1000), having a large minimum distance, where for example d _min is a fraction of n, and therefore makes it possible to compete with these turbo-codes and these codes. LDPC.

In relation to FIG. 1, the main steps implemented by an error correction coding method according to the invention are presented. Such a method is particularly suitable for implementing a global self-dual error correction code, that is to say capable of being represented by a generating matrix comprising, in its systematic form, an identity matrix and a matrix from the source data (X) to the invertible redundancy data ().

As illustrated in FIG. 1, the coding method implements:

a first level coding step 11, denoted by C _N1 , for example receiving input data X after permutations, and for example outputting redundancy data R after permutations. Such a first-level coding step implements at least two basic coding modules, connected on the one hand to all the variables associated with the source data and the redundancy data, and on the other hand to internal variables;

a first 121 and a second 122 second level coding steps, denoted respectively C _N2j1 and C _N2,2 , each implementing at least two basic coding modules connected only to the internal variables of the first level coding step 11 C _N1 after permutations;

a first 131 and a second 132 first level permutation steps, denoted respectively π ₀ and π. The first permutation step 131 π ₀ is implemented between the first level coding step 11 C _m and the first second level coding step 121 C _N2 , i, and therefore receives, as input, on the one hand the source data X and on the other hand the input data and output data obtained from the first second level coding step 121 C _N2j i. The second permutation step 132 π ₁ is implemented between the first-level coding step 11 C _m and the second second-level coding step 122 C _{N2 2} and therefore outputs, on the one hand, the data R redundancy and on the other hand input data and output data to the second second level coding step 122 C _{N2 2} .

In particular, it should be noted that each basic coding module implements an auto-dual basic code, which can be represented by a generating matrix comprising, in its systematic form, an identity matrix and a data transmission matrix. input to the invertible output data.

We consider here a general definition of duality, also called iso-duality, as expressed in particular in the document "Handbook of coding theory", V.S. Pless and W.C.

Huffman - Volume I - Chapter 3 - pages 177 and 199. This definition imposes the only constraint on the invertibility of the matrix of passage of the input data to the output data.

FIG. 2 more specifically illustrates the structure of a corresponding coding device, in the form of a Tanner graph comprising three coding stages, said "Cortex-Compact".

Such a device receives as input source data X, organized for example in blocks of m bits. The first source data block comprises, for example, the information bits x ₀ to x _m -i, the second block the information bits x _m to a¾m-i _> ··· _< the (k + 1) th block the information bits x _k - _m to χ¾_ι, with k a multiple of m. Such a device outputs redundancy data, also organized in blocks of m bits. The first redundancy data block comprises, for example, the redundancy bits r ₀ to r _m _, the second block the redundancy bits r _m to r _2m _i, the (k + 1) th block the redundancy bits r _k _ _m to r _k _ _lt with k a multiple of m.

It should be noted that according to the example illustrated in FIG. 2, the source data are associated with input variables and placed to the left of the Tanner graph representative of the coding device, and the redundancy data are associated with output variables and are placed to the right of the Tanner graph. This is only a choice of representation, and some of the redundancy data (or even all the redundancy data) could be placed to the left of the Tanner graph, and therefore associated with input variables. of the Tanner graph. Similarly, the number of information bits k is not necessarily equal to the number of redundancy bits (n-k).

Such a coding device comprises at least:

a first level coding stage 21 comprising at least two basic coding modules Cb, connected on the one hand to all the variables associated with the source data x _t and to the redundancy data, for / ^' ranging from 0 to k-1 and on the other hand internal variables dj and fj, for example for j ranging from 0 to 2k-1, via a first 231 or a second 232 first level permutation stage;

a first 221 and a second 222 second level coding stages, each connected to the first level coding stage 21 respectively via the first 231 or second 232 first level permutation stage.

Each second level coding stage comprises at least two basic coding modules Cb, connected only to the internal variables of the first level coding stage 21, via a first 231 or a second 232 stage. first level permutation.

The only variables that can be accessed are the input and output variables of the Tanner graph, which are associated with source and / or redundancy data. Other internal variables are not transmitted to the decoder.

According to the illustrated example, each basic coding module implements the same basic code noted Cb. Of course, the basic coding modules can implement different basic codes, within the same coding device. Indeed, the different coding modules are independent. Preferably, the number of inputs (respectively the number of outputs) of each basic coding module is identical.

For example, we consider that m = 4 and that each basic coding module implements a Hamming code (8, 4, 4). Such a code is optimal for its length n = 8 and its dimension k = 4 with a minimum distance d _min = 4. This basic Hamming code (8.4.4) is auto-dual and has all its code words. of multiple weights of 4. It is therefore said by definition auto-dual type-II.

According to another example, it is considered that m = 1 and that each basic coding module implements a simple repetition code, a code word of which is obtained from a repetition of a source data item. For example, the redundancy bit r ₀ = x ₀ is obtained from the source bit x ₀ . This base code is auto-dual of type-l.

According to other examples, the basic coding modules implement Golay codes (like the code (24, 12, 8), with m = 12), codes defined on quaternary alphabets Z4, identity codes, simple repetition codes, etc.

Returning to FIG. 2, and considering that each basic coding module implements a Hamming code (8, 4, 4), the first first level permutation stage 231, implementing a permutation π ₀ , receives, on the one hand, bits of information in packets of four bits, noted for example x ₀ _ ₃ for the packet of information bits x _Q , x, x ₂ , x ^), on the other hand internal variables input and output of coding modules of the second level coding second stage 221, also in packets of four bits.

Thus, each basic coding module Cb of the first second-level coding stage 221 is connected to four internal variables, denoted e.g. d ₀ _ ₃ for the packet (d _0, d _1, d _2, d _3). These four internal variables are transformed linearly, modulo 2, into four image variables, noted for example f ₀ _ ₃ for the packet (ο _< Λ _< 2 _< 3) <according to the basic code of Hamming (8, 4, 4) , as :

where P is the matrix of passage of the input data d ₀ _ ₃ to the output data ₀ _ ₃ corresponding to the dimension identity matrix 4, inverted modulo 2:

0 1 1 1

P = 1 0 1 1

1 1 0 1

1 1 1 0

It is noted that the outputs of each basic coding module of the different coding stages can be switched locally to obtain "local" codes with a good minimum distance d _min . For example, it is possible to swap the four bits ₀ _ ₃ to obtain a code "Local" of great minimum distance. We note that there are 14 = 24 possible permutations for a vector of four bits.

The first first-level permutation stage 231 is connected to the input variables corresponding to k to k information bits (χ ₀ _ ^ _ ^) and 2k internal variables (do- _(f _ei) o- _(f latter ₎₎ - These variables 3k, after permutation, are connected to the first level of coding stage 21.

The first level coding stage 21 implements 3k / 4 basic Hamming coding modules (8,4,4), delivering k redundancy bits (r ₀ _ _(fe _ ₁ - ₎ ) and 2k variables. internal

If we consider a symmetrical structure, the second first level permutation stage 232 receives these 3k variables, implements a permutation π ₁ = π ₀ ^_1 and delivers, on the one hand, four-bit packet redundancy bits, for example noted r ₀ _ ₃ for the redundancy bit packet _Q , r, r ₂ , r ^), on the other hand input and output internal variables of the coding modules of the second second level coding stage 222, also in packets of four bits.

It is noted that it is possible to find very good global correcting codes by keeping the mirror symmetry constraint between the source data and the redundancy data on this structure, with respect to the middle axis of the Tanner graph. Such symmetry allows a folding with respect to this axis and therefore a decoding by pairs of symmetrical variables. The consequence is the possibility of designing efficient probabilistic propagation algorithms (BP) that are faster to converge because they work on pairs (X _j , r _j ) for i = 0, 1,. . . , k - 1.

Thus, if the number of information bits is equal to k as shown in the example above, then the total length of the global code is n = 2k and the size of the permutations π ₀ and π ₁ is equal to l = 3k for a Hamming base code (8.4.4) per packet of 4 information bits, which also makes 2k internal variables dj, ie a bit associated with an internal variable per code bit.

It should be noted that such a symmetrical structure is however not mandatory. In particular, it is possible to define an asymmetrical structure by using unsymmetrical permutations in the first and second stages of permutation of i-th level (ie π ₁ ≠ π ₀ ^_1 ), a number of different coding modules in the first and second level of i-th level coding, and / or coding modules implementing different basic codes in the first and second levels of i-th level coding, for i≥ 1. It is also possible to generalize the structure by taking a larger number of internal variables, and thus basic coding modules, at the level of the q-th level coding stages, with q≥2.

FIG. 3 thus illustrates an example of a coding device implementing:

a first level coding stage 31, comprising basic coding modules B0, B1, etc .;

two stages of first level switching 321, 322, on either side of the first level coding stage 31;

two second level coding stages 331, 332, on either side of the first level set formed by the first level coding stage 31 and the two first level permutation stages 321, 322, one of which first stage comprising basic coding modules A0, A1, etc., and a second stage comprising basic coding modules CO, C1, etc .;

two levels of second level permutation 341, 342, on either side of the set formed by the first level set and the two second level coding stages

331, 332;

two third level coding stages 351, 352 on either side of the second level set formed by the first level set, the two second level coding stages 331, 332, and the two permutation stages second level stage 341, 342, including a first stage comprising basic coding modules DO, D1, etc., and a second stage comprising basic coding modules E0, E1, etc .;

two third-level permutation stages 361, 362, on either side of the set formed by the second-level set and the two third-level coding stages 351, 352;

two levels of fourth level coding 371, 372 on either side of the third level set formed by the second level set, the two third level coding stages 351, 352, and the two stages of third level permutation 361, 362.

It should be noted, however, that such an increase in the number of internal variables makes the structure more complex and renders it less possible to perform iterative decoding by propagation of probabilities.

It will also be noted, referring to FIG. 2, that since the basic coding modules of the first level coding stage 21 each implement a Hamming code (8, 4, 4) of all-multiples weight of 4, the equivalent code of the first level coding stage 21 is of weight multiple of 4. By subtraction, the set of internal variables d _Q ₂ k ^and o 2¾ also forming a weight code multiple of 4, each code word formed by the bits of information χ ₀ _ ^ _ ^ and the redundancy bits r ₀ _ ( _fe _ ₁ - ₎ is of multiple weight of 4 and therefore the overall code obtained, called Cortex-Compact, is also auto-dual type-I l.

Finally, we note that the existence of a global code is ensured only if we can solve the system of equations linking all the variables together, through the basic codes. Equivalently, this means that it is possible to determine a generator matrix of the global code whose determinant is non-zero (for example equal to 1 (modulo 2) in the binary case), or that the generator matrix comprises, under its systematic form, an identity matrix, and a matrix for passing source data to invertible redundancy data.

From the structure illustrated in Figure 2, it is thus possible to determine a system of equations. Indeed, such a Tanner graph comprises input variables, corresponding for example to the information bits, and output variables, corresponding for example to the redundancy bits, the redundancy bits being linked to the information bits by through constraints and permutations.

These constraints can be of two types:

the constraints of the equality type, corresponding to a repetition of the variable connected to this constraint;

the modulo 2 addition type constraints, corresponding to a "or exclusive" type logic constraint.

These constraints and permutations make it possible to define algebraic relations, and to compute a generator matrix making it possible to perform the coding. In particular, the calculation of the redundancy data must be done by the pre-calculation of the transition matrix, which can be constructed from the system of equations.

Thus, an encoder according to the invention takes input source data X, in the form of packets or a continuous stream, and outputs at least one code word, comprising the source data X and redundancy data. These code words can be conveyed in a transmission channel or stored on a medium, and then decoded by a decoder according to the invention.

In particular, such a decoder can also use a Tanner graph as illustrated in FIG. 2, to correct erase-type errors in particular.

For example, as illustrated in FIG. 4, the decoder receives as input at least one codeword, comprising the source data X and redundancy data R possibly corrupted with error, and delivers an estimate of the source data X.

Such a decoding method implements, symmetrically to the coding: a first-level decoding step 41, denoted DC _N1 , receiving as input a code word formed of source data X and / or redundancy, after permutations, and outputting an estimate of the source data X, after permutations. Such a first-level decoding step implements at least two basic decoding modules, connected on the one hand to all the variables associated with the source data and the redundancy data of the codeword, and on the other hand to internal variables;

a first 421 and a second 422 second level decoding steps, respectively denoted DC _{N2 1} and DC _{N2 2} , each implementing at least two basic decoding modules connected only to the internal variables of the first decoding step 41 DC level _N1 , after permutations;

a first 431 and a second 432 first level permutation steps, denoted respectively π ₀ and π. The first permutation step 431 π ₀ is implemented between the first level decoding step 41 DC _N i and the second second level decoding step 421 DC _N2 , i, and thus receives, as input, a part of the code word formed by the source data X and / or redundancy R and, secondly, the input data and output data obtained from the first second level decoding step 421 DC _N2j i. The second permutation step 432 π ₁ is implemented between the first level decoding step 41 DC _N i and the second second level decoding step 422 DC _{N2 2} and therefore outputs, on the one hand, a estimating the source data and secondly input data and output data at the second second level decoding step 422 DC _{N2 2} .

In particular, it should be noted that each decoding module implements an auto-dual basic code, which can be represented by a generating matrix comprising, in its systematic form, an identity matrix and an input data passage matrix. to the invertible output data.

The operation of this decoder is similar to that of the encoder described above. It is therefore not explained in more detail. In particular, the decoding can be implemented using a "Belief Propagation" type algorithm, according to which the received data are those of the received code word c = (x, r), possibly noisy, in the form of a vector probabilities or metrics (for example log likelihood ratio or LLR: Log (~~)) · The values of this vector associated with the input and output variables of the Tanner graph are propagated between the nodes of the graph , which are the basic codes of the structure.

5.2 Construction and implementation of the Golay code (24, 12, 8) The construction and use of a Golay code (24, 12, 8) in Cortex-Compact form according to the invention is now presented in relation to FIGS. 5A and 5B.

The Tanner graph representative of the coding device illustrated in FIG. 5A comprises: a first level coding stage 51, comprising nine basic coding modules denoted B0 to B8;

a first level second coding stage 521, comprising three basic coding modules denoted AO to A2;

a second second level coding stage 522, comprising three basic coding modules denoted C0 to C2;

a first stage of first level permutation 531;

a second stage of first level permutation 532.

Each basic coding module implements a Hamming code (8.4.4), followed by a local permutation taking, for example, a four-bit packet at the index positions {0,1,2,3 ), and outputting these same bits at index positions {0,2,1,3) respectively. It should be noted that another local permutation could be implemented, such as the local permutation taking a four-bit packet at the index positions {0,1,2,3), and outputting these same bits to the positions of index {0,3,1,2) respectively.

Moreover, the twelve bits of information (source), denoted x ₀ to x _llt, are associated with input variables of the Tanner graph, and the twelve redundancy bits, denoted r ₀ to r _1, are associated with variables output of the Tanner graph.

The information bits are in four-bit packets on the first level first permutation stage 531. The first level first permutation stage 531 is therefore connected to input variables associated with a first set of source data and redundancy, here the information bits x ₀ to x _l . The first level first permutation stage 531 is also connected, at the input, to the inputs and outputs of the first second level coding stage 521. More specifically, each of the three basic coding modules AO, A1, A2 of the first stage second level coding 521 receives as input a packet of four bits, respectively denoted d ₀ to d ₃ , d ₄ to d ₇ , and d ₈ to d _11t and outputs a packet of four bits, respectively denoted f ₀ to f ₃ , f ₄ to f ₇ , and f ₈ to / ₁₁ according to the Hamming base code (8, 4, 4). Each packet of four bits f ₀ to f _3, f ₄ f _7, f ₈ and f _llt undergoes local permutation {0,1,2,3) → {0,2,1,3) as shown in Figure 5A. The first level first permutation stage 531 is thus connected, as input, to the 12 information bits x ₀ to x ₁ and to 24 internal bits d ₀ to d ₁ and f ₀ to f ₁ associated with internal variables. According to this example, there is therefore a basic coding module for each four-bit packet associated with input variables. The first first-level permutation stage 531 implements of 4-cyclic permutation of length l = 36, such that, by selecting / ^'the position of an input bit ₀ and π (ί) the position of that bit at the exit, we have:

i≡ 0 (mod 4): π ₀ (ί) = i- 2 (mod l)

i≡ 1 (mod 4): π ₀ (ί) = i- 2 (mod l)

i≡ 2 (mod 4): π ₀ (ί) = i + 2 (mod l)

i≡ 3 (mod 4): π ₀ (ί) = i + 2 (mod l)

As a variant, other permutations could be implemented, such as affine permutations associating a bit / input symbol with the position i, with the same bit / symbol at the position a * i + b, with a prime number with the length (or order) 1 of the permutation implemented by the first or second stage of first level permutation, and b an integer such that b <a.

As a result, the first level first permutation stage 531 outputs the 12 information bits x ₀ to x ₁ and the 24 internal bits d ₀ to d ₁ and f ₀ to f _{1 are} exchanged at the first coding stage. level.

More specifically, each basic coding module of the first level coding stage 531 receives two information bits, and two input or output bits of a basic coding module of the first coding second stage. level 521, through the first level first permutation stage 531.

For example, the first basic coding module B0 receives the input bits d ₀ and d _lt and the output bits f ₉ and f _11t the second basic coding module B1 receives the output bits f ₀ and f ₂ , and the information bits x ₂ and x ₃ , the third basic coding module B2 receives the input bits d ₂ and d ₃ and the information bits x ₄ and x ₅ , the fourth coding module of base B3 receives the output bits f _x and f ₃ , and the input bits d ₄ and d ₅ , the fifth basic coding module B4 receives the output bits f ₄ and f ₆ , and the information bits x ₆ and x ₇ , the sixth basic coding module B5 receives the input bits d ₆ and d ₇ , and the information bits x ₈ and x ₉ , the seventh basic coding module B 6 receives the bits of output f ₅ and f ₇ , and the input bits d ₈ and d ₉ , the eighth base coding module B7 receives the information bits x ₁₀ and x _11t the the output bits f ₈ and f _w , and the ninth basic coding module B8 receives the information bits x ₀ and x _lt and the input bits d ₁₀ and d ₁ .

Each basic coding module of the first level coding stage 51 receives as input a four bit packet and outputs a four bit packet in accordance with the Hamming base code (8.4.4). The bits at the output of the coding module undergo a local permutation, in a local permutation module not illustrated, according to the permutation {0,1,2,3} → {0,2,1,3}. The outputs of the first level coding stage 51 are connected to the first level first permutation stage 532. This second level of first level permutation 532 implements a permutation π _{1 that is the} inverse of the permutation implemented by the first level. first level permutation stage 531, such that π ₁ = π ₀ ^_1 . This second top-level permutation stage 532 is connected, at the output, on the one hand to output variables associated with a second set of source data and redundancy, here the redundancy bits r ₀ to r _llt and other at the inputs and outputs of the second second level coding stage 522. More specifically, each of the three basic coding modules CO, C1, C2 of the second second level coding stage 522 receives as input a four bit packet, denoted respectively d ₁₂ to d ₁₅ , d ₁₆ to d ₁₉ , and d ₂₀ to d ₂₃ , and outputs a packet of four bits, denoted respectively f ₁₂ to f ₁₅ , f ₁₆ to f ₁₉ , and f ₂₀ to f ₂₃ , according to the basic code of Hamming (8,4,4). Each four-bit packet f ₁₂ to f _15, f ₁₆ to f ₁₉ and f ₂₀ to f ₂₃ undergoes local permutation {0,1,2,3) → {0,2,1,3). The first level first permutation stage 532 is thus connected, at the output, to the 12 redundancy bits r ₀ to r ₁ and to 24 internal bits d ₁₂ to d ₂₃ and f ₁₂ to f ₂₃ associated with internal variables.

In particular, if we consider the basic coding module B8 for example, the internal variables associated with the bits d ₁₀ , d ₁₁ d ₂₂ and d ₂₃ are linked by constraints to the information bits x ₀ and x ₁ and the redundancy bits r ₀ and r _lt and therefore have information on the channel, which promotes decoding.

From such a Tanner graph, it is possible to write a system of equations taking into account the constraints that the bits of information and redundancy of a word must respect to be a word of the global code.

In particular, it is recalled that a global code can be represented by such a structure if the pre-calculation of the generator matrix determinant obtained from the system of equations combining all the Boolean equations of the structure is non-zero.

Thus, from the Tanner graph illustrated in FIG. 5A, it is possible to write and solve a system of 60 equations (4 equations obtained from each basic coding module), in which the unknowns are the associated data. to internal variables and redundancy data

For example, the equations obtained from the basic encoding module AO of the first level of second level coding are such that: d ₁ + d ₂ + d ₃ + f ₀ = 0, d ₀ + d ₂ + d ₃ + f ₂ = 0, d ₀ + d ₁ + d ₃ + f = 0 and d ₀ + d ₁ + d ₂ + f ₃ = 0. The equations obtained from the basic coding module BO of the coding stage first level are such that: f ₉ + n + f ₂₁ + x ₃ = 0, f ₉ + n + f ₂₃ + x ₂ = 0, d ₁₂ + f ₁₁ + x ₂ + x ₃ = 0 and d ₁₃ + f ₉ + x ₂ + x ₃ = 0. The equations obtained from the basic coding module CO of the second stage of second-level coding are such that: d _lt + d ₁₃ + d ₁₅ + f ₁₂ = 0, d _lt + d ₁₂ + d ₁₅ + f ₁₄ = 0, d ₁₂ + d ₁₃ + d ₁₅ + f ₁₃ = 0 and d _l + d ₁₂ + d ₁₃ + f ₁₅ = 0.

It is thus possible to "pre-calculate" a passage matrix making it possible to determine the redundancy bits from the information bits (also called "transfer matrix").

During the construction of the code, for example, the basic code that one wishes to use in the basic coding modules is defined, which makes it possible to define the number of internal variables. Note that the higher the number of internal variables, the more powerful the overall code obtained. By adding to these internal variables the number of input variables associated with source data, the number of entries of the first-level coding stage is obtained. It is thus possible to define the number of basic coding modules to be used in the first level coding stage.

The generator matrix of the Golay code obtained from the graph of FIG. 5A, composed of an identity matrix and of the matrix for moving from the source data to the redundancy data, is illustrated in FIG. 5B, where the white circles correspond to 0. and the black circles correspond to 1.

5.3 Construction and implementation of an auto-dual code (72, 36, 12)

The construction and use of an auto-dual code (72, 36, 12) of type-II in the Cortex-Compact form according to the invention is now presented in relation with FIGS. 6A and 6B.

The Tanner graph representative of the coding device illustrated in FIG. 6A comprises: a first level coding stage 61, comprising 27 basic coding modules denoted BO to B26;

a first second level coding stage 621, comprising 9 basic coding modules denoted A0 to A8;

a second second-level coding stage 622, comprising 9 basic coding modules denoted CO to C8;

a first level permutation first stage 631;

a second stage of first level permutation 632.

According to the illustrated example, each basic coding module implements a Hamming code (8.4.4), followed by:

for the basic coding modules of the first second level coding stage 621, no local permutation (or a local permutation identity ({0,1,2,3) → {0,1,2,3}),

for the basic coding modules of the first level coding stage 61, a local permutation taking as input a four bit packet at the index positions {0,1,2,3), and outputting these same bits at positions of index {0,1,3,2) respectively ({0,1,2,3) → {0,1,3, 2)),

for the basic coding modules of the second second-level coding stage 622, a local permutation taking a four-bit packet at the index positions {0,1,2,3), and outputting these same bits at index positions {0,2,1,3) respectively ({0,1,2,3) → {0,2,1,3)).

According to a second example, not illustrated, each basic coding module implements a Hamming code (8.4.4), followed by a local permutation taking as input a four-bit packet at the index positions {0 , 1,2,3), and outputting these same bits at index positions {3,0,2,1) respectively.

Moreover, the 36 information bits (source), denoted x ₀ to x ₃₅ , are associated with input variables of the Tanner graph, and the 36 redundancy bits, denoted r ₀ to r ₃₅ are associated with output variables of the Tanner graph.

The information bits are in four-bit packets on the first-level first-pass 631 stage. The first-level first-pass 631 stage is also connected, as input, to the inputs and outputs of the first-second coding stage. Level 621. The first level first permutation stage 631 is thus connected, as input, to the 36 information bits and to the internal 72 bits.

According to the illustrated example, the first first-level permutation stage 631 implements a 4-cyclic permutation, such that, by noting / ^' the position of a bit at the input and π ₀ (ί) the position of this same bit. output bit:

(π ₀ (ί) = 5 + i (mod 108) if i≡ 0 (mod 4)

7T ₀ (j) = -18 + i (mod 108) if i≡ l (mod 4)

π ₀ (ί) = 18 + i (mod 108) if i≡ 2 (mod 4)

7T ₀ (j) = -5 + i (mod 108) if i≡ 3 (mod 4)

The bits obtained after permutations are delivered to the first level coding stage

61.

According to the second example, not illustrated, the first level of first level permutation 631 implements an affine permutation of length l = 108, such that, by noting / ^' the position of an input bit and π ₀ (ί) the position of this same bit at the output, ₀ (i) = 7i (mod 108), and delivers the permutated bits to the first level coding stage 61.

In the illustrated example, each basic coding module of the first-level coding stage 61 receives a four-bit packet as input and outputs a four-bit packet in accordance with the basic Hamming code (8.4 , 4), after local permutation {0,1,2,3) → {0,1,3,2). The outputs of the first level coding stage 61 are connected to the second first level permutation stage 632. This second first level permutation stage 632 implements a permutation π _{1 that is the} inverse of the permutation implemented by the first level 632. first level permutation stage 631, such that π ₁ = π ₀ ^_1 . This second top-level permutation stage 532 is connected, at the output, on the one hand the redundancy bits r ₀ to r _35, and secondly to the inputs and outputs of the second level second coding stage 622.

Thus, from the Tanner graph illustrated in FIG. 6A, it is possible to write and solve a system of 180 equations (4 equations per basic coding module).

The generator matrix of the type-11 auto-dual code (72,36,12) obtained from the graph of FIG. 6A, composed of an identity matrix and the matrix for passing from the source data to the redundancy data, is illustrated in FIG. 6B, where the white circles correspond to 0 and the black circles correspond to 1.

Claims

An error correction coding device capable of implementing a global error correction code associating redundancy data with source data,

said global correction code being capable of being represented by a generating matrix comprising, in its systematic form, an identity matrix and a matrix for passing said source data to said invertible redundancy data,

characterized in that said coding device comprises:

two stages of first-level permutation, of which:

a first level switching stage (231; 321; 531; 631) connected, as input, firstly to input variables associated with a first set of said source and / or redundancy data; and on the other hand to internal variables associated with input data and output data of a first second level coding stage (221; 331; 521; 621), and o a second first level permutation stage (232). ; 322; 532; 632) connected, on the output, on the one hand to output variables associated with a second set of said source and / or redundancy data, and on the other hand to internal variables associated with data of inputting and outputting data of a second second-level coding stage (222; 332; 522; 622), said first set and said second set forming a code word, and a first-level coding stage (21; 31; 51; 61) connected on the one hand to the variables associated with the data of e output of said first first level permutation stage and secondly variables associated with the input data of said second first level permutation stage,

each coding stage comprising at least two basic coding modules each implementing a basic code that can be represented by a generator matrix comprising, in its systematic form, an identity matrix and an input data passage matrix to the invertible output data.

2. An error correcting coding device according to claim 1, characterized in that it comprises at least two permutation stages of q-th level, with q an integer greater than or equal to 2, of which:

a first q-th level permutation stage (341, 361) connected, as input, to internal variables associated with the input data and the output data of a first coding stage of (q + 1) - th level (351, 371), and, at output, internal variables associated with the input data and the output data of a first level q-th level coding stage (331, 351); a second connected level switching level (342, 362) to internal variables associated with the input data and the output data of a second q-th level coding stage (332, 352) and, at the output, to internal variables associated with the input data and the output data of a second (q + 1) -th level coding stage (352, 372).

An error correcting coding device according to any of claims 1 and 2, characterized in that each basic coding module of said one or more level coding stages comprises c inputs and outputs, and that each stage of permutation of i-th level implements a permutation of the type c-cyclic, with / ^' and c of integers higher or equal to 1.

4. An error correcting coding device according to any one of claims 1 and 2, characterized in that each i-th level permutation stage implements an affine permutation, with i an integer greater than or equal to 1.

5. An error correcting coding device according to any one of claims 1 to 4, characterized in that the at least one i-th level coding stage each comprise at least two local permutation modules, each local permutation module. permuting the internal variables obtained at the output of a basic coding module, with i an integer greater than or equal to 1.

6. Error correcting coding device according to any one of claims 1 to 5, characterized in that said device has a symmetrical structure.

7. Error-correcting coding device according to any one of claims 1 to 6, characterized in that the number of internal variables is twice the number of variables associated with the source data.

8. An error correcting coding device according to any one of claims 1 to 7, characterized in that said basic codes belong to the group comprising:

a Hamming code;

an identity code;

a Golay code;

a simple repetition code.

Error correction coding device according to one of Claims 1 to 8, characterized in that all the basic coding modules implement an identical basic code.

Error-correcting coding device according to any one of Claims 1 to 9, characterized in that all of said coding and permutation stages form a Tanner graph whose inputs are said associated input variables. to a first set said source and redundancy data, and the outputs are said output variables associated with a second set of said source and redundancy data.

11. An error correction coding method capable of implementing a global error correction code associating redundancy data with source data.

characterized in that said coding method implements:

two steps of first-level permutation, including:

a first step of first-level permutation (131) receiving, on the input side, on the one hand a first set of said source and / or redundancy data, and on the other hand input data and output data obtained at from a first second level coding step (121), and

a second step of first-level permutation (132) delivering, on the one hand, a second set of said source and / or redundancy data, and on the other hand input data and output data obtained at from a second second-level coding step (122),

said first set and said second set forming a codeword, and a first level coding step (11) receiving the output data of said first first level permutation step and outputting input data to said second step of first level permutation,

12. Error correction decoding device, able to retrieve source data from a received code word,

said source data having been coded by a global error correction code associating redundancy data with said source data, said global correction code being capable of being represented by a generating matrix comprising, in its systematic form, an identity matrix and a matrix passing said source data to said invertible redundancy data,

characterized in that said decoding device comprises:

two stages of first-level permutation, of which: a first level of first-level permutation connected, in input, on the one hand to input variables associated with a first set of said source and / or redundancy data, and on the other hand to internal variables associated with input data and output data of a second level decoding first stage, and

a second stage of first-level permutation connected, on the output, on the one hand to output variables associated with a second set of said source and / or redundancy data, and on the other hand to internal variables associated with data. input and output data of a second second level decoding stage,

said first set and said second set forming said codeword, and a first-level decoding stage connected on the one hand to the variables associated with the output data of said first first-level permutation stage and on the other hand to the variables associated with the first-level input data of said second first level permutation stage,

13. Error correction decoding method, able to retrieve source data from a received code word,

characterized in that said decoding method implements:

two steps of first-level permutation, including:

a first step of first-level permutation (431) receiving, as input, on the one hand a first set of said source and / or redundancy data, and on the other hand input data and output data obtained at from a first second-level decoding step (421), and o a second first-level permutation step (432) outputting, on the one hand, a second set of said source and / or redundancy data, and on the other hand input data and output data obtained from a second second level decoding step (432),

said first set and said second set forming said code word, and a first level decoding step (41) receiving the output data of said first level first permutation step and outputting input data to said second step of first level permutation,

A computer program comprising instructions for implementing an encoding method according to claim 11 or a decoding method according to claim 13 when said program is executed by a processor.