WO2015197027A1 - 一种访问NVMe存储设备的方法和NVMe存储设备 - Google Patents

一种访问NVMe存储设备的方法和NVMe存储设备 Download PDF

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Publication number
WO2015197027A1
WO2015197027A1 PCT/CN2015/082540 CN2015082540W WO2015197027A1 WO 2015197027 A1 WO2015197027 A1 WO 2015197027A1 CN 2015082540 W CN2015082540 W CN 2015082540W WO 2015197027 A1 WO2015197027 A1 WO 2015197027A1
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Prior art keywords
request message
access request
cpu
protocol format
module
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PCT/CN2015/082540
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English (en)
French (fr)
Inventor
郭海涛
常胜
余洲
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华为技术有限公司
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Priority to EP15811543.6A priority Critical patent/EP3147792A4/en
Publication of WO2015197027A1 publication Critical patent/WO2015197027A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0661—Format or protocol conversion arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Definitions

  • the present invention relates to the field of storage technologies, and in particular, to a method for accessing an NVMe storage device and an NVMe storage device.
  • the high-speed peripheral component interconnect (English: Peripheral Component Interconnect Express, PCIe for short) is the latest bus and interface standard. It belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, which represents the next-generation input/ Output I/O interface standard.
  • a PCIe solid state storage device (such as a solid state disk (SSD)) refers to a solid state storage device connected to a PCIe interface of a central processing unit (CPU).
  • the first-level cache and the second-level cache are used, and the traditional hard disk is intermixed to form hierarchical storage, realizing automatic migration of data between the solid-state storage device and the traditional hard disk, and automatically transferring infrequently accessed data to a lower storage level. That is, the traditional hard disk, which releases a higher level of storage space, that is, the storage space of the solid-state storage device, gives more frequently accessed data, thereby accelerating the storage performance of the system.
  • NVMe Non-Volatile Memory Express
  • the NVMe storage device is directly connected to the PCIe interface of the central processing unit (English: Center Process Unit, CPU for short), without serial advanced technology attachment (English: Serial Advanced Technology Attachment, SATA for short). Interface and Serial Attached Small Computer System Interface (SAS), which reduces the protocol overhead on the Host Bus Adapter (HBA).
  • HBA Host Bus Adapter
  • the driver of the NVMe storage device can be directly connected to the block device layer of the operating system (English: Operating System, OS for short) without using the access request queue of the OS, the enqueue/dequeue scheduling and the small computer system interface. (English: Small Computer System Interface; shorthand: SCSI) layer, compared with the traditional SAS and SSD methods, reduced 50% delay.
  • OS Operating System
  • SCSI Small Computer System Interface
  • the NVMe storage device includes a controller and a storage unit, which are deployed at the near end of the CPU and have high requirements in the fields of power supply, heat dissipation, and space. Moreover, due to the limitation of the number of PCIe interfaces of the CPU, the number of NVMe storage devices hanging on the CPU is limited and cannot be expanded.
  • An embodiment of the present invention provides a method and an NVMe storage device of an NVMe storage device, where the NVMe storage device includes a control module and a storage module, wherein the control module is deployed locally near the CPU, and the storage module including the storage unit is deployed in the The remote end of the CPU, the control module and the storage module transmit data through a communication protocol capable of realizing long-distance transmission, such as an Ethernet protocol, so that the NVMe storage device that is originally integrated as a whole is deployed in two On both sides of the Ethernet, the problem of power supply, heat dissipation, and space of the NVMe storage device brought by the controller and the storage unit of the NVMe storage device in the prior art as a whole is solved.
  • a communication protocol capable of realizing long-distance transmission such as an Ethernet protocol
  • an embodiment of the present invention provides an NVMe storage device, where the device includes a control module and a storage module, wherein the control module and the central processing unit CPU are connected to each other through a high-speed peripheral component interconnect PCIe bus;
  • the control module is configured to receive an access request message in a PCIe protocol format sent by the CPU, where the access request message in the PCIe protocol format includes an operation instruction and an access address information of the CPU, where the PCIe protocol format is The access request message is converted into an access request message in a second protocol format, where the access request message in the second protocol format includes the operation instruction and access address information of the CPU, and the access request message in the second protocol format Sended to the storage module;
  • the storage module is configured to receive an access request message in the second protocol format, and convert the access request message in the second protocol format into an access request message in a third protocol format, where the third protocol format
  • the access request message includes the operation instruction and the access address information of the CPU, and the operation instruction and the access address information of the CPU are obtained from the access request message of the third protocol format, according to the operation instruction. Accessing the storage unit in the storage module with the access address information of the CPU.
  • the second protocol format is an Ethernet protocol or a ray channel protocol.
  • the device further includes a switching module, where the switching module is connected to at least one of the storage modules, in the PCIe protocol format
  • the access request message further includes device identification information of the NVMe storage module to be accessed by the CPU;
  • the control module is further configured to determine device address information of the NVMe storage module to be accessed by the CPU according to device identification information of the NVMe storage module to be accessed by the CPU in the access request message of the PCIe protocol format, and The device address information of the NVMe storage module to be accessed by the CPU is carried in the access request message of the second protocol format;
  • the switching module is configured to receive an access request message of the second protocol format sent by the control module, and according to the device address of the NVMe storage module to be accessed by the CPU in the access request message of the second protocol format And forwarding the access request message of the second protocol format to a storage module to be accessed by the CPU.
  • control module is specifically configured to:
  • an embodiment of the present invention provides a method for accessing an NVMe storage device, where the method is applied to an NVMe storage device, where the device includes a control module and a storage module, wherein the control module and the central processing unit CPU pass
  • the high speed peripheral component interconnects the PCIe bus, and the method includes:
  • the control module receives an access request message in a PCIe protocol format sent by the CPU, where the access request message in the PCIe protocol format includes an operation instruction and access address information of the CPU;
  • the control module converts the access request message of the PCIe protocol format into an access request message of a second protocol format, where the access request message of the second protocol format includes the operation instruction and access address information of the CPU;
  • the control module sends an access request message of the second protocol format to the storage module
  • the storage module receives an access request message of the second protocol format, and the The access request message of the second protocol format is converted into the access request message of the third protocol format, where the access request message of the third protocol format includes the operation instruction and the access address information of the CPU;
  • the storage module acquires the operation instruction and the access address information of the CPU from the access request message of the third protocol format, and the storage unit in the storage module according to the operation instruction and the access address information of the CPU Make an access.
  • the second protocol format is an Ethernet protocol or a ray channel protocol.
  • the NVMe storage device further includes a switching module, where the switching module is connected to at least one of the storage modules, the PCIe
  • the access request message of the protocol format further includes device identification information of the NVMe storage module to be accessed by the CPU.
  • the control module determines device address information of the NVMe storage module to be accessed by the CPU according to the device identification information of the NVMe storage module to be accessed by the CPU in the access request message of the PCIe protocol format, and the CPU The device address information of the NVMe storage module to be accessed is carried in the access request message of the second protocol format;
  • the control module sends an access request message of the second protocol format to the switching module
  • the switching module receives the access request message of the second protocol format sent by the control module, according to the device address information of the NVMe storage module to be accessed by the CPU in the access request message of the second protocol format,
  • the access request message of the second protocol format is forwarded to a storage module to be accessed by the CPU.
  • the control module determines, according to the device identifier information of the NVMe storage module that the CPU is to access in the access request message of the PCIe protocol format.
  • the device address information of the NVMe storage module to be accessed by the CPU specifically includes:
  • the address mapping relationship table is configured to save a correspondence between a device identifier of at least one of the storage modules and a device address.
  • the embodiment of the invention provides a method for accessing an NVMe storage device and an NVMe storage device, the device comprising a control module and a storage module, wherein the control module and the central processing unit CPU are connected by a high-speed peripheral component interconnection PCIe bus.
  • the control module receives an access request message in a PCIe protocol format sent by the CPU, where the access request message in the PCIe protocol format includes an operation instruction and access address information of the CPU, and the access request message in the PCIe protocol format is used.
  • the storage module receives the access request message of the second protocol format, and converts the access request message of the second protocol format into an access request message of a third protocol format, where the third protocol
  • the operation request instruction and the access address information of the CPU are included in the access request message of the format, and the operation instruction and the access address information of the CPU are obtained from the access request message of the third protocol format, according to the operation.
  • the instruction and the access address information of the CPU access the storage unit in the storage module.
  • control module and the central processing unit CPU are connected through the PCIe bus, and the control module and the storage module realize data transmission through a second protocol capable of realizing long-distance transmission, such as an Ethernet protocol, so that
  • a second protocol capable of realizing long-distance transmission such as an Ethernet protocol
  • the NVMe storage device as a whole is deployed on two sides of the Ethernet, that is, the control module is deployed near the CPU, and the storage module is deployed at the remote end of the CPU, thereby solving the NVMe storage device in the prior art.
  • the controller and the storage unit are deployed as a whole to provide power supply, heat dissipation, and space issues of the NVMe storage device brought about by the near end of the CPU.
  • FIG. 1 is a schematic diagram of an NVMe storage system provided by the prior art
  • FIG. 2 is a schematic diagram of an NVMe storage device according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of another NVMe storage device according to an embodiment of the present disclosure.
  • FIG. 4 is a flow chart of a method for accessing an NVMe storage device
  • FIG. 5 is a flow chart of another method for accessing an NVMe storage device.
  • the deployment method of the NVMe storage device is as shown in FIG. 1, and includes: a central processing unit CPU and an NVMe storage device.
  • the NVMe storage device includes a controller and a storage unit, and the controller and the storage unit as a whole are attached to the CPU through a PCIe interface of the CPU.
  • the controller and the storage unit of the NVMe storage device have certain requirements in the fields of power supply, heat dissipation, space, and the like, the controller and the storage unit are deployed as a whole at the near end of the CPU.
  • the NVMe storage device has higher requirements in the fields of power supply, heat dissipation, and space.
  • the present invention implements the problems of power supply, heat dissipation, space, and the like of the NVMe storage device that is disposed at the near end of the central processing unit CPU by the controller and the storage unit in the NVMe storage device in the prior art.
  • An example provides a new NVMe storage device.
  • the device includes a control module 201 and a storage module 202, wherein the control module 201 is connected to a central processing unit CPU through a high speed peripheral component interconnect PCIe bus, the control The module and the storage module perform data transmission by using a second protocol format that supports long-distance transmission;
  • the control module 201 is configured to receive an access request message in a PCIe protocol format sent by the CPU, where the access request message in the PCIe protocol format includes an operation instruction and access address information of the CPU, and the PCIe protocol format is used.
  • the access request message is converted into an access request message in a second protocol format, where the access request message in the second protocol format includes the operation instruction and access address information of the CPU, and the second protocol format is An access request message is sent to the storage module.
  • the control module and the storage module perform data transmission through a second protocol, wherein the second protocol is capable of remote transmission. And a network protocol with good extended features.
  • the second protocol may be an Ethernet protocol or a Fibre Channel protocol.
  • the central processing unit CPU When the central processing unit CPU needs to access the storage module of the NVMe storage device, it is required to send an access request message in the PCIe protocol format to the control module, where the access request message in the PCIe protocol format carries the data packet in the NVMe format.
  • the NVMe format data packet includes operation instruction information of the CPU, such as a read operation instruction or a write operation instruction, that is, the CPU accessing the NVMe storage device includes reading data in the NVMe storage device or Data is stored to the NVMe storage device.
  • the data packet further includes address information of the NVMe storage module to be accessed by the CPU, that is, access address information of the CPU.
  • the control module and the storage module After the control module receives the access request message in the PCIe protocol format, the control module and the storage module perform data transmission by using a second protocol format. Specifically, the control module and the storage module are The connected interface is an interface that supports the second protocol format. Therefore, the control module needs to convert the access request message of the PCIe protocol format into an access request message of a second protocol format, where the second protocol format is accessed.
  • the request message carries the data packet of the NVMe format, where the data packet of the NVMe format includes the operation instruction information, such as a read operation instruction and a write operation instruction, and further includes an NVMe storage module to be accessed by the CPU. Address information, that is, access address information of the CPU.
  • the first processing module may be an Application Specific Integrated Circuit (ASIC) or a Field-Programmable Gate Array (FPGA), or may be Other processing units are not limited in this embodiment of the present invention.
  • ASIC Application Specific Integrated Circuit
  • FPGA Field-Programmable Gate Array
  • the storage module 202 is configured to receive an access request message in the second protocol format, and convert the access request message in the second protocol format into an access request message in a third protocol format, where the third protocol
  • the operation request instruction and the access address information of the CPU are included in the access request message of the format, and the operation instruction and the access address information of the CPU are obtained from the access request message of the third protocol format, according to the operation.
  • the instruction and the access address information of the CPU access the storage unit in the storage module.
  • the access request message of the second protocol format needs to be converted into an access request message of a third protocol format, specifically, the third protocol format, It is a device-customized protocol format, which may be a PCIe protocol format, or a second protocol format, or other protocol formats, which is not limited by the embodiment of the present invention. Therefore, after receiving the access request message in the second protocol format, the storage module needs to parse the access request message in the second protocol format. Specifically, the parsing process is:
  • the storage module converts the access request message of the second protocol format into an access request message of a third protocol format, and obtains the operation instruction and the access address of the CPU from the access request message of the third protocol format. And accessing the storage unit in the storage module according to the operation instruction and the access address information of the CPU to implement a read operation or a write operation.
  • the part of the storage module that performs protocol conversion on the received access request message of the second protocol format may be an application specific integrated circuit (English: Application Specific Integrated Circuit, ASIC) or a field programmable gate array.
  • ASIC Application Specific Integrated Circuit
  • FPGA Field-Programmable Gate Array
  • the embodiment of the invention provides a method for accessing an NVMe storage device and an NVMe storage device, the device comprising a control module and a storage module, wherein the control module and the central processing unit CPU are connected by a high-speed peripheral component interconnection PCIe bus.
  • the control module receives an access request message in a PCIe protocol format sent by the CPU, where the access request message in the PCIe protocol format includes an operation instruction and access address information of the CPU, and the access request message in the PCIe protocol format is used.
  • the storage module receives the access request message of the second protocol format, and converts the access request message of the second protocol format into an access request message of a third protocol format, where the third protocol
  • the operation request instruction and the access address information of the CPU are included in the access request message of the format, and the operation instruction and the access address information of the CPU are obtained from the access request message of the third protocol format, according to the operation.
  • the instruction and the access address information of the CPU access the storage unit in the storage module.
  • the control module and the central processing unit CPU are connected through the PCIe bus, and the control module and the storage module realize data transmission through a second protocol capable of realizing long-distance transmission, such as an Ethernet protocol, so that
  • a second protocol capable of realizing long-distance transmission such as an Ethernet protocol
  • the control module is deployed near the CPU, and the storage module is deployed at the remote end of the CPU, thereby solving the problem that the controller and the storage portion of the NVMe storage device in the prior art are deployed as a whole in the CPU.
  • the problems of power supply, heat dissipation, and space of the NVMe storage device brought by the terminal are connected through the PCIe bus, and the control module and the storage module realize data transmission through a second protocol capable of realizing long-distance transmission, such as an Ethernet protocol, so that The original NVMe storage device as a whole is split into two deployments.
  • the control module is deployed near the CPU, and the storage module is deployed at the remote end of the CPU, thereby solving the problem that the
  • the embodiment of the present invention further provides an NVMe storage device, and the storage device further includes a switch module.
  • the switching module 203 is connected to the at least one storage module 202, and the access request message in the PCIe protocol format further includes device identification information of the NVMe storage module to be accessed by the CPU;
  • the control module 201 is further configured to determine device address information of the NVMe storage module to be accessed by the CPU according to the device identifier information of the NVMe storage module to be accessed by the CPU in the access request message of the PCIe protocol format. And carrying the device address information of the NVMe storage module to be accessed by the CPU in the access request message of the second protocol format;
  • the switching module 203 is configured to receive an access request message of the second protocol format sent by the control module, and the device of the NVMe storage module to be accessed by the CPU according to the access request message in the second protocol format Address information, forwarding the access request message of the second protocol format to a storage module to be accessed by the CPU.
  • the PCIe interface on the CPU of the CPU is limited. For example, if there are three PCIe interfaces on the CPU, the CPU can only access at most three NVMe storage devices.
  • the A switching module is added between the control module and the storage module, and the switching module supports forwarding of an access request message in a second protocol format for communication between the control module and the storage module, where the switch module can be configured with A plurality of interfaces enable a plurality of storage modules to be simultaneously connected to the switching module.
  • the CPU can only access one storage module corresponding to the control module by sending an access request message to a control module. Therefore, the CPU
  • the access request message of the sent PCIe protocol format carries only the operation instruction information and the access address information of the CPU.
  • the CPU sends an access request message to a control module, because the control module corresponds to at least one storage module through the switch module.
  • the PCIe protocol format access request message sent by the CPU to the control module further needs to include the CPU to access Device identification information of the storage module, such as device number information.
  • the device identification information of the storage module needs to be converted into the device address information of the storage module in the second protocol format, for example, the The second protocol format is an Ethernet protocol, where the address information of the storage module is the MAC address information of the storage module, and the device address information of the storage module is carried in the second protocol format of the second protocol format.
  • the request message is an Ethernet protocol, where the address information of the storage module is the MAC address information of the storage module, and the device address information of the storage module is carried in the second protocol format of the second protocol format.
  • control module may determine, according to the device identification information of the NVMe storage module to be accessed by the CPU in the access request message of the PCIe protocol format, and the address mapping relationship table, the NVMe to be accessed by the CPU.
  • control module may further convert the device identification information of the storage module into device address information by using other methods, for example, converting the device identification information of the storage module to be accessed by the CPU by using a preset algorithm.
  • the device address information of the storage module to be accessed by the CPU is not limited in this embodiment of the present invention.
  • the control module sends an access request message of a second protocol format carrying the storage module device address information to be accessed by the CPU to the switching module.
  • the switching module forwards the access request message of the second protocol format to the storage module by using device address information of the storage module to be accessed by the CPU in the access request message of the second protocol format.
  • the NVMe storage device also performs settings for enhancing reliability in the following two aspects:
  • a retransmission buffer is set in the control module and the storage module.
  • a phenomenon of reading or storing data may occur due to instability of the switching module.
  • a retransmission buffer is set in the control module and the storage module.
  • the retransmission cache is configured to resend an access request message in a PCIe protocol format to the NVMe storage device when the central processor CPU fails to read or store data
  • the control module is Converting, in the retransmission cache, the access request message in the PCIe protocol format to an access request message in a second protocol format, and sending the access request message in the second protocol format to the switch module
  • the storage module is retransmitted Transmitting, in the cache, the access request message of the second protocol format sent by the switching module in the cache into an access request message in a third protocol format, and using the access request message in the third protocol format
  • the operation instruction information and the access address information of the CPU access the storage unit in the NVMe storage device.
  • a flow control mechanism is implemented in the switch module.
  • the switching module when the interface of the switching module is blocked, the switching module sends an alert message to the central processing unit CPU and the NVMe storage device, where the alert message includes the central processing unit CPU and the NVMe storage device. Stop sending data to the switch module.
  • An embodiment of the present invention provides an NVMe storage device, where the device includes a control module, a switch module, and at least one storage module, wherein, between the switch module and the storage module, due to the control module and the switch module
  • the NVMe storage device that is originally deployed as a whole is deployed on both sides of the Ethernet, that is, the control module is deployed close to the CPU, and the storage module is deployed on the CPU.
  • the remote end solves the problems of power supply, heat dissipation, and space of the NVMe storage device brought by the controller and the storage portion of the NVMe storage device in the prior art as a whole.
  • the switch module can be configured to connect multiple interfaces to multiple storage devices, thereby solving the problem that the number of NVMe storage devices accessed by the CPU is limited by the number of PCIe interfaces of the CPU.
  • An embodiment of the present invention provides a method for accessing an NVMe storage device, where the method is applied to an NVMe storage device, where the device includes a control module and a storage module, wherein the control module and the central processing unit CPU are interconnected by a high-speed peripheral component.
  • the PCIe bus is connected, and in conjunction with FIG. 4, the method includes:
  • the control module receives an access request message in a PCIe protocol format sent by the CPU, where the access request message in the PCIe protocol format includes an operation instruction and access address information of the CPU.
  • the control module converts the access request message in the PCIe protocol format into an access request message in a second protocol format, where the access request message in the second protocol format includes the operation instruction and an access address of the CPU. information.
  • the control module sends an access request message of the second protocol format to the storage module.
  • the storage module receives the access request message in the second protocol format, and converts the access request message in the second protocol format into an access request message in a third protocol format, where the third protocol format is The operation request message and the access address information of the CPU are included in the access request message.
  • the storage module acquires the operation instruction and the access address information of the CPU from the access request message of the third protocol format, and according to the operation instruction and the access address information of the CPU, the storage module The storage unit is accessed.
  • An embodiment of the present invention provides a method for accessing an NVMe storage device.
  • a control module is connected to a central processing unit CPU through a PCIe bus, and a second protocol capable of realizing long-distance transmission is implemented between the control module and the storage module.
  • the Ethernet protocol implements data transmission.
  • the NVMe storage device which is originally integrated as a whole, is deployed on both sides of the Ethernet. That is, the control module is deployed locally near the CPU, and the storage module is deployed at the remote end of the CPU. Therefore, the problem of power supply, heat dissipation, space and the like of the NVMe storage device brought by the controller and the storage portion of the NVMe storage device as a whole in the near-end of the CPU is solved.
  • the embodiment of the present invention further provides a method for accessing the NVMe storage device. Referring to FIG. 5, the method includes:
  • the control module receives an access request message in a PCIe protocol format sent by the CPU, where the access request message in the PCIe protocol format includes an operation instruction, device identifier information of an NVMe storage device to be accessed by the CPU, and the CPU access address information.
  • the control module converts the access request message in the PCIe protocol format into an access request message in a second protocol format, where the access request message in the second protocol format of the control module includes the operation instruction, Device address information of the NVMe storage device to be accessed by the CPU and access address information of the CPU.
  • control module is configured to: according to the device identification information of the NVMe storage module to be accessed by the CPU in the access request message of the PCIe protocol format, and the address mapping And determining the device address information of the NVMe storage module to be accessed by the CPU, where the address mapping relationship table is configured to save a correspondence between the device identifier and the device address of the at least one storage module.
  • the control module sends an access request message of the second protocol format to the switching module.
  • the switching module receives the access request message in the second protocol format sent by the control module, and the device address information of the NVMe storage module to be accessed by the CPU in the access request message in the second protocol format. And forwarding the access request message of the second protocol format to a storage module to be accessed by the CPU.
  • the storage module receives the access request message in the second protocol format, and converts the access request message in the second protocol format into an access request message in a third protocol format, where the third protocol format is The operation request message and the access address information of the CPU are included in the access request message.
  • the storage module acquires the operation instruction and the access address information of the CPU from the access request message of the third protocol format, and the storage module is configured according to the operation instruction and the access address information of the CPU.
  • the storage unit is accessed.
  • An embodiment of the present invention provides a method for accessing an NVMe storage device, where the method is applied to an NVMe storage device, where the device includes a control module, a switch module, and at least one storage module, wherein the control module and the switch
  • the module, the switching module and the storage module perform data transmission through a network protocol capable of realizing long-distance transmission, such as an Ethernet protocol, and the NVMe storage device that is originally integrated as a whole is deployed in the Ethernet.
  • the control module is deployed close to the CPU, and the storage module is deployed at the far end of the CPU, thereby solving the problem that the controller and the storage part of the NVMe storage device in the prior art are deployed as a whole at the near end of the CPU.
  • the switch module can be configured to connect multiple interfaces to multiple storage devices, thereby solving the problem that the number of NVMe storage devices accessed by the CPU is limited by the number of PCIe interfaces of the CPU.
  • the storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

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Abstract

一种访问NVMe存储设备的方法和NVMe存储设备，解决了NVMe存储设备的供配电、散热和空间等问题。该方法包括：控制模块接收CPU发送的PCIe协议格式的访问请求消息（401），将所述PCIe协议格式的访问请求消息转换为第二协议格式的访问请求消息（402），将所述第二协议格式的访问请求消息发送至存储模块（403）；所述存储模块将所述第二协议格式的访问请求消息转换为第三协议格式的访问请求消息（404），从所述第三协议格式的访问请求消息中获取所述操作指令和所述CPU的访问地址信息，根据所述操作指令和所述CPU的访问地址信息对所述存储模块中的存储单元进行访问（405）。该方法适用于存储技术领域。

Description

一种访问NVMe存储设备的方法和NVMe存储设备 技术领域
本发明涉及存储技术领域，尤其涉及一种访问NVMe存储设备的方法和NVMe存储设备。
背景技术
在目前的网络应用场景中，高速外围组件互联(英文：Peripheral Component Interconnect express，简称：PCIe)是最新的总线和接口标准，属于高速串行点对点双通道高带宽传输，它代表着下一代输入/输出I/O接口标准。
PCIe固态存储设备(如固态硬盘(英文：Solid State Disk，简称：SSD))指的是与中央处理器(英文：Central Processing Unit，简称：CPU)的PCIe接口相连接的固态存储设备，通常作为一级缓存和二级缓存来使用，与传统硬盘混插构成分级存储，实现数据在固态存储设备和传统硬盘之间的自动迁移，将不常访问的数据自动移到存储层次较低的层次，即传统硬盘，从而释放出较高层次的存储空间，即固态存储设备的存储空间，给更频繁访问的数据，从而加快了系统的存储性能。
快速非易失性存储(英文：Non-Volatile Memory Express，简称：NVMe)标准是一个针对使用PCIe SSD的企业和普通客户端系统开发的存储控制器接口标准，NVMe架构下的存储器具有低能耗，高性能的特点。在目前的存储器架构中，NVMe的技术实现如下：
在硬件上，将NVMe存储设备直接连接到中央处理器(英文：Center Process Unit，简称：CPU)的PCIe接口上，而不通过串行高级技术附件(英文：Serial Advanced Technology Attachment，简称：SATA)接口和串行连接小型计算机系统接口(英文：Serial Attached Small Computer System Interface，简称：SAS)，从而减少了主机总线适配器(英文：Host Bus Adapter，简称：HBA)上的协议开销。
在软件上，NVMe存储设备的驱动可以直接连接到操作系统(英文：Operating System，简称：OS)的块设备层，而不使用OS的访问请求队列，入队/出队调度和小型计算机系统接口(英语：Small Computer System Interface；简写：SCSI)层，与传统的SAS和SSD的方式相比，减少了 50％的延时。
NVMe存储设备包括控制器和存储单元，部署在CPU的近端，对供配电、散热和空间等领域有较高的要求。并且，由于CPU的PCIe接口数量的限制，使得挂在CPU上的NVMe存储设备的数量有限，无法扩展。
发明内容
本发明的实施例提供一种NVMe存储设备的方法和NVMe存储设备，该NVMe存储设备包括控制模块和存储模块，其中，所述控制模块部署在靠近CPU的本地，包含存储单元的存储模块部署在CPU的远端，所述控制模块和所述存储模块通过能够实现远距离传输的通信协议，如以太网协议进行数据的传输，这样，将原来作为整体的NVMe存储设备一分为二的部署在以太网的两侧，解决了现有技术中NVMe存储设备的控制器和存储单元作为一个整体部署在CPU的近端所带来的所述NVMe存储设备的供配电、散热和空间等问题。
为达到上述目的，本发明的实施例采用如下技术方案：
第一方面，本发明实施例提供了一种NVMe存储设备，该设备包括控制模块和存储模块，其中，所述控制模块与中央处理器CPU通过高速外围组件互联PCIe总线相连；
所述控制模块，用于接收所述CPU发送的PCIe协议格式的访问请求消息，所述PCIe协议格式的访问请求消息中包含操作指令和所述CPU的访问地址信息，将所述PCIe协议格式的访问请求消息转换为第二协议格式的访问请求消息，所述第二协议格式的访问请求消息中包含所述操作指令和所述CPU的访问地址信息，将所述第二协议格式的访问请求消息发送至所述存储模块；
所述存储模块，用于接收所述第二协议格式的访问请求消息，并将所述第二协议格式的访问请求消息转换为第三协议格式的访问请求消息，其中，所述第三协议格式的访问请求消息中包含所述操作指令和所述CPU的访问地址信息，从所述第三协议格式的访问请求消息中获取所述操作指令和所述CPU的访问地址信息，根据所述操作指令和所述CPU的访问地址信息对所述存储模块中的存储单元进行访问。
在第一种可能的实施方式中，结合第一方面，所所述第二协议格式是以太网协议或光线通道协议。
在第二种可能的实施方式中，结合第一方面或第一种可能的实施方式，该设备还包括交换模块，所述交换模块与至少一个所述存储模块相连接，所述PCIe协议格式的访问请求消息中还包含所述CPU所要访问的NVMe存储模块的设备标识信息；
所述控制模块，还用于根据所述PCIe协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备标识信息，确定所述CPU所要访问的NVMe存储模块的设备地址信息，并将所述CPU所要访问的NVMe存储模块的设备地址信息承载于所述第二协议格式的访问请求消息中；
所述交换模块，用于接收所述控制模块发送的所述第二协议格式的访问请求消息，根据所述第二协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备地址信息，将所述第二协议格式的访问请求消息转发至所述CPU所要访问的存储模块。
在第三种可能的实施方式中，结合第二种可能的实施方式，所述控制模块具体用于：
根据所述PCIe协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备标识信息，以及地址映射关系表，确定所述CPU所要访问的NVMe存储模块的设备地址信息，其中，所述地址映射关系表用于保存至少一个所述存储模块的设备标识与设备地址的对应关系。
第二方面，本发明实施例提供了一种访问NVMe存储设备的方法，该方法应用于一种NVMe存储设备，该设备包括控制模块和存储模块，其中，所述控制模块与中央处理器CPU通过高速外围组件互联PCIe总线相连，该方法包括：
所述控制模块接收所述CPU发送的PCIe协议格式的访问请求消息，所述PCIe协议格式的访问请求消息中包含操作指令和所述CPU的访问地址信息；
所述控制模块将所述PCIe协议格式的访问请求消息转换为第二协议格式的访问请求消息，所述第二协议格式的访问请求消息中包含所述操作指令和所述CPU的访问地址信息；
所述控制模块将所述第二协议格式的访问请求消息发送至所述存储模块；
所述存储模块接收所述第二协议格式的访问请求消息，并将所述第 二协议格式的访问请求消息转换为第三协议格式的访问请求消息，其中，所述第三协议格式的访问请求消息中包含所述操作指令和所述CPU的访问地址信息；
所述存储模块从所述第三协议格式的访问请求消息中获取所述操作指令和所述CPU的访问地址信息，根据所述操作指令和所述CPU的访问地址信息对存储模块中的存储单元进行访问。
在第一种可能的实施方式中，结合第二方面，所述第二协议格式是以太网协议或光线通道协议。
在第二种可能的实施方式中，结合第二方面或第一种可能的实施方式，所述NVMe存储设备还包括交换模块，所述交换模块与至少一个所述存储模块相连接，所述PCIe协议格式的访问请求消息中还包含所述CPU所要访问的NVMe存储模块的设备标识信息，在所述控制模块接收所述CPU发送的所述PCIe协议格式的访问请求消息之后，该方法还包括：
所述控制模块根据所述PCIe协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备标识信息，确定所述CPU所要访问的NVMe存储模块的设备地址信息，并将所述CPU所要访问的NVMe存储模块的设备地址信息承载于所述第二协议格式的访问请求消息中；
所述控制模块将所述第二协议格式的访问请求消息发送至所述交换模块；
所述交换模块接收所述控制模块发送的所述第二协议格式的访问请求消息，根据所述第二协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备地址信息，将所述第二协议格式的访问请求消息转发至所述CPU所要访问的存储模块。
在第三种可能的实施方式中，结合第二种可能的实施方式，所述控制模块根据所述PCIe协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备标识信息，确定所述CPU所要访问的NVMe存储模块的设备地址信息具体包括：
所述控制模块根据所述PCIe协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备标识信息，以及地址映射关系表，确定所述CPU所要访问的NVMe存储模块的设备地址信息，其中， 所述地址映射关系表用于保存至少一个所述存储模块的设备标识与设备地址的对应关系。
本发明实施例提供了一种访问NVMe存储设备的方法和NVMe存储设备，该设备包括控制模块和存储模块，其中，所述控制模块与中央处理器CPU通过高速外围组件互联PCIe总线相连。所述控制模块接收所述CPU发送的PCIe协议格式的访问请求消息，所述PCIe协议格式的访问请求消息中包含操作指令和所述CPU的访问地址信息，将所述PCIe协议格式的访问请求消息转换为第二协议格式的访问请求消息，所述第二协议格式的访问请求消息中包含所述操作指令和所述CPU的访问地址信息，将所述第二协议格式的访问请求消息发送至所述存储模块；所述存储模块接收所述第二协议格式的访问请求消息，并将所述第二协议格式的访问请求消息转换为第三协议格式的访问请求消息，其中，所述第三协议格式的访问请求消息中包含所述操作指令和所述CPU的访问地址信息，从所述第三协议格式的访问请求消息中获取所述操作指令和所述CPU的访问地址信息，根据所述操作指令和所述CPU的访问地址信息对所述存储模块中的存储单元进行访问。在该NVMe存储设备中，控制模块与中央处理器CPU通过PCIe总线相连接，控制模块与存储模块之间通过能够实现远距离传输的第二协议，如以太网协议实现数据的传输，这样，将原来作为整体的NVMe存储设备一分为二的部署在以太网的两侧，即控制模块部署在靠近CPU的本地，存储模块部署在CPU的远端，从而解决了现有技术中NVMe存储设备的控制器和存储单元作为一个整体部署在CPU的近端所带来的所述NVMe存储设备的供配电、散热和空间等问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术提供的一种NVMe存储系统示意图；
图2为本发明实施例提供的一种NVMe存储设备示意图；
图3为本发明实施例提供的另一种NVMe存储设备示意图；
图4为一种访问NVMe存储设备的方法流程图；
图5为另一种访问NVMe存储设备的方法流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在现有的存储技术中，NVMe存储设备的部署方法如图1所示，包括：中央处理器CPU和NVMe存储设备。所述NVMe存储设备包括控制器和存储单元，所述控制器和存储单元作为一个整体，通过所述CPU的PCIe接口挂接在所述CPU上。
由于所述NVMe存储设备的控制器和存储单元都对供配电、散热和空间等领域有一定的要求，将所述控制器和所述存储单元作为一个整体部署在所述CPU的近端，使得所述NVMe存储设备对供配电、散热和空间等领域有更高的要求。
针对现有技术中NVMe存储设备中的控制器与存储单元作为一个整体部署在中央处理器CPU的近端所带来的所述NVMe存储设备的供配电、散热和空间等问题，本发明实施例提供了一种新的NVMe存储设备，结合图2，该设备包括控制模块201和存储模块202，其中，所述控制模块201与中央处理器CPU通过高速外围组件互联PCIe总线相连，所述控制模块和所述存储模块通过支持远距离传输的第二协议格式进行数据的传输；
所述控制模块201，用于接收所述CPU发送的PCIe协议格式的访问请求消息，所述PCIe协议格式的访问请求消息中包含操作指令和所述CPU的访问地址信息，将所述PCIe协议格式的访问请求消息转换为第二协议格式的访问请求消息，所述第二协议格式的访问请求消息中包含所述操作指令和所述CPU的访问地址信息，将所述第二协议格式的 访问请求消息发送至所述存储模块。
为实现将所述存储模块部署在中央处理器CPU的远端的目的，所述控制模块与所述存储模块通过第二协议进行数据的传输，其中，所述第二协议为能够实现远距离传输，且具有良好的扩展特性的网络协议。具体的，所述第二协议可以是以太网协议或光纤通道协议。
当中央处理器CPU需要访问所述NVMe存储设备的存储模块时，需要向所述控制模块发送一个PCIe协议格式的访问请求消息，所述PCIe协议格式的访问请求消息中携带有NVMe格式的数据包，所述NVMe格式的数据包中包含有所述CPU的操作指令信息，如读操作指令或写操作指令，即所述CPU访问所述NVMe存储设备包括读取所述NVMe存储设备中的数据或者向所述NVMe存储设备存储数据。所述数据包中还包括所述CPU所要访问的NVMe存储模块的地址信息，即所述CPU的访问地址信息。
所述控制模块接收到所述PCIe协议格式的访问请求消息后，由于所述控制模块与所述存储模块通过第二协议格式进行数据的传输，具体的，所述控制模块和所述存储模块相连接的接口为支持第二协议格式的接口，因此，所述控制模块需要将所述PCIe协议格式的访问请求消息转换为第二协议格式的访问请求消息，其中，所述第二协议格式的访问请求消息中携带有所述NVMe格式的数据包，所述NVMe格式的数据包中包含有所述操作指令信息，如读操作指令和写操作指令，还包括所述CPU所要访问的NVMe存储模块的地址信息，即所述CPU的访问地址信息。
具体的，所述第一处理模块可以是：专用集成电路(英文：Application Specific Integrated Circuit，简称：ASIC)或现场可编程门阵列(英文：Field－Programmable Gate Array，简称：FPGA)，也可以是其他处理单元，本发明实施例对此不做限定。
所述存储模块202，用于接收所述第二协议格式的访问请求消息，并将所述第二协议格式的访问请求消息转换为第三协议格式的访问请求消息，其中，所述第三协议格式的访问请求消息中包含所述操作指令和所述CPU的访问地址信息，从所述第三协议格式的访问请求消息中获取所述操作指令和所述CPU的访问地址信息，根据所述操作指令和所述CPU的访问地址信息对所述存储模块中的存储单元进行访问。
当存储模块接收到所述第二协议格式的访问请求消息后，需要将所述第二协议格式的访问请求消息转换为第三协议格式的访问请求消息，具体的，所述第三协议格式，是设备商自定义的协议格式，可以为PCIe协议格式，也可以为所述第二协议格式，还可以其他协议格式，本发明实施例对此不做限定。因此，所述存储模块接收到所述第二协议格式的访问请求消息后，需要对第二协议格式的访问请求消息进行解析，具体的，解析过程为：
所述存储模块将所述第二协议格式的访问请求消息转换为第三协议格式的访问请求消息，从所述第三协议格式的访问请求消息中获取所述操作指令和所述CPU的访问地址信息，根据所述操作指令和所述CPU的访问地址信息对存储模块中的存储单元进行访问，实现读操作或写操作。
具体的，所述存储模块中对接收到的第二协议格式的访问请求消息进行协议转换的部分可以为专用集成电路(英文：Application Specific Integrated Circuit，简称：ASIC)或现场可编程门阵列(英文：Field－Programmable Gate Array，简称：FPGA)，也可以是其他处理单元，本发明实施例对此不做限定。
本发明实施例提供了一种访问NVMe存储设备的方法和NVMe存储设备，该设备包括控制模块和存储模块，其中，所述控制模块与中央处理器CPU通过高速外围组件互联PCIe总线相连。所述控制模块接收所述CPU发送的PCIe协议格式的访问请求消息，所述PCIe协议格式的访问请求消息中包含操作指令和所述CPU的访问地址信息，将所述PCIe协议格式的访问请求消息转换为第二协议格式的访问请求消息，所述第二协议格式的访问请求消息中包含所述操作指令和所述CPU的访问地址信息，将所述第二协议格式的访问请求消息发送至所述存储模块；所述存储模块接收所述第二协议格式的访问请求消息，并将所述第二协议格式的访问请求消息转换为第三协议格式的访问请求消息，其中，所述第三协议格式的访问请求消息中包含所述操作指令和所述CPU的访问地址信息，从所述第三协议格式的访问请求消息中获取所述操作指令和所述CPU的访问地址信息，根据所述操作指令和所述CPU的访问地址信息对所述存储模块中的存储单元进行访问。在该NVMe存储设备中，控制模块与中央处理器CPU通过PCIe总线相连接，控制模块与存储模块之间通过能够实现远距离传输的第二协议，如以太网协议实现数据的传输，这样，将原来作为整体的NVMe存储设备一分为二的部署 在以太网的两侧，即控制模块部署在靠近CPU的本地，存储模块部署在CPU的远端，从而解决了现有技术中NVMe存储设备的控制器和存储部分作为一个整体部署在CPU的近端所带来的所述NVMe存储设备的供配电、散热和空间等问题。
进一步的，为解决与CPU相连的NVMe存储设备的个数受CPU的PCIe接口数量的限制的问题，本发明实施例还提供了一种NVMe存储设备，结合图3，该存储设备还包括交换模块203；所述交换模块203与至少一个所述存储模块202相连接，所述PCIe协议格式的访问请求消息中还包括所述CPU所要访问的NVMe存储模块的设备标识信息；
所述控制模块201，还用于根据所述PCIe协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备标识信息，确定所述CPU所要访问的NVMe存储模块的设备地址信息，并将所述CPU所要访问的NVMe存储模块的设备地址信息承载于所述第二协议格式的访问请求消息中；
所述交换模块203，用于接收所述控制模块发送的所述第二协议格式的访问请求消息，根据所述第二协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备地址信息，将所述第二协议格式的访问请求消息转发至所述CPU所要访问的存储模块。
具体的，中央处理器CPU上的PCIe接口有限，举例来说，所述CPU上有三个PCIe接口，则所述CPU最多只能访问3个NVMe存储设备，为解决这一问题，可以在所述控制模块和存储模块之间增加如下交换模块，所述交换模块支持所述控制模块和所述存储模块之间进行通信的第二协议格式的访问请求消息的转发，所述交换模块上可以设置有多个接口，使得多个存储模块可以同时连接在所述交换模块上。
当所述控制模块和所述存储模块之间没有所述交换模块时，所述CPU通过向一个控制模块发送访问请求消息，只能访问该控制模块所对应的一个存储模块，因此，所述CPU发送的PCIe协议格式的访问请求消息中只携带有所述操作指令信息以及所述CPU的访问地址信息。
但是，当所述控制模块和所述存储模块之间有所述交换模块时，所述CPU通过向一个控制模块发送访问请求消息时，由于该控制模块通过所述交换模块对应着至少一个存储模块，所述CPU向所述控制模块发送的PCIe协议格式的访问请求消息中还需要包含所述CPU所要访问 的存储模块的设备标识信息，如设备号信息。
当所述控制模块接收到所述PCIe协议格式的访问请求消息后，需要将所述存储模块的设备标识信息转换为第二协议格式的所述存储模块的设备地址信息，举例来说，所述第二协议格式为以太网协议，则所述存储模块的地址信息为所述存储模块的MAC地址信息，所述存储模块的设备地址信息承载于所述第二协议格式的第二协议格式的访问请求消息中。
具体的，所述控制模块可以根据所述PCIe协议格式的访问请求消息中的所述CPU所要访问的所述NVMe存储模块的设备标识信息，以及地址映射关系表，确定所述CPU所要访问的NVMe存储模块的设备地址信息，其中，所述地址映射关系表用于保存至少一个所述存储模块的设备标识与设备地址的对应关系。
当然，所述控制模块还可以通过其他方式将所述存储模块的设备标识信息转换为设备地址信息，例如，通过某种预设的算法，将所述CPU所要访问的存储模块的设备标识信息转换为所述CPU所要访问的存储模块的设备地址信息，具体的，本发明实施例对此不做限定。
所述控制模块将携带有所述CPU所要访问的存储模块设备地址信息的第二协议格式的访问请求消息发送至所述交换模块。
所述交换模块通过所述第二协议格式的访问请求消息中的所述CPU所要访问的存储模块的设备地址信息，将所述第二协议格式的访问请求消息转发至所述存储模块。
关于所述存储模块的详细技术特征可参见上述实施例，本发明实施例对此不再赘述。
需要说明的是，为了增强所述中央处理器CPU访问NVMe设备来存储或读取数据的可靠性，在该NVMe存储设备还对如下两个方面进行了用于增强可靠性的设置：
第一方面，在所述控制模块和存储模块中设置重传缓存。
具体的，当所述中央处理器CPU访问所述NVMe存储设备来读取或存储数据时，由于所述交换模块的不稳定性，可能会发生读取或存储数据失败的现象。为了避免上述现象，在所述控制模块和存储模块中设置重传缓存。所述重传缓存，用于当所述中央处理器CPU读取或存储数据失败时，向所述NVMe存储设备重新发送PCIe协议格式的访问请求消息，所述控制模块在其 重传缓存中将所述PCIe协议格式的访问请求消息转换为第二协议格式的访问请求消息，并将所述第二协议格式的访问请求消息发送至交换模块，所述存储模块在其重传缓存中将接收到的所述交换模块发送的第二协议格式的访问请求消息在其重传缓存中转换为第三协议格式的访问请求消息，并通过所述第三协议格式的访问请求消息中的操作指令信息和所述CPU的访问地址信息，访问所述NVMe存储设备中的存储单元。
第二方面，在所述交换模块中实现流控机制。
具体的，当所述交换模块的接口发生阻塞时，所述交换模块向所述中央处理器CPU和NVMe存储设备发送提醒消息，所述提醒消息包括所述中央处理器CPU和所述NVMe存储设备停止向所述交换模块发送数据。
本发明实施例提供了一种NVMe存储设备，该设备包括控制模块，交换模块和至少一个存储模块，其中，由于所述控制模块和所述交换模块，所述交换模块和所述存储模块之间通过能够实现远距离传输的网络协议进行数据的传输，将原来作为整体的NVMe存储设备一分为二的部署在以太网的两侧，即控制模块部署在靠近CPU的本地，存储模块部署在CPU的远端，从而解决了现有技术中NVMe存储设备的控制器和存储部分作为一个整体部署在CPU的近端所带来的所述NVMe存储设备的供配电、散热和空间等问题。并且，所述交换模块上可以设置多个接口与多个存储设备相连接，从而解决了CPU访问的NVMe存储设备的数量受到CPU的PCIe接口数量限制的问题。
本发明实施例提供了一种访问NVMe存储设备的方法，该方法应用于一种NVMe存储设备，该设备包括控制模块和存储模块，其中，所述控制模块与中央处理器CPU通过高速外围组件互联PCIe总线相连，结合图4，该方法包括：
401、所述控制模块接收所述CPU发送的PCIe协议格式的访问请求消息，所述PCIe协议格式的访问请求消息中包含操作指令和所述CPU的访问地址信息。
402、所述控制模块将所述PCIe协议格式的访问请求消息转换为第二协议格式的访问请求消息，所述第二协议格式的访问请求消息中包含所述操作指令和所述CPU的访问地址信息。
403、所述控制模块将所述第二协议格式的访问请求消息发送至所述存储模块。
404、所述存储模块接收所述第二协议格式的访问请求消息，并将所述第二协议格式的访问请求消息转换为第三协议格式的访问请求消息，其中，所述第三协议格式的访问请求消息中包含所述操作指令和所述CPU的访问地址信息。
405、所述存储模块从所述第三协议格式的访问请求消息中获取所述操作指令和所述CPU的访问地址信息，根据所述操作指令和所述CPU的访问地址信息对存储模块中的存储单元进行访问。
具体的，该方法实施例的详细技术特征可参见上述NVMe存储设备的实施例，本发明实施例对此不再赘述。
本发明实施例提供了一种访问NVMe存储设备的方法，在该方法中，控制模块与中央处理器CPU通过PCIe总线相连接，控制模块与存储模块之间通过能够实现远距离传输的第二协议，如以太网协议实现数据的传输，将原来作为整体的NVMe存储设备一分为二的部署在以太网的两侧，即控制模块部署在靠近CPU的本地，存储模块部署在CPU的远端，从而解决了现有技术中NVMe存储设备的控制器和存储部分作为一个整体部署在CPU的近端所带来的所述NVMe存储设备的供配电、散热和空间等问题。
进一步的，为解决与CPU相连的NVMe存储设备的个数受CPU的PCIe接口数量的限制的问题，本发明实施例还提供了一种访问NVMe存储设备的方法，结合图5，该方法包括：
501、所述控制模块接收所述CPU发送的PCIe协议格式的访问请求消息，所述PCIe协议格式的访问请求消息中包含操作指令、所述CPU所要访问的NVMe存储设备的设备标识信息和所述CPU的访问地址信息。
502、所述控制模块将所述PCIe协议格式的访问请求消息转换为第二协议格式的访问请求消息，其中，所述控制模块所述第二协议格式的访问请求消息中包含所述操作指令、所述CPU所要访问的NVMe存储设备的设备地址信息和所述CPU的访问地址信息。
具体的，所述控制模块根据所述PCIe协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备标识信息，以及地址映 射关系表，确定所述CPU所要访问的NVMe存储模块的设备地址信息，其中，所述地址映射关系表用于保存至少一个所述存储模块的设备标识与设备地址的对应关系。
503、所述控制模块将所述第二协议格式的访问请求消息发送至所述交换模块。
504、所述交换模块接收所述控制模块发送的所述第二协议格式的访问请求消息，根据所述第二协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备地址信息，将所述第二协议格式的访问请求消息转发至所述CPU所要访问的存储模块。
505、所述存储模块接收所述第二协议格式的访问请求消息，并将所述第二协议格式的访问请求消息转换为第三协议格式的访问请求消息，其中，所述第三协议格式的访问请求消息中包含所述操作指令和所述CPU的访问地址信息。
506、所述存储模块从所述第三协议格式的访问请求消息中获取所述操作指令和所述CPU的访问地址信息，根据所述操作指令和所述CPU的访问地址信息对存储模块中的存储单元进行访问。
具体的，该方法的实施例的详细实施过程可参见上述NVMe存储设备的实施例，本发明实施例对此不再赘述。
本发明实施例提供了一种访问NVMe存储设备的方法，该方法应用于一种NVMe存储设备，该设备包括控制模块，交换模块和至少一个存储模块，其中，由于所述控制模块和所述交换模块，所述交换模块和所述存储模块之间通过能够实现远距离传输的网络协议，如以太网协议，进行数据的传输，将原来作为整体的NVMe存储设备一分为二的部署在以太网的两侧，即控制模块部署在靠近CPU的本地，存储模块部署在CPU的远端，从而解决了现有技术中NVMe存储设备的控制器和存储部分作为一个整体部署在CPU的近端所带来的所述NVMe存储设备的供配电、散热和空间等问题。并且，所述交换模块上可以设置多个接口与多个存储设备相连接，从而解决了CPU访问的NVMe存储设备的数量受到CPU的PCIe接口数量限制的问题。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述 的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (8)

  1. 一种NVMe存储设备，其特征在于，该设备包括控制模块和存储模块，其中，所述控制模块与中央处理器CPU通过高速外围组件互联PCIe总线相连；
    所述控制模块，用于接收所述CPU发送的PCIe协议格式的访问请求消息，所述PCIe协议格式的访问请求消息中包含操作指令和所述CPU的访问地址信息，将所述PCIe协议格式的访问请求消息转换为第二协议格式的访问请求消息，所述第二协议格式的访问请求消息中包含所述操作指令和所述CPU的访问地址信息，将所述第二协议格式的访问请求消息发送至所述存储模块；
    所述存储模块，用于接收所述第二协议格式的访问请求消息，并将所述第二协议格式的访问请求消息转换为第三协议格式的访问请求消息，其中，所述第三协议格式的访问请求消息中包含所述操作指令和所述CPU的访问地址信息，从所述第三协议格式的访问请求消息中获取所述操作指令和所述CPU的访问地址信息，根据所述操作指令和所述CPU的访问地址信息对所述存储模块中的存储单元进行访问。
  2. 根据权利要求1所述的NVMe存储设备，其特征在于，所述第二协议格式是以太网协议或光线通道协议。
  3. 根据权利要求1或2所述的NVMe存储设备，其特征在于，该设备还包括交换模块，所述交换模块与至少一个所述存储模块相连接，所述PCIe协议格式的访问请求消息中还包含所述CPU所要访问的NVMe存储模块的设备标识信息；
    所述控制模块，还用于根据所述PCIe协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备标识信息，确定所述CPU所要访问的NVMe存储模块的设备地址信息，并将所述CPU所要访问的NVMe存储模块的设备地址信息承载于所述第二协议格式的访问请求消息中；
    所述交换模块，用于接收所述控制模块发送的所述第二协议格式的访问请求消息，根据所述第二协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备地址信息，将所述第二协议格式的访问请求消息转发至所述CPU所要访问的存储模块。
  4. 根据权利要求3所述的NVMe存储设备，其特征在于，所述控制模块具体用于：
    根据所述PCIe协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备标识信息，以及地址映射关系表，确定所述CPU所要访问的NVMe存储模块的设备地址信息，其中，所述地址映射关系表用于保存至少一个所述存储模块的设备标识与设备地址的对应关系。
  5. 一种访问NVMe存储设备的方法，其特征在于，该方法应用于一种NVMe存储设备，该设备包括控制模块和存储模块，其中，所述控制模块与中央处理器CPU通过高速外围组件互联PCIe总线相连，该方法包括：
    所述控制模块接收所述CPU发送的PCIe协议格式的访问请求消息，所述PCIe协议格式的访问请求消息中包含操作指令和所述CPU的访问地址信息；
    所述控制模块将所述PCIe协议格式的访问请求消息转换为第二协议格式的访问请求消息，所述第二协议格式的访问请求消息中包含所述操作指令和所述CPU的访问地址信息；
    所述控制模块将所述第二协议格式的访问请求消息发送至所述存储模块；
    所述存储模块接收所述第二协议格式的访问请求消息，并将所述第二协议格式的访问请求消息转换为第三协议格式的访问请求消息，其中，所述第三协议格式的访问请求消息中包含所述操作指令和所述CPU的访问地址信息；
    所述存储模块从所述第三协议格式的访问请求消息中获取所述操作指令和所述CPU的访问地址信息，根据所述操作指令和所述CPU的访问地址信息对存储模块中的存储单元进行访问。
  6. 根据权利要求5所述的方法，其特征在于，所述第二协议格式是以太网协议或光线通道协议。
  7. 根据权利要求5或6所述的方法，其特征在于，所述NVMe存储设备还包括交换模块，所述交换模块与至少一个所述存储模块相连接，所述PCIe协议格式的访问请求消息中还包含所述CPU所要访问的NVMe存储模块的设备标识信息，在所述控制模块接收所述CPU 发送的所述PCIe协议格式的访问请求消息之后，该方法还包括：
    所述控制模块根据所述PCIe协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备标识信息，确定所述CPU所要访问的NVMe存储模块的设备地址信息，并将所述CPU所要访问的NVMe存储模块的设备地址信息承载于所述第二协议格式的访问请求消息中；
    所述控制模块将所述第二协议格式的访问请求消息发送至所述交换模块；
    所述交换模块接收所述控制模块发送的所述第二协议格式的访问请求消息，根据所述第二协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备地址信息，将所述第二协议格式的访问请求消息转发至所述CPU所要访问的存储模块。
  8. 根据权利要求7所述的方法，其特征在于，所述控制模块根据所述PCIe协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备标识信息，确定所述CPU所要访问的NVMe存储模块的设备地址信息具体包括：
    所述控制模块根据所述PCIe协议格式的访问请求消息中的所述CPU所要访问的NVMe存储模块的设备标识信息，以及地址映射关系表，确定所述CPU所要访问的NVMe存储模块的设备地址信息，其中，所述地址映射关系表用于保存至少一个所述存储模块的设备标识与设备地址的对应关系。
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