WO2015186170A1

WO2015186170A1 - Calculation circuit diagnostic device and calculation circuit diagnostic program

Info

Publication number: WO2015186170A1
Application number: PCT/JP2014/064598
Authority: WO
Inventors: 怜也市岡
Original assignee: 三菱電機株式会社
Priority date: 2014-06-02
Filing date: 2014-06-02
Publication date: 2015-12-10

Abstract

A reference calculation unit (120) calculates the result of a first reference calculation expression by use of a first reference circuit which is one of a plurality of calculation circuits provided to a CPU (101), and with which it is possible to correctly calculate the result of a calculation expression. A diagnostic calculation unit (130) calculates the result of a first diagnostic calculation expression by use of a first circuit to be diagnosed, which is a calculation circuit to be diagnosed and is selected from among the plurality of calculation circuits provided to the CPU, said first diagnostic calculation expression having the same result as the first reference calculation expression. A calculation circuit diagnostic unit (140) compares the calculated result of the first diagnostic calculation expression, as calculated by the diagnostic calculation unit, with the calculated result of the first reference calculation expression, as calculated by the reference calculation unit, and determines, on the basis of the comparison result, whether the first circuit to be diagnosed is a calculation circuit with which it is possible to correctly calculate the result of a calculation expression.

Description

Arithmetic circuit diagnostic device and arithmetic circuit diagnostic program

The present invention relates to a technique for diagnosing an arithmetic circuit.

Conventionally, an arithmetic unit provided in a CPU (Central Processing Unit) has been diagnosed using a technique called walking-bit. Walking-bit is a method in which the input value is changed bit by bit, and it is determined whether an expected value for the input value is obtained for each input value. If the expected value for at least one of the input values cannot be obtained, it is determined that the arithmetic unit is out of order. Walking-bit is disclosed in Non-Patent Document 1.

When all the arithmetic units of the CPU are diagnosed by walking-bit, there is a problem that the total data size of expected values becomes enormous.
For example, when an adder that performs the operation “add R1 R2” is diagnosed by walking-bit, the same number of expected values as the number of R1 patterns multiplied by the number of R2 patterns is required. That is, if R1 is 34 patterns and R2 is 34 patterns, 1156 (= 34 × 34) expected values are required. If the data size of one expected value is 32 bits, the total data size of the expected values is about 4 kilobytes (= 1156 × 32 bits).
Further, the CPU includes a plurality of adders, and each adder has a plurality of addressing modes. Therefore, when trying to diagnose all the arithmetic units of the CPU, the total data size of expected values reaches several hundred kilobytes. In this case, since all expected values cannot be stored in a system with a limited storage capacity such as an embedded system, the walking-bit cannot be applied.

JP 2007-047993 A JP 2002-318706 A Japanese Patent Laid-Open No. 11-085554 JP 62-206642 A

An object of the present invention is to reduce the storage capacity necessary for diagnosing an arithmetic circuit.

The arithmetic circuit diagnostic apparatus of the present invention is
Using a first reference circuit that is an arithmetic circuit that obtains a correct calculation result, a reference calculation unit that calculates a first reference calculation expression;
Using a first diagnostic circuit that is an arithmetic circuit to be diagnosed, a diagnostic arithmetic unit that calculates a first diagnostic arithmetic expression that obtains the same arithmetic result as the first reference arithmetic expression;
The operation result of the first diagnostic operation expression calculated by the diagnosis operation unit is compared with the operation result of the first reference operation expression calculated by the reference operation unit, and the first result is calculated based on the comparison result. And an arithmetic circuit diagnostic unit that determines whether the diagnostic circuit is an arithmetic circuit that can obtain a correct arithmetic result.

According to the present invention, another arithmetic circuit can be diagnosed using an arithmetic circuit that can obtain a correct arithmetic result. As a result, it is not necessary to store an expected value to be compared with the calculation result of another arithmetic circuit, and the storage capacity necessary for diagnosing the other arithmetic circuit is reduced.

1 is a configuration diagram of an embedded system 100 according to Embodiment 1. FIG. 3 is a diagram illustrating a plurality of arithmetic circuits provided in the CPU 101 in Embodiment 1. FIG. 3 is a flowchart illustrating arithmetic circuit diagnosis processing of the embedded system 100 according to the first embodiment. Is a table showing the relationship between the operation result of the arithmetic operation result and diagnostic calculating formula Z ₂ reference arithmetic expression Z ₁ in the first embodiment. 3 is a diagram illustrating a relationship among a plurality of arithmetic circuits in Embodiment 1. FIG. 2 is a hardware configuration diagram of the embedded system 100 according to Embodiment 1. FIG.

Embodiment 1 FIG.
A mode for reducing the storage capacity necessary for diagnosing the arithmetic circuit will be described.

FIG. 1 is a configuration diagram of an embedded system 100 according to the first embodiment.
The configuration of the embedded system 100 in the first embodiment will be described with reference to FIG. However, the configuration of the embedded system 100 may not be the same as the configuration shown in FIG.

The embedded system 100 (an example of a logic circuit diagnostic device) is a computer that is embedded in an electronic device such as a home appliance or an FA device, and is an example of an information processing device that performs information processing by the CPU 101. FA is an abbreviation for Factory Automation.
The embedded system 100 includes a CPU 101, a basic circuit diagnosis unit 110, a reference operation unit 120, a diagnosis operation unit 130, an operation circuit diagnosis unit 140, a diagnosis result output unit 150, and a diagnosis storage unit 190.

The CPU 101 includes a plurality of arithmetic circuits that perform different types of operations such as four arithmetic operations, logical operations, and shift operations. The arithmetic circuit is also called an arithmetic unit or an arithmetic device.

The basic circuit diagnosis unit 110 calculates a reference arithmetic expression using a reference circuit. Then, the basic circuit diagnosis unit 110 determines whether the reference circuit is a normal operation circuit that can obtain a correct operation result based on the operation result of the reference operation expression.
The reference circuit is a predetermined arithmetic circuit among a plurality of arithmetic circuits provided in the CPU 101.
The reference arithmetic expression is an arithmetic expression including an operation performed by the reference circuit. The reference arithmetic expression is determined in advance.

The reference arithmetic unit 120 calculates a reference arithmetic expression using a reference circuit.
The reference circuit is a basic circuit that is determined by the basic circuit diagnosis unit 110 to be a normal arithmetic circuit.
The reference arithmetic expression is an arithmetic expression including an operation performed by the reference circuit or an arithmetic expression including an operation performed by the reference circuit. The reference arithmetic expression is determined in advance.

The diagnostic calculation unit 130 calculates a diagnostic calculation formula using a diagnostic circuit.
The diagnostic circuit is an arithmetic circuit for diagnosing whether a correct arithmetic result is obtained from among a plurality of arithmetic circuits provided in the CPU 101.
The diagnosis arithmetic expression is an arithmetic expression that obtains the same operation result as the reference arithmetic expression. The diagnostic arithmetic expression is an arithmetic expression including an arithmetic operation performed by the diagnostic circuit or an arithmetic expression including an arithmetic operation performed by the diagnostic circuit. The diagnostic calculation formula is determined in advance.

The arithmetic circuit diagnosis unit 140 compares the operation result of the diagnostic operation expression calculated by the diagnosis operation unit 130 with the operation result of the reference operation expression calculated by the reference operation unit 120, and correct operation of the diagnosis circuit based on the comparison result It is determined whether the result is a normal arithmetic circuit that can obtain a result.

The diagnosis result output unit 150 outputs the diagnosis results of a plurality of arithmetic circuits provided in the CPU 101 based on the determination result of the determination by the arithmetic circuit diagnosis unit 140.
For example, when all the arithmetic circuits are normal arithmetic circuits, the diagnostic result output unit 150 outputs a message indicating that all the arithmetic circuits are operating normally as a diagnostic result.
For example, when the first arithmetic circuit is not a normal arithmetic circuit but an abnormal arithmetic circuit, the diagnostic result output unit 150 outputs a message indicating that the first arithmetic circuit has failed as a diagnostic result.

The diagnostic storage unit 190 stores data used, generated, or input / output by the embedded system 100.
For example, the diagnosis storage unit 190 stores a reference calculation result 191, a diagnosis calculation result 192, a diagnosis result file 193, an expected value table 199, and the like.
The reference calculation result 191 is data indicating the calculation result of the reference calculation expression calculated by the reference calculation unit 120.
The diagnostic calculation result 192 is data indicating the calculation result of the diagnostic calculation formula calculated by the diagnostic calculation unit 130.
The diagnosis result file 193 is data indicating the diagnosis result.
The expected value table 199 is data used for diagnosing the basic circuit. The expected value table 199 includes the correct operation result (expected value) of the operation expression in association with the input value (operand) input to the operation circuit. The input value corresponds to an assigned value to be assigned to the arithmetic expression.

FIG. 2 is a diagram illustrating a plurality of arithmetic circuits provided in the CPU 101 in the first embodiment.
A plurality of arithmetic circuits provided in the CPU 101 in Embodiment 1 will be described with reference to FIG. However, the CPU 101 may include arithmetic circuits other than the plurality of arithmetic circuits illustrated in FIG. Further, the CPU 101 may not include at least one of the arithmetic circuits illustrated in FIG.

The CPU 101 includes an addition circuit 201, a subtraction circuit 202, a multiplication circuit 203, and a division circuit 204. These are arithmetic circuits that perform four arithmetic operations.
The adder circuit 201 is an arithmetic circuit that performs addition.
The subtraction circuit 202 is an arithmetic circuit that performs subtraction.
The multiplication circuit 203 is an arithmetic circuit that performs multiplication.
The division circuit 204 is an arithmetic circuit that performs division.

The CPU 101 includes an OR circuit 211, an AND circuit 212, an exclusive OR circuit 213, a logic NOT circuit 214, and a sign inversion circuit 215. These are arithmetic circuits that perform logical operations.
The logical sum circuit 211 is an arithmetic circuit for obtaining a logical sum.
The logical product circuit 212 is an arithmetic circuit for obtaining a logical product.
The exclusive OR circuit 213 is an arithmetic circuit for obtaining an exclusive OR.
The logical negation circuit 214 is an arithmetic circuit that performs logical negation that inverts a bit value included in a bit string representing a binary value.
The sign inversion circuit 215 is an arithmetic circuit that performs sign inversion to invert the bit value of the sign bit in the bit string including the sign bit representing the sign (positive or negative). The sign bit is the most significant bit (leftmost bit).

The CPU 101 includes a left shift circuit 221, an arithmetic right shift circuit 222, and a logical right shift circuit 223. These are arithmetic circuits for performing a shift operation.
The left shift circuit 221 is an arithmetic circuit that performs a left shift that shifts a bit value included in a bit string to the left.
The arithmetic right shift circuit 222 is an arithmetic circuit that performs an arithmetic right shift that shifts the bit value included in the bit string to the right except the bit value of the sign bit.
The logical right shift circuit 223 is an arithmetic circuit that performs a logical right shift that shifts the bit value included in the bit string including the bit value of the sign bit to the right.

FIG. 3 is a flowchart showing arithmetic circuit diagnosis processing of the embedded system 100 according to the first embodiment.
An arithmetic circuit diagnosis process of the embedded system 100 according to the first embodiment will be described with reference to FIG. However, the arithmetic circuit diagnosis process may not be the same as the process shown in FIG.

In S101, the basic circuit diagnosis unit 110 calculates an addition operation expression using the adder circuit 201, and determines whether the adder circuit 201 is a normal operation circuit based on the operation result.
The addition arithmetic expression is an arithmetic expression including addition, and is an example of a reference arithmetic expression. The adder circuit 201 is an example of a basic circuit.
For example, the basic circuit diagnosis unit 110 determines whether the adder circuit 201 is a normal arithmetic circuit by a technique called walking-bit. Non-patent document 1 discloses the walking-bit.

For example, the basic circuit diagnosis unit 110 determines whether the adder circuit 201 is a normal arithmetic circuit as follows.
The basic circuit diagnosis unit 110 inputs an input value to the adder circuit 201 to cause the adder circuit 201 to calculate an addition operation expression.
The basic circuit diagnosis unit 110 acquires the expected value associated with the input value from the expected value table 199.
The basic circuit diagnosis unit 110 compares the operation result obtained by the adder circuit 201 with the acquired expected value, and determines whether the adder circuit 201 is a normal operation circuit based on the comparison result.
When the calculation result is the same as the expected value, the addition circuit 201 is a normal calculation circuit. When the calculation result is different from the expected value, the adding circuit 201 is not a normal calculation circuit but a failed calculation circuit (abnormal calculation circuit).

The basic circuit diagnosis unit 110 may generate a plurality of input values by a technique called walking-bit. When a technique called walking-bit is used, a plurality of input values are generated by shifting a bit having a bit value of 1. The basic circuit diagnosis unit 110 may acquire an input value from the expected value table 199 or the like.
When the calculation result is the same as the expected value for all input values, the adder circuit 201 is a normal calculation circuit. When the calculation result is different from the expected value in at least one of the input values, the addition circuit 201 is not a normal calculation circuit.
This is the end of the description of S101.

In S102, the basic circuit diagnosis unit 110 calculates a logical negation expression using the logic negation circuit 214, and determines whether the logic negation circuit 214 is a normal computation circuit based on the computation result.
The logical negation arithmetic expression is an arithmetic expression including logical negation, and is an example of a reference arithmetic expression. The logic negation circuit 214 is an example of a basic circuit.
The method for determining whether the logical negation circuit 214 is a normal arithmetic circuit is the same as the method for determining whether the adder circuit 201 is a normal arithmetic circuit in S101.
This is the end of the description of S102.

In S103, the basic circuit diagnosis unit 110 calculates a logical sum operation expression using the logical sum circuit 211, and determines whether the logical sum circuit 211 is a normal arithmetic circuit based on the calculation result.
The logical sum arithmetic expression is an arithmetic expression composed of logical sum and is an example of a reference arithmetic expression. The OR circuit 211 is an example of a basic circuit.
The method for determining whether the OR circuit 211 is a normal arithmetic circuit is the same as the method for determining whether the adder circuit 201 is a normal arithmetic circuit in S101.
This is the end of the description of S103.

S101 to S103 may be in any order.
After S101 to S103 are completed, the process proceeds from S111 to S114.
However, if it is determined in S101 that the adding circuit 201 is not a normal arithmetic circuit, the process does not proceed to S111 and S112.
If it is determined in S102 that the logical negation circuit 214 is not a normal arithmetic circuit, the process does not proceed to S112, S113, and S114.
If it is determined in S103 that the OR circuit 211 is not a normal arithmetic circuit, the process does not proceed to S114.
If the process does not proceed to any of S111 to S114, the process proceeds to S190.

In S111, the reference operation unit 120 inputs the input value (X, Y) to the adder circuit 201 (an example of the first reference circuit), thereby causing the adder circuit 201 to input a reference operation expression for the multiplier circuit (first An example of a reference arithmetic expression) is calculated. The adder circuit 201 is a normal arithmetic circuit.
Further, the diagnostic operation unit 130 inputs the same input value as the input value input to the addition circuit 201 to the multiplication circuit 203 (an example of the first diagnosis circuit), thereby causing the multiplication circuit 203 to perform a diagnostic operation for the multiplication circuit. An expression (an example of a first diagnostic calculation expression) is calculated. The diagnostic arithmetic expression for the multiplication circuit is an arithmetic expression that obtains the same calculation result as the reference arithmetic expression for the multiplication circuit.
Then, the arithmetic circuit diagnosis unit 140 compares the operation result obtained by the reference operation unit 120 with the operation result obtained by the diagnosis operation unit 130, and whether the multiplication circuit 203 is a normal operation circuit based on the comparison result. judge.
When the calculation result obtained by the reference calculation unit 120 is the same as the calculation result obtained by the diagnosis calculation unit 130, the multiplication circuit 203 is a normal calculation circuit.

The reference calculation unit 120 may generate a plurality of input values by a technique called walking-bit. Non-patent document 1 discloses the walking-bit.
When the calculation results obtained by the reference calculation unit 120 are the same as the calculation results obtained by the diagnosis calculation unit 130 for all input values, the multiplication circuit 203 is a normal calculation circuit. When the operation result obtained by the reference operation unit 120 differs from the operation result obtained by the diagnosis operation unit 130 for at least one of the input values, the multiplication circuit 203 is not a normal operation circuit.

For example, the reference arithmetic expression for the multiplication circuit is an arithmetic expression for obtaining a value obtained by adding the Y values X by addition. This reference arithmetic expression is represented by X + X +. However, the number of X is Y.
For example, the diagnostic arithmetic expression for the multiplication circuit is an arithmetic expression for obtaining a value obtained by multiplying the value X by the value Y by multiplication. This diagnostic arithmetic expression is represented by X * Y.
In this case, as shown in FIG. 4, X * Y = X + X +... + X holds regardless of the values of X and Y. In other words, the diagnostic arithmetic expression for the multiplier circuit is an arithmetic expression that can obtain the same arithmetic result as the reference arithmetic expression for the multiplier circuit. In FIG. 4, “nnnnb” means that “nnnn” is a binary value.
Figure 4 is a table showing a relationship between the operation result of the arithmetic operation result and diagnostic calculating formula Z ₂ reference arithmetic expression Z ₁ in the first embodiment.

In S112, the reference calculation unit 120 adds the input values (X, Y) to the addition circuit 201 (an example of the first reference circuit) or the logical negation circuit 214 (an example of the second reference circuit). The circuit 201 and the logic negation circuit 214 are caused to calculate a reference arithmetic expression (an example of a first reference arithmetic expression) for the subtraction circuit. The adder circuit 201 and the logic negation circuit 214 are normal arithmetic circuits.
The diagnostic operation unit 130 also subtracts the subtraction circuit 202 by inputting the same input value as the input value input to the addition circuit 201 or the logical negation circuit 214 to the subtraction circuit 202 (an example of the first diagnosis circuit). A diagnostic arithmetic expression for the circuit (an example of a first diagnostic arithmetic expression) is calculated. The diagnostic arithmetic expression for the subtraction circuit is an arithmetic expression that obtains the same operation result as the reference arithmetic expression for the subtraction circuit.
Then, the arithmetic circuit diagnosis unit 140 compares the operation result obtained by the reference operation unit 120 with the operation result obtained by the diagnosis operation unit 130, and whether the subtraction circuit 202 is a normal operation circuit based on the comparison result. judge.
When the calculation result obtained by the reference calculation unit 120 is the same as the calculation result obtained by the diagnosis calculation unit 130, the subtraction circuit 202 is a normal calculation circuit.

The reference calculation unit 120 and the diagnosis calculation unit 130 may generate a plurality of input values by a technique called walking-bit (similar to S111).

For example, the reference arithmetic expression for the subtraction circuit obtains the value obtained by inverting the sign of the value Y by obtaining the one's complement of the value Y by logical negation and adding 1 to the one's complement of the value Y. This is an arithmetic expression for obtaining a value obtained by subtracting the value Y from the value X by adding a value obtained by inverting the sign of the value Y to X. This reference arithmetic expression is represented by X + (^ Y + 1). However, ^ Y means the logical negation of Y, that is, the one's complement of Y. The one's complement of the value Y is a value represented by a bit string obtained by inverting the bit value included in the bit string representing the value Y in binary. The value obtained by inverting the sign of the value Y is a value corresponding to the two's complement of the value Y.
For example, the diagnostic arithmetic expression for the subtraction circuit is an arithmetic expression for obtaining a value obtained by subtracting the value Y from the value X by subtraction. This diagnostic arithmetic expression is represented by XY.
In this case, XY = X + (^ Y + 1) holds. That is, the diagnostic calculation formula for the subtraction circuit is a calculation formula that can obtain the same calculation result as the reference calculation formula for the subtraction circuit.

In S113, the reference operation unit 120 inputs the input value (X) to the logic negation circuit 214 (an example of the first reference circuit), whereby the reference operation expression for the sign inverting circuit (first An example of the reference calculation formula is calculated. The logic negation circuit 214 is a normal arithmetic circuit.
Further, the diagnostic operation unit 130 inputs the same input value as the input value input to the logic negation circuit 214 to the sign inversion circuit 215 (an example of the first diagnosis circuit), whereby the sign inversion circuit 215 receives the sign inversion circuit. Diagnostic calculation formula (an example of the first diagnostic calculation formula) is calculated. The diagnostic arithmetic expression for the sign inversion circuit is an arithmetic expression that can obtain the same operation result as the reference arithmetic expression for the sign inversion circuit.
The arithmetic circuit diagnosis unit 140 compares the operation result obtained by the reference operation unit 120 with the operation result obtained by the diagnosis operation unit 130, and the sign inversion circuit 215 is a normal operation circuit based on the comparison result. To determine.
When the calculation result obtained by the reference calculation unit 120 is the same as the calculation result obtained by the diagnosis calculation unit 130, the sign inversion circuit 215 is a normal calculation circuit.

For example, the reference arithmetic expression for the sign inverting circuit is an arithmetic expression that obtains a value obtained by inverting the sign of the value X by obtaining the one's complement of the value X by logical negation and adding 1 to the one's complement of the value X. It is. This reference arithmetic expression is represented by (^ X + 1).
For example, the diagnostic arithmetic expression for the sign inversion circuit is an arithmetic expression for obtaining a value obtained by inverting the sign of the value X by sign inversion. This diagnostic arithmetic expression is represented by NEG X. However, NEG means sign inversion.
In this case, NEG X = (^ X + 1) holds. That is, the diagnostic arithmetic expression for the sign inversion circuit is an arithmetic expression that obtains the same operation result as the reference arithmetic expression for the sign inversion circuit.

In S114, the reference operation unit 120 inputs the input values (X, Y) to the logical NOT circuit 214 (an example of the first reference circuit) or the logical sum circuit 211 (an example of the second reference circuit). The logical negation circuit 214 and the logical sum circuit 211 are caused to calculate a reference arithmetic expression (an example of a first reference arithmetic expression) for the AND circuit. The logical negation circuit 214 and the logical sum circuit 211 are normal arithmetic circuits.
Further, the diagnostic operation unit 130 inputs the same input value as the input value input to the logical NOT circuit 214 or the logical sum circuit 211 to the logical product circuit 212 (an example of the first diagnostic circuit). 212 is caused to calculate a diagnostic operation expression for the AND circuit (an example of the first diagnosis operation expression). A diagnostic operation expression for an AND circuit is an operation expression that obtains the same operation result as a reference operation expression for an AND circuit.
Then, the arithmetic circuit diagnosis unit 140 compares the operation result obtained by the reference operation unit 120 with the operation result obtained by the diagnosis operation unit 130, and the logical product circuit 212 is a normal operation circuit based on the comparison result. To determine.
When the calculation result obtained by the reference calculation unit 120 is the same as the calculation result obtained by the diagnosis calculation unit 130, the sign inversion circuit 215 is a normal calculation circuit.

For example, the reference arithmetic expression for the logical product circuit calculates the logical sum of the X bit string representing the value X and the Y bit string representing the value Y, and inverts the bit value included in the logical sum bit string representing the obtained logical sum. This is an arithmetic expression for obtaining a bit string by logical negation. This reference arithmetic expression is represented by ^ (A OR B). However, OR means logical sum.
For example, a diagnostic operation expression for a logical product circuit obtains an inverted X bit string obtained by inverting a bit value included in an X bit string and an inverted Y bit string obtained by inverting a bit value included in a Y bit string by logical negation, and an inverted X bit string. Is an arithmetic expression for obtaining the logical product of the inverted Y bit string. This diagnostic arithmetic expression is represented by (^ A) AND (^ B). However, AND means a logical product.
In this case, (^ A) AND (^ B) = ^ (A OR B) holds. In other words, the logical AND circuit diagnostic arithmetic expression is an arithmetic expression that obtains the same operation result as the AND circuit reference arithmetic expression.

S111 to S114 may be out of order.
After S111 to S114 are completed, the process proceeds from S121 to S123.
However, if it is determined in S111 that the multiplication circuit 203 is not a normal arithmetic circuit, the process does not proceed to S121.
If it is determined in S112 that the subtraction circuit 202 is not a normal arithmetic circuit, the process does not proceed to S122.
If it is determined in S114 that the logical product circuit 212 is not a normal arithmetic circuit, the process does not proceed to S123.
If the process does not proceed to any of S121 to S123, the process proceeds to S190.

In S121, the reference calculation unit 120 inputs the input value (X, Y) to the multiplication circuit 203 (an example of the first diagnostic circuit or the first reference circuit), thereby causing the multiplication circuit 203 to use the left shift circuit. A reference arithmetic expression (second reference arithmetic expression or an example of the first reference arithmetic expression) is calculated. The multiplier circuit 203 is a normal arithmetic circuit.
In addition, the diagnostic operation unit 130 inputs the same input value as the input value input to the multiplication circuit 203 to the left shift circuit 221 (second diagnostic circuit or an example of the first diagnostic circuit), whereby the left shift circuit 221 causes the left shift circuit diagnostic arithmetic expression (second diagnostic arithmetic expression or an example of the first diagnostic arithmetic expression) to be calculated. The diagnostic operation expression for the left shift circuit is an operation expression that obtains the same operation result as the reference operation expression for the left shift circuit.
The arithmetic circuit diagnosis unit 140 compares the operation result obtained by the reference operation unit 120 with the operation result obtained by the diagnosis operation unit 130, and the left shift circuit 221 is a normal operation circuit based on the comparison result. To determine.
When the calculation result obtained by the reference calculation unit 120 is the same as the calculation result obtained by the diagnosis calculation unit 130, the left shift circuit 221 is a normal calculation circuit.

For example, the reference arithmetic expression for the left shift circuit is an arithmetic expression that obtains a value obtained by multiplying a value X by a power of 2 to a value obtained by multiplying the value X by a power of 2 to the Y power. This reference arithmetic expression is represented by X * 2 ^ Y. However, 2 ^ Y means 2 to the power of Y.
For example, the diagnostic arithmetic expression for the left shift circuit is an arithmetic expression for obtaining a value represented by a bit string obtained by shifting the bit string representing the value X to the left by Y bits by left shift. This diagnostic arithmetic expression is represented by X << Y. However, X << Y means that the bit string representing the value X is shifted to the left by Y bits.
In this case, X << Y = X * 2 ^ Y holds. In other words, the diagnostic calculation formula for the left shift circuit is a calculation formula that obtains the same calculation result as the reference calculation formula for the left shift circuit.

In S122, the reference operation unit 120 inputs the input value (X, Y) to the subtraction circuit 202 (an example of the first diagnostic circuit or the first reference circuit), thereby causing the subtraction circuit 202 to reference the division circuit. An arithmetic expression (second reference arithmetic expression or an example of the first reference arithmetic expression) is calculated. The subtraction circuit 202 is a normal arithmetic circuit.
Further, the diagnostic operation unit 130 inputs the same input value as the input value input to the subtracting circuit 202 to the dividing circuit 204 (second diagnostic circuit or an example of the first diagnostic circuit), whereby the dividing circuit 204 is input. A diagnostic arithmetic expression for the division circuit (an example of the second diagnostic arithmetic expression or the first diagnostic arithmetic expression) is calculated. The diagnostic arithmetic expression for the divider circuit is an arithmetic expression that obtains the same calculation result as the reference arithmetic expression for the divider circuit.
Then, the arithmetic circuit diagnosis unit 140 compares the operation result obtained by the reference operation unit 120 with the operation result obtained by the diagnosis operation unit 130, and whether the division circuit 204 is a normal operation circuit based on the comparison result. judge.
When the calculation result obtained by the reference calculation unit 120 is the same as the calculation result obtained by the diagnosis calculation unit 130, the division circuit 204 is a normal calculation circuit.

For example, the reference arithmetic expression for the division circuit is an arithmetic expression for obtaining a value representing the number of times the value Y can be subtracted from the value X by subtraction. This reference arithmetic expression is represented by (XY−Y... −Y). However, (XY−Y... −Y) means that the number of times that the value Y can be subtracted from the value X is counted.
For example, the diagnostic arithmetic expression for the division circuit is an arithmetic expression for obtaining a quotient obtained by dividing the value X by the value Y by division. This diagnostic arithmetic expression is represented by X / Y.
In this case, X / Y = (XY−Y... −Y) holds. That is, the diagnostic arithmetic expression for the divider circuit is an arithmetic expression that can obtain the same calculation result as the reference arithmetic expression for the divider circuit.

In S123, the reference operation unit 120 performs an AND circuit 212 (an example of a first diagnostic circuit), a logical NOT circuit 214 (an example of a first reference circuit), or an OR circuit 211 (an example of a second reference circuit). By inputting the input value (X, Y) into the logical product circuit 212, the logical negation circuit 214, and the logical sum circuit 211, the reference arithmetic expression for the exclusive OR circuit (an example of the second reference arithmetic expression) is provided. Calculate. The logical product circuit 212, the logical NOT circuit 214, and the logical sum circuit 211 are normal arithmetic circuits.
In addition, the diagnostic operation unit 130 inputs the same input value as the input value input to the logical product circuit 212, the logical NOT circuit 214, or the logical sum circuit 211 to the exclusive OR circuit 213 (an example of a second diagnostic circuit). By doing so, the exclusive OR circuit 213 is caused to calculate a diagnostic operation expression for the exclusive OR circuit (an example of the second diagnosis operation expression). The diagnostic operation expression for the exclusive OR circuit is an operation expression that obtains the same operation result as the reference operation expression for the exclusive OR circuit.
Then, the arithmetic circuit diagnostic unit 140 compares the arithmetic result obtained by the reference arithmetic unit 120 with the arithmetic result obtained by the diagnostic arithmetic unit 130, and the exclusive OR circuit 213 is a normal arithmetic circuit based on the comparison result. It is determined whether it is.
When the calculation result obtained by the reference calculation unit 120 is the same as the calculation result obtained by the diagnosis calculation unit 130, the exclusive OR circuit 213 is a normal calculation circuit.

For example, a reference arithmetic expression for an exclusive OR circuit obtains an inverted X bit string and an inverted Y bit string by logical negation, obtains a first AND bit string and a second AND bit string, This is an arithmetic expression for obtaining a logical sum of a logical product bit string and a second logical product bit string. The inverted X bit string is a bit string obtained by inverting the bit value included in the X bit string representing the value X, and the inverted Y bit string is a bit string obtained by inverting the bit value included in the Y bit string representing the value Y. The first AND bit string is a bit string that represents the logical product of the X bit string and the inverted Y bit string, and the second AND bit string is a bit string that represents the logical product of the inverted X bit string and the Y bit string. This reference arithmetic expression is represented by (X AND ^ Y) OR (^ X AND Y).
In this case, the diagnostic arithmetic expression for the exclusive OR circuit is an arithmetic expression for obtaining an exclusive OR of the X bit string and the Y bit string. This diagnostic arithmetic expression is represented by X XOR Y. However, XOR means exclusive OR.
In this case, X XOR Y = (X AND ^ Y) OR (^ X AND Y) holds. That is, the diagnostic operation expression for the exclusive OR circuit is an operation expression that obtains the same operation result as the reference operation expression for the exclusive OR circuit.

S121 to S123 may be out of order.
After S121 to S123 are completed, the process proceeds to S131.
However, if it is determined in S122 that the division circuit 204 is not a normal arithmetic circuit, the process proceeds to S190 instead of S131.

In S131, the reference calculation unit 120 inputs input values (X, X, D) to the division circuit 204 (an example of the second diagnostic circuit or the first reference circuit) or the multiplication circuit 203 (an example of the normal calculation circuit or the second reference circuit). By inputting (Y), the division circuit 204 and the multiplication circuit 203 are caused to calculate the reference arithmetic expression (an example of the third reference arithmetic expression or the first reference arithmetic expression) for the arithmetic right shift circuit. The division circuit 204 and the multiplication circuit 203 are normal arithmetic circuits.
In addition, the diagnostic calculation unit 130 inputs the same input value as the input value input to the division circuit 204 or the multiplication circuit 203 to the arithmetic right shift circuit 222 (an example of the third diagnosis circuit or the first reference circuit). Thus, the arithmetic right shift circuit 222 is caused to calculate a diagnostic arithmetic expression for the arithmetic right shift circuit (a third diagnostic arithmetic expression or an example of the first diagnostic arithmetic expression). The diagnostic arithmetic expression for the arithmetic right shift circuit is an arithmetic expression that obtains the same operation result as the reference arithmetic expression for the arithmetic right shift circuit.
Then, the arithmetic circuit diagnosis unit 140 compares the operation result obtained by the reference operation unit 120 with the operation result obtained by the diagnosis operation unit 130, and based on the comparison result, the arithmetic right shift circuit 222 is a normal operation circuit. Determine if there is.
When the calculation result obtained by the reference calculation unit 120 is the same as the calculation result obtained by the diagnosis calculation unit 130, the arithmetic right shift circuit 222 is a normal calculation circuit.

For example, the reference arithmetic expression for the arithmetic right shift circuit is an arithmetic expression that obtains a quotient obtained by dividing the value X by 2 to the Y power by obtaining 2 to the Y power by division. This reference arithmetic expression is represented by X / (2 ^ Y).
For example, a diagnostic arithmetic expression for an arithmetic right shift circuit is an arithmetic expression that obtains a value represented by a bit string obtained by shifting a bit string representing a value X to the right by Y bits excluding a sign bit representing a sign of the value X by arithmetic right shift. . This diagnostic arithmetic expression is represented by X SHARY Y. However, SHA means arithmetic right shift.
In this case, X SHARY Y = X / (2 ^ Y) holds. That is, the diagnostic arithmetic expression for the arithmetic right shift circuit is an arithmetic expression that obtains the same arithmetic result as the reference arithmetic expression for the arithmetic right shift circuit.
After S131, the process proceeds to S141. However, if it is determined in S131 that the arithmetic right shift circuit 222 is not a normal arithmetic circuit, the process proceeds to S190 instead of S141.

In S <b> 141, the reference operation unit 120 transfers the arithmetic right shift circuit 222 (an example of the third diagnostic circuit or the first reference circuit) or the exclusive OR circuit 213 (an example of the normal operation circuit or the second reference circuit). By inputting the input values (X, Y), the arithmetic right shift circuit 222 and the exclusive OR circuit 213 receive the reference arithmetic expression (fourth reference arithmetic expression or first reference arithmetic expression) for the logical right shift circuit. (Example). The arithmetic right shift circuit 222 and the exclusive OR circuit 213 are normal arithmetic circuits.
In addition, the diagnosis operation unit 130 applies the same input value as the input value input to the arithmetic right shift circuit 222 or the exclusive OR circuit 213 to the logical right shift circuit 223 (an example of the fourth diagnosis circuit or the first diagnosis circuit). ) Causes the logical right shift circuit 223 to calculate a logical arithmetic expression for the logical right shift circuit (a fourth diagnostic arithmetic expression or an example of the first diagnostic arithmetic expression). The diagnostic arithmetic expression for the logical right shift circuit is an arithmetic expression that obtains the same arithmetic result as the reference arithmetic expression for the logical right shift circuit.
Then, the arithmetic circuit diagnosis unit 140 compares the operation result obtained by the reference operation unit 120 with the operation result obtained by the diagnosis operation unit 130, and based on the comparison result, the logical right shift circuit 223 is a normal operation circuit. Determine if there is.
When the calculation result obtained by the reference calculation unit 120 is the same as the calculation result obtained by the diagnosis calculation unit 130, the logical right shift circuit 223 is a normal calculation circuit.

For example, the reference arithmetic expression for the logical right shift circuit is an arithmetic expression for obtaining a logical sum of a maximum value bit string and a shift bit string by obtaining a shift bit string by arithmetic right shift. The shift bit string is a bit string obtained by shifting the X bit string representing the value X to the right by Y bits excluding the X code bit representing the sign of the value X. The maximum value bit string is a bit string composed of a sign bit having a bit value of 0 and another bit having a bit value of 1, that is, a bit string representing a positive maximum value. This reference arithmetic expression is represented by (X SHA Y) AND 0x7FFFFFFF. However, 0x7FFFFFFFF means the maximum value bit string.
For example, a diagnostic arithmetic expression for a logical right shift circuit is an arithmetic expression for obtaining a bit string obtained by shifting an X bit string (including an X sign bit) to the right by Y bits by a logical right shift. This diagnostic arithmetic expression is represented by X SHLR Y. However, SHLR means a logical right shift.
In this case, X SHLR Y = (X SHA Y) AND 0x7FFFFFFF holds. That is, the reference arithmetic expression for the logical right shift circuit is an arithmetic expression that obtains the same operation result as the diagnostic arithmetic expression for the logical right shift circuit.
After S141, the process proceeds to S190.

In S190, the diagnosis result output unit 150 outputs the diagnosis results of a plurality of arithmetic circuits included in the CPU 101 based on the determination results of S101 to S141.
After S190, the arithmetic circuit diagnosis process ends.

FIG. 5 is a diagram illustrating a relationship among a plurality of arithmetic circuits in the first embodiment.
In FIG. 5, the arithmetic circuit at the start point of the arrow is a normal arithmetic circuit that calculates the reference arithmetic expression, and the arithmetic circuit at the end point of the arrow is a diagnostic circuit that calculates the diagnostic arithmetic expression.
For example, the adder circuit 201 and the logic negation circuit 214 are arithmetic circuits at the start point of an arrow indicating the subtractor circuit 202, and therefore calculate a reference arithmetic expression for the subtractor circuit. On the other hand, since the subtraction circuit 202 is an arithmetic circuit at the end point of the arrow, it calculates a diagnostic arithmetic expression for the subtraction circuit.

FIG. 6 is a hardware configuration diagram of the embedded system 100 according to the first embodiment.
A hardware configuration of the embedded system 100 according to the first embodiment will be described with reference to FIG. However, the hardware configuration of the embedded system 100 may not be the same as the configuration shown in FIG.

The embedded system 100 is a computer including an arithmetic device 901, an auxiliary storage device 902, a main storage device 903, a communication device 904, and an input / output device 905.
The arithmetic device 901, auxiliary storage device 902, main storage device 903, communication device 904, and input / output device 905 are connected to the bus 909.

The arithmetic device 901 is a CPU (Central Processing Unit) that executes a program.
The auxiliary storage device 902 is, for example, a ROM (Read Only Memory), a flash memory, or a hard disk device.
The main storage device 903 is, for example, a RAM (Random Access Memory).
The communication device 904 performs communication via the Internet, a LAN (local area network), a telephone line network, or other networks in a wired or wireless manner.
The input / output device 905 is, for example, a mouse, a keyboard, or a display device.

The program is stored in the auxiliary storage device 902.
For example, an operating system (OS) is stored in the auxiliary storage device 902. Further, a program for realizing the function described as “˜unit” is stored in the auxiliary storage device 902.
The program is stored in the auxiliary storage device 902, loaded into the main storage device 903, read into the arithmetic device 901, and executed by the arithmetic device 901.

“Determining”, “Determining”, “Extracting”, “Detecting”, “Settings”, “Registering”, “Selecting”, “Generating”, “To” Information, data, files, signal values or variable values indicating the results of processing such as “input”, “output of”, etc. are stored in the main storage device 903 or the auxiliary storage device 902.

In the first embodiment, for example, the following technique has been described.
Embodiment 1 proposes a technique for reducing the storage capacity necessary for storing an expected value. Specifically, two expressions that use different arithmetic circuits with the same result are calculated, and the respective results are compared. If the results match, it is determined that there is no failure, and if the results do not match, it is determined that there is a failure.
However, for the adder circuit 201, the logical NOT circuit 214, and the logical sum circuit 211 that are the basis of all the arithmetic circuits, the expected value of the operation result is stored in the storage unit, the operation result is compared with the expected value, Based on the failure detection. The reason is that it is possible to detect a failure of each arithmetic circuit even when both different arithmetic circuits are faulty and the arithmetic result is the same by chance. By comparing the operation result obtained using the operation circuit that has been confirmed not to be in failure with the operation result obtained using the operation circuit to be diagnosed, both different operation circuits are It is possible to avoid a case where a failure occurs and the calculation result becomes the same by chance, and it is possible to detect a failure of all the operation circuits.

According to the first embodiment, for example, the following effects can be obtained.
A failure of the arithmetic circuit of the CPU 101 can be detected.
The storage capacity for storing the expected value can be reduced.
Since it can be realized by software, it is not necessary to add hardware for diagnosis and can be realized at low cost.
Since it corresponds to general operations such as four arithmetic operations, logical operations, and shift operations, it can be applied to various CPUs 101.

The first embodiment is an example of a form of the embedded system 100.
That is, the embedded system 100 may not include some of the components described in the first embodiment. Further, the embedded system 100 may include components that are not described in the first embodiment.
The embedded system 100 may be a device that diagnoses a plurality of arithmetic circuits included in another computer.
At least one arithmetic circuit other than the adder circuit 201, the logical NOT circuit 214, and the logical sum circuit 211 may be diagnosed by the basic circuit diagnostic unit 110 using the expected value.

The processing procedure described in the first embodiment using a flowchart or the like is an example of the processing procedure of the method and program according to the first embodiment. The method and program according to the first embodiment may be realized by a processing procedure that is partially different from the processing procedure described in the first embodiment.

In the first embodiment, “to part” can be read as “to process”, “to process”, “to program”, “to apparatus”, and the like.

100 embedded system, 101 CPU, 110 basic circuit diagnostic unit, 120 reference arithmetic unit, 130 diagnostic arithmetic unit, 140 arithmetic circuit diagnostic unit, 150 diagnostic result output unit, 190 diagnostic storage unit, 191 reference arithmetic result, 192 diagnostic arithmetic result, 193 diagnosis result file, 199 expected value table, 201 addition circuit, 202 subtraction circuit, 203 multiplication circuit, 204 division circuit, 211 logical sum circuit, 212 logical product circuit, 213 exclusive logical sum circuit, 214 logical negation circuit, 215 code Inversion circuit, 221 left shift circuit, 222 arithmetic right shift circuit, 223 logical right shift circuit, 901 arithmetic device, 902 auxiliary storage device, 903 main storage device, 904 communication device, 905 input / output device, 909 bus.

Claims

Using a first reference circuit that is an arithmetic circuit that obtains a correct calculation result, a reference calculation unit that calculates a first reference calculation expression;
Using a first diagnostic circuit that is an arithmetic circuit to be diagnosed, a diagnostic arithmetic unit that calculates a first diagnostic arithmetic expression that obtains the same arithmetic result as the first reference arithmetic expression;
The operation result of the first diagnostic operation expression calculated by the diagnosis operation unit is compared with the operation result of the first reference operation expression calculated by the reference operation unit, and the first result is calculated based on the comparison result. An arithmetic circuit diagnostic apparatus comprising: an arithmetic circuit diagnosis unit that determines whether the diagnostic circuit is an arithmetic circuit that can obtain a correct arithmetic result.
The first reference circuit is an arithmetic circuit that performs addition,
The first reference arithmetic expression is an arithmetic expression for obtaining a value obtained by adding up Y values X, and
The first diagnostic circuit is an arithmetic circuit that performs multiplication,
The arithmetic circuit diagnosis apparatus according to claim 1, wherein the first diagnostic arithmetic expression is an arithmetic expression for obtaining a value obtained by multiplying the value X by a value Y by multiplication.
The reference calculation unit calculates the first reference calculation expression using the first reference circuit and a second reference circuit from which a correct calculation result is obtained,
The first reference circuit is an arithmetic circuit that performs addition,
The second reference circuit is an arithmetic circuit that performs a logical negation to invert a bit value included in a bit string representing a value,
The first reference arithmetic expression is an arithmetic expression for obtaining a value obtained by inverting the sign of the value X by obtaining the one's complement of the value X by logical negation and adding 1 to the one's complement of the value X. ,
The diagnostic calculation unit calculates the first diagnostic calculation formula using the first diagnostic circuit,
The first diagnostic circuit is an arithmetic circuit that performs sign inversion to invert a sign representing positive and negative,
The arithmetic circuit diagnosis apparatus according to claim 1, wherein the first diagnosis arithmetic expression is an arithmetic expression for obtaining a value obtained by inverting the sign of the value X by sign inversion.
The reference calculation unit calculates the first reference calculation expression using the first reference circuit and a second reference circuit from which a correct calculation result is obtained,
The first reference circuit is an arithmetic circuit that performs addition,
The second reference circuit is an arithmetic circuit that performs a logical negation to invert a bit value included in a bit string representing a value,
The first reference arithmetic expression obtains the one's complement of the value Y by logical negation, obtains a value obtained by inverting the sign of the value Y by adding 1 to the one's complement of the value Y, and obtains the value X Is an arithmetic expression for obtaining a value obtained by subtracting the value Y from the value X by adding a value obtained by inverting the sign of the value Y to
The diagnostic calculation unit calculates the first diagnostic calculation formula using the first diagnostic circuit,
The first diagnostic circuit is an arithmetic circuit that performs subtraction,
2. The arithmetic circuit diagnosis apparatus according to claim 1, wherein the first diagnostic arithmetic expression is an arithmetic expression for subtracting a value obtained by subtracting the value Y from the value X. 3.
The reference calculation unit calculates the first reference calculation expression using the first reference circuit and a second reference circuit from which a correct calculation result is obtained,
The first reference circuit is an arithmetic circuit that performs a logical negation to invert a bit value included in a bit string representing a value,
The second reference circuit is an arithmetic circuit for obtaining a logical sum,
The first reference arithmetic expression obtains a logical sum of an X bit string representing the value X and a Y bit string representing the value Y, and logically negates the bit string obtained by inverting the bit value included in the obtained logical sum bit string. Is an arithmetic expression obtained by
The diagnostic calculation unit calculates the first diagnostic calculation expression using the first reference circuit and the first diagnostic circuit,
The first diagnostic circuit is an arithmetic circuit for obtaining a logical product,
The first diagnostic arithmetic expression obtains an inverted X bit string obtained by inverting the bit value included in the X bit string and an inverted Y bit string obtained by inverting the bit value included in the Y bit string by logical negation, and The arithmetic circuit diagnosis apparatus according to claim 1, wherein the arithmetic circuit diagnosis apparatus calculates a logical product with the inverted Y bit string.
In the case where the arithmetic circuit diagnosis unit determines that the first diagnostic circuit is an arithmetic circuit that can obtain a correct arithmetic result, the reference arithmetic unit uses the first diagnostic circuit to perform a second reference arithmetic operation. Calculate the expression,
The diagnostic calculation unit uses a second diagnostic circuit to be diagnosed to calculate a second diagnostic calculation formula that obtains the same calculation result as the second reference calculation formula,
The arithmetic circuit diagnosis unit compares the operation result of the second diagnostic operation expression calculated by the diagnosis operation unit with the operation result of the second reference operation expression calculated by the reference operation unit, and compares the result. The arithmetic circuit diagnosis apparatus according to claim 1, wherein the second diagnostic circuit determines whether or not the second diagnostic circuit is an arithmetic circuit that can obtain a correct arithmetic result.
The first diagnostic circuit is an arithmetic circuit that performs multiplication,
The second reference arithmetic expression is an arithmetic expression that obtains a value obtained by multiplying a value X by a power of 2 to the value obtained by multiplying the value X by the power of 2 to the Y power,
The second diagnostic circuit is an arithmetic circuit that performs a left shift to shift a bit string to the left,
7. The arithmetic circuit diagnosis apparatus according to claim 6, wherein the second diagnostic arithmetic expression is an arithmetic expression for obtaining a value represented by a bit string obtained by shifting a bit string representing a value X by Y bits to the left by left shifting.
The first diagnostic circuit is an arithmetic circuit that performs subtraction,
The second reference arithmetic expression is an arithmetic expression for obtaining a value representing the number of times the value Y can be subtracted from the value X by subtraction,
The second diagnostic circuit is an arithmetic circuit that performs division,
The arithmetic circuit diagnosis apparatus according to claim 6, wherein the second diagnostic arithmetic expression is an arithmetic expression for obtaining a quotient obtained by dividing the value X by the value Y by division.
The reference calculation unit calculates the second reference calculation expression using the first diagnostic circuit, the first reference circuit, and a second reference circuit that obtains a correct calculation result,
The first diagnostic circuit is an arithmetic circuit for obtaining a logical product,
The first reference circuit is an arithmetic circuit that performs a logical negation to invert a bit value,
The second reference circuit is an arithmetic circuit for obtaining a logical sum,
The second reference arithmetic expression is obtained by logically negating an inverted X bit string obtained by inverting the bit value included in the X bit string representing the value X and an inverted Y bit string obtained by inverting the bit value included in the Y bit string representing the value Y. A first logical product bit string representing a logical product of the X bit string and the inverted Y bit string, and a second logical product bit string representing a logical product of the inverted X bit string and the Y bit string; Is an arithmetic expression for obtaining a logical sum of the logical product bit string and the second logical product bit string,
The diagnostic calculation unit calculates the second diagnostic calculation formula using the second diagnostic circuit,
The second diagnostic circuit is an arithmetic circuit for obtaining an exclusive OR,
The arithmetic circuit diagnosis device according to claim 6, wherein the second diagnostic arithmetic expression is an arithmetic expression for obtaining an exclusive OR of the X bit string and the Y bit string.
The reference arithmetic unit uses the second diagnostic circuit to determine a third reference arithmetic operation when the arithmetic circuit diagnostic unit determines that the second diagnostic circuit is an arithmetic circuit that can obtain a correct arithmetic result. Calculate the expression,
The diagnostic calculation unit uses a third diagnostic circuit to be diagnosed to calculate a third diagnostic calculation formula that obtains the same calculation result as the third reference calculation formula,
The arithmetic circuit diagnosis unit compares the operation result of the third diagnostic operation expression calculated by the diagnosis operation unit with the operation result of the third reference operation expression calculated by the reference operation unit, and compares the result. The arithmetic circuit diagnosis device according to claim 6, wherein the third diagnostic circuit determines whether the arithmetic circuit can obtain a correct arithmetic result based on the calculation result.
The reference calculation unit calculates the third reference calculation expression using the second diagnostic circuit and a normal calculation circuit that obtains a correct calculation result,
The second diagnostic circuit is an arithmetic circuit that performs division,
The normal arithmetic circuit is an arithmetic circuit that performs multiplication,
The third reference arithmetic expression is an arithmetic expression that obtains the quotient obtained by dividing the value X by 2 to the Y power, and obtains the quotient obtained by dividing the value X by the power of 2 Y,
The diagnostic calculation unit calculates the third diagnostic calculation expression using the third diagnostic circuit,
The third diagnostic circuit is an arithmetic circuit that performs an arithmetic right shift to shift a bit string including a sign bit representing a sign to the right except for the sign bit,
The third diagnostic arithmetic expression is an arithmetic expression for obtaining, by arithmetic right shift, a value represented by a bit string obtained by shifting a bit string representing the value X to the right by Y bits except for a sign bit representing the sign of the value X. The arithmetic circuit diagnosis apparatus according to claim 10.
When the arithmetic circuit diagnosis unit determines that the third diagnostic circuit is an arithmetic circuit that can obtain a correct arithmetic result, the reference arithmetic unit uses the third diagnostic circuit to perform a fourth reference arithmetic operation. Calculate the expression,
The diagnostic calculation unit uses a fourth diagnostic circuit to be diagnosed to calculate a fourth diagnostic calculation formula that obtains the same calculation result as the fourth reference calculation formula,
The arithmetic circuit diagnosis unit compares the operation result of the fourth diagnostic operation expression calculated by the diagnosis operation unit with the operation result of the fourth reference operation expression calculated by the reference operation unit, and compares the result. The arithmetic circuit diagnosis apparatus according to claim 10, wherein the fourth diagnostic circuit determines whether the arithmetic circuit can obtain a correct arithmetic result based on the calculation result.
The reference calculation unit calculates the fourth reference calculation expression using the third diagnostic circuit and a normal calculation circuit that obtains a correct calculation result,
The third diagnostic circuit is an arithmetic circuit that performs an arithmetic right shift to shift a bit string including a sign bit representing a sign to the right except for the sign bit,
The normal arithmetic circuit is an arithmetic circuit for obtaining a logical product,
The fourth reference arithmetic expression obtains a shift bit string obtained by shifting the X bit string representing the value X by Y bits to the right excluding the X sign bit representing the sign of the value X, and the bit value is 0. An arithmetic expression for obtaining a logical product of a bit string composed of a sign bit and another bit having a bit value of 1 and the shift bit string,
The diagnostic computation unit computes the fourth diagnostic computation expression using the fourth diagnostic circuit,
The fourth diagnostic circuit is an arithmetic circuit that performs a logical right shift that shifts a bit string to the right including a sign bit representing a sign,
13. The arithmetic circuit diagnosis according to claim 12, wherein the fourth diagnostic arithmetic expression is an arithmetic expression for obtaining a bit string obtained by shifting the X bit string including the X sign bit to the right by Y bits to the right by a logical right shift. apparatus.
Using a first reference circuit, which is an arithmetic circuit that obtains a correct calculation result, a reference calculation process for calculating a first reference calculation expression;
Using a first diagnostic circuit, which is an arithmetic circuit to be diagnosed, a diagnostic arithmetic process for calculating a first diagnostic arithmetic expression that obtains the same arithmetic result as the first reference arithmetic expression;
The operation result of the first diagnostic operation expression calculated by the diagnosis operation process is compared with the operation result of the first reference operation expression calculated by the reference operation process, and the first result is calculated based on the comparison result. An arithmetic circuit diagnosis program for causing a computer to execute arithmetic circuit diagnosis processing for determining whether the diagnostic circuit is an arithmetic circuit that can obtain a correct arithmetic result.