WO2015177927A1

WO2015177927A1 - Information processing device

Info

Publication number: WO2015177927A1
Application number: PCT/JP2014/063715
Authority: WO
Inventors: 谷口　斉; 伊部　英史; 巧上薗
Original assignee: 株式会社日立製作所
Priority date: 2014-05-23
Filing date: 2014-05-23
Publication date: 2015-11-26

Abstract

A software-based implementation technology regarding soft error tolerance is provided. An information processing device is provided with: two or more processors; a memory that can be read or written from each of the processors that are associated therewith in advance; and a result comparison unit that compares the results of operation by the processors and identifies an operation result, wherein each processor stores information identifying at least a processing state in a contact region of the memory that cannot be written by the other processors. The processor, after executing a predetermined process, reads the processing state identifying information from the contact region associated with any of the other processors that perform the same process as the predetermined process, and, if the information matches the processing state of the processor, instructs the result comparison unit to compare the results of operation.

Description

Information processing device

The present invention relates to the technology of an information processing apparatus.

As a background technology in this technical field, there is a lock step technology that operates two processors in synchronization.

In the above technology, the soft error resistance can be improved by operating the two processors synchronously. However, in this technique, depending on the required soft error tolerance and the system temporary suspension allowable time, it may be better to realize the technique by a technique such as mutual monitoring, tripling, or monitoring by an external CPU. In other words, since the optimum hardware design is different for each device to be developed, the development period and cost may increase.

An object of the present invention is to increase the degree of freedom of hardware design by realizing soft error tolerance by software.

The present application includes a plurality of means for solving at least a part of the above-described problems, and examples thereof are as follows. In order to solve the above problems, an information processing apparatus according to the present invention compares two or more processors, a memory that can be read and written from each processor associated in advance, and an operation result obtained by comparing the operation results by the processor. And a result comparison unit for identifying, wherein the processor stores at least information for identifying a processing state in a communication area on the memory where writing from another processor other than the processor is disabled, When the processor executes a predetermined process, the processor reads out information specifying the processing state from the communication area associated with any one of the processors that performs the same process as the process. If the result matches the processing state, the result comparison unit is instructed to compare the calculation result.

According to the present invention, it is possible to increase the degree of freedom in hardware design by realizing soft error tolerance by software without depending on a specific hardware structure. Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

1 is a configuration diagram of an information processing apparatus according to a first embodiment of the present invention. It is a block diagram of the information processing apparatus which concerns on the 2nd Embodiment of this invention. It is a block diagram of the information processing apparatus which concerns on the 3rd Embodiment of this invention. It is a figure which shows the example of the hardware constitutions of the information processing apparatus to which embodiment of this invention is applied. It is a figure which shows the example of the flowchart of the software processing of the information processing apparatus to which embodiment of this invention is applied. It is a figure which shows the example of the software hierarchy structure of the information processing apparatus to which embodiment of this invention is applied.

Embodiments of an information processing apparatus and a communication apparatus using the same that have been made resistant to soft errors according to the present invention will be described with reference to the drawings. Information processing devices are communication devices such as hubs, routers, gateways, firewalls, etc., but are not limited to these, and various information processing devices such as server devices, mobile phones, tablet terminals, personal computers, smart meters, etc. It may be.

FIG. 1 is a configuration diagram of an information processing apparatus according to the first embodiment of the present invention. The information processing apparatus according to the first embodiment includes a first processor 1 to an nth processor 1n, which are two or more processors, and a first local memory 2 to an nth local memory provided for each processor. 2n, a result comparison unit / error processor detection unit 3, and a shared storage unit 40.

The shared storage unit 40 has a bank which is a storage area associated with each processor in advance. In the shared storage unit 40, a bank associated with a processor can be both read and written from the processor. In addition, access to the bank from a processor other than the associated processor can be read. That is, the shared storage unit 40 can function as a communication area to other processors.

In this way, any one of the first processor 1 to the n-th processor 1n caused an unexpected operation due to a soft error due to the configuration in which the shared storage unit 40 can only be read with an uncorrelated processor. Even in this case, it is possible to prevent erroneous data from being written in the shared storage unit 40 associated with another processor.

In order to realize such an embodiment, two or more processors are required. If three processors are provided, TMR (Triple Modular Redundant) can be realized, so that even better error resistance can be realized. In addition, it is more preferable to provide four processors because the vulnerability of TMR can be overcome.

The first local memory 2 to the nth local memory 2n associated with each of the first processor 1 to the nth processor 1n store programs to be executed and data. In the first bank 4 to the n-th bank corresponding to each processor provided in the shared storage unit 40, an internal state, a calculation state, a calculation result, and the like are stored as information for specifying a processing state of each processor. The Note that the programs executed by each processor are substantially the same. Each of the first processor 1 to the n-th processor 1n reads the state of the other processor from the bank 4n associated with the other processor, and from the user designation and / or information in the shared storage unit 40, the DMR ( The configuration is such that Double Modular Redundant, TMR, and nMR (n is greater than 3) are changed according to a predetermined standard.

Further, the first processor 1 to the n-th processor 1n autonomously make a determination such as waiting for the next process when the calculation of the other processor is not completed by comparing with the calculation result of the own processor. Further, such comparison and standby processing is performed at the timing of flushing the cache such as SRAM to the local memory. That is, the program is executed in a loosely synchronized state with other processors. Each processor outputs the calculation result to the result comparison unit / error processor detection unit 3 in order to verify whether or not the correct calculation result has been obtained when the calculation result of two or more processors including its own processor is obtained. Instruct to compare.

The result comparison unit / error processor detection unit 3 compares the calculation results in each processor and instructs the shared storage unit 40 to store the calculation results as necessary. Further, a processor that does not obtain a calculation result within an expected predetermined period (for example, within a period until the cache is flushed to the local memory) is detected, and a reset instruction 5 is issued to the processor. For example, in the case of an operation result mismatch when there are two processors, both processors are instructed to perform recalculation (not shown). Furthermore, in order to deal with the vulnerability of TMR, the processor is reset at an appropriate timing (not shown).

By doing as described above, DMR, TMR, and nMR (n is greater than 3) having different tolerances for soft error tolerance and tolerance levels for system suspension can be realized with one type of hardware architecture. According to such a first embodiment, it is possible to further increase the degree of freedom in hardware design by realizing soft error tolerance by software. In other words, it can be said that the hardware can be shared to reduce the development man-hours and realize cost reduction.

FIG. 2 is a configuration diagram of an information processing apparatus according to the second embodiment of the present invention. The information processing apparatus according to the second embodiment includes a first processor 1 to an nth processor 1n that are two or more processors, and a first local memory 2 to an nth local memory 2n provided for each processor. And a result comparison unit / error processor detection unit 3. Further, in each of the first local memory 2 to the nth local memory 2n, there are provided shared storage units 7 to 7n that are shared with other processors other than the processors associated in advance. . Each of the storage units 7 to 7n is a partial storage area of each of the first local memory 2 to the nth local memory 2n. Each storage unit of the shared storage unit 7 to the shared storage unit 7n is capable of both reading and writing from a processor associated in advance. In addition, access to the storage unit from other processors than the associated processor can be read. That is, each of the storage units 7 to 7n can function as a communication area to other processors.

Since the shared storage unit 7 to the shared storage unit 7n can be read only with the processors that are not associated with each other in this way, any one of the first processor 1 to the n-th processor 1n is caused by a soft error. Even when an unexpected operation is performed, it is possible to prevent erroneous data from being written in the shared storage unit 7 to the shared storage unit 7n associated with other processors.

In order to realize such an embodiment, two or more processors are required. When three processors are provided, TMR can be realized, so that even better error resistance can be realized. In addition, it is more preferable to provide four processors because the vulnerability of TMR can be overcome.

The first local memory 2 to the nth local memory 2n associated with each of the first processor 1 to the nth processor 1n store programs to be executed and data. In the shared storage unit 7 to shared storage unit 7n, an internal state, a calculation state, a calculation result, and the like are stored as information for specifying the processing state of each processor. Note that the programs executed by each processor are substantially the same. Each of the first processor 1 to the n-th processor 1n reads the state of the other processor from the shared storage unit 7 to the shared storage unit 7n associated with the other processor, and is designated by the user and / or the shared storage unit. 7 to DMR, TMR, and nMR (n is larger than 3) are changed from information in the shared storage unit 7n according to a predetermined standard.

The result comparison unit / error processor detection unit 3 compares the calculation results in each processor and stores the calculation results 6 in the shared storage unit 7 to the shared storage unit 7n as necessary. Further, a processor that does not obtain a calculation result within an expected predetermined period (for example, within a period until the cache is flushed to the local memory) is detected, and a reset instruction 5 is issued to the processor. For example, in the case of an operation result mismatch when there are two processors, both processors are instructed to perform recalculation (not shown). Furthermore, in order to deal with the vulnerability of TMR, the processor is reset at an appropriate timing (not shown).

FIG. 3 is a configuration diagram of an information processing apparatus according to the third embodiment of the present invention. The information processing apparatus according to the third embodiment includes a first processor 1 to an nth processor 1n, which are two or more processors, and a first local memory 2 to an nth local memory 2n provided for each processor. And an error processor detection unit 8.

Further, in each of the first local memory 2 to the nth local memory 2n, there are provided shared storage units 7 to 7n that are shared with other processors other than the processors associated in advance. . Each of the storage units 7 to 7n is a partial storage area of each of the first local memory 2 to the nth local memory 2n. Each storage unit of the shared storage unit 7 to the shared storage unit 7n is capable of both reading and writing from a processor associated in advance. In addition, access to the storage unit from other processors than the associated processor can be read. That is, each of the storage units 7 to 7n can function as a communication area to other processors.

Further, the first processor 1 to the n-th processor 1n autonomously make a determination such as waiting for the next process when the calculation of the other processor is not completed by comparing with the calculation result of the own processor. Further, such comparison and standby processing is performed at the timing of flushing the cache such as SRAM to the local memory. That is, the program is executed in a loosely synchronized state with other processors. Then, each processor compares the operation results and identifies the operation results by majority vote, etc., in order to verify whether the correct operation results have been obtained when the operation results of two or more processors including its own processor are obtained. To do. Then, the first processor 1 to the n-th processor 1 n issue an instruction to store the calculation results to the shared storage unit 7 to the shared storage unit 7 n.

The error processor detection unit 8 detects a processor for which an operation result is not obtained within an assumed predetermined period (for example, within a period until the cache is flushed to the local memory), and issues a reset instruction 5 to the processor. For example, in the case of an operation result mismatch when there are two processors, both processors are instructed to perform recalculation (not shown). Furthermore, in order to deal with the vulnerability of TMR, the processor is reset at an appropriate timing (not shown).

FIG. 4 is a configuration example of the soft error tolerance information processing device 9 including the arithmetic unit 10 having the configuration according to any one of the first to third embodiments. The soft error tolerant information processing device 9 includes an arithmetic unit 10 having a configuration according to any one of the first to third embodiments, a ROM (Read Only Memory) 11 for recording various programs, and the like. And an input / output interface unit 12 (hereinafter abbreviated as input / output IF) for performing input / output with an external device. The input / output IF 12 is connected to an input device 13 such as a keyboard, an output device 14 such as a display, and an input / output device 15 that exchanges various information related to information processing targets.

By adopting the configuration as described above, even when a soft error occurs in one processor included in the arithmetic unit 10, the influence of the error can be contained in the processor and its local memory. Therefore, it can be said that the soft error tolerance information processing apparatus 9 can be restored simply by resetting the corresponding processor. Furthermore, since the operation unit 10 can be operated by appropriately switching any one of DMR, TMR, and nMR, an appropriate operation result can be obtained, and information processing can be continued even at the time of the corresponding error.
Furthermore, the hardware of the arithmetic unit 10 can be made common to reduce the development man-hours and realize cost reduction.

FIG. 5 is a diagram showing an example of a flowchart of software processing of the information processing apparatus to which the first embodiment or the second embodiment of the present invention is applied. A flowchart of software processing of the information processing apparatus to which the third embodiment is applied will be described later. Since each of the first processor 1 to the n-th processor 1n performs the same processing, the description will be made assuming that the first processor 1 performs the processing representatively for the sake of simplicity.

The first processor 1 performs initialization (step S001). Specifically, the first processor 1 initializes the processor itself and initializes the corresponding first local memory 2.

Then, the first processor 1 initializes the shared storage unit (step S002). Specifically, the first processor 1 includes a calculation program start PC (program counter) stored in the bank of the shared storage unit 40 or the shared storage unit 7, a start PC of the next calculation program, and processor status information ( Initialize calculation wait, calculation in progress, calculation end wait, next calculation wait, etc.).

Then, the first processor 1 loads information such as predetermined calculation conditions into the shared storage unit 40 or the shared storage unit 7, and turns on the calculation waiting flag of the common storage unit (step S003).

Then, the first processor 1 reads the calculation waiting flag in the shared storage unit of the other processor and determines the calculation start (step S004). Specifically, the first processor 1 reads the status information of the other processors in the shared storage unit 40 or the shared storage unit 7n, autonomously determines the overall system state from the other processor states, and starts the calculation. As a result, the program is executed in a gradual synchronization state in all the processors.

Then, the first processor 1 performs calculation (step S005). Specifically, the first processor 1 executes a program executed by the first processor itself. The first processor 1 can store the survival signal of the own processor in the bank 4 or the shared storage unit 7 associated with the own processor of the shared storage unit 40 and can check the survival signal from other processors during the calculation. By doing so, it may be possible to detect and reset an abnormal processor.

Then, the first processor 1 stores the calculation result in the shared storage unit 40 or the shared storage unit 7 and turns on the calculation end flag (step S006).

Then, the first processor 1 determines the status of other processors (step S007). Specifically, the first processor 1 reads the calculation end flag of the bank 4n of the shared storage unit 40 of the other processor or the shared storage unit 7n, and waits for the processing until the calculation end flag of the other processor is completed. When the calculation is completed, the result comparison unit / error processor detection unit 3 is instructed to perform comparison processing.

Then, the result comparison unit / error processor detection unit 3 determines the majority of the calculation results (step S008). Specifically, the result comparison unit / error processor detection unit 3 reads out the calculation result stored in the shared storage unit of all the processors constituting the DMR, TMR, and nMR, and determines the majority (for example, the number of processors is 3 Perform in the above case) or perform error determination on one of the processors (implemented when the number of processors is 2) to identify the calculation result.

The above is the software processing flow of the information processing apparatus to which the first embodiment or the second embodiment of the present invention is applied. As a result, as a result of calculation by each processor, a calculation result can be obtained while avoiding a soft error. In addition, when a significant calculation result cannot be obtained, for example, the results are different among a plurality of processors, a significant calculation result can be obtained by re-execution. In addition, since the configurations of the DMR, TMR, and nMR can be appropriately set according to the situation, the dependency on the hardware configuration can be further reduced.

In step S007, when checking the calculation end flag of the shared storage unit of the other processor and waiting until the calculation of all the processors is completed, the survival signal of the other processor is checked to detect an abnormality. The abnormal processor may be reset (mutual monitoring during calculation).

In addition, when the calculation of another processor does not end even after a predetermined calculation period (for example, until the cache is flushed to the memory), the processor may be reset as an abnormal processor. When the processing is performed, it may be considered that the calculation of the other core is completed when the calculation of the processor is completed by subtracting the number of processors that performed the processing from the total number of processors.

In step S008, if the calculation result is different in the error determination, all the processors are reset and recalculated. In the case of majority decision, a correct calculation result is obtained when the calculation results of two or more processors match. At this time, processors having different calculation results may be reset by assuming that an abnormality has occurred.

In addition, the flow of software processing of the information processing apparatus in the third embodiment is basically the same, but the main body that determines the majority of the calculation results in step S008 is one of the processors. Is different.

FIG. 6 is a diagram showing an example of the software hierarchy of the information processing apparatus to which the embodiment of the present invention is applied. The hardware layer 601 is a hardware layer of the information processing apparatus. Above the hardware layer 601 is a driver layer 602 that operates the hardware. A soft error resistance layer 603 is provided on the hardware layer 601 and / or the driver layer 602. The soft error resilience layer 603 includes at least switching of resilience methods such as DMR, TMR, and nMR, gradual synchronous operation based on status information of other processors in the shared storage unit, mutual monitoring during computation, Abstracts programs related to soft error tolerance such as majority decision, detection / reset of abnormal processors, recovery and resynchronization of abnormal processors.

It is desirable to place an OS (Operating System) layer 604 and a middleware library layer 605 in the upper layer of the soft error tolerance layer 603, but it is not essential. For example, when the information processing apparatus is an embedded control system apparatus, the OS may not be installed. On the soft error resistance layer 603 or the OS layer 604 and the middleware library layer 605, a user application 606 (an application 606 created by the user) is arranged. By adopting such a software hierarchical structure, the user application layer need not be aware of soft error tolerance. The software production man-hours are almost the same as the software production man-hours for non-soft error tolerance, and the increase in software development man-hours due to soft error tolerance can be suppressed.

In addition, each configuration, function, processing unit, processing means, and the like of each of the above embodiments may be realized by hardware by designing a part or all of them with, for example, an integrated circuit. Each of the above-described configurations, functions, and the like may be realized by software by interpreting and executing a program that realizes each function by the processor. Information such as programs, tables, and files that realize each function can be stored in a memory, a hard disk, a recording device such as an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.

Also, the control lines and information lines indicate what is considered necessary for the explanation, and not all the control lines and information lines on the product are necessarily shown. Actually, it may be considered that almost all the components are connected to each other.

The information processing apparatus according to the present invention has been described above based on the first to third embodiments. Note that the information processing apparatus is not limited to a so-called general-purpose computer, but may be applied to a communication apparatus such as a router or a gateway.

In addition, the present invention may be applied to devices that measure household power consumption, water consumption, gas consumption, and the like, such as mobile devices and smart meters. In the above, this invention was demonstrated centering on embodiment.

DESCRIPTION OF SYMBOLS 1 ... 1st processor, 2 ... 1st local memory, 3 ... Result comparison part and error processor detection part, 4 ... 1st bank, 5 ... Reset instruction, 6 ..Storage instruction, 7 ... shared storage unit, 8 ... error processor detection unit

Claims

Two or more processors,
A memory that can be read and written from each of the processors associated in advance;
A result comparison unit that compares the calculation results by the processor and identifies the calculation results;
The processor stores at least information for specifying a processing state in a communication area on the memory where writing from another processor other than the processor is disabled,
When the processor executes a predetermined process, the processor reads out information specifying the processing state from the communication area associated with any one of the processors that performs the same process as the process. Instructing the result comparison unit to compare the operation result when the processing state matches.
An information processing apparatus characterized by that.
The information processing apparatus according to claim 1,
The processor requests the result comparison unit to perform a process for re-execution of the predetermined process when the information specifying the read processing state does not match within a predetermined period.
An information processing apparatus characterized by that.
The information processing apparatus according to claim 1, wherein:
The processor requests the result comparison unit to re-execute the predetermined process when the read-out information specifying the processing state is information specifying the occurrence of an error;
An information processing apparatus characterized by that.
The information processing apparatus according to any one of claims 1 to 3,
The memory is provided in association with each processor,
An information processing apparatus characterized by that.
An information processing apparatus according to any one of claims 1 to 4,
The predetermined period is an interval for flushing the cache.
An information processing apparatus characterized by that.
Two or more processors,
A memory that is readable and writable from each processor associated in advance;
The processor stores at least information for specifying a processing state in a communication area on the memory where writing from another processor other than the processor is disabled,
When the processor executes a predetermined process, the processor reads out information specifying the processing state from the communication area associated with any one of the processors that performs the same process as the process. When the processing state matches, the operation result by the processor is compared to identify the operation result;
An information processing apparatus characterized by that.
Two or more processors,
A memory that can be read and written from each of the processors associated in advance;
A result comparison unit that compares the calculation results by the processor and identifies the calculation results;
The processor stores at least information for specifying a processing state in a communication area on the memory where writing from another processor other than the processor is disabled,
When the processor executes a predetermined process, the processor reads out information specifying the processing state from the communication area associated with any one of the processors that performs the same process as the process. Instructing the result comparison unit to compare the operation result when the processing state matches.
A communication device.