WO2015176252A1 - Procédé et appareil de traitement de données - Google Patents

Procédé et appareil de traitement de données Download PDF

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Publication number
WO2015176252A1
WO2015176252A1 PCT/CN2014/078021 CN2014078021W WO2015176252A1 WO 2015176252 A1 WO2015176252 A1 WO 2015176252A1 CN 2014078021 W CN2014078021 W CN 2014078021W WO 2015176252 A1 WO2015176252 A1 WO 2015176252A1
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data
data units
sub
matrix
units
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PCT/CN2014/078021
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English (en)
Chinese (zh)
Inventor
杨文斌
王童童
王心远
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华为技术有限公司
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Priority to PCT/CN2014/078021 priority Critical patent/WO2015176252A1/fr
Priority to CN201480024928.1A priority patent/CN105210333B/zh
Publication of WO2015176252A1 publication Critical patent/WO2015176252A1/fr

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  • the present invention relates to the field of communications technologies, and in particular, to a data processing method and apparatus.
  • Ethernet interfaces may have 400 Gigabit Ethernet (English: gigabit ethernet, GE for short) and 1 terabit ethernet (TE).
  • Ethernet depending on the requirements, there are transmission circuits that support different transmission rates or bit widths.
  • the transmission rate supported by the single data interface of the transmission circuit is inversely proportional to the number of data interfaces. For example, in an Ethernet with a total rate of 400 gigabits (English: gigabit, abbreviated as G), it can be implemented by 16 transmission circuits A supporting a 25G rate data interface, or through 8 data interfaces supporting 50G rates.
  • Transmission Circuit ⁇ When the transmission circuit A needs to transmit data to the transmission circuit B, it is necessary to convert 16 data streams in the transmission circuit A into 8 data streams and transmit them to the transmission circuit B.
  • the transmission circuit B when the transmission circuit B needs to transmit data to the transmission circuit A, it is necessary to convert the eight data streams in the transmission circuit B into 16 data streams and transmit them to the transmission circuit A.
  • the transmission circuit C and the transmission circuit D include the same number of data interfaces, for example, all of which contain 16 data interfaces supporting 25G rates.
  • the order of the data in the data stream changes.
  • the above transformation is collectively referred to as data processing.
  • a change in the bit width of the data stream occurs.
  • the above data processing can also be referred to as a bit width transform.
  • data processing can be achieved by interleaving or deinterleaving the data stream. Specifically, multiple data streams are interleaved into one data stream. Or, disassemble one of the interleaved data streams Weaving into multiple data streams.
  • FIG. 1 a typical process of interleaving two data streams into one data stream.
  • the data stream L1 includes 6 data units, which are 01 to 06, respectively.
  • the data stream L2 also includes six data units, which are 07 to 12, respectively.
  • a data stream L3 comprising 12 data units is obtained.
  • the above method can double the transmission rate. Data processing from 16 25G rate conversions to 8 50G rates can be implemented in the manner shown in FIG.
  • the rate of multiple data streams after data processing must be the same.
  • the manner of interleaving is specifically that a plurality of data streams are interleaved into one data stream.
  • Current data processing can only support data processing with integer multiple coefficients. For example, 16 data streams are transformed into 8 data streams (16 is an integer 2 times 2). The eight data streams are transformed into four data streams (8 is an integer of 2 times 2). Alternatively, by deinterleaving, the four data streams are transformed into eight data streams.
  • the number of data streams before and after data processing needs to meet specific constraints and is not flexible.
  • the transmission rate of the Ethernet interface may be more and more.
  • the transmission circuit A through 16 data interfaces supporting the rate of 25G needs to transmit data through the transmission circuit C through 10 data interfaces supporting the rate of 40G, the current technology is Data processing is not possible. Limits the development of Ethernet. Summary of the invention
  • the technical problem solved by the present invention is to provide a data processing method and apparatus for implementing flexible data processing to meet the development requirements of Ethernet.
  • the present invention provides a data processing method, the method comprising:
  • the transform circuit receives M data streams through M receiving ports, each of the M data streams includes n data units, and the M receiving ports correspond to the M data streams, where the M Each data stream corresponds to a matrix of M xn , each element in the matrix of M xn is a data unit, the matrix of M xn includes M lxn matrices, and each of the M lxn matrices is 1 X
  • the matrix of n corresponds to one data stream, the matrix of M 1 X n and the M data Flow-correspondingly, n data units in each of the matrix of 1 X n n are respectively n data units in the corresponding data stream, and the matrix of the M 1 X n
  • the data unit located on the right of any two of the n data units in the matrix of each 1 X n is received by the conversion circuit earlier than the time when the data unit located on the left is received by the conversion circuit
  • the transform circuit respectively generates N data streams by using M data units in the matrix of
  • the transform circuit sends the N data streams through N output ports, where the N output ports correspond to the N data streams, where M and N are both positive integers.
  • the at least one data stream is composed of M data units, M data units in a matrix of the i-th MX 1 in the matrix of the n MX 1 and M in a matrix using the ith MX 1
  • the M data units included in the at least one data stream generated by the data units are the same, and each of the N data streams includes the same number of data units.
  • two adjacent data units in each of the N data streams are from different codes. Word codeword.
  • the two adjacent data units in each of the N data streams are the same forward error correction FEC.
  • Two adjacent data units in each of the N data streams are data units output by two FEC circuits, respectively.
  • the transforming circuit generates the N data streams by using M data units in the matrix of the n MX 1 to specifically generate the M data units by using M data units in the matrix of the jth MX 1
  • At least one data stream wherein the generating the at least one data stream composed of the M data units by using the M data units in the matrix of the jth M x 1 specifically includes:
  • the transform circuit interleaves the X groups of data units to generate a data stream consisting of M data units, and the M data units in the matrix of the jth MX 1 specifically include the X groups of data units, each group
  • the number of data units in the data unit is M/X, the codeword from which the data unit of any one of the X data units is derived and the data unit from the other group of data units in the X group of data units
  • the codeword is different, and X is an integer greater than one.
  • the transforming circuit generates the N data streams by using M data units in the matrix of the n MX 1 to specifically generate the M data units by using M data units in the matrix of the jth MX 1
  • the transform circuit interleaves Q groups of data units in each of the P sets to generate P data streams consisting of M data units, and M data units in the matrix of the jth MX 1 All the data units in the P sets are the same, each of the P sets is composed of Q group data units, and the code words from the data units in any one of the Q data units Unlike the codeword from which the data unit in the other group of data units in the Q group of data units is derived, the number of data units in each group of data units is M/(PXQ), and both P and Q are integers greater than one.
  • Each data unit in the matrix of M xn is composed of k sub-data units
  • the at least one data stream is composed of MX k sub-data units
  • the matrix of the i-th MX 1 in the matrix of the n MX 1 M x k sub-data units are the same as M x k sub-data units included in at least one data stream generated by M x k sub-data units in the matrix of the i-th M x 1 , each of the N data streams
  • the data streams include the same number of sub-data units.
  • Two adjacent sub-data units in each of the N data streams are from different codewords.
  • Two adjacent sub-data units in each of the N data streams belong to two data units output by the same forward error correction FEC circuit, or
  • Two adjacent sub-data units in each of the N data streams are from two FEC circuits.
  • the transforming circuit generates the N data streams by using Mx k sub-data units in the matrix of the n ⁇ ⁇ 1 to specifically generate MX k sub-data units in a matrix of the j-th MX 1 to generate Mxk sub-data And generating at least one data stream composed of the units, wherein: generating, by using MX k sub-data units in the matrix of the j-th Mx 1 , at least one data stream composed of Mxk sub-data units specifically includes:
  • the transform circuit interleaves the X sets of sub-data units to generate a data stream consisting of M k sub-data units, and the Mxk sub-data units in the matrix of the j-th MX 1 specifically include the X-group sub-data units
  • the number of sub-data units in each group of sub-data units is (Mxk) /X, the codeword from which the sub-data unit of any one of the X sub-data units is derived and the X-group sub-data unit
  • the sub-data units in the other group sub-data units are different from the codewords, and X is an integer greater than one.
  • the transform circuit generates the N data streams by using MX k sub-data units in the matrix of the n MX 1 to specifically comprise generating Mxk sub-data units by using Mxk sub-data units in a matrix of the j-th MX 1
  • At least one data stream, wherein generating at least one data stream composed of Mxk sub-data units by using MX k sub-data units in the matrix of the j-th Mx 1 specifically includes:
  • the transform circuit interleaves Q groups of sub-data units in each of the P sets to generate P data streams consisting of MX k sub-data units, MX k of the j-th MX 1 matrix
  • the data unit is identical to all of the P data sets, each of the P sets is composed of Q group sub data units, and any one of the Q group sub data units
  • the codeword from which the sub-data unit in the cell is derived is different from the codeword from which the sub-data unit in the other group of sub-data units in the Q-group sub-data unit is derived, and the number of sub-data units in each group of sub-data units is (M xk / ( P x Q ), P and Q are all integers greater than one.
  • the present invention provides a data processing apparatus, the apparatus comprising:
  • a receiving unit configured to receive M data streams by using M receiving ports, where each of the M data streams includes n data units, where the M receiving ports correspond to the M data streams.
  • the M data streams correspond to a matrix of MX n , each element in the matrix of the MX n is a data unit, the matrix of the M xn includes M 1 x n matrices, and the M 1 x n matrices Each matrix of 1 X n corresponds to 1 data stream, and the matrix of M 1 X n corresponds to the M data streams, and each of the M 1 X n matrices is 1 X n
  • a generating unit configured to generate N data streams by using M data units in a matrix of n MX 1 in the matrix of the M xn respectively, and generating the N data streams specifically includes using the n M 1
  • Each matrix of M 1 in the matrix generates at least one data stream;
  • an output unit configured to send the N data streams by using N output ports, where the N output ports correspond to the N data streams, where M and N are both positive integers.
  • the at least one data stream generated by the generating unit is composed of M data units, and the M data units in the matrix of the i-th M x 1 in the matrix of the n M 1 and the using the ith M x
  • the M data units included in the at least one data stream generated by the M data units in the matrix of 1 are the same, and each of the N data streams includes the same number of data units.
  • the two adjacent ones of the N data streams generated by the generating unit The data units are from different codewords.
  • Two adjacent data units in each of the N data streams generated by the generating unit are data units output by the same forward error correction FEC circuit, or
  • Two adjacent data units in each of the N data streams generated by the generating unit are data units output by two FEC circuits, respectively.
  • the generating unit generates at least one data stream composed of M data units by using M data units in the matrix of the jth M x 1 , wherein the M data units in the matrix of the jth M x 1 are generated
  • the at least one data stream composed of M data units specifically includes:
  • the generating unit interleaves the X groups of data units to generate a data stream composed of M data units, where the M data units in the matrix of the jth MX 1 specifically include the X groups of data units, each group The number of data units in the data unit is M/X, the codeword from which the data unit of any one of the X data units is derived and the data unit from the other group of data units in the X group of data units The codeword is different, and X is an integer greater than one.
  • the generating unit generates at least one data stream composed of M data units by using M data units in the matrix of the jth M x 1 , wherein the M data units in the matrix of the jth M x 1 are generated
  • the at least one data stream composed of M data units specifically includes:
  • the generating unit interleaves the Q group data units in each of the P sets to generate P data streams composed of M data units, and the M data units in the matrix of the jth MX 1 and All the data units in the P sets are the same, each of the P sets is composed of Q group data units, and the code words from the data units in any one of the Q data units Unlike the codeword from which the data unit in the other group of data units in the Q group of data units is derived, the number of data units in each group of data units is M/(PXQ), and both P and Q are integers greater than one.
  • Each of the data units in the matrix of M xn is composed of k sub-data units, and the at least one data stream generated by the generating unit is composed of MX k sub-data units, the n MX 1 M x k sub-data units in the matrix of the i-th M x 1 in the matrix and MX k sub-data contained in at least one data stream generated by using MX k sub-data units in the matrix of the i-th M x 1
  • the units are the same, and each of the N data streams includes the same number of sub-data units.
  • Two adjacent sub-data units in each of the N data streams generated by the generating unit are from different codewords.
  • the two adjacent sub-data units of each of the N data streams generated by the generating unit belong to Two data units output by the same forward error correction FEC circuit, or
  • Two adjacent sub-data units of each of the N data streams generated by the generating unit are respectively from two FEC circuits.
  • the generating unit generates the N data streams by using the MX k sub-data units in the matrix of the n MX 1 to specifically generate the M x k sub-data by using the MX k sub-data units in the matrix of the j-th MX 1 At least one data stream composed of the units, wherein generating, by using MX k sub-data units in the matrix of the j-th M x 1 to generate at least one data stream composed of MX k sub-data units, specifically includes:
  • the generating unit interleaves the X groups of sub-data units to generate a data stream composed of M k sub-data units, and the MX k sub-data units in the matrix of the j-th MX 1 specifically include the X-group sub-data Unit, the number of sub-data units in each group of sub-data units is (M xk ) /X, the codeword from which the sub-data unit of any one of the X sub-data units is derived and the X-group sub-unit The sub-data units in the other group of sub-data units in the data unit are different from the codeword, and X is an integer greater than one.
  • Generating unit generates M x k sub-data units in the matrix of n n x 1
  • the N data streams specifically include generating at least one data stream composed of M x k sub-data units by using MX k sub-data units in the matrix of the j-th MX 1 , wherein MX in the matrix of the j-th M x 1 is utilized.
  • the k sub-data units generate at least one data stream composed of M x k sub-data units, and specifically include:
  • the generating unit interleaves Q groups of sub-data units in each of the P sets to generate P data streams consisting of MX k sub-data units, MX k of the j-th MX 1 matrix
  • the data unit is identical to all of the P data sets, and each of the P sets is composed of a Q group of sub data units, and any one of the Q group of sub data units is in the sub data unit.
  • the codeword from which the sub-data unit is derived is different from the codeword from which the sub-data unit in the other group of sub-data units in the Q-group sub-data unit is derived, and the number of sub-data units in each group of sub-data units is (M xk ) / ( P x Q ), P and Q are all integers greater than one.
  • the M data streams before data processing correspond to a matrix of M X n .
  • the value of the number N of data streams generated by the data units in the matrix of MX n realizes the function of flexible processing of integer multiple coefficients of M and non-integer multiple coefficients, and satisfies the development requirements of Ethernet.
  • FIG. 2 is a flowchart of a data processing method according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a matrix of M x n according to an embodiment of the present invention.
  • FIG. 4a is a schematic diagram of data processing according to an embodiment of the present invention.
  • Figure 4b is a schematic diagram of a reverse operation of data processing according to an embodiment of the present invention
  • Figure 5a is a schematic diagram of data processing according to an embodiment of the present invention
  • Figure 5b is a schematic diagram of a reverse operation of data processing according to an embodiment of the present invention
  • Figure 6a is a schematic diagram of data processing according to an embodiment of the present invention
  • FIG. 6b is a schematic diagram of data processing according to an embodiment of the present invention
  • FIG. 7 is a structural diagram of a device of a data processing apparatus according to an embodiment of the present invention.
  • the number of data streams obtained after data processing may only be an integer multiple of the number of data streams sent by the PCS through multiple FEC modules.
  • 16 25G data streams are transformed into 8 50G data streams.
  • 16 25G data streams are transformed into four 100G data streams.
  • the above data processing techniques cannot achieve the above requirements.
  • the 400G Ethernet scenario it is not possible to convert 16 25G data streams into 10 40G data streams.
  • the M data streams before the data processing correspond to a matrix of MX n to the MX. n M in the matrix of n
  • the matrix of X 1 performs data processing, and by controlling the value of the number n of data units included in the M data streams, the number N of data streams generated by the data units in the matrix of the MX n finally can be controlled.
  • the value of the data processing function of the integer multiple coefficient of M and the non-integer multiple coefficient is realized flexibly, and the current development requirements of Ethernet are satisfied.
  • Embodiments of the present invention provide specific implementations of data processing. Any two adjacent data units in the data stream obtained after data processing are respectively derived from different code words (English: codeword).
  • the receiving device can distribute a plurality of consecutive erroneous data units in the transmission link to the plurality of data streams through reverse operation of data processing. on. Improve the error correction capability of the entire data transmission system.
  • the data processing in this application refers to processing M data streams to generate N data streams.
  • the reverse operation of data processing in this application refers to processing the N data streams to generate the M data streams. That is, the reverse operation of performing data processing can restore the M data streams before data processing.
  • the execution body of the data processing may be a transform circuit.
  • the conversion circuit can be a component in a PHY, a PHY chip, a system chip, or a multi-port Ethernet device.
  • the PHY can be implemented by an FPGA or an ASIC.
  • the PHY may be a component in a network interface card (NIC), and the NIC may be a line card or a physical interface card (PIC).
  • the PHY may include a Media-Independent Interface ( ⁇ ) for interfacing to the MAC.
  • the PHY chip can include a plurality of PHYs.
  • the PHY chip can be implemented by an FPGA or an ASIC.
  • the system chip can include multiple MACs and multiple PHYs.
  • the system chip can be implemented by an FPGA or an ASIC.
  • the multi-port Ethernet device can be an Ethernet hub, an Ethernet router, or an Ethernet switch.
  • the multi-port Ethernet device includes a plurality of ports, each of which may include a system chip, and the system chip may include a MAC and a PHY.
  • the multi-port Ethernet device can also have multiple MACs Integrate into a MAC chip and integrate multiple PHYs into one PHY chip.
  • the multi-port Ethernet device can also integrate multiple MACs and multiple PHYs into one system chip.
  • the execution body of the reverse operation of the data processing may be an inverse transform circuit.
  • the inverse transform circuit can be a component in a PHY, PHY chip, system chi or multi-port Ethernet device.
  • the N data streams may be sent to the first optical module.
  • the first optical module may perform electro-optical conversion on the N data streams to obtain an optical signal.
  • the first optical module may send the optical signal to the second optical module through an optical fiber.
  • the second optical module may obtain the N data streams (electric signals) by performing photoelectric conversion on the optical signals.
  • the second optical module may send the N data streams to the inverse transform circuit.
  • the inverse transform circuit can process the N data streams to generate the M data streams.
  • the transform circuit and the first optical module can be components of a local multi-port Ethernet device.
  • the second optical module and the inverse transform circuit can be components of a peer multiport Ethernet device.
  • the local multi-port Ethernet device can communicate with the peer multi-port Ethernet device through the optical fiber.
  • FIG. 2 it is a flowchart of a data processing method according to an embodiment of the present invention, where the method includes:
  • the transform circuit receives M data streams through M receiving ports. Each of the M data streams includes n data units. The M receiving ports correspond to the M data streams. The M data streams correspond to a matrix of MX n . Each element in the matrix of MX n is a data unit.
  • the matrix of M xn includes M 1 x n matrices. The M 1 xn Each 1 xn matrix in the matrix corresponds to 1 data stream. The M +1 matrixes correspond to the M data streams.
  • the n data units in the matrix of each of 1 X n of the M 1 X n matrix are respectively n data units in the corresponding data stream.
  • the data unit located on the right of any two of the n data units in the matrix of 1 ⁇ 1 n of the M 1 ⁇ n matrix is received by the transform circuit earlier than the data unit located on the left side The time received by the conversion circuit.
  • the M data streams are data processing data streams that need to be processed.
  • the M data streams may be data streams output by the FEC module of the PCS.
  • the data stream output by the FEC module of the PCS may be a data stream that has not been subjected to data processing.
  • the M data streams may also be data processed data streams. It should be noted that in order to make the expression of the scheme clearer and clearer, the mathematical basic concepts of the matrix are used in S201 to describe the M data streams.
  • FIG. 3 is a schematic diagram of a matrix of M X n provided by this embodiment.
  • Each of the M data streams constitutes one row of the matrix of the M x n, and each row is composed of n data units. That is to say, each row corresponds to a matrix of 1 X n.
  • the matrix of M X n includes M 1 x n matrices.
  • the n data units in each of the M-stream data streams are, from left to right, a first data unit to an n-th data unit.
  • the i-th data unit in each of the M-stream data streams constitutes the i-th column of the matrix of the M X n (where i is any one of n).
  • Each column consists of M data units. That is to say, each column corresponds to a matrix of M X 1 .
  • the matrix of M X n includes n matrices of M X 1 . Any one of the two adjacent data units of the matrix of any one of the M 1 X n matrices located on the right side (for example, the data unit a in FIG. 3) is located on the left side (for example, in FIG. 3)
  • the data unit b) will be received by the conversion circuit first.
  • the viewing angle of the matrix according to the M X n is defined.
  • the flow directions of the M data streams are from left to right. This is defined for the sake of clarity, and is not intended to limit the flow of data streams in all scenarios to which the embodiments of the present invention are applied, from left to right.
  • S202 The conversion circuit generates N data streams by using M data units in the matrix of n MX 1 in the matrix of the MX n respectively. Generating the N data streams specifically includes generating at least one data stream using a matrix of each of the n MX 1 matrices.
  • S203 The transform circuit sends the N data streams through N output ports. The N output ports correspond to the N data streams. Where M and N are both positive integers.
  • M and N are integers greater than one.
  • M can be equal to 2, 3 or 4.
  • N can be equal to 2, 3 or 4.
  • M can be greater than N.
  • M can also be equal to N.
  • M can also be less than N.
  • the M data streams to be subjected to the data processing are 16 data streams
  • the number N of the data streams obtained by the data processing after the data processing may be any one of 1 to 16 by the conversion method of the embodiment. It can also be an integer greater than 16.
  • the transform circuit performing data processing performs data processing from M data streams to N data streams
  • the M data streams before data processing correspond to a matrix of M x n.
  • Data processing is performed on the n M x 1 matrices in the matrix of the M x n respectively, thereby obtaining N data streams.
  • the data processing is flexible and helps to meet the development requirements of Ethernet.
  • the present embodiment further provides different granularity situations that may exist when the data processing is specifically implemented, and how to solve the high-speed data transmission network during the data transmission process. The problem is described.
  • the granularity in the data stream obtained after data processing may be different for different application scenarios (the higher the granularity, the smaller the minimum unit in the data stream. The lower the granularity, the data stream. The smallest unit is larger).
  • the embodiment of the present invention mainly analyzes two cases, and the other refers to a case where the data stream before data processing and the data stream after data processing do not change. The other is the case where the data stream before data processing and the data stream after data processing have changed. In the second case, the granularity of the data stream after data processing can be larger than the granularity of the data stream before data processing.
  • the present invention gives a case where the granularity of the data stream before and after data processing does not change.
  • a preferred embodiment is specifically:
  • the at least one data stream generated using the matrix of each of M x 1 of the n M x 1 matrices is composed of M data units.
  • M data units in the matrix of the i-th MX 1 in the matrix of n MX 1 and at least one data stream generated by M data units in the matrix of the i-th M x 1 M data units are the same.
  • Each of the N data streams includes the same number of data units.
  • the data streams before and after data processing have the same granularity, and are all data units.
  • the size of the data unit can be either a bit or a symbol.
  • the transmission rates of the N data streams after the data processing are the same. That is to say, the number of data streams obtained after data processing of each M 1 matrix is the same. The number of data units in each data stream in the N data streams is the same. Any one of the n M x 1 matrices can only be used once during the above data processing. For example, M is
  • the matrix of M 1 is specifically a matrix of 16 1 .
  • the 16 1 matrix contains 16 data units.
  • the 16 data units are U0 to U15 from top to bottom. If the 16 ⁇ 1 matrix needs to generate two data streams A1 and A2 for output (ie, two of the N data streams) by data processing, the 16 ⁇ 1 matrix is used for generation.
  • the A1 has 8 data units, for example, 8 data units U0 to U7.
  • the data unit used to generate the A2 is the 8 data units U8 to U15.
  • any one of the 16 data units U0 to U15 cannot simultaneously appear in at least two of the N data streams (e.g., A1 and A2) output by the conversion circuit.
  • any one of the 16 data units U0 to U15 cannot appear in the same data stream (for example, A1 or A2) in the N data streams multiple times.
  • the data stream obtained by each M x 1 matrix is the same. Since it is necessary to generate N data streams, for the matrix of the n M x 1 in the matrix of the M xn, the number of data streams for output generated by each of the M x 1 matrices is N /n. The value of n needs to meet the constraint that N/n is a positive integer.
  • Each of the data units in the matrix of M xn is composed of k sub-data units.
  • the at least one data stream is comprised of MX k sub-data units.
  • the included M x k sub-data units are the same.
  • Each of the N data streams includes the same number of sub-data units.
  • the granularity (that is, the data unit) of the M data streams before data processing is a symbol.
  • the size of a symbol can be 10 bits.
  • the granularity (i.e., sub-data units) of the N data streams obtained after data processing are all bits.
  • each data unit is composed of a plurality of sub-data units having a size of 1 bit (e.g., one symbol is 10 bits).
  • the matrix of any one of the n M x l matrices includes a total of M X k sub-data units.
  • the number of sub-data units in each of the N data streams is the same. Any one of the M x k sub-data units in the n M X 1 matrix can be used only once during the above data processing.
  • the following describes how the data processing solves the problem of high bit error rate in the data transmission process of the high-speed data transmission network, and analyzes at least two different situations in the data processing described above.
  • the N data streams in the first embodiment are further limited, and the granularity of the data stream before and after the data processing does not change, and is limited to:
  • Two adjacent data units in each of the N data streams are from different code words (English: codeword).
  • the granularity of the data stream before and after data processing changes (for example, the granularity of the data stream after the data processing is larger than the granularity of the data stream before the data processing), it is limited to:
  • Two adjacent sub-data units in each of the N data streams are from different code words Codeword.
  • the FEC module in the PCS can receive codewords. After the FEC module converts the codeword into multiple data units, multiple data units are output. The FEC module can also generate codewords and convert the codewords into multiple data units. After the FEC module codeword is converted into multiple data units, multiple data units can be output.
  • a FEC module generates a codeword, the codeword can only be generated by the same FEC module. That is, it is not possible that part of the codeword is generated by one FEC module, and another part of the codeword is generated by another FEC module.
  • the FEC module receives a codeword the codeword can only be received by the same FEC module.
  • the FEC module performs FEC encoding on the data unit and outputs the data unit in the form of a data stream.
  • the codeword size may be different for different FEC algorithms. For example, in the scenario of the RS-FEC (528, 514) algorithm, the size of a codeword is 5280 bits. If a data unit has a size of 10 bits, one code word includes 528 data units.
  • the FEC module After the data unit included in a codeword is output by the FEC module in the form of a data stream or a plurality of data streams, the FEC module will continue to output the data unit included in the received next codeword. That is to say, the data units in the data stream output by one FEC module may all come from the same code word, or may be from different code words.
  • the receiving device performs the reverse operation of the data processing on the data stream on the transmission link, the consecutive multiple erroneous data units that are all from the same codeword are still likely to be located on one data stream or from the same code word. On multiple data streams. Therefore, the receiving device needs to correct a plurality of consecutive erroneous data units in accordance with the FEC principle. The error correction success rate of the receiving device is relatively low.
  • Two adjacent data units in each data stream after the limited data processing are from different code words
  • the consecutive plurality of erroneous data units are respectively from different code words.
  • the consecutive multiple erroneous data units from different codewords are not located on the same data stream, or are not located from the same codeword.
  • the continuity of the erroneous data unit is reduced after the reverse operation of the data processing.
  • the number of erroneous data units belonging to one codeword is also reduced.
  • the two adjacent data units in each of the N data streams from different code words can be implemented in the following two ways:
  • two adjacent data units in each of the N data streams are data units output by two FEC circuits.
  • the granularity of the data stream changes before and after the data processing (for example, the granularity of the data stream after the data processing is larger than the granularity of the data stream before the data processing), the following is adjacent to each of the N data streams.
  • the effect of two sub-data units from different code words is illustrated. Similar to the case where the granularity of the data stream before and after data processing does not change, when two data units adjacent to each data stream after the limited data processing are from different code words, if the data stream after the data processing is in the transmission process If a data stream has consecutive multiple error sub-data units, then these consecutive multiple error sub-data units are from different code words.
  • the receiving device After the receiving device reverses the data processing of the data stream on the transmission link, these consecutive multiple erroneous sub-data units from different codewords will be distributed to multiple data streams from different codewords. Therefore, the continuity of the erroneous sub-data unit is reduced after the reverse operation of the data processing. In addition, the number of erroneous sub-data units belonging to one codeword is also reduced.
  • the receiving device performs error correction on a plurality of data streams having a small number of erroneous sub-data units, the error correction success rate is high.
  • the adjacent two sub-data units in each of the N data streams from different code words can be implemented in the following two ways:
  • FIG. 4a is a schematic diagram of data processing according to an embodiment of the present invention.
  • the conversion circuit 400 has four receiving ports, and receives four data streams Al, A2, A3, and A4, respectively.
  • Each data stream contains 3 data units.
  • the four data streams correspond to a 4 x 3 matrix, and each element in the 4 x 3 matrix is a data unit.
  • the data units in data streams A1 and A2 are all from one codeword.
  • the data units in data streams A3 and A4 are all from another code word.
  • the transform circuit 400a generates three data streams by using four data units in each of the four 4 1 matrixes of the 4 x 3 matrix, respectively.
  • the four data units in each of the 4 1 matrix are processed into one data stream consisting of 4 data units.
  • the location of the data unit in one of the data streams B1 can be as shown. It can be seen that aOl and a04 from the same codeword are separated by bOl from the other codeword, and bOl and b04 from the same codeword are separated by a04 from the other codeword.
  • the four data streams Al, A2, A3, and A4 in Figure 4a can come from the same FEC module. Of course, it is also possible that A1 and A2 come from one FEC module, and A3 and A4 come from another FEC module.
  • Shown in Figure 4a is an example of generating a data stream using a matrix of any one of M x 1 in the matrix of M xn .
  • the case where the granularity of the data stream before and after the data processing changes (for example, the granularity of the data stream after the data processing is larger than the granularity of the data stream before the data processing) is similar to the case shown in FIG. 4a.
  • the only difference is that the smallest unit of the constituent data streams B1, B2 and B3 becomes a sub-data unit constituting the data unit in the data streams A1 to A4.
  • the present invention also provides an embodiment of a data stream after a data processing consisting of M data units in a matrix of M x 1 , specifically:
  • the transforming circuit generates the N data streams by using M data units in the matrix of the n MX 1 to specifically generate the M data units by using M data units in the matrix of the jth MX 1 At least one data stream.
  • the generating, by using the M data units in the matrix of the jth MX 1 , the at least one data stream composed of the M data units specifically includes: the transform circuit interleaving the X groups of data units to generate the M data units.
  • the M data units in the matrix of the jth M X 1 specifically include the X groups of data units.
  • the number of data units in each group of data units is M/X.
  • the codeword from which the data unit in any one of the X sets of data units is derived is different from the codeword from which the data unit in the other set of data units in the X set of data units is derived.
  • X is an integer greater than one.
  • the position shown by j has a 4 x 1 matrix.
  • the 4 x 1 matrix includes aO1 and a04 from the same codeword, and bO1 and b04 from the other codeword.
  • the 4 ⁇ 1 matrix contains the above four data units.
  • X may be 2 or 4.
  • the above 4 data units are divided into 2 sets of data units.
  • the codeword from which the data unit of the data unit of the two sets of data units is derived is different from the codeword from which the data unit of the other of the two sets of data units is derived.
  • one set of data units consists of aOl and a04
  • the other set of data units consists of bOl and b04.
  • each group of data units includes only one data unit.
  • the interleaving method generally takes one data unit from each group of interleaving and then arranges them in the same order. Then, one data unit is taken from each of the interleaved groups, and then the previous arrangement continues to continue in the same arrangement order. Until the data units contained in each group of data units are arranged. Any two adjacent data units in the data stream thus interleaved must come from different code words.
  • each time a data unit is fetched from each group may be in a certain order of selection, so that when the data stream is subsequently operated, it can effectively determine which code word or which FEC module the data unit comes from.
  • X two sets of data units, by aOl and a04
  • the aOl of the set of data units is located in front of a04.
  • the bO1 of the set of data units consisting of bO1 and b04 is located in front of b04.
  • the order of selection for interleaving may be that the first aOl and bOl are arranged in order, and then the subsequent a04 and b04 are selected in the same order. Alternatively, first select the data unit located at the back and then select the data unit at the front.
  • the present invention does not limit how interleaving is performed, as long as any two adjacent data units in the data stream ultimately composed for output are from different code words.
  • the data processing of the integer multiple coefficient may specifically be to interleave a plurality of data streams (three data streams) into one data stream.
  • the present invention also provides an embodiment of a data stream after a data processing consisting of M X k sub-data units in a matrix of M X 1 , specifically:
  • the transform circuit generates the N data streams by using M x k sub-data units in the matrix of the n M x 1 to specifically generate MX k sub-data units in a matrix of the j-th MX 1 to generate M x k sub-sub- At least one data stream composed of data units.
  • the M X k sub-data units in the matrix of the jth M x l are used to generate at least one data stream consisting of M x k sub-data units including:
  • the transform circuit interleaves the X sets of sub-data units to generate a data stream consisting of M X k sub-data units.
  • the M x k sub-data units in the matrix of the j-th M X 1 specifically include the X-group sub-data units.
  • the number of sub-data units in each group of sub-data units is (M x k ) /X.
  • the codewords from which the sub-data units of any one of the X sets of sub-data units are derived are different from the codewords from which the sub-data units of the other sets of sub-data units of the X-group of sub-data units are derived.
  • X is an integer greater than one.
  • the position shown by j has a 4 x 1 matrix.
  • the 4 x 1 matrix is included from a oi and a04 of the same codeword, and bOl and b04 from another codeword.
  • the matrix of 4 ⁇ 1 includes the above four data units, each of which is a symbol of size, and a symbol size of 10 bits is taken as an example, that is, one data unit contains 10 sub-data units.
  • X may be 2 or 4.
  • the 40 sub-data units included in the above 4 data units are divided into 2 groups of sub-data units, and the sub-data units belonging to the same data unit are divided into the same group of sub-data units.
  • the codewords from which the sub-data units of the set of sub-data units are from the two sets of sub-data units are different from the codewords from which the sub-data units of the other set of sub-data units of the two sets of sub-data units are derived.
  • one set of sub-data units is composed of a total of 20 sub-data units included in aO1 and a04
  • the other set of sub-data units is composed of a total of 20 sub-data units included in bO1 and b04.
  • X is 4
  • the 40 sub-data units included in the above 4 data units are divided into 4 groups of sub-data units, and the sub-data units belonging to the same data unit are divided into the same group of sub-data units.
  • the interleaving method generally takes one sub-data unit from each group of interleaving and then arranges them in the same order. Then, one sub-data unit is taken from each of the interleaved groups, and then the previous permutation continues to be arranged in the same permutation order. Until the sub-data units contained in each group of sub-data units are arranged. Any two adjacent sub-data units in the data stream thus interleaved must come from different code words.
  • each time a sub-data unit is fetched from each group may be in a certain order, so that when the data stream is subsequently operated, it can effectively determine which code word or which FEC module the sub-data unit comes from.
  • the present invention does not limit how interleaving is performed, as long as any two adjacent sub-data units in the data stream for the final output are from different code words.
  • the bit error rate generated during data transmission on the transmission link is relatively high.
  • the data stream transmitted on the transmission link may have consecutive data units with errors. How to reduce the impact of the data unit in which the error occurred on the entire transmission network is also a problem that needs to be solved.
  • a preferred embodiment of the invention is provided for this purpose.
  • the data streams A1 to A4 are data streams that are not subjected to data processing.
  • A1 and A2 come from one FEC Module.
  • A3 and A4 come from another FEC module.
  • the data streams A1 to A4 are subjected to data processing as shown in Fig. 4a to obtain data streams B1 to B3.
  • the data streams B1 to B3 are transmitted to the receiving device.
  • the receiving device performs a reverse operation of data processing on the data streams B1 to B3.
  • Figure 4b is a schematic diagram of a reverse operation of data processing in accordance with the present invention.
  • the data stream B 1 has an error (such as a black bold rectangle) in the four data units a01, b01, a04, and b04 in B1 during transmission.
  • the receiving device 400b performs the data streams A1 to A4 obtained after the reverse operation operation of the data processing.
  • the above four error-generating data units are respectively distributed in A1 to A4.
  • the success rate of the error correction of the A1 to A4 data streams by the receiving device 400b is greater than the success rate of error correction for a data stream containing four consecutive data units (eg, aO1, bO1, a04, and b04) that have errors. .
  • the granularity of the data stream after the data processing is approximately the granularity of the data stream before the data processing
  • the continuous error data unit appears on the transmission link
  • the data The case where the granularity of the data stream before and after processing does not change is similar, except that the granularity of the data streams B1 to B3 in the transmission process become sub-data units.
  • the granularity of the data stream obtained after the reverse operation of the data processing will be restored to the granularity before the data processing.
  • the effect of error correction on the error data unit and the granularity of the data stream before and after data processing are the same.
  • the error data unit in the data stream after the reverse operation of the data processing is the same, and will not be described here.
  • FIG. 5a is a schematic diagram of data processing according to an embodiment of the present invention.
  • the conversion circuit 500a has eight receiving ports, and receives eight data streams A1 to A8, respectively.
  • Each data stream contains 3 data units.
  • the above 8 data streams correspond to a matrix of 8 x 3 .
  • Each element in the 8 x 3 matrix is a data unit.
  • the data units in data streams A1 through A4 are all from one codeword, and the data units in data streams A5 through A8 are all from another codeword.
  • the transform circuit 500a generates six data streams using data units in three 8 ⁇ 1 matrices in the 8 ⁇ 3 matrix, respectively.
  • Each of the 8 X 1 matrices generates two data streams consisting of 8 data units.
  • Each data stream consists of 4 data units.
  • the adjacent two data units in any of the two data streams generated are from different code words.
  • the distribution of data units in the two data streams B1 and B2 obtained by data processing can be as shown in Fig. 5a.
  • AOl and a04 from the same codeword are separated by bOl from the other codeword.
  • A07 and alO from the same codeword are separated by b07 from another codeword.
  • the eight data streams A1 through A8 in Figure 5a may be from the same FEC module. It is also possible that A1 to A4 are from one FEC module and A5 to A8 are from another FEC module.
  • Figure 5a is a schematic diagram of the generation of two data streams for a matrix of any one of the M x n matrices.
  • the granularity of the data stream changes before and after data processing (for example, the granularity of the data stream after the data processing is larger than the granularity of the data stream before the data processing))
  • the difference is only the composed data stream.
  • the smallest unit in B1 to B6 becomes a sub-data unit constituting the data unit in the data streams A1 to A8.
  • the present invention also provides an embodiment of a preferred two data streams consisting of M data units in a matrix of M x 1 , specifically:
  • the generating, by using the M data units in the matrix of the n MX 1 to generate the N data streams specifically includes: generating, by using M data units, M data units in the matrix of the jth MX 1 At least one data stream.
  • the generating, by using the M data units in the matrix of the jth M x 1 to generate the at least one data stream that is composed of the M data units specifically includes:
  • the transform circuit interleaves the Q sets of data units in each of the P sets to generate P data streams consisting of M data units.
  • the M data units in the matrix of the jth MX 1 are the same as all the data units in the P sets.
  • Each of the P sets is composed of
  • the Q group data unit is composed.
  • the codeword from which the data unit of any one of the Q data units is derived is different from the codeword from which the data unit of the other group of data units in the Q data unit is derived.
  • the number of data units in each group of data units is M/( PXQ ). Both P and Q are integers greater than one.
  • the position described in j in Figure 5a contains an 8 x 1 matrix.
  • the 8 x 1 matrix consists of a01, a04, a07, and al0 from the same codeword, and eight data units b01, b04, b07, and blO from the other codeword.
  • the two data streams generated after data processing have the same number of data units.
  • Each of the two sets includes 4 data units. Since each codeword from which the data unit in any one of the Q data units has to be satisfied is different from the code word from which the data unit in the other group of data units in the Q group data unit is derived, in each set The number of data units from different codewords is equal.
  • any two of a01, a04, a07, and alO from the same codeword and any two of b01, b04, b07, and blO from another codeword.
  • Q can take 2 or 4. Take a collection containing aOl, a04, bOl, and b04 as an example.
  • Q Take a collection containing aOl, a04, bOl, and b04 as an example.
  • Q 2
  • the above four data units are divided into two sets of data units.
  • the codeword from which the data unit of any one of the two sets of data units is derived is different from the codeword from which the data unit of the other set of data units of the two sets of data units is derived.
  • One of the two sets of data units consists of a oi and a 04, and the other set of data units consists of bOl and b04.
  • Q is 4, the above four data units are divided into four groups of data units. Each group of data units includes only one data unit.
  • the 6 data streams are further processed for data.
  • the data processing of the integer multiple coefficient may specifically be that multiple data streams (two data) Stream) interleaved into a stream of data.
  • the present invention also provides a preferred matrix in an MX 1 matrix.
  • An embodiment of the MX k sub-data units constituting two data streams is specifically: the transform circuit generating the N data streams by using the M x k sub-data units in the n M x 1 matrices, including using the jth MX k sub-data units in the matrix of MX 1 generate at least one data stream composed of M x k sub-data units, wherein MX k sub-data are generated by using MX k sub-data units in the matrix of the j-th M x 1
  • the at least one data stream composed by the unit specifically includes:
  • the transform circuit interleaves Q groups of sub-data units in each of the P sets to generate P data streams consisting of MX k sub-data units, MX k of the j-th MX 1 matrix
  • the data unit is identical to all of the P data sets, and each of the P sets is composed of a Q group of sub data units, and any one of the Q group of sub data units is in the sub data unit.
  • the codeword from which the sub-data unit is derived is different from the codeword from which the sub-data unit in the other group of sub-data units in the Q-group sub-data unit is derived, and the number of sub-data units in each group of sub-data units is (M xk ) / ( P x Q ), P and Q are all integers greater than one.
  • the position described in j in Figure 5a contains an 8 x 1 matrix.
  • the matrix of 8 ⁇ 1 includes a01, a04, a07, and al0 from the same codeword, and 8 data units b01, b04, b07, and blO from another codeword.
  • Any 8 x 1 matrix generates two data streams.
  • P 2.
  • the size of each data unit is a symbol, and a symbol size of 10 bits is taken as an example, which is equivalent to one data unit containing 10 sub-data units.
  • the 80 sub-data units included in the above 8 data units are divided into two sets.
  • the number of sub-data units from different codewords in each set is equal.
  • 40 sub-data units included in aO1, a04, bO1, and b04 are preferably placed in one set, and 40 sub-data units included in a07, al0, b07, and blO are placed in another set.
  • the 40 sub-data units in each set constitute a Q group of sub-data units.
  • Q can take 2 or 4. Containing 40 sub-data units contained in aOl, a04, bOl, and b04 The collection is an example.
  • Q is 2
  • the above 40 sub-data units are divided into two groups of sub-data units.
  • the codewords from which the sub-data units of any one of the two sets of sub-data units are derived are different from the codewords from which the sub-data units of the other sets of sub-data units of the two sets of sub-data units are derived.
  • One set of sub-data units of the two sets of sub-data units is composed of 20 sub-data units included in aO1 and a04, and the other set of sub-data units is composed of 20 sub-data units included in bO1 and b04.
  • Q 4
  • the above 40 sub-data units are divided into 4 groups of sub-data units. Each group of sub-data units includes only 10 sub-data units contained in one data unit.
  • the present invention does not limit how interleaving is performed, as long as any two adjacent sub-data units in the data stream ultimately composed for output are from different code words.
  • During the data transmission after data processing there may be consecutive consecutive data units with errors in the data stream transmitted on the transmission link.
  • a preferred embodiment of the invention is provided for this purpose.
  • the data streams A1 to A8 are data streams that have not been subjected to data processing.
  • A1 to A4 come from an FEC module.
  • A5 to A8 come from another FEC module.
  • the data streams A1 to A8 are subjected to data processing as shown in Fig. 5a to obtain data streams B1 to B6.
  • Data streams B1 through B6 are sent to the receiving device.
  • the receiving device performs a reverse operation of data processing on the data streams B1 to B6. Specifically, the reverse operation corresponding to the data processing rules of the data streams B1 to B6 is processed using the data streams A1 to A8.
  • FIG. 5b is a schematic diagram of a reverse operation of data processing according to an embodiment of the present invention.
  • the data stream B 1 has an error (such as a black bold rectangle) in the four data units aO1, bO1, a04, and b04 in B1 during transmission.
  • the receiving device 500b performs the data streams A1 to A8 obtained after the reverse operation operation of the data processing.
  • the above four error-generating data units are distributed in Al, A2, A5, and A6, respectively. There are no consecutive erroneous data units in the four data streams, and the number of erroneous data units in the same code word is also reduced.
  • data streams A1 and A2 from the same codeword have only two erroneous data units, and no four erroneous data units are distributed in the data stream from the same codeword.
  • the FEC module that corrects errors on A1 and A2 only needs to face two erroneous data units (one data stream and one erroneous data unit).
  • the receiving device 500b The success rate of error correction for the Al, A2, A5, and A6 data streams, respectively, is greater than the success rate for error correction of a data stream containing four consecutive data units that have errors (eg, a01, b01, a04, and b04).
  • the granularity of the data stream changes before and after data processing (for example, the granularity of the data stream after the data processing is larger than the granularity of the data stream before the data processing), when the continuous error data unit appears on the transmission link, and the data
  • the granularity of the data stream before and after processing is similar, except that the granularity of the data streams B1 to B6 in the transmission process become sub-data units, and the granularity of the data stream obtained after the reverse operation of the data processing is restored.
  • the granularity before data processing The effect of error correction on the error data unit and the granularity of the data stream before and after data processing are the same.
  • the error data unit in the data stream after the reverse operation of the data processing is the same, and will not be described here.
  • the FEC module in the PCS converts the received codeword into a data unit.
  • the converted data unit can be 1 bit in size or symbol Symbol.
  • the size of a Symbol can be one or more bits, such as 10 bits.
  • the commonly used data processing generally includes two methods.
  • One data processing method has the same granularity of the data stream before and after the data processing, that is, the minimum composition of the data stream before and after the data processing is the data.
  • the unit, and the size of the data unit are the same. For example, the data unit size of the data stream before data processing is a symbol, and the data unit size of the data stream after the data processing is also a symbol.
  • Another way of data processing is that the granularity of the data stream before and after data processing is different.
  • the omitted data unit size before data processing is a symbol
  • the minimum composition of the data stream after data processing becomes a sub-data unit constituting the data unit.
  • each sub-data unit size is a bit.
  • FIG. 6a is the present invention.
  • FIG. 6a A schematic diagram of a data processing provided by an embodiment.
  • the granularity of the data stream after data processing is bit
  • the granularity of the data stream before data processing is a symbol
  • each data unit is composed of a plurality of sub-data units
  • the data stream after data processing is composed of sub-data units.
  • the sub-data unit size is a bit, and each sub-data unit is a sub-data unit included in the data unit before data processing.
  • the conversion circuit 600a has four receiving ports. Four data streams Al, A2, A3, and A4 are received, respectively. Each data stream contains 3 data units, each of which is a symbol of size. These 4 data streams correspond to a 4 x 3 matrix. Each element in the 4 x 3 matrix is a symbol, each symbol H does not include 10 sub-data units, and each sub-data unit is 1 bit.
  • the transform circuit 600a generates three data streams by using data units in three 4 ⁇ 1 matrices of the 4 x 3 matrix, respectively.
  • the granularity of the generated data stream is increased, so that the granularity of each data stream after the generation is increased to a sub-data unit.
  • B1 as shown in Fig. 6a is a data stream processed by bit-sized data.
  • B1 is composed of 40 sub-data units of size 1 bit, wherein each sub-data unit consists of one bit.
  • FIG. 6b is a schematic diagram of data processing according to an embodiment of the present invention.
  • the granularity of data processing is a symbol, that is, the data streams before and after data processing are all composed of data units.
  • the conversion circuit 600b has four receiving ports, and receives four data streams Al, A2, A3, and A4, respectively.
  • Each data stream contains 3 data units, each of which is a symbol of size, and these 4 data streams correspond to a 4 x 3 matrix.
  • Each element in the 4 x 3 matrix is a symbol.
  • the transform circuit 600b generates three data streams by using data units in three 4 X 1 matrices in the 4 x 3 matrix, respectively.
  • B1 as shown in Fig. 6b is the same as the data stream before data processing, and is composed of data units of size and symbol.
  • Embodiment 3 The data processing between the layers of the electric layer needs to be symbolized.
  • the embodiment of the symbol-sized interleaving method provided by the present invention can effectively be compatible with data processing between the electrical layer and the optical layer. If any two adjacent symbols in the data stream after the data processing are from different code words, the optical module design complexity of the optical layer can be effectively simplified, and the cost reduction effect can be achieved.
  • Embodiment 3 the symbol-sized interleaving method provided by the present invention can effectively be compatible with data processing between the electrical layer and the optical layer. If any two adjacent symbols in the data stream after the data processing are from different code words, the optical module design complexity of the optical layer can be effectively simplified, and the cost reduction effect can be achieved.
  • This embodiment is an apparatus embodiment corresponding to the first embodiment and the second embodiment.
  • FIG. 7 it is a structural diagram of a data processing apparatus according to an embodiment of the present invention.
  • the apparatus includes: a receiving unit 701, M data streams are received through M receiving ports.
  • the M Each data stream in the data stream includes n data units.
  • the M receiving ports correspond to the M data streams.
  • the M data streams correspond to a matrix of MX n .
  • Each element in the matrix of MX n is a data unit.
  • the matrix of M xn includes M lxn matrices.
  • Each of the matrix of 1 X X n matrix corresponds to 1 data stream.
  • the M 1 xn matrices correspond to the M data streams.
  • n data units in the matrix of each of 1 M ⁇ ⁇ of the M 1 X n matrices are respectively n data units in the corresponding data stream.
  • the data unit located on the right of any two of the n data units in the matrix of 1 ⁇ ⁇ in the matrix of 1 ⁇ is received by the conversion circuit earlier than the data located on the left side The time at which the unit was received by the transform circuit.
  • the receiving unit 701 can be specifically a receiver.
  • the generating unit 702 is configured to generate N data streams by using M data units in the matrix of n M x 1 in the matrix of the ⁇ ⁇ ⁇ , respectively.
  • Generating the N data streams specifically includes generating at least one data stream by using a matrix of each of the n M X 1 matrices.
  • the generating unit 702 can be specifically a converter. For a description of the generating unit, refer to the related description in Embodiment 1 S202, and details are not described herein again.
  • the output unit 703 is configured to send the N data streams through the N output ports.
  • the N output ports correspond to the N data streams. Where M and N are both positive integers.
  • the output unit 703 can be specifically a transmitter.
  • the output unit 703 can be specifically a transmitter.
  • the generating unit refer to the related description in Embodiment 1 S203, and details are not described herein again.
  • the apparatus shown in FIG. 7 can implement the data processing methods in Embodiment 1 and Embodiment 2.
  • the granularity of the data stream after the data processing may be changed compared to the granularity of the data stream before the data processing, and the at least one data stream generated by the generating unit 702 according to the granularity of the data processing may be
  • the data unit composition can also consist of sub-data units.
  • a description of the granularity of the data flow please refer to the related description in the second embodiment. Said.
  • the present invention provides a preferred embodiment, specifically:
  • the at least one data stream generated by the generating unit 702 is composed of M data units.
  • the data units are the same.
  • Each of the N data streams includes the same number of data units.
  • Each of the data units in the matrix of ⁇ consists of k sub-data units.
  • the at least one data stream generated by the generating unit 702 is composed of Mxk sub-data units.
  • the sub-data units are the same.
  • Each of the N data streams includes the same number of sub-data units.
  • the N data streams are further limited, and the granularity of the data stream before and after the data processing does not change, and is limited to: each of the N data streams generated by the generating unit 702 Adjacent two of the data streams
  • the data units are from different code words.
  • the granularity of the data stream before and after data processing changes (for example, the granularity of the data stream after the data processing is larger than the granularity of the data stream before the data processing), it is limited to:
  • Two adjacent sub-data units in each of the N data streams generated by the generating unit 702 are from different code words.
  • the two adjacent data units in each of the N data streams generated by the generating unit 702 are data units output by the same forward error correction FEC circuit.
  • two adjacent data units in each of the N data streams generated by the generating unit 702 are data units output by two FEC circuits.
  • the mode 1 of each of the N data streams is Two adjacent sub-data units of each of the N data streams generated by the generating unit 702 belong to two data units output by the same forward error correction FEC circuit.
  • two adjacent sub-data units in each of the N data streams generated by the generating unit 702 are from two FEC circuits.
  • the embodiment of the invention further provides a preferred generating unit, which is specifically:
  • the generating unit 702 generates at least one data stream composed of M data units using M data units in the matrix of the jth M x 1 .
  • the generating, by using the M data units in the matrix of the jth M x 1 , the at least one data stream that is composed of the M data units specifically includes: the generating unit 702 interleaving the X groups of data units to generate the M data.
  • the M data units in the matrix of the jth M x 1 specifically include the X group data units.
  • the number of data units in each group of data units is M/X.
  • the codeword from which the data unit in any one of the X sets of data units is derived is different from the codeword from which the data unit in the other set of data units in the X set of data units is derived, and X is an integer greater than one.
  • the generating unit 702 generates the N data streams by using the M x k sub-data units in the matrix of the n M x 1 to specifically generate the M xk by using MX k sub-data units in the matrix of the jth MX 1 At least one data stream consisting of sub-data units.
  • generating at least one data stream composed of M x k sub-data units by using M x k sub-data units in the matrix of the jth M x 1 specifically includes:
  • the generating unit 702 interleaves the X sets of sub-data units to generate a data stream composed of M x k sub-data units.
  • the M x k sub-data units in the matrix of the jth M x 1 specifically include the X sets of sub-data units.
  • the number of sub-data units in each group of sub-data units is (M x k) /X.
  • the codewords from the sub-data units of any one of the X sets of sub-data units are different from the codewords from which the sub-data units of the other sets of sub-data units of the X-group of sub-data units are derived.
  • X is an integer greater than one.
  • the generating unit 702 generates a plurality of data streams by using a matrix of any one of the matrices of M X n .
  • the generation unit 702 will use the matrix of any one of M X 1 to generate two data streams as an example for description.
  • the granularity of the data stream before and after data processing has not changed:
  • the generating unit 702 generates at least one data stream composed of M data units by using M data units in the matrix of the jth M x 1 , wherein the M data units in the matrix of the jth M x 1 are utilized
  • Generating at least one data stream consisting of M data units specifically includes: the generating unit 702 interleaving the Q group data units in each of the P sets to generate P data streams composed of M data units.
  • the M data units in the matrix of the jth M X 1 are the same as all the data units in the P sets.
  • Each of the P sets is composed of Q sets of data units.
  • the codewords from any of the set of data units in the Q group of data units are different.
  • the number of data units in each set of data units is M/( P x Q ). Both P and Q are integers greater than one.
  • the generating unit 702 generates the N data streams by using the M x k sub-data units in the matrix of the n M x 1 to specifically generate the M xk by using MX k sub-data units in the matrix of the jth MX 1 At least one data stream composed of the sub-data units, wherein generating at least one data stream composed of M x k sub-data units by using M x k sub-data units in the matrix of the j-th M x 1 specifically includes:
  • the generating unit 702 interleaves the Q group of sub data units in each of the P sets to generate P data streams composed of MX k sub data units.
  • the M x k sub-data units in the matrix of the j-th MX 1 are the same as all the sub-data units in the P sets.
  • Each of the P sets consists of Q sets of sub-data units.
  • the codeword from which the sub-data unit of any one of the Q sub-data units is derived is different from the codeword from which the sub-data unit of the other group of sub-data units of the Q-group sub-data unit is derived.
  • the number of sub-data units in each group of sub-data units is (M xk ) / ( P x Q ). Both P and Q are integers greater than one.
  • the technical solution of the present invention which is essential or contributes to the prior art, may be embodied in the form of a software product, which may be stored in a storage medium such as a ROM/RAM or a disk.
  • An optical disk or the like includes instructions for causing a computer device (which may be a personal computer, a server, or a network communication device such as a media gateway) to perform the methods described in various embodiments of the present invention or portions of the embodiments.

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  • Error Detection And Correction (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

La présente invention concerne, dans le mode de réalisation décrit, un procédé et appareil de traitement de données. Chaque flux parmi M flux de données reçus par un circuit de conversion comporte n unités de données, les M flux de données correspondant à une matrice M×n dont chaque élément est une unité de données, le circuit de conversion emploie M unités de données dans n matrices M×1 au sein de la matrice M×n pour générer N flux de données, et la génération des N flux de données comportant spécifiquement les étapes consistant à employer chaque matrice M×1 parmi les n matrices M×1 pour générer au moins un flux de données. Comme on peut le voir ici, lorsque le circuit de conversion effectue un traitement de données des M flux de données vers les N flux de données, les M flux de données avant le traitement de données correspondent à une seule matrice M×n. Les N flux de données sont obtenus respectivement par le traitement de données des n matrices M×1 au sein de la matrice M×n. Dans la solution technique décrite ci-dessus, le traitement de données est relativement souple, ce qui se prête à la satisfaction des exigences de développement d'Ethernet.
PCT/CN2014/078021 2014-05-21 2014-05-21 Procédé et appareil de traitement de données WO2015176252A1 (fr)

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WO2005076554A1 (fr) * 2004-02-05 2005-08-18 Zakrytoe Aktsionernoe Obschestvo Intel Procede et appareil pour reduire la diaphonie dans un systeme de communication mimo
CN101242189B (zh) * 2007-02-09 2010-05-19 卓胜微电子（上海）有限公司 指针寻址时间解交织方法
CN101944972B (zh) * 2010-09-20 2013-04-24 华为技术有限公司 编解码方法、装置以及通信系统
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CN1728629A (zh) * 2005-07-27 2006-02-01 杭州华为三康技术有限公司 多路物理层接口复用传输装置
CN101854222A (zh) * 2009-03-31 2010-10-06 华为技术有限公司 一种数据处理的方法、通信装置和系统
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US20140091958A1 (en) * 2012-09-28 2014-04-03 Nicholas P. Cowley Methods and arrangements for high-speed digital-to-analog conversion

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