WO2015174979A1

WO2015174979A1 - Intrinsically safe universal i/o device using programmable asic

Info

Publication number: WO2015174979A1
Application number: PCT/US2014/038074
Authority: WO
Inventors: Daniel Milton ALLEY; Robert Villamil
Original assignee: Ge Intelligent Platforms, Inc.
Priority date: 2014-05-15
Filing date: 2014-05-15
Publication date: 2015-11-19

Abstract

Provided a universal input output (I/O) device controllable via a controller for processing two or more signal types. The I/O device includes two or more channel switch blocks and two or more progammable gain amplifier (PGA), each of the PGAs corresponding to one of the channel switch blocks. The controller is configured to (i) control settings of each of the PGAs and (ii) connect each of the channel switch blocks to user terminals via an analog to digital converter (ADC) and at least one digital to analog converter (DAC) via the PGA settings. Each of the swith blocks is configurable for assignment to all of the signal types. Current levels associated with the PGA control settings are limited to threshold values to ensure intrinsic safety.

Description

INTRINSICALLY SAFE UNIVERSAL I/O DEVICE

USING PROGRAMMABLE ASIC

I. Field of the Invention

[0001] The present invention relates generally to universal analog input/output (I/O) devices. More particularly, the present invention relates to an application specific integrated circuit (ASIC) I/O configured for channel switching and fault detection.

II. Background of the Invention

[0002] Conventional I/O devices are manufactured for operation in a number of different environments subjected to a variety of certification standards. One such standard is the atmosphere explosibles (ATEX) certification, which requires special sealed cabinets with wiring contained within their threaded sealed conduits. Similar cabinets are routinely used on oil rigs, and other similar environments.

[0003] The conventional I/O devices also are configured for accommodating many different signal modes including, for example, resistance temperature detectors (RTDs), thermocouples, microampere loop in, microampere loop out, highway addressable remote transmitter (HART) in, and HART out. In these arrangements, each device's electronics is optimized for performance including safety.

[0004] The use of programmable electronic devices providing coverage of these signal modes and types (e.g. universal analog I/O) can greatly reduce the quantity of types of devices installed at a site, simplifying installation and recurring maintenance costs. However, the universal nature of the device channels requires that the same intrinsic safety requirements, such as those directed by International Electrotechnical Commission (IEC) standard 60079, apply at all times on all modes of device configurations.

[0005] Another consideration is that non-intrinsically safe field wiring must he placed in a threaded rigid metal conduit per National Electrical Code (NEC) Standard 501.10. Use of threaded conduit protects the wiring from cuts that could cause a spark.

[0006] Given the various performance and safety requirements, conventional approaches are devoid of a single, programmable or reconfigurable device capable of satisfying the performance requirements, while at the same time satisfying intrinsic safety requirements.

III. Summary of Embodiments of the Invention

[0007] Given the aforementioned deficiencies, a need exists for methods and systems for use on oil rigs, and similar environments, for providing intrinsically safe circuits while eliminating the need for multiple devices.

[0008] In certain circumstances, in embodiment of the present invention includes a universal input output (I/O) device controllable via a controller for processing two or more signal types. The I/O device includes two or more channel switch blocks and two or more programmable gain amplifier (PGA), each of the PGAs corresponding to one of the channel switch blocks. The controller is configured to (i) control settings of each of the PGAs and (ii) connect each of the channel switch blocks to user terminals via an analog to digital converter (ADC) and at least one digital to analog converter (DAC) via the PGA settings. Each of the switch blocks is configurable for assignment to all of the signal types.

[0009] Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. It is noted that the invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.

IV. Brief Description of the Drawings

[0010] The accompanying drawings, which are incorporated herein and fonn part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the relevant art(s) to make and use the invention.

[0011] FIG. 1 is a block diagram illustration of an exemplary universal I/O device constructed and arranged in accordance with an embodiment of the present invention.

[0012] FIGs. 2A - 2C are more detailed block diagram illustrations of the exemplary I/O device of FIG. 1 associated with various signal types.

[0013] FIG. 3 is a more detailed block diagram illustration of an exemplary current limiting component for intrinsic safe modes of the device of FIG. 1.

[0014] FIG. 4 is an illustration of exemplary signal paths within a channel of the I/O device depicted in FIG. 1. [0015] FIG. 5 is an exemplary illustration of a technique for a redundant I/O device in accordance with embodiments of the present invention.

[0016] FIG. 6 is an illustration of an exemplary method of practicing an embodiment of the present invention.

V. Detailed Description of Embodiments of the Invention

[0017] While the present invention is described herein with illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those skilled in the art with access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the invention would be of significant utility.

[0018] A universal I/O device constructed in accordance with the embodiments can be configured and programmed to replace the need for a quantity of other products (e.g.,

ASICs). For example, in cases where a particular test bed creates the need for multiple

ASICs because of different equipment, connection, and signal types, embodiments of the present invention facilitate use of a single ASIC instead of multiple ASICs.

[0019] Additionally, intrinsic safety is provided where energy available at user terminals must be minimized to reduce occurrences of sparks. In some cases, sparks can be catastrophic, especially in explosive atmosphere environments.

[0020] In the embodiments, the features noted above are built into the ASIC itself, using switch channel blocks to provide switching between one or more DACs and an

ADC, for performance measurements. Simultaneously, gain and fault detection are also provided. [0021] Embodiments of the present invention include a method of using a universal I/O ASIC capable of intrinsic safety to provide both mode switching and support of fault detection towards meeting I EC standard 60079 requirements for intrinsic safety, while not requiring the threaded conduit to protect the cables.

[0022] Each channel of the interface may be assigned to different signal types, with all channels limited in energy sufficient to satisfy intrinsic safety standards. Energy limiting exists at the channel switching for signal types through internal circuitry within an ASIC, limit circuitry at the DAC output stages, and at the I/O device terminal board.

[0023] FIG. 1 is a block diagram illustration of an exemplary universal I/O device 100 constructed and arranged in accordance with an embodiment of the present invention. The exemplary I/O device 100 uses a pair of channel switch blocks 101 a and 101b for selectively facilitating connectivity to a variety of external devices. In providing multiple separate channel switch blocks 101a and 101b, the embodiments enable each channel of the I/O device to be assigned to a different signal type, with all channels sufficiently limited in energy to satisfy intrinsic safety standards.

[0024] In the embodiments, the intrinsic safety aspects ensure that for user specified voltage potentials, an amount of corresponding available current that can flow is inherently limited. It is recognized that the enhanced user programmability and configurability, provided in the embodiments, also introduces levels of risk. For example, a user could inadvertently configure or wire the system for improper signal paths. [0025] In the absence of corresponding intrinsic safety features, this inadvertent configuration could unknowingly result in voltage levels that could produce a spark. In the embodiments, when safety mode is activated, current levels are limited to user programmable thresholds. These thresholds prevent the current from reaching levels high enough to cause a spark or trigger an explosion.

[0026] By way of example and not limitation, each of the channel switch blocks 101a and 101b may be assigned to signal types such as RTD, voltage and thermocouple, contact, mA and HART, solid state contact and the like. The signal types, or modes, are selectable via user programmable via user programmable signal paths. Although the I/O device 100 uses two channels, the present invention is not so limited. For example, the present invention can include I/O devices having two or more channel switch blocks pairs or channel switch blocks.

[0027] In FIG. 1, the I/O device 100 includes DACs 102a/102b and an ADC 104. The DACs 102a and 102b convert current or voltage signals associated with the channel switch blocks 101a and 101b, respectively. In addition to providing conversions, the DACs 102a/ 102b provide an additional measure of safety by ensuring that sale voltage output ranges associated with supply voltages for one signal mode will be consistent with voltage output ranges associated with other signal modes.

[0028] High side and low side power switches are provided for digital power control. High side switches (HSSW) 103a and 103b are provided for high-side channels A & B, respectively. HSSW 103a and 103b include current limiting and timing to protect against short conditions from wiring faults. Similarly, low side switches 103c and 103d are provided for low-side channels A & B, respectively. HSSW 103c and 103d provide paths to common, with overcurrent detection.

[0029] Similar to a conventional circuit breaker, the overcurrent condition will force the switches to open while sending fault information to the ASIC status registers within the logic control module 112 for access by the interface 118. Intrinsic safety requires that the amount of current be low - limiting to under 50 mA at 24V operation for the high side switches.

[0030] User tenninations, or terminals (e.g., screws) 10S provide a connection point for interface types, such as wire interfaces. The terminals 10S also include intrinsic safety mechanisms, such as electrostatic discharge (BSD) protection, in addition to providing electromagnetic compatibility (EMC) filtering.

[0031] One or more PGAs 109 allow channels within the I/O device 100, such as channels associated with the channel switch blocks 101a and 101b, to sense combinations of terminal and mA sensing inputs. A logic control module 1 12 provides microprocessor control of the I/O device 100 via the DACs 102a/l02b, and the ADC 104. The logic control module 1 12 also provides control of settings within the PGAs 109 and switches within the device 100 via control logic 1 14.

[0032] An isolation boundary 116 provides electrical isolation between external conductors and minimizes inductances as one further intrinsic safety feature. For example, the isolation barrier 116 limits the level of energy traversing the terminals 105.

[0033] An I/O interface 1 18, via an Ethernet connection, a backplane, or a conventional PLC, facilitates connection between the external I/O device 100 and external modules, other ASICs, and the like. In a universal I/O device constructed in accordance with the embodiments, about 80% of the circuit design is of similar design. By way of example, and not limitation, in the example of FIG. 1, circuitry within the I/O device 100 is substantially reproducible within ASICS across various product lines.

[0034] FIGs. 2A - 2C are more detailed block diagram illustrations of the exemplary I/O device 100 of FIG. 1 associated with various signal types. That is, the I/O device 100 can be assigned to RTD, voltage and thermocouple, and HART signals, to name a few. A circuit 200 in FIG. 2A, for example, is programmed for assignment to RTD signals. Embodiments of the present invention are not limited to the implementation depicted in FIG. 2A. For example, the I/O device 100 can accommodate 2, 3, or 4-6 wire RTDs, and the like.

[0035] Similarly, a circuit 202 in FIG. 2B can be programed for assignment to thermocouple and voltage inputs signals. An exemplary circuit 204 can be programmed for assignment to current loop devices. As stated above with respect to FIG. 2A, embodiments of the present invention are not limited to the depictions of FIGs. 2B and 2C. Other implementations of thermocouple, voltage, and current loop devices, covering many other the signal types are known to those of skill in the art, and would be within the spirit and scope of the present invention.

[0036] FIG. 3 is a more detailed block diagram illustration of an exemplary current limiting component 300 for providing another level of intrinsic safety for the external I/O device 100 of FIG. 1. More particularly, FIG. 3 addresses an exemplary technique of using a current limiter to provide intrinsic safety via energy limiting. [0037] As depicted in FIG. 3, a current limiter 301 is placed in fine with terminals 302. A load 303 is clamped to a specific voltage (e.g., to 24V) such that a load side switch 304 in FIG. 3 becomes intrinsically safe. In certain embodiments, the current limiter 301 is rated at 50 mA. The present invention, however, is not limited to the specific approach depicted in FIG. 3. Various other methods, such as disabling high side switches discussed above, are within the spirit and scope of the present invention.

[0038] FIG. 4 is a block diagram illustration of exemplary signal paths within channel 400 of an ASIC 401. For purposes of illustration, reference characters in FIG. 4, such as DAC 402 and ADC 404, correspond to similarly numbered reference characters (e.g., the DAC 102 and the ADC 104) in FIG. 1.

[0039] Generally, FIG. 4 depicts various components associated with the I/O device 100, discussed above, tied together to facilitate channel assignments. In FIG. 4, voltage and current levels are enforced by the IEC60079 standard. IEC60079 limits these voltage and current levels to defined ranges. Combinations of switch settings, discussed more fully below, in each channel of the ASIC 401, along with PGA settings, ADC settings, and DAC settings, facilitate the channel assignments.

[0040] FIG. 4 more specifically depicts internal operation of dual signal paths within the device channel 400 for possible current and voltage sources. That is, the I/O device channel 400 is configured to connect channels within a DAC 402 and an ADC 404 to user terminals 405. The DAC 402 includes an ability to source a regulated current or voltage to a selected pin of the ASIC 401 , such as DACOUT1 pin. [0041] Switches within the ASIC 401 allow a signal output from the DAC 402 via DACOUT1 pin to connect to an I/0+ terminal via switches SW2A/B and SW15 to terminal block 405. A return path 406 occurs via IOPIN2 from an I/O- to a channel common via switch SW3A to ground. The return path 406 also includes an exemplary series resistance (i.e., resense 407) to allow for return path current sensing using an input port 408 to the ASIC 401.

[0042] The operation of switches within the ASIC 401 described above provides intrinsic safety in several ways. First, the DAC 402 is limiting the current (e.g., to 24 inA or less). Second, the switch SW3A 3 provides protection in the form of an open circuit if the current is too high. The resistor rsense 407 is configured to provide load side sensing, make measurements across the resistor 407, and the ADC 404 near the PGA 409. The return path current is essentially what the DAC 402 has programmed to do, amounting to confirmation that the ASIC 401 is performing optimally.

[0043] For voltage mode, there are several adjustable series resistances that are responsive to, or can be used to compensate for the measured output current. For example, the resistor 407 is an exemplary low side sense, where a path associated with PGA 409 is desirably maintained below about 8V for differential signals.

[0044] The DAC 402 also includes a sensing line 410 to provide voltage feedback, with a switch SW18A/B closed for terminal voltage and switch SW10B used when the voltage feedback is internal to the ASIC 401 (e.g. diagnostic self-testing). Input switches 41 ! coupled to the PGA 409 enable the ADC 404 to sense combinations of inputs from the sensing line 410, the return path 406, and the input port 408 for further control of the DAC 402 and a control process block 412 via a controller 414. The foregoing processes ensure the current going out of VOUT of the DAC 402 is below a user programmable spark prevention threshold.

[0045] FIG. 5 is an exemplary illustration of an I/O device S00 configured for either simplex or redundant operation in accordance with embodiments of the present invention. In the I/O device S00, I/O terminals 502 are fanned, via terminal connectors 503, across up to three acquisition devices. Current burden resistors 504 and 506 are on the terminal board 508 (to allow a constant resistance while the ASIC in each acquisition device sense the voltage due to the current flow).

[0046] In an embodiment, the terminal board 508 has an exemplary local current source for the 24V output, typically using a current limiter 509 that desirably limits the output current to about 50 mA. EMI/EMC filtering and transient protection are also included on the terminal board. Polymer fuses 510-516 provide protection for extremely large faults due to user wiring, as well as allow for intrinsic safe versions of the same design (remove fuse 510 to prevent the high side switch from being available or incorrectly configured).

[0047] Polyfuses 512 and 514 allow for current loop signals (e.g., 3 to 24 mA) to pass while desirably opening at below about 88 mA. Thermal derating for polymer materials on the terminal board 508 at an exemplary minimum temperature (about -20C) is 140% and at an exemplary maximum temperature (about 65C) is 60%. During an exemplary operational scenario, one or more of the polyfuses 510-514 can be configured to open below a user programmable threshold for intrinsic safety protection against higher currents due to component failure.

[0048] Although embodiments of the present invention discussed above are implemented using an ASIC, the present invention is not so limited. For example, other embodiments of the present invention can be implemented using discrete parts. That is, individual components, discussed above, could be used to be used to assign different signal types to each of multiple channels while incorporating the intrinsic safety features discussed herein.

[0049] One such discrete example can include using four screws per channel, having a dedicated common terminal for signal return. Current sensing would be on the high side (10+) to directly sense the DAC current, instead of on the return path as in the ASIC (done to limit the voltage levels in the ASIC internal circuitry). The DAC serves as the current and voltage limiter.

[0050] Another discrete example can be configured to reduce the probability of fault conditions by using a separate current limiter. Thus, any faulty wiring at the terminal (e.g., P24OUT terminal) will not impact the DAC directly.

[0051] Yet another discrete example can be configured to match the ASIC, with three screws using a programmable switch (relay) for the ground return connection to IO-. The relay can use a hermetically sealed contact for intrinsic safety, as well as have the contact rated for the worst case current. Other such examples of using discrete components are readily available, are understood by those of skill in the art, and all within the spirit and scope of the present invention. [0052] FIG. 6 is an illustration of an exemplary method 600 of practicing an embodiment of the present invention. In the method 600, an ASIC controllable via a controller for processing two or more signal types is programmed. The ASIC includes two or more channel switch blocks, and two or more programmable gain amplifier (PGA), each of the PGAs corresponding to one of the channel switch blocks.

[0053] In a step 602, at least one PGA is configured via a user programmable setting, the configuring connecting at least one of the channel switch blocks to user terminals. A voltage level associated, with the configuring, is determined in step 604. In step 606, the determined voltage level is compared with a threshold value. In step 608, the determined voltage level is limited to a lower of the threshold value and the determined voltage level in response to the comparing.

CONCLUSION

[0054] The present invention has been described above with the aid of functional building layers illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional layers have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0055] It is to be appreciated that the Detailed Description section, and not the Summary and Abstract sections, is intended to be used to interpret the claims. The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present invention as contemplated by the inventor(s), and thus, are not intended to limit the present invention and the appended claims in any way.

Claims

WHAT IS CLAIMED IS:

1. A universal input output (I/O) device controllable via a controller for processing two or more signal types, the I/O device comprising:

two or more channel switch blocks; and

two or more programmable gain amplifier (PGA), each of the PGAs

corresponding to one of the channel switch blocks;

wherein the controller is configured to (i) control settings of each of the PGAs and (ii) connect each of the channel switch blocks to user terminals via an analog to digital converter (ADC) and at least one digital to analog converter (DAC) via the PGA settings; and

wherein each of the switch blocks is configurable for assignment to all of the signal types.

2. The universal I/O device of claim 1 , wherein the device is an application specific integrated circuit (ASIC); and

wherein the channel switch blocks and the PGAs are formed within the ASIC, each PGA being representative of a PGA signal path.

3. The universal I/O device of claim 2, wherein the device includes intrinsic safety components.

4. The universal I/O device of claim 3, further comprising an isolation barrier configured for electronic coupling to the controller.

5. The universal I/O device of claim 1, wherein each switch block is representative of a single channel within the I/O device.

6. The universal I/O device of claim 5, wherein the signal types include at least one from including a resistance temperature detectors (RTD), voltage,

thermocouple, mA, highly addressable remote transmitter (HART), and solid state contact.

7. The universal I/O device of claim 6, wherein the settings are selectable via user programming modes.

8. The universal I/O device of claim 7, wherein the user terminals are configured for at least one from the group including (i) electrostatic discharge protection and (it) electromagnetic compatibility filtering.

9. The universal I/O device of claim 8, wherein a quantity of the DACs corresponds to a quantity of the two more channel switch blocks.

10. The universal I/O device of claim 9, wherein each of the channel switch blocks corresponds to one of the DACs.

11. Hie universal I/O device of claim 1 , wherein each of the channel switch blocks is configurable for independent assignment to a corresponding one of the signal types.

12. The universal I/O device of claim 1 , wherein the assignment is

independent.

13. An application specific integrated circuit (ASIC) controllable via a controller for processing two or more signal types, the ASIC comprising:

two or more channel switch blocks; and

two or more programmable gain amplifier (PGA), each of the PGAs

corresponding to one of the channel switch blocks;

14. The ASIC of claim 13, wherein the ASIC includes intrinsic safety components.

15. The ASIC of claim 14, further comprising an isolation barrier configured For electronic coupling to the controller.

16. The ASIC of claim 15, wherein each switch block is representative of a single channel.

17. The ASIC of claim 16, wherein the signal types include at least one from including a resistance temperature detectors (RTD), voltage, thermocouple, mA, highly addressable remote transmitter (MART), and solid state contact.

18. The ASIC of claim 17, wherein the settings are selectable via user programming modes.

19. The ASIC of claim 18, wherein the user terminals are configured for at least one from the group including (i) electrostatic discharge protection and (ii) electromagnetic compatibility filtering.

20. A method for programming an application specific integrated circuit (ASIC) controllable via a controller for processing two or more signal types, the ASIC including two or more channel switch blocks, and two or more programmable gain amplifier (PGA), each of the PGAs corresponding to one of the channel switch blocks, the method comprising:

configuring at least one of the PGAs via a user programmable setting, the configuring connecting at least one of the channel switch blocks to user terminals;

determining a voltage level associated with the configuring;

comparing the determined voltage level with a threshold value; and

limiting the determined voltage level to a lower of the threshold value and the determined voltage level in response to the comparing.