WO2015170958A1 - An etch-free method for conductive electrode formation - Google Patents

An etch-free method for conductive electrode formation Download PDF

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Publication number
WO2015170958A1
WO2015170958A1 PCT/MY2015/000026 MY2015000026W WO2015170958A1 WO 2015170958 A1 WO2015170958 A1 WO 2015170958A1 MY 2015000026 W MY2015000026 W MY 2015000026W WO 2015170958 A1 WO2015170958 A1 WO 2015170958A1
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layer
polymer layer
photo
polymer
metallic layer
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French (fr)
Inventor
Hing Wah Lee
Daniel Chia Sheng Bien
Khairul Anuar ABD WAHID
Khairom Nizam ATAN@MOHAM
Anifah Zakaria
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Mimos Bhd
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Mimos Bhd
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00031Regular or irregular arrays of nanoscale structures, e.g. etch mask layer
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/621Providing a shape to conductive layers, e.g. patterning or selective deposition
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00Manufacture or treatment of microstructural devices or systems
    • B81C2201/01Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0147Film patterning
    • B81C2201/015Imprinting
    • B81C2201/0153Imprinting techniques not provided for in B81C2201/0152
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00Manufacture or treatment of microstructural devices or systems
    • B81C2201/01Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0156Lithographic techniques
    • B81C2201/0159Lithographic techniques not provided for in B81C2201/0157

Definitions

  • the present invention relates generally to an etch-free method for conductive electrode formation, more particularly a fabrication method for conductive electrode structure comprising the formation of high aspect ratio polymer structures by lithographic techniques, followed by self-aligning of a conductive metal layer onto the formed polymer by physical metal deposition to define the conductive electrode structures.
  • conductive metal electrodes In semiconductor device fabrication, formation of conductive metal electrodes is essential when creating device platforms for MEMS and NEMS sensors and actuators applications. At present, these conductive metal electrode structures are typically formed by either etching a deposited metal layer in a wet chemical etchant or gaseous plasma, lifting off the metallic layer at unwanted areas by chemically etching a polymer resist material or self-aligning the metal onto plasma etched substrate.
  • the present invention provides an etch-free method for conductive electrode formation.
  • the present invention proposes a method to fabricate conductive electrodes, the method being independent of any masking material as it does not require any chemical or gaseous plasma etching.
  • an etch-free method for conductive electrode formation comprises depositing an insulating layer on a substrate, spin coating a first polymer layer on the substrate, patterning the first polymer layer by photo-lithography and depositing a conductive metal layer by physical deposition to form a top metallic layer and a bottom metallic layer.
  • the method further comprises spin coating a second polymer layer on the top metallic layer and the bottom metallic layer and patterning the second polymer layer by photo-lithography to selectively expose the top metallic layer and the bottom metallic layer.
  • the first polymer layer has high aspect ratio of at least 10:1.
  • the first polymer layer is of non-conductive material to electrically isolate the top metallic layer and the bottom metallic layer.
  • the second polymer layer (116) is of non-conductive material.
  • the first polymer layer and second polymer layer is of polyimide, SU-8 or poly- methyl methacrylate (PMMA) material.
  • the depositing the conductive metal layer is by metal evaporation.
  • patterning the first polymer layer by photo-lithography defines the first polymer layer with a vertical sidewall with a minimum aspect ratio of 15. In another embodiment of the present invention, patterning the first polymer layer by photo-lithography defines the first polymer layer with an undercut sidewall with a minimum aspect ratio of 5.
  • FIGURES 1 (a), (b) & (c) illustrate an etch-free method for conductive electrode formation.
  • FIGURE 2 illustrates a device with conductive electrodes fabricated by an etch-free method.
  • FIGURE 3 (a) illustrates a photo-lithographically patterned polymer layer with vertical sidewalls.
  • FIGURE 3 (b) illustrates a photo-lithographically patterned polymer layer with undercut sidewalls.
  • FIGURE 4 illustrates a device with a top metallic layer embedded by a second polymer layer.
  • FIGURE 5 illustrates a device with a bottom metallic layer embedded by a second polymer layer.
  • FIGURE 6 illustrates a device with a combination of exposed and embedded top and bottom metallic layers.
  • the present invention relates to an etch-free method for conductive electrode formation.
  • this specification will describe the present invention according to the preferred embodiments of the present invention. However, it is to be understood that limiting the description to the preferred embodiments of the invention is merely to facilitate discussion of the present invention and it is envisioned that those skilled in the art may devise various modifications and equivalents without departing from the scope of the appended claims.
  • the present invention more particularly relates a fabrication method for conductive electrode structure comprising the formation of high aspect ratio polymer structures by lithographic techniques, followed by self-aligning of a conductive metal layer onto the formed polymer by physical metal deposition to define the conductive electrode structures.
  • the present invention proposes a method to fabricate conductive electrodes, the method being independent of any masking material as it does not require any chemical or gaseous plasma etching.
  • the number of electrode structures formed may be of single, dual or in an array type with potential applications as electrical conductivity sensor, gas sensor, pressure sensor and electrochemical sensor.
  • FIGURES 1 (a), (b) & (c) illustrate an etch-free method for conductive electrode formation.
  • FIGURE 2 illustrates a device with conductive electrodes fabricated by an etch-free method.
  • the method according to the present invention begins with the step of depositing an insulating layer (104) on a substrate (102) as shown in FIGURE 1 (a).
  • the substrate is a silicon based substrate and the insulating layer serves as an isolation layer between the metal electrodes and the silicon substrate.
  • the method is followed by spin coating a first polymer layer (106) on the substrate (102) and patterning the first polymer layer (106) by photo-lithography as shown in FIGURE 1 (b).
  • the first polymer layer (106) patterned by photo-lithography has a high aspect ratio of at least 10: 1 .
  • the first polymer layer (106) is of a non-conductive material and highly chemical resistant, for instance of polyimide, SU-8 or poly-methyl methacrylate (PMMA) material, to electrically isolate the top metallic layer (108) and the bottom metallic layer (1 10). Thereafter, a conductive metal layer is deposited by physical deposition such as metal evaporation to form a top metallic layer (108) and a bottom metallic layer (1 10) as shown in FIGURE 1 (c).
  • PMMA poly-methyl methacrylate
  • FIGURE 3 (a) illustrates a photo-lithographically patterned polymer layer with vertical sidewalls.
  • FIGURE 3 (b) illustrates a photo-lithographically patterned polymer layer with undercut sidewalls.
  • the high aspect ratio first polymer layer (106) comprises of a vertical sidewall as shown in FIGURE 3(a) or an undercut sidewall as shown in FIGURE 3(b).
  • the undercut sidewall is typically achieved when using a negative type photo-polymer.
  • a minimum aspect ratio of 15 is required where the height of the polymer needs to be at least 15 times higher than the conductive metal thickness while with an undercut sidewall type structure a minimum aspect ratio of 5 is sufficient.
  • the lower aspect ratio is an advantage where a more planar device structure is required.
  • Another advantage of having an undercut sidewall structure is that both the physical evaporation and sputtering methods can be used for metal deposition, whereas with vertical sidewall structures the metal deposition process is limited to physical evaporation where vertical directionality during metal deposition process is important.
  • all the metal electrode structures can be exposed as shown in FIGURE 1 or selectively exposed by spin coating a second polymer layer (1 16) on the top metallic layer (108) and the bottom metallic layer (1 10) and patterning the second polymer layer (1 16) by photo-lithography to selectively expose the top metallic layer (108) and the bottom metallic layer (1 10).
  • the second polymer layer (1 16) is of non-conductive material and highly chemical resistant, for instance of polyimide, SU-8 or poly-methyl methacrylate (PMMA) material.
  • Both the first polymer layer (106) and second polymer layer (1 16) can be of the same type of material or different types of material with typical thickness in the range of 5 pm to 50 pm. Similar to the first polymer layer (106), the second polymer layer (1 16) is formed by photo-lithographic method without any chemical or plasma etching.
  • FIGURE 4 illustrates a device with a top metallic layer embedded by a second polymer layer.
  • FIGURE 5 illustrates a device with a bottom metallic layer embedded by a second polymer layer.
  • FIGURE 6 illustrates a device with a combination of exposed and embedded top and bottom metallic layers.
  • the second polymer layer (1 16) is coated and patterned to enclose and embed the top electrodes (1 19).
  • the similar process is used to enclose and embed the bottom electrodes (1 17) with the second polymer layer (1 16) leaving the top electrode structure (122) exposed.
  • FIGURE 6 it is also possible to expose or embed selected top (122, 1 19) and bottom (120,1 17) electrodes by photo-lithographically defining the second polymer layer (116). This is done by designing the lithographic reticule accordingly.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Analytical Chemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

The present invention provides an etch-free method for conductive electrode formation. The method comprises depositing an insulating layer (104) on a substrate (102), spin coating a first polymer layer (106) on the substrate (102), patterning the first polymer layer (106) by photo-lithography and depositing a conductive metal layer by physical deposition to form a top metallic layer (108) and a bottom metallic layer (110).

Description

AN ETCH-FREE METHOD FOR CONDUCTIVE ELECTRODE FORMATION
FIELD OF INVENTION The present invention relates generally to an etch-free method for conductive electrode formation, more particularly a fabrication method for conductive electrode structure comprising the formation of high aspect ratio polymer structures by lithographic techniques, followed by self-aligning of a conductive metal layer onto the formed polymer by physical metal deposition to define the conductive electrode structures.
BACKGROUND ART
In semiconductor device fabrication, formation of conductive metal electrodes is essential when creating device platforms for MEMS and NEMS sensors and actuators applications. At present, these conductive metal electrode structures are typically formed by either etching a deposited metal layer in a wet chemical etchant or gaseous plasma, lifting off the metallic layer at unwanted areas by chemically etching a polymer resist material or self-aligning the metal onto plasma etched substrate.
All these methods involved an etching process by either wet chemical or gaseous plasma at certain stages to form the final electrode structures. These methods would typically utilise high powered plasma, heated acid or solvents and ultrasonic agitation. This sometimes makes finding a robust masking material difficult as it needs to withstand the harsh etching conditions mentioned above.
Methods such as lift-off which is used to form noble metal electrodes create other potential process issues such as "ear-effect" and surface contamination as the metal in the etch solution re-deposits onto the substrate surface while etching of the substrate may also cause unintentional damage or fracture to the substrate itself, hence making it more fragile. Also, when forming a high aspect ratio structure on a conducting or semiconducting substrate such as silicon, coating of an insulating layer is required to isolate the electrical effect from the substrate. This limits the type of insulating material and fabrication process that can be used.
SUMMARY OF INVENTION
The present invention provides an etch-free method for conductive electrode formation. The present invention proposes a method to fabricate conductive electrodes, the method being independent of any masking material as it does not require any chemical or gaseous plasma etching.
In one aspect of the present invention is an etch-free method for conductive electrode formation that comprises depositing an insulating layer on a substrate, spin coating a first polymer layer on the substrate, patterning the first polymer layer by photo-lithography and depositing a conductive metal layer by physical deposition to form a top metallic layer and a bottom metallic layer.
In another aspect of the present invention, the method further comprises spin coating a second polymer layer on the top metallic layer and the bottom metallic layer and patterning the second polymer layer by photo-lithography to selectively expose the top metallic layer and the bottom metallic layer.
The first polymer layer has high aspect ratio of at least 10:1. The first polymer layer is of non-conductive material to electrically isolate the top metallic layer and the bottom metallic layer. The second polymer layer (116) is of non-conductive material. The first polymer layer and second polymer layer is of polyimide, SU-8 or poly- methyl methacrylate (PMMA) material. The depositing the conductive metal layer is by metal evaporation.
In one embodiment of the present invention, patterning the first polymer layer by photo-lithography defines the first polymer layer with a vertical sidewall with a minimum aspect ratio of 15. In another embodiment of the present invention, patterning the first polymer layer by photo-lithography defines the first polymer layer with an undercut sidewall with a minimum aspect ratio of 5. The present invention consists of features and a combination of parts hereinafter fully described and illustrated in the accompanying drawings, it is being understood that various changes in the details may be made without departing from the scope of the invention or sacrificing any of the advantages of the present invention.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
To further clarify various aspects of some embodiments of the present invention, a more particular description of the invention will be rendered by references to specific embodiments thereof, which are illustrated, in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. The invention will be described and explained with additional specificity and detail through the accompanying drawings in which:
FIGURES 1 (a), (b) & (c) illustrate an etch-free method for conductive electrode formation.
FIGURE 2 illustrates a device with conductive electrodes fabricated by an etch-free method.
FIGURE 3 (a) illustrates a photo-lithographically patterned polymer layer with vertical sidewalls. FIGURE 3 (b) illustrates a photo-lithographically patterned polymer layer with undercut sidewalls.
FIGURE 4 illustrates a device with a top metallic layer embedded by a second polymer layer.
FIGURE 5 illustrates a device with a bottom metallic layer embedded by a second polymer layer.
FIGURE 6 illustrates a device with a combination of exposed and embedded top and bottom metallic layers. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The present invention relates to an etch-free method for conductive electrode formation. Hereinafter, this specification will describe the present invention according to the preferred embodiments of the present invention. However, it is to be understood that limiting the description to the preferred embodiments of the invention is merely to facilitate discussion of the present invention and it is envisioned that those skilled in the art may devise various modifications and equivalents without departing from the scope of the appended claims.
The present invention more particularly relates a fabrication method for conductive electrode structure comprising the formation of high aspect ratio polymer structures by lithographic techniques, followed by self-aligning of a conductive metal layer onto the formed polymer by physical metal deposition to define the conductive electrode structures. The present invention proposes a method to fabricate conductive electrodes, the method being independent of any masking material as it does not require any chemical or gaseous plasma etching. The number of electrode structures formed may be of single, dual or in an array type with potential applications as electrical conductivity sensor, gas sensor, pressure sensor and electrochemical sensor.
Reference is now made collectively to FIGURES 1 (a), (b) & (c) as well as FIGURE 2. FIGURES 1 (a), (b) & (c) illustrate an etch-free method for conductive electrode formation. FIGURE 2 illustrates a device with conductive electrodes fabricated by an etch-free method.
The method according to the present invention begins with the step of depositing an insulating layer (104) on a substrate (102) as shown in FIGURE 1 (a). The substrate is a silicon based substrate and the insulating layer serves as an isolation layer between the metal electrodes and the silicon substrate. The method is followed by spin coating a first polymer layer (106) on the substrate (102) and patterning the first polymer layer (106) by photo-lithography as shown in FIGURE 1 (b). The first polymer layer (106) patterned by photo-lithography has a high aspect ratio of at least 10: 1 . The first polymer layer (106) is of a non-conductive material and highly chemical resistant, for instance of polyimide, SU-8 or poly-methyl methacrylate (PMMA) material, to electrically isolate the top metallic layer (108) and the bottom metallic layer (1 10). Thereafter, a conductive metal layer is deposited by physical deposition such as metal evaporation to form a top metallic layer (108) and a bottom metallic layer (1 10) as shown in FIGURE 1 (c).
Reference is now made collectively to FIGURES 3(a) & 3(b). FIGURE 3 (a) illustrates a photo-lithographically patterned polymer layer with vertical sidewalls. FIGURE 3 (b) illustrates a photo-lithographically patterned polymer layer with undercut sidewalls. With photo-lithography, the high aspect ratio first polymer layer (106) comprises of a vertical sidewall as shown in FIGURE 3(a) or an undercut sidewall as shown in FIGURE 3(b). The undercut sidewall is typically achieved when using a negative type photo-polymer. With vertical sidewall structure, a minimum aspect ratio of 15 is required where the height of the polymer needs to be at least 15 times higher than the conductive metal thickness while with an undercut sidewall type structure a minimum aspect ratio of 5 is sufficient. The lower aspect ratio is an advantage where a more planar device structure is required. Another advantage of having an undercut sidewall structure is that both the physical evaporation and sputtering methods can be used for metal deposition, whereas with vertical sidewall structures the metal deposition process is limited to physical evaporation where vertical directionality during metal deposition process is important.
Depending on the required application, all the metal electrode structures can be exposed as shown in FIGURE 1 or selectively exposed by spin coating a second polymer layer (1 16) on the top metallic layer (108) and the bottom metallic layer (1 10) and patterning the second polymer layer (1 16) by photo-lithography to selectively expose the top metallic layer (108) and the bottom metallic layer (1 10). The second polymer layer (1 16) is of non-conductive material and highly chemical resistant, for instance of polyimide, SU-8 or poly-methyl methacrylate (PMMA) material. Both the first polymer layer (106) and second polymer layer (1 16) can be of the same type of material or different types of material with typical thickness in the range of 5 pm to 50 pm. Similar to the first polymer layer (106), the second polymer layer (1 16) is formed by photo-lithographic method without any chemical or plasma etching.
Reference is now made collectively to FIGURE 3, FIGURE 4 and FIGURE 5. FIGURE 4 illustrates a device with a top metallic layer embedded by a second polymer layer. FIGURE 5 illustrates a device with a bottom metallic layer embedded by a second polymer layer. FIGURE 6 illustrates a device with a combination of exposed and embedded top and bottom metallic layers. With reference to FIGURE 4, to expose the bottom electrodes (120) the second polymer layer (1 16) is coated and patterned to enclose and embed the top electrodes (1 19). With reference to FIGURE 5, the similar process is used to enclose and embed the bottom electrodes (1 17) with the second polymer layer (1 16) leaving the top electrode structure (122) exposed. With reference to FIGURE 6, it is also possible to expose or embed selected top (122, 1 19) and bottom (120,1 17) electrodes by photo-lithographically defining the second polymer layer (116). This is done by designing the lithographic reticule accordingly.

Claims

An etch-free method for conductive electrode formation, the method comprises
depositing an insulating layer (104) on a substrate (102); spin coating a first polymer layer (106) on the substrate (102);
patterning the first polymer layer (106) by photo-lithography; and depositing a conductive metal layer by physical deposition to form a top metallic layer (108) and a bottom metallic layer (1 10).
A method according to claim 1 wherein the method further comprises
spin coating a second polymer layer (116) on the top metallic layer (108) and the bottom metallic layer (1 10); and
patterning the second polymer layer (1 16) by photo-lithography to selectively expose the top metallic layer (108) and the bottom metallic layer (1 10).
A method according to claim 1 wherein the first polymer layer (106) has high aspect ratio of at least 10:1.
A method according to claim 1 wherein the first polymer layer (106) is of non- conductive material to electrically isolate the top metallic layer (108) and the bottom metallic layer (110).
A method according to claim 2 wherein the second polymer layer (1 16) is of non-conductive material.
A method according to claims 1 and 2 wherein the first polymer layer (106) and second polymer layer (116) is of polyimide, SU-8 or poly-methyl methacrylate (PMMA) material.
7. A method according to claim 1 wherein patterning the first polymer layer (106) by photo-lithography defines the first polymer layer (106) with a vertical sidewall (1 12) with a minimum aspect ratio of 15.
A method according to claim 1 wherein patterning the first polymer layer (106) by photo-lithography defines the first polymer layer (106) with an undercut sidewall (11 ) with a minimum aspect ratio of 5.
9. A method according to claim 1 wherein the depositing the conductive metal layer is by metal evaporation.
PCT/MY2015/000026 2014-05-07 2015-04-29 An etch-free method for conductive electrode formation Ceased WO2015170958A1 (en)

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MYPI2014701169 2014-05-07

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7094622B1 (en) * 2003-08-27 2006-08-22 Louisiana Tech University Foundation, Inc. Polymer based tunneling sensor
US20070013266A1 (en) * 2005-06-17 2007-01-18 Industrial Technology Research Institute Method of fabricating a polymer-based capacitive ultrasonic transducer
US20090023288A1 (en) * 2007-07-19 2009-01-22 Electronics And Telecommunications Research Institute Method of manufacturing nanoelectrode lines using nanoimprint lithography process
US20100065819A1 (en) * 2006-10-05 2010-03-18 Hitachi Chemical Co., Ltd. Well-aligned, high aspect-ratio, high-density silicon nanowires and methods of making the same
US20100143848A1 (en) * 2008-12-09 2010-06-10 Kanti Jain Patterning methods for stretchable structures

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7094622B1 (en) * 2003-08-27 2006-08-22 Louisiana Tech University Foundation, Inc. Polymer based tunneling sensor
US20070013266A1 (en) * 2005-06-17 2007-01-18 Industrial Technology Research Institute Method of fabricating a polymer-based capacitive ultrasonic transducer
US20100065819A1 (en) * 2006-10-05 2010-03-18 Hitachi Chemical Co., Ltd. Well-aligned, high aspect-ratio, high-density silicon nanowires and methods of making the same
US20090023288A1 (en) * 2007-07-19 2009-01-22 Electronics And Telecommunications Research Institute Method of manufacturing nanoelectrode lines using nanoimprint lithography process
US20100143848A1 (en) * 2008-12-09 2010-06-10 Kanti Jain Patterning methods for stretchable structures

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