WO2015167477A1

WO2015167477A1 - Printhead for depositing fluid onto a surface

Info

Publication number: WO2015167477A1
Application number: PCT/US2014/035951
Authority: WO
Inventors: Ning GE; Jianhua Yang; Zhiyong Li
Original assignee: Hewlett-Packard Development Company, L.P.
Priority date: 2014-04-29
Filing date: 2014-04-29
Publication date: 2015-11-05

Abstract

A printhead for depositing fluid onto a surface is described. The printhead includes a nozzle, a firing chamber to hold an amount of fluid and an ejector to eject the amount of fluid through the nozzle. The printhead also includes a number of memristor cells. Each memristor cell includes a memristor, a column select transistor and a row select transistor. A memristor is active when a corresponding column select transistor and row select transistor are closed. The printhead also includes a number of column shift registers to selectively close the column select transistors for a column of memristor cells. The printhead also includes a number of row shift registers to selectively close the row select transistors for a row of memristor cells.

Description

PRINTHEAD FOR DEPOSITING FLUID ONTO A SURFACE

BACKGROUND

[0001] A memory system may be used to store data. In some examples, imaging devices, such as printheads may include memory to store information relating to printer cartridge identification, security information, and authentication information, among other types of information.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The accompanying drawings illustrate various examples of the principles described herein and are a part of the specification. The illustrated examples do not limit the scope of the claims.

[0003] Fig. 1 is a diagram of a printer cartridge and printhead for depositing fluid onto a surface according to one example of the principles described herein.

[0004] Fig. 2 is a block diagram of a printer cartridge for depositing fluid onto a surface according to one example of the principles described herein.

[0005] Fig. 3 is diagram of a memristor bank of a printhead according to one example of the principles described herein.

[0006] Fig. 4 is a diagram of a memristor cell according to one example of the principles described herein.

[0007] Fig. 5 is flowchart of a method for addressing memristor cells in a printhead according to one example of the principles described herein.

[0008] Fig. 6 is a diagram of a memristor bank in a printhead according to one example of the principles described herein. [0009] Fig. 7 is another diagram of a memristor bank in a printhead according to one example of the principles described herein.

[0010] Figs. 8A and 8B illustrate a shifting of an active logic state by a shift register according to one example of the principles described herein.

[0011] Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements.

DETAILED DESCRIPTION

[0012] Memory devices are used to store information for a printer cartridge. For example, in a printer cartridge, memory may be used to allow a controller to identify printer cartridge characteristics. The controller may be an Application-Specific Integrated Circuit (ASIC) on a printer cartridge that is connected to a controlling device. Such information allows the controller to adjust operation of the printer to ensure correct operation. Other examples of information that may be stored includes identification information, serial numbers, security information, feature information, Anti-Counterfeiting (ACF) information, among other types of information. However, while such memory devices may be beneficial, certain characteristics may reduce their effective use.

[0013] For example, an increasing trend in counterfeiting may lead to current memory devices being too small to contain sufficient anti-counterfeiting information and security and authentication information. Additionally, with loyalty customer reward programs, new business models and other customer relation management programs through cloud-printing and other printing architectures, additional market data, customer appreciation value information, encryption information, and other types of information on the rise, a

manufacturer may desire to store more information on a memory device.

Additionally, as technology advances, space on a printhead may be at a premium, such that manufacturers may want more information stored on less space. [0014] Still further, memory may be divided into a number of memory divisions. Each of these memory divisions may be associated with a distinct identification line, by which the memory divisions may be accessed to read data from, and write data to. For efficiency, it may be desirable to divide memory into smaller divisions. However, so doing may increase the number of control lines used to read data from, and write data to the memory divisions.

[0015] Accordingly, the printer cartridge and printhead disclosed herein allow for additional memory storage in a smaller footprint. For example, the printer cartridge and printhead disclosed herein describe a number of memristor banks that are dynamically addressed via a number of shift registers. The use of memristor banks may be beneficial in that they provide a greater storage capacity than other non-volatile memory devices all while maintaining a relative small footprint on the printhead. Still further, dynamically addressing the memristors using a number of shift registers may be beneficial by simplifying the access to, and retrieval of information stored in a memristor bank as a fewer number of control signals are used. Still further, memristors can be

manufactured and implemented relatively cheaply, thereby reducing the cost associated with printhead production.

[0016] The present disclosure describes a printhead for depositing fluid onto a surface. The printhead includes a nozzle, a firing chamber to hold an amount of fluid, and a firing resistor to eject the amount of fluid through the nozzle. The printhead also includes a number of memristor cells. Each memristor cell includes a memristor, a column select transistor, and a row select transistor. A memristor is active when the corresponding column select transistor and row select transistor are closed. The printhead also includes a number of column shift registers to selectively close the column select transistors for a column of memristor cells. The printhead also includes a number of row shift registers to selectively close the row select transistors for a row of memristor cells.

[0017] The present disclosure describes a printer cartridge for deposit fluid onto a surface. The cartridge includes a fluid supply, a controller to generate at least one control signal, and a printhead to deposit fluid onto a surface. The printhead may include a number of memristor banks. A memristor bank may include a number of memristor cells. Each memristor cell may include a memristor, a column select transistor, and a row select transistor. The printer cartridge may include a column shift register that includes column identifiers for each column of the memristor bank. The column shift register may selectively close a number of column select transistors based on the column identifiers and the at least one control signal. The printer cartridge may also include a row shift register that includes row identifiers for each row of the memristor bank. The row shift register may selectively close number of row select transistors based on the row identifiers and the at least one control signal.

[0018] As used in the present specification and in the appended claims, the term "memory" may refer to an element that stores information. Memory may be divided into sub-categories. For example, memory may include a number of memory banks. Accordingly, "memory banks" may refer to a division of memory and may be further divided. For example, each memory bank may include an array of memory cells as defined below.

[0019] As used in the present specification and in the appended claims, the term "memristor" may refer to a passive two-terminal circuit element that maintains a functional relationship between the time integral of current, and the time integral of voltage. In some examples, when used as memory, a memristor may be referred to as a Resistance Random Access Memory

(RRAM) device.

[0020] As used in the present specification and in the appended claims, the term "memristor cell" may refer to a component of a memristor bank that includes a memristor, a column select transistor, and a row select transistor. A memristor cell or memristor that is "active" may refer to a memristor cell in which the memristor is available to store data and may be accessed by a controller of the printer. By comparison, a memristor cell or memristor that is "inactive" may refer to a memristor cell in which the memristor is unavailable to store data. A memristor cell, or memristor, may be active when the column select transistor and row select transistor are closed, in other words, when the column select transistor and row select transistor form a closed circuit with the controller.

[0021] As used in the present specification and in the appended claims, the term "printer cartridge" may refer to a device used in the ejection of ink, or other fluid, onto a print medium. In general, a printer cartridge may be a fluidic ejection device that dispenses fluid such as ink, wax, polymers or other fluids. A printer cartridge may include a printhead. In some examples, a printhead may be used in printers, graphic plotters, copiers and facsimile machines. In these examples, a printhead may eject ink, or another fluid, onto a medium such as paper to form a desired image.

[0022] Still further, as used in the present specification and in the appended claims, the term "a number of or similar language may include any positive number including 1 to infinity; zero not being a number, but the absence of a number.

[0023] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough

understanding of the present systems and methods. It will be apparent, however, to one skilled in the art that the present apparatus, systems, and methods may be practiced without these specific details. Reference in the specification to "an example" or similar language means that a particular feature, structure, or characteristic described is included in at least that one example, but not necessarily in other examples.

[0024] Turning now to the figures, Fig. 1 is a diagram of a printer cartridge (100) for ejecting fluid onto a surface according to one example of the principles described herein. The printer cartridge (100) may include a printhead (101) to carry out at least a part of the functionality of depositing fluid onto a surface. The printer cartridge (100) may include a fluid supply (123) for supplying the fluid to the printhead (101 ) for deposition onto a surface. In some examples, the fluid may be ink. For example, the printer cartridge (100) may be an inkjet printer cartridge, the printhead (101) may be an inkjet printhead, and the ink may be inkjet ink. [0025] The printhead (101) may include a number of components for depositing a fluid onto a surface. For example, the printhead (101) may include a firing resistor (124), a firing chamber (125), and a nozzle (126). The nozzle (126) may be a component that includes a small opening through which fluid, such as ink, is deposited onto a surface, such as a print medium. The firing chamber (125) may include a small amount of fluid. The firing resistor (124) is a component that heats up in response to an applied voltage. As the firing resistor (124) heats up, a portion of the fluid in the firing chamber (125) vaporizes to form a bubble. This bubble pushes liquid fluid out the nozzle (126) and onto the surface. As the vaporized fluid bubble pops, a vacuum pressure within the firing chamber (125) draws fluid into the firing chamber (125) from the fluid supply (123), and the process repeats.

[0026] The printhead (101) and printer cartridge (100) may also include other components to carry out various functions related to printing. For simplicity, in Fig. 1, a number of these components and circuitry included in the printhead (101) and printer cartridge (100) are not indicated; however such components may be present in the printhead (101) and printer cartridge (100). In some examples, the printer cartridge (100) is removable from a printing system for example, as a disposable printer cartridge.

[0027] Fig. 2 is a diagram of a printer cartridge (200) for depositing fluid onto a surface according to one example of the principles described herein. In some examples, the printer cartridge (200) includes a printhead (201) that carries out at least a part of the functionality of the printer cartridge (200). For example, the printhead (201) may include a number of nozzles (Fig. 1, 126). The printhead (201) ejects drops of fluid from the nozzles (Fig. 1, 126) onto a print medium in accordance with a received print job. The printhead (201) may also include other circuitry to carry out various functions related to printing. In some examples, the printhead (201) is part of a larger system such as an integrated printhead (IPH). The printhead (201) may of varying types. For example, the printhead (201) may be a thermal inkjet (TIJ) printhead or a piezoelectric inkjet (PIJ) printhead, among other types of printhead (201). As used herein, and in the appended claims, an "ejector" is a mechanism for ejecting fluid through a nozzle from a firing chamber, where the ejector may include a firing resistor or other thermal device, a piezoelectric element or other mechanism for ejecting fluid from the firing chamber.

[0028] The printhead (201) includes memristor memory (202) to store information relating to at least one of the printer cartridge (200) and the printhead (201). In some examples, the memristor memory (202) includes a number of memristor devices formed in the printhead (201). To store information, each memristor device may be set to a particular logic state. As memristor devices are non-volatile, this logic state is retained even when power is removed from the printhead (201).

[0029] The number of memristor devices are grouped together into memristor banks (203), a number of memristor banks (203) making up the memristor memory (202). The memristor memory (202) may be used to store any type of data. Examples of data that may be stored in the memristor memory (202) include fluid supply specific data and/or fluid identification data, fluid characterization data, fluid usage data, printhead (201) specific data, printhead (201) identification data, warranty data, printhead (201)

characterization data, printhead (201) usage data, authentication data, security data, Anti-Counterfeiting data (ACF), ink drop weight, firing frequency, initial printing position, acceleration information, and gyro information, among other forms of data. In a number of examples, the memristor memory (202) is written at the time of manufacturing and/or during the operation of the printer cartridge (200).

[0030] In some examples, the printer cartridge (200) may include a controller (204) that receives a control signal from an external computing device. The controller (204) may be an Application-Specific Integrated Circuit (ASIC) found on the printer cartridge (200). The controller (204) may execute computer usable program code, such that the computer usable program code, when executed via, for example, the controller (204), manages the functions or acts specified in the flowchart and/or block diagram block or blocks.

[0031] The controller (204) may facilitate storing memory to the memory banks (203). For example, the controller (204) may be coupled to the printhead (201), via a control line such as an identification line. Via the identification line, the controller (204) may change the resistance state of a number of memristor devices in the memristor banks (203) to effectively store information to those memristor banks (203). For example, the controller (204) may send data such as authentication data, security data, and print job data, in addition to other types of data to the printhead (201) to be stored on the memristor memory (202).

[0032] While specific reference is made to an identification line, the controller (204) may share a number of lines of communication with the printhead (201), such as data lines, clock lines, and fire lines. For simplicity, in Fig. 2 the different communication lines are indicated by a single arrow.

[0033] Fig. 3 is diagram of a memristor bank (303) of a printhead (Fig.

1. 101) according to one example of the principles described herein. As described above, a printhead (Fig. 1 , 101) may include memristor memory (Fig.

1. 102) divided into a number of memristor banks (303). The printhead (Fig. 1, 101) may include any number of memristor banks (303). Each memristor bank (303) may further be divided into a number of memristor cells (305) arranged in rows and columns as a memristor array (316), as depicted in Fig. 3. For example, a memristor array (316) may be divided into a number of memristor cells (305-1 , 305-2, 305-3, 305-4). While Fig. 3 depicts a 2x2 memristor array (316), the memristor array (316) may include any number of rows and columns of memristor cells (305). For example, a memristor array (316) may be an 8x8 array of memristor cells (205).

[0034] Each of the memristor banks (303) may be coupled to an identification (ID) line (312) such that each memory cell (305) therein is coupled to the ID line (312). Via the ID line (312), a controller (Fig. 2, 204) may read data from, and write data to, the memristor cells (305). Accordingly, each memory cell (305) may be individually accessed by the ID line (312). More specifically, the ID line (312) may be able to access, and retrieve, information from an activated memory cell (305) whose row select transistor and column select transistor are both closed. [0035] As will be described in more detail below, each memristor cell (305) may be used to store information and may include a memristor, a column select transistor and a row select transistor. More specifically, each memristor cell (305) may store a bit of information. A memory cell (305) is activated, or can store information, when both the column select transistor and a row select transistor corresponding to the memristor cell (305) are closed.

[0036] Each memristor bank (303) may include a corresponding address register (306) that identifies a memristor cell (305) to activate. The address register (306) may be located on the memristor bank (303). In other words, the address register (306) may be located on the printhead (Fig. 1, 101). More specifically, the address register (306) for each memory bank (303) may close columns and rows of transistors in order to activate a particular memristor cell (305). To this end, the address register (306) may include a number of column shift registers (307) and a number of row shift registers (308) to close columns and rows of transistors.

[0037] For simplicity, the address register (306) in Fig. 3 is depicted as having a single column shift register (307) and a single row shift register (308). However, an address register (306) may have a number of column shift registers (307) equal to the number of columns in a memristor array (316) and a number of row shift registers (308) equal to the number of rows in a memristor array (316). For example, as depicted in Fig. 3, the memristor array (316) may have two columns of memristor cells (305); a first column including two memristor cells (305-1, 305-3) and a second column including two memristor cells (305-2, 305-4). In this example, the address register (306) may include two column shift registers (307). Similarly, the memristor array (316) of Fig. 2 may have two rows of memristor cells (305); a first row including two memristor cells (305-1 , 305-2) and a second row including two memristor cells (305-3, 305-4). In this example, the address register (306) may include two row shift registers (308).

[0038] In one example, the address register (306), via the column shift register (307) and the row shift register (308), may selectively close column select transistors and row select transistors based on a control signal (309). For example, a column shift register (307) with a logic state of 1 may indicate that a particular column of transistors is to be closed. Similarly, a row shift register

(308) with a logic state of 1 may indicate that a particular row of transistors is to be closed. By comparison, a logic state of 0 may indicate that a particular row or column of transistors is to be open.

[0039] The address register (306) may selectively close column select transistors and row select transistors by shifting an active logic state between the column shift registers (307) and the row shift registers (308). The active logic state is based on the control signal (309).

[0040] An example of shifting an active logic state between shift registers is given below. The address register (306) receives a control signal

(309) and sequentially passes the control signal (309) through the column shift registers (307) to identify a column of transistors to close. In other words, the output of a first column shift register (307) may be the input of a second column shift register (307).

[0041] A specific example is given as follows. In this example, a first column shift register (307) processes the control signal (309) to determine whether or not to close the corresponding first column of transistors. The first column shift register (307) then produces an output that is passed to a second column shift register (307) to similarly determine whether or not to close the corresponding second column of transistors. This process is repeated for each of the column shift registers (307) such that a single column of transistors may be closed.

[0042] A signal may also be sequentially passed through the row shift registers (308). In other words, the first row shift register (308) may receive a signal, process the signal to determine whether or not to close the

corresponding first row of transistors, and then produce an output that is passed to a second row shift register (308) to similarly determine whether or not to close the corresponding second row of transistors. This process is repeated for each of the row shift registers (308) such that a single row of transistors may be closed. [0043] In some examples, a first row shift register (308) may receive a signal from the column shift register (307). In other words, the input of the row shift register (308) may be the output of a column shift register (307). In another example, the first row shift register (308) may receive a second control signal (309) similar to a first control signal (309) directed to the column shift register (307). In these examples, a single memristor cell (305) may be activated by selecting a column of transistors to close and a row of transistors to close.

More detail concerning passing a control signal (309) through column shift registers (307) and row shift registers (308) is given below in connection with Figs. 6 and 7.

[0044] A memristor that has both a closed column select transistor and a closed row select transistor may be activated. While Fig. 3 depicts a single control (309) signal passed to both the column shift register (307) and the row shift register (308), in some examples, the row shift register (308) and the column shift register (307) may receive distinct controls signals (309). The control signal (309) may be passed in accordance with a number of different clock signals. For example, a number of non-overlapping clock signals may be used to adjust the resistance states of different memory nodes within a shift register. The shifting of resistance states of the different nodes may indicate an output of a particular shift register. More detail regarding the shifting of an active logic state between shift registers (307, 308) is given below in connection with Figs. 8A and 8B.

[0045] In some examples, the printhead (Fig. 1, 101) may also include a pulldown resistor (not shown) to discharge the memristor cells (305) and to regulate voltage passing through the memristor bank (303).

[0046] Fig. 4 is a diagram of a memristor cell (405) according to one example of the principles described herein. As described above, each memory cell (405) in a memory bank (Fig. 3, 303) may include a memristor (415), a column select transistor (413) and a row select transistor (414). A memristor (415) may store information by virtue of the memristor (415) resistance state. A memristor (415) may be accessed by an ID line (412) when activated. An active memristor (4 5) may be one where the column select transistor (413) and the row select transistor (414) are both closed, as described above. Accordingly, the column select transistor (413) may be coupled to the column shift register (Fig. 3, 307) whereby the column shift register (Fig. 3, 307) may selectively close the column select transistor (413). Similarly, the row select transistor (414) may be coupled to the row shift register (Fig. 3, 308) whereby the row shift register (Fig. 3, 308) may selectively close the row select transistor (414). In some examples, the column select transistor (413) and the row select transistor (414) may be metal oxide field effect transistors (MOSFETs). The column select transistor (413) and the row select transistor (414) may be n-type

(NMOS) transistors.

[0047] An inactive memristor (415) is a memristor (415) in which either the column select transistor (413) or the row select transistor (414) are open. An inactive memristor (415) may have a logic value of 0, which may correspond to a low resistance state. By comparison, an active memristor (415) may be one in which both the column select transistor (413) and the row select transistor (414) are both closed, giving the memristor (415) a logic value of 1, which may correspond to a high resistance state.

[0048] Fig. 5 is flowchart of a method (500) for addressing memristor cells (Fig. 3, 305) in a printhead (Fig. 1, 101) according to one example of the principles described herein. The method (500) may include providing (block 501) a column selection to a column shift register (Fig. 3, 307). For example, as described above, an address register (Fig. 3, 306) may receive a control signal (Fig. 3, 309) that is passed to a first column shift register (Fig. 3, 307). The first column shift register (Fig. 3, 307) may then process the control signal (Fig. 3, 309) to determine whether to close a corresponding column of column select transistors (Fig. 4, 413). The first column shift register (Fig. 3, 307) may then pass an output onto another column shift register (Fig. 3, 307) to repeat the process. In this fashion, the number of column shift registers (Fig. 3, 307) each may pass an active logic state amongst one another to indicate which particular column select transistors (Fig. 4, 413) are to be closed.

[0049] The method (500) may also include providing (block 502) a row selection to a row shift register (Fig. 3, 308). For example, the row shift register (Fig. 3, 308) receives a signal. The signal may be the control signal (Fig. 3, 309), or an output signal from a column select register (Fig. 3, 307). The first row shift register (Fig. 3, 308) processes the signal to determine whether to close a corresponding row of row select transistors (Fig. 4, 41 ). The first row shift register (Fig. 3, 308) then passes an output onto another row shift register (Fig. 3, 308) to repeat the process. In this fashion, the number of row shift registers (Fig. 3, 308) each may pass an active logic state amongst one another to indicate which particular row select transistors (Fig. 4, 14) are to be closed.

[0050] In some examples, the row selection may be provided by a column shift register (Fig. 3, 307). For example, the row shift registers (Fig. 3,

308) may be positioned in series after the column shift registers (Fig. 3, 307) such that the last column shift register (Fig. 3, 307) passes an output to the first row shift register (Fig. 3, 308) as an input. More detail concerning this orientation is given in connection with Fig. 6. In this example, both the row selection and the column selection are based on the initial control signal (Fig. 3,

309) and the outputs of other shift registers.

[0051] In another example, the row selection may be independent of the column selection. For example, the row shift registers (Fig. 3, 308) may be parallel to the column shift registers (Fig. 3, 307). In this example, the address register (Fig. 3, 306) may receive a first control signal (Fig. 3, 309) that is passed to the column shift registers (Fig. 3, 307) and also may receive a second control signal (Fig. 3, 309) that is passed to the row shift registers (Fig. 3, 309). More detail concerning this orientation is given in connection with Fig. 7. In this example, the column selection is based on a first control signal and the row selection is based on a second, and distinct, control signal.

[0052] The method (500) may also include selectively activating a memristor cell (Fig. 3, 305) by closing (block 503) a number of column select transistors (Fig. 4, 413) based on the column selection and by closing a number of row select transistors (Fig. 4, 414) based on the row selection. In other words, the column shift register (Fig. 3, 307) that ultimately receives an active logic state of 1 may close the corresponding column select transistors (Fig. 4, 413) and the other column shift registers (Fig. 3, 307) may maintain the corresponding column select transistors (Fig. 4, 413) open. Similarly, the row shift register (Fig. 3, 308) that ultimately receives an active logic state of 1 may close the corresponding row transistors (Fig. 4, 414) and the other row shift registers (Fig. 3, 308) may maintain the corresponding row transistors (Fig. 4, 414) open.

[0053] Fig. 6 is a diagram of a memristor bank (Fig. 2, 203) in a printhead (Fig. 1, 101) according to one example of the principles described herein. As described above in some examples, the column shift registers (607) and row shift registers (608) may be loaded serially. In this example, the address register (606) may receive a control signal (609) that is passed to a first column shift register (607-1). The first column shift register (607-1) may process the control signal (609) to determine whether a first column of column select transistors (Fig. 4, 413) should be closed. The processing of a signal by a shift register may be referred to as a shifting cycle. The first shift register (607-1) then has an output, which may be passed, or shifted, to a second column register (607-2). The second column register (607-2) may then process the output of the first column register (607-1) to determine whether a second column of transistors (Fig. 4, 413) should be closed. In other words, the second column shift register (607-2) executes a shifting cycle. The second column shift register (607-2) then outputs a signal, which may be passed, or shifted, to a third column shift register (607-3). The process is then repeated for subsequent column shift registers (607-4, 607-5, 607-6, 607-7, 607-8).

[0054] In this example, the last column shift register (607-8) may have an output that is passed to the first row shift register (608-1). Similar to as described above, the first row shift register (608-1) then executes a shifting cycle and outputs a signal that is passed, or shifted, to the second row shift register (608-2). This process repeats for the remaining row shift registers (608- 2, 608-3, 608-4, 608-5, 608-6, 608-7, 608-8). In this fashion a column of column select transistors (Fig. 4, 413) to close is selected and a row of row select transistors (Fig. 4, 414) to close is selected and a corresponding memristor (Fig. 4, 415) is activated. In this example, to activate a single memristor (Fig. 4, 415) a number of cycles equal to the sum of the number of column shift registers (607) and the number of row shift registers (608) is performed. For example, as depicted in Fig. 6, 16 cycles would be used to activate a memristor cell (Fig. 3, 305).

[0055] Fig. 7 is another diagram of a memristor bank (Fig. 2, 203) in a printhead (Fig. 1, 101) according to one example of the principles described herein. As described above, a memristor bank (Fig. 2, 203) may include a number of memristor cells (705) arranged in rows and columns. An address register (Fig. 3, 306) may include a number of column shift registers (707) and a number of row shift registers (708). For simplicity, two column shift registers (707-1, 707-2) and two row shift registers (708-1 , 708-2) are depicted in Fig. 7.

[0056] As described above, in some examples, the column shift registers (707) may receive a different control signal (709) than the row shift registers (708). For example, a first column shift register (707-1) may receive a first control signal (709-1) that is processed by the column shift registers (707) to select a particular row of column select transistors (Fig. 4, 413) to close. For example, the first control signal (709-1) may indicate that column select transistors (Fig. 4, 413) corresponding to the first column register (707-1) are to close. Accordingly, the column select transistors (Fig. 4, 413) corresponding to a first memristor cell (705-1) and a third memristor cell (705-3) may be closed.

[0057] Similarly, a first row shift register (708-1) may receive a second control signal (709-2) that is processed by the row shift registers (708) to select a particular row of row select transistors (Fig. 4, 414) to close. For example, the second control signal (709-2) may indicate that row select transistors (Fig. 4, 413) corresponding to the second row shift register (708-2) are to close.

Accordingly, the row select transistors (Fig. 4, 414) corresponding to a third memristor cell (705-3) and a fourth memristor cell (705-4) may be closed.

[0058] In this example, as both the column select transistor (Fig. 4, 413) and the row select transistor (Fig. 4, 414) for the third memristor cell (705- 3) are closed, the third memristor cell (705-3) may be activated. By

comparison, as neither the column select transistor (Fig. 4, 413) nor the row select transistor (Fig. 4, 414) for the second memristor cell (705-2) are closed, the second memristor cell (705-2) may be inactive. Similarly, as just the column select transistor (Fig. 4, 413) for the first memristor cell (705-1) and the row select transistor (Fig. 4, 414) for the fourth memristor cell (705-4) are closed, neither the first memristor cell (705-1) nor the fourth memristor cell (705-4) are active.

[0059] As two control signals (709-1, 709-2) are used, the number of cycles to indicate an active memristor cell (705) may equal the number of column shift registers (707), the number of row shift registers (708). For example, given an 8x8 memory bank (Fig. 2, 202), it may take the first control signal (709-1) 8 cycles to complete a shift through all column shift registers (707), and may take the second control signal (709-2) the same 8 cycles, executed in parallel, to complete a shift through all row shift registers (708).

[0060] Figs. 8A and 8B illustrate a shifting of an active logic state by a shift register according to one example of the principles described herein. The shift register depicted in Fig. 8B may be either a column shift register (Fig. 3, 307) or a row shift register (Fig. 3, 308). A single shift register (Fig. 3, 307, 308) is indicated in Fig. 8B by the dashed box.

[0061] As described above, the shift registers (Fig. 3, 307, 308) may shift an active logic state between shift registers (Fig. 3, 307, 308) based on a number of clock signals (817). Fig. 8A depicts a number of clock signals (817) that may be used to time the shifting of an active logic state between the shift registers (Fig. 3, 307, 308). More specifically, each clock signal (817-1, 817-2, 817-3, 817-4) may turn on a particular transistor or charge a particular memory node (821) of a shift register (Fig. 3, 307, 308) based on a pulse (820) sent to the memory node (821). For simplicity, Fig. 8A depicts a single pulse

(820) with a reference numeral; however, each clock signal (817-1, 817-2, 817- 3, 817-4) may include similar pulses. Each pulse (820) may represent a voltage that is sent through the shift register (Fig. 3, 307, 308) to charge a memory node

(821) . The value of the voltage pulse (820) is indicated on the y-axis (818) and may represent a voltage value such as 15 V.

[0062] The distinct clock signals (817) may operate sequentially such that different pulses (820) are sent at different times for each clock signal (817). The timing of the pulses (820) is indicated on the x-axis (819) of Fig. 8A. [0063] Referring now to Fig. 8B, initially, a first memory node (821- 1) may be charged up, i.e., set to a logical value of 1 via the first clock signal (817-1). The second clock signal (817-2) at a subsequent time, may evaluate the first memory node (821-1) relative to the control signal (809). For example, if the control signal (809) has a logical value of 1 , then the first node (821-1) may be discharged, i.e., set to a logical value of 0 via the second clock signal (817-2). This output (822-1) may be passed and used to evaluate the second memory node (821-2).

[0064] A third clock signal (817-3) may charge up the second memory node (821-2), i.e., set the logical value of the second memory node (821-2) to 1. Then a fourth clock signal (817-4) may evaluate the second memory node (821-2) based on the first memory node (821-1) output (822-2). In this example, the charged second memory node (821-2) and the discharged output (822-2) may result in the second memory node (821-2) remaining charged and passing the corresponding logic value of 1 as an output (822-2) to another shift register (Fig. 3, 307, 308). Subsequent shift registers (Fig. 3, 307, 308) may function similarly to pass the active logic state, .i.e., the logic value of 1, among the different shift registers (Fig. 3, 307, 308).

[0065] While Figs. 8A and 8B specifically identify a dynamic memory circuit mechanism of the shift register (Fig. 3, 307, 308) any number of other mechanisms may be used to shift an active logic state between shift registers (Fig. 3, 307, 308). For example, a delay flip-flop ("D-flip flop") may be used to shift an active logic state between shift registers (Fig. 3, 307, 308).

[0066] Aspects of the present system and method are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to examples of the principles described herein. Each block of the flowchart illustrations and block diagrams, and combinations of blocks in the flowchart illustrations and block diagrams, may be implemented by computer usable program code. The computer usable program code may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the computer usable program code, when executed via, for example, a processor or other programmable data processing apparatus, implement the functions or acts specified in the flowchart and/or block diagram block or blocks. In one example, the computer usable program code may be embodied within a computer readable storage medium; the computer readable storage medium being part of the computer program product. In one example, the computer readable storage medium is a non-transitory computer readable medium.

[0067] A device and method for regulating memristor switching pulses may have a number of advantages, including: (1) allowing more storage space on a printhead in less space; (2) reducing the amount of control signals used to address memory; (3) reducing shifting time; (4) not necessitating a change to the controller; and (5) being backwards compatible with controllers.

[0068] The preceding description has been presented to illustrate and describe examples of the principles described. This description is not intended to be exhaustive or to limit these principles to any precise form disclosed. Many modifications and variations are possible in light of the above teaching.

Claims

WHAT IS CLAIMED IS: . A printhead for depositing fluid onto a surface, the printhead comprising: a nozzle;

a firing chamber to hold an amount of fluid;

an ejector to eject the amount of fluid through the nozzle;

a number of memristor cells, each memristor cell comprising:

a memristor;

a column select transistor; and

a row select transistor;

in which a memristor is active when the corresponding column select transistor and row select transistor are closed;

a number of column shift registers to selectively close the column select transistors for a column of memristor cells; and

a number of row shift registers to selectively close the row select transistors for a row of memristor cells.

2. The printhead of claim 1 , in which the fluid is inkjet ink.

3. The printhead of claim 1 , in which a column shift register and a row shift register close column select transistors and row select transistors based on a control signal.

4. The printhead of claim 1, in which:

a column shift register closes column select transistors based on a first control signal; and

a row shift register closes row select transistors based on a second control signal.

5. The printhead of claim 1 , in which the column select transistors and row select transistors that are closed are identified by shifting an active logic state between shift registers to a corresponding column shift register and a

corresponding row shift register.

6. The printhead of claim 1 , in which at least one shift register shifts an active logic state to another shift register.

7. The printhead of claim 6, in which the at least one shift register shifts an active logic state based on at least one clock signal.

8. The printhead of claim 6, in which the active logic state is derived based on at least one control signal.

9. A printer cartridge for depositing fluid onto a surface, the cartridge comprising:

a fluid supply;

a controller to generate at least one control signal; and

a printhead to deposit fluid onto a surface, the printhead comprising; a number of memristor banks comprising a number of memristor cells, each memristor cell comprising:

a memristor;

a column transistor; and

a row transistor;

a column shift register comprising column identifiers for each column of the memristor bank, the column shift register selectively closing a number of column select transistors based on the column identifiers and the at least one control signal; and

a row shift register comprising row identifiers for each row of the memristor bank, the row shift register selectively closing a number of row select transistors based on the row identifiers and the at least one control signal.

10. The cartridge of claim 9, in which:

the fluid is inkjet ink;

the printer cartridge is an inkjet printer cartridge; and

the printhead is an inkjet printhead.

11. The cartridge of claim 9, in which at least one of the column shift register and the row shift register derive at least one of a column selection and a row selection based on the at least one control signal and a number of output signals from other shift registers.

12. The cartridge of claim 9, in which the column selection and the row selection are based on a single control signal.

13. The cartridge of claim 9, in which the column selection is based on a first control signal and the row selection is based on a second control signal.

14. The cartridge of claim 9, in which the column shift register and row shift registers are loaded in parallel.

15. The device of claim 9, in which the column shift register and the row shift register are loaded in series.