WO2015163831A1

WO2015163831A1 - A programmable logic circuit for night sight systems

Info

Publication number: WO2015163831A1
Application number: PCT/TR2014/000125
Authority: WO
Inventors: Cemil KIZILOZ
Original assignee: Aselsan Elektronik Sanayi Ve Ticaret Anonim Sirketi
Priority date: 2014-04-21
Filing date: 2014-04-21
Publication date: 2015-10-29
Also published as: UA130283U; TN2016000467A1

Abstract

The present invention relates to a programmable logic circuit (1), which is developed for day and night sight systems (thermal camera, day tv camera, etc.), is designed using hardware description language, can be implemented, and is capable of making the details on an image visible without requiring any other intelligent device.

Description

A PROGRAMMABLE LOGIC CIRCUIT FOR NIGHT SIGHT SYSTEMS

Field of the Invention

The present invention relates to a programmable logic circuit, which is developed for day and night sight systems (thermal camera, day tv camera, etc.), is designed using hardware description language, can be implemented, and is capable of making the details on an image visible without requiring any other intelligent device.

Background of the Invention

Previously, in the sight systems developed, programmable logic circuits and processors were used together, and mathematical operations requiring high speed and performance were implemented by using programmable logic circuits (FPGA-Field Programmable Gate Array, etc.) and image enhancement algorithms and decision mechanisms were implemented by using processors.

The Chinese patent document no. CN102158653, an application in the state of the art, discloses a device and method for acquiring a data with high dynamic range in real time. The said invention functions with an embedded image processing system. The device comprises an FPGA logic device, a CCD (Charge Coupled Device) imaging array, a video dedicated A/D chip, a coprocessor DSP (Digital Signal Processor) and a SRAM (static random access memory). By means of the method disclosed by the invention, the image with high dynamic range is generated in real time. The quality of the image shot by the CCD is improved.

The United States patent document no. US2013125184, an application in the state of the art, discloses a system which can perform high resolution broadcasting b means of FPGA. In this invention, two or more low resolution video signals are combined to create a high resolution signal in real-time High Definition format, such as 1080 p.

The Japanese patent document no. JPH10210424, an application in the state of the art, discloses a conversion device which can control image quality and can convert the video signal into the desired clock frequency. In the said invention, the sharpness degree of an image edge is controlled by processing the data that is inputted to the FPGA from a personal computer. In the applications in the state of the art, using both a programmable logic circuit and a processor makes the design structure complex and requires designing a communication mechanism for the two units. Using different processors on different projects leads to making the same design again, and causes increase of design, verification and documentation periods and loss of inefficiency. Using a processor in addition to the programmable logic circuit requires use of peripherals such as a flash ram or a program ram and this in turn increases the power consumption of the system. Since the transfer function used in the present image processing algorithms to obtain output image from input image is implemented as an 8 to 16 piecewise linear function, output image histogram cannot follow exact intended distribution, but a distribution similar to the intended one.

Summary of the Invention

The objective of the present invention is to provide a programmable logic circuit, which is developed for day and night sight systems (thermal camera, day tv camera, etc.), is designed using hardware description language, can be implemented, and is capable of making the details on an image visible without requiring any other intelligent device. Detailed Description of the Invention A programmable logic circuit developed to fulfill the objective of the present invention is illustrated in the accompanying figure wherein:

Figure 1 is the schematic view of the programmable logic circuit.

The components shown in the figures are each given reference numbers as follows:

1. Programmable logic circuit

2. Filter block

3. Statistics block

4. Histogram ram

5. Coefficient finder block

6. Coefficient ram

7. Transfer function block

8. Interface block

A programmable logic circuit; which is developed for day and night sight systems, is designed using hardware description language, can be implemented, and is capable of making the details on an image visible without requiring any other intelligent device; basically comprises

at least one filter block (2) which is adapted to find the low frequency and high frequency image contents of the unprocessed input video,

at least one statistics block (3) which is adapted to find histogram (distribution) of the low frequency image content,

at least one histogram ram (4) which is adapted to store the histogram of the low frequency image content,

- at least one coefficient finder block (5) which is adapted to compute the transfer function that is used to increase the output video contrast with respect to the intended distribution, at least one coefficient ram (6) which is adapted to store the coefficients, at least one transfer function block (7) which is adapted to generate the enhanced video according to the transfer function and to add high frequency components to the video,

- at least one interface block (8) which is adapted to allow connection to the serial interface.

In the preferred embodiment of the present invention, the programmable logic circuit (1) comprises a filter block (2) which is adapted to find the low frequency and high frequency image contents of the unprocessed input video, a statistics block (3) which is adapted to find histogram (distribution) of the low frequency image content, and a histogram ram (4) which is adapted to store the histogram of the low frequency image content. The programmable logic circuit (1) further comprises a coefficient finder block (5) which is adapted to compute the transfer function that is used to increase the output video contrast with respect to the intended distribution, a coefficient ram (6) which is adapted to store the coefficients, a transfer function block (7) which is adapted to generate the enhanced video according to the transfer function and to add high frequency components to the video, and an interface block (8) which is adapted to allow connection to the serial interface.

In one embodiment of the present invention, the programmable logic circuit (1) "IP" produces output data according to "Rayleigh" distribution with default values. If a different output data distribution is desired, the intended distribution values can be written into the distribution logs in the statistics block (3) via the interface block (8) and video output can be provided in this distribution.

In another embodiment of the invention, mathematical formulation of the function implemented by the programmable logic circuit (1 ) of the present invention is as follows: histogram value of an unprocessed image (ranging from 0 to L) can be represented with the function hist_input(i); total pixel number on the image can be computed by hist _ input(i) cumulative histogram value, normalized to "1" for any value, represented as cum_hist_input(n) is computed by hist _ input(i) ^ hist _ input(i)

(0=° )/( '- )); similarly; if the histogram of output video is hist_out(i), for output video cumulative histogram value normalized to T, which is cum_hist_out(n), is represented as

n L

hist _ out(i) ^ hist _ out(i)

(( <=° ) / ( ^<=° ));

and enhanced image is obtained by computing T(i) function so as to equalize cum_hist_input(i) and cum_hist_out(i).

In another embodiment of the invention, hist_input(i) values are calculated by the statistics block (3) provided on the programmable logic circuit (1) of the present invention, and are stored in the coefficient ram (6) for values 0 to L and by adding up the number of image data used in this calculation, the total histogram value, cum_hist_input(L) value is computed.

In the preferred embodiment of the invention, the coefficient finder block (5), which is located on the programmable logic circuit (1), computes the cum_hist_input(i) value corresponding to the cum_hist_out(i) value for each value from 0 to 255 (256 values) in order to equalize the cum_hist_out(i) value and cum_hist_out(i) value and thus the transfer function block (7) calculates T(i). The coefficient finder block (5) stores these values in the coefficient ram. In one embodiment of the invention, the transfer function block (7) located on the programmable logic circuit (1) generates the enhanced image data according to the transfer function for each value of the unprocessed image data.

In monochrome image, thermal cameras usually have 8 bit video output, as this color depth represents the value human eye can recognize. For 8 bit video output, 256 point piecewise transfer function is used and this way the most real-like distribution is attained for 8 bits at the video output. Using a 256 point piecewise function causes to use more logic gates, however an output distribution which is closest to the desired distribution is achieved. Furthermore, the image is divided into its low frequency and high frequency components by the two dimensional filter block (2), the edge information in the high frequency components is reinforced and is added to the processed (enhanced) image; so sharper images are achieved.

In another embodiment of the present invention, thanks to the programmable logic circuit (1), a synchronous design is implemented. So the delay values between the logic circuits can be controlled and the design can be implemented on different vendor programmable logic circuits. Furthermore, the video data transmitted by the video synchronization signals can be processed and it can work with any video format since the only requirement is 8192 clock cycles gap time between two consecutive frames. In another embodiment of the invention, the programmable logic circuit (1) of the present invention generates an output video in the same format with the format of the input video; and as 256 point piecewise linear function is used for transfer function, best output image distribution is achieved. Furthermore, video output with different distributions can be allowed by the interface block (8).

Claims

1. A programmable logic circuit (1); which is developed for day and night sight systems, is designed using hardware description language, can be implemented, and is capable of making the details on an image visible without requiring any other intelligent device; basically characterized by

- at least one filter block (2) which is adapted to find the low frequency and high frequency image contents of the unprocessed input video,

- at least one coefficient finder block (5) which is adapted to compute the transfer function that is used to increase the output video contrast with respect to the intended distribution,

at least one coefficient ram (6) which is adapted to store the coefficients, at least one transfer function block (7) which is adapted to generate the enhanced video according to the transfer function and to add high frequency components to the video,

at least one interface block (8) which is adapted to allow connection to the serial interface.

2. A programmable logic circuit (1) according to Claim 1, characterized by the filter block (2) which divides the image into its low frequency and high frequency components by means of its two dimensional structure.

3. A programmable logic circuit (1) according to Claim 1, characterized by the filter block (2) which reinforces the edge information in the high frequency components and adds it to the processed (enhanced) image.

4. A programmable logic circuit (1) according to Claim 1, characterized by the filter block (2) which enables to achieve sharper processed images.

5. A programmable logic circuit (1) according to Claim 1, characterized by the transfer function block (7) which generates the processed (enhanced) image data according to the transfer function for each value of the unprocessed image data.

6. A programmable logic circuit (1) according to Claim 1, characterized by the interface block (8) by which, if a different output data distribution is desired, the intended distribution values can be written into the distribution logs and video output can be provided in this distribution.