WO2015151261A1

WO2015151261A1 - Nonvolatile memory system and information processing system

Info

Publication number: WO2015151261A1
Application number: PCT/JP2014/059873
Authority: WO
Inventors: 由子長坂; 純司小川; 拓実仁藤
Original assignee: 株式会社日立製作所
Priority date: 2014-04-03
Filing date: 2014-04-03
Publication date: 2015-10-08

Abstract

[Problem] To propose a nonvolatile memory system and an information processing system that are capable of allowing for an increased number of writes. [Solution] A nonvolatile memory system provided with a nonvolatile memory and a nonvolatile memory controller, wherein said nonvolatile memory controller is characterized in that the controller: classifies and manages a plurality of physical blocks in the nonvolatile memory according to the attributes of the data in the physical blocks, while managing refresh determination threshold values or defective block determination threshold values which differ with different attributes; and, when data is to be written to a physical block, selects, as the target physical block, a physical block which is classified as having the same attributes as the data to be written.

Description

Nonvolatile memory system and information processing system

The present invention relates to a nonvolatile memory system and an information processing system.

In a non-volatile memory such as a flash memory, it is known that data cannot be written any more if writing is repeated many times (limit of the number of times that data can be written). Further, there is known a characteristic (retention characteristic) in which recorded data is lost when the elapsed time after writing is long and the same value as that at the time of writing cannot be read.

Therefore, Patent Document 1 discloses a technique of adding data with ECC (Error Correcting Code) having a correction capability of a plurality of bits at the time of writing and reading data by correcting the faulty bit using ECC at the time of reading. Yes.

In Patent Document 1, a spare flash memory block is provided, and if the error rate at the time of correction is larger than a predetermined threshold value m, a process of transferring data to the spare or another flash block (refresh process) is executed. A technique is disclosed in which if the error rate is greater than a predetermined threshold value n (n> m), the read-out block is determined as a defective block that will not be used thereafter (defective block determination).

In Patent Document 2, the refresh process is not executed at the time of reading, but is executed when the elapsed time after writing the data in the flash memory exceeds a predetermined value, so that the data disappears with the passage of time. Corresponding techniques are disclosed.

In general, a flash memory system periodically performs refresh processing using the techniques described in Patent Documents 1 and 2, and data is correctly read and written until the entire flash memory system reaches a certain number of times of writing. Assured.

Here, the conventional flash memory system is often used as a part of the storage system. On the other hand, in recent years, it is used as a server-connected flash memory system. The server-connected flash memory system refers to a system used as a server main memory expansion or a system used as a storage system that operates in close cooperation with the server.

When the flash memory system is used as a server-connected flash memory system, the number of times of writing increases as compared to when it is used as a part of the storage system. This results in the problem that the flash memory system reaches its useful life before the server reaches its useful life.

Therefore, in recent years, there is a strong need for a technique for improving the limit of the number of writable times in a flash memory system. Of course, even if the flash memory system is used as a part of the storage system as in the prior art, it is better to improve the limit of the number of writable times.

JP 2010-61507 A US Pat. No. 7,325,090

The conventional flash memory system is assumed to be used as a part of the storage system, so even if power is not supplied for a long time (for example, time in years) due to power failure or removal of the flash memory system, data Need to guarantee. Specifically, it is necessary to ensure that the error rate is equal to or lower than the error rate correctable by ECC when data is read again.

For this reason, the conventional flash memory system controls to refresh frequently by setting a sufficiently small refresh judgment period and to refresh early by setting a sufficiently small error rate as a refresh judgment threshold. Also, control is performed so that a sufficiently small error rate is set as a defective block determination threshold value and determined as a defective block at an early stage.

However, the conventional flash memory system is defective even though it is frequently written by the refresh process, pressing the limit of the number of writeable times, and the error rate is much smaller than the error rate that can be corrected by ECC. Decide that it is a block and reduce the number of usable blocks. Therefore, there is a problem that the number of writable times as a whole flash memory system is reduced.

On the other hand, when using a flash memory system that has been developed in recent years as an expansion of the main memory of the server, the data on the main memory may be erased when the power is turned off. It is not necessary to guarantee only the data.

In other words, when the flash memory system is used as the main memory expansion of the server, the refresh determination threshold value, the bad block determination threshold value, and the determination cycle thereof are uniform even though it is not necessary to guarantee the data recorded in the flash memory system for a long time. Therefore, there is a problem that the number of writable times of the entire system is limited.

The case where the flash memory system here is used as the main memory expansion of the server means, for example, that the application or middleware program treats the main memory and the flash memory system as one storage space, and only the data that is frequently accessed is used as appropriate. This is a case where the calculation is taken from the flash memory system into the main memory. In addition, when the database processes one query, the data read from the database does not fit in the main memory, so that a temporary area is secured in the flash memory system.

Also, when the flash memory system is used as a storage system that operates in close cooperation with the server, the guaranteed time of data after the power is turned off varies greatly depending on the type of data. For example, if a flash memory system is used as a permanent storage destination, a yearly guarantee is required, whereas if a checkpoint of a long-term job executed on the server is periodically written to the flash memory system, the job It is meaningless to record checkpoint data for a time longer than re-executing, and a daily or weekly guarantee is sufficient.

That is, when the flash memory system is used as a storage system that operates in close cooperation with the server, the server can determine and instruct the guaranteed time of data after the power is turned off. Since the bad block determination threshold and these determination cycles are set uniformly, there is a problem that the number of writable times of the entire system is limited.

In addition, the server may copy frequently referenced data in the storage system into a high-speed flash memory system and perform only read-out reference. Data in the flash memory system in this state is called clean, and the state of data in which there is no original data in the storage system and the latest data is only in the flash memory system is called dirty.

If the data is clean, even if the data in the flash memory system is lost due to the retention characteristics, the server only needs to read the data from the worst storage system. This determination cycle can be set larger than that for dirty data.

That is, in this case, in the flash memory system, it is impossible to determine whether the data is clean or dirty, and the refresh determination threshold, the bad block determination threshold, and these determination cycles are set uniformly, so that the entire system There is a problem that the number of writable times is limited.

The present invention has been made in consideration of the above points, and proposes a nonvolatile memory system and an information processing system capable of improving the limit of the number of writable times.

In order to solve such a problem, in the present invention, in a nonvolatile memory system including a nonvolatile memory and a nonvolatile memory controller, the nonvolatile memory controller classifies and manages a plurality of physical blocks in the nonvolatile memory according to data attributes. On the other hand, when different refresh determination threshold values or bad block determination threshold values are managed for each attribute and data is written to the physical block, a physical block classified as the same attribute as the write target data attribute is selected as the write destination. It is characterized by.

In order to solve such a problem, in the present invention, in an information processing system including a computer system and a nonvolatile memory system, the computer system issues an attribute instruction that indicates an attribute of data to the nonvolatile memory system. When the memory system receives the attribute instruction, the memory system classifies and manages a plurality of physical blocks in the nonvolatile memory according to the attribute of the data based on the received attribute instruction, and on the other hand, a different refresh determination threshold or bad block for each attribute When the determination threshold value is managed and data is written to the physical block, a physical block classified into the same attribute as the attribute of the data to be written is selected as a writing destination.

According to the present invention, the limit of the number of writable times can be improved.

1 is an overall configuration diagram of an information processing system in the present embodiment. It is a whole block diagram of another information processing system. 1 is an overall configuration diagram of a flash memory system. It is an internal block diagram of flash memory. It is an internal block diagram of a block. It is an internal block diagram of a page. It is a logical block diagram of a logical address table. It is a logical block diagram of a physical address table. It is a logic block diagram of a threshold value table. It is a logic block diagram of a history table. It is a conceptual block diagram of a physical block management list group. It is an internal block diagram of a management list. It is an internal block diagram of a command. It is an internal block diagram of another command. It is an internal block diagram of another command. It is a processing flow which shows a writable frequency improvement process. It is a processing flow which shows a writable frequency improvement process. It is a processing flow which shows an attribute instruction command reception process. It is a processing flow which shows a write instruction command reception process. It is a processing flow which shows a write instruction command reception process. It is a processing flow which shows a read instruction command reception process. It is a processing flow which shows the invalidation instruction command reception processing. It is a processing flow which shows refresh determination and bad block determination. It is a processing flow which shows refresh determination and bad block determination. It is a processing flow which shows the 2nd writeable frequency improvement process. It is a processing flow which shows the 3rd writeable frequency improvement process. It is a processing flow which shows the 3rd writeable frequency improvement process. It is an internal block diagram of main memory. It is a data arrangement block diagram in an information processing system. It is the 1st processing flow by an application. It is the 2nd processing flow by middleware. It is the 3rd processing flow by middleware. It is the 4th processing flow by an application. It is the 5th processing flow by middleware. It is the 6th processing flow by an application or middleware.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

(1) First Embodiment (1-1) Overall Configuration FIG. 1 shows the overall configuration of an information processing system 1 in the present embodiment. The information processing system 1 includes a host CPU (Central Processing Unit) 101, a main memory 102, a flash memory system 103, and a storage system 104. The host CPU 101 is communicably connected to each unit via signal lines 105-107.

The flash memory system 103 receives a data read / write instruction from the host CPU 101 via the signal line 106. Further, in the present embodiment, the flash memory system 103 receives the RT (Retention Time) time of data and information (attribute information) indicating that the data is clean or dirty from the host CPU 101.

FIG. 2 shows the overall configuration of another information processing system 1A. The flash memory system 103 is different from the information processing system 1 in FIG. 1 in that the flash memory system 103 is arranged in the storage system 104. In the information processing system 1A, the flash memory system 103 receives a data read / write instruction from the storage controller CPU 108 and receives attribute information.

In the following description, the configuration of the information processing system 1 in FIG. 1 will be described in detail, but it may be applied to the information processing system 1A in FIG.

(1-2) Internal Configuration FIG. 3 shows the internal configuration of the flash memory system 103. The flash memory system 103 includes a flash memory controller 111 and a plurality of flash memories 119.

In the flash memory controller 111, when the processor 113 receives a data read / write instruction from the host CPU 101 via the signal line 106 and the host interface 112, the processor 113 accesses a RAM (Random Access Memory) 115 and stores the flash stored in the RAM 115. The block management information 115A is referred to or updated.

The processor 113 accesses the flash memory 119 via the flash memory interface 116 with reference to the flash block management information 115A. When the instruction from the host CPU 101 is a read instruction, the processor 113 temporarily stores data to be read in the buffer 114 via the flash memory interface 116 and then issues a read completion notification to the host CPU 101.

The flash memory interface 116 includes an error correction circuit 116A. The error correction circuit 116A performs error correction using the ECC (FIG. 6) added to the data when reading the data. Then, the corrected data and the error rate at the time of reading are stored in the buffer 114. On the other hand, when the instruction from the host CPU 101 is a write instruction, the processor 113 temporarily stores the data to be written in the buffer 114 and then writes it in the flash memory 119. The error correction circuit 116A adds ECC (FIG. 6) to the data when writing the data.

Further, when receiving the attribute information from the host CPU 101, the processor 113 accesses the RAM 115 and appropriately updates the flash block management information 115A. Further, the processor 113 performs a refresh determination process and a defective block determination process on the blocks in the flash memory 119 based on a predetermined determination cycle.

FIG. 4 shows the internal configuration of the flash memory 119. The flash memory 119 is composed of a plurality of blocks 125. A block 125 is a storage area of an erase unit.

FIG. 5 shows the internal configuration of the block 125. The block 125 is composed of a plurality of pages 126. The page 126 is a storage area in read / write units.

FIG. 6 shows the internal structure of the page 126. The page 126 includes data 127 and ECC (Error Correcting Code) 128.

(1-3) Table Configuration FIGS. 7 to 12 show the detailed configuration of the flash block management information 115A stored in the RAM 115. FIG. The drawings in FIGS. 7 to 12 will be described below.

FIG. 7 shows a logical configuration of the logical address table 201. The logical address table 201 is used to convert a logical address included in a read / write instruction from the host CPU 101 into a physical address. In the present embodiment, it is used for storing attribute information. Specifically, the logical address table 201 includes a logical address column 202, a page valid / invalid column 203, a physical page address column 204, and an attribute number column 205.

The logical address column 202 stores a logical address included in the read / write instruction from the host CPU 101. The page valid / invalid column 203 stores information indicating whether data is stored in the page. In addition, when data is stored in the page, valid is stored, and when data is not stored, invalid is stored.

Also, the physical page address column 204 stores the physical page address of the flash memory 119. Here, the block number and page number are stored as physical page addresses. The attribute number column 205 stores attribute information including RT time and information indicating dirty or clean. Here, numbers assigned in advance to a plurality of attribute information are stored.

Accordingly, in the case of FIG. 7, for example, data is stored in the physical page address associated with the logical address having the logical address “10” (valid), and this logical address has the block number “101”, the page It is shown that the number is associated with the physical page address indicated by “0”. Further, it is shown that the data stored in the physical page address has attribute information “RT = 1 month or more, dirty”.

Note that “RT = 1 month or more, dirty” indicates data that needs to be guaranteed for one month or more after being written in the flash memory 119, and is data that is not currently written in the storage system 104. It is attribute information.

FIG. 8 shows a logical configuration of the physical address table 206. The physical address table 206 is used to convert a physical address into a logical address. Specifically, the physical address table 206 includes a physical page address column 207, a page valid / invalid column 208, and a logical address column 209.

The physical page address field 207 stores the physical page address of the flash memory 119. Here, the block number and page number are stored as physical page addresses. The page valid / invalid column 208 stores information (valid or invalid) indicating whether or not data is stored in the page. The logical address column 209 stores a logical address included in the read / write instruction from the host CPU 101.

Accordingly, in the case of FIG. 8, for example, data is stored in the physical page address indicated by the block number “101” and the page number “0” (valid), and this physical page address has the logical address “10”. It is shown that it is associated with the logical address.

FIG. 9 shows a logical configuration of the threshold value table 211. The threshold value table 211 is used for managing attribute information set in advance. Specifically, the threshold table 211 includes an attribute number column 212, a refresh determination cycle column 213, a refresh determination threshold column 214, and a defective block determination threshold column 215.

In the attribute number column 212, an attribute number that uniquely identifies a combination of RT time and information indicating clean or dirty is stored. In the present embodiment, a plurality of blocks are managed as a plurality of block groups for each attribute indicated by the attribute number. Data of a certain attribute is written to any block in the block group of that attribute.

Also, the refresh determination period column 213 stores a period for executing the refresh determination process. The refresh determination threshold value column 214 stores a threshold value (first allowable error rate) used for determining whether or not to execute the refresh process in the refresh determination process. The bad block determination threshold value column 215 stores a threshold value (second allowable error rate) used for determining whether or not the block is a bad block in the bad block determination process.

Accordingly, in the case of FIG. 9, for example, the attribute number “1” is an attribute number for managing data “RT = 1 month or more, dirty”, and the refresh determination cycle of the attribute data indicated by this attribute number Is “ITVL1”, the refresh threshold is “RF1”, and the bad block determination threshold is “BAD1”.

Here, the attribute number is set to 6 types from 1 to 6. However, this is not restrictive, and the range of RT time to be the same attribute is instructed by the management console etc. at the time of system initialization. It is determined. The values of the refresh determination period, the refresh determination threshold value, and the defective block determination threshold value are determined by the system designer based on the error characteristics of the flash memory 119 evaluated in advance.

Also, the short RT time means that the data guarantee time may be short, and it is not necessary to frequently execute the refresh process. Therefore, the smaller the RT time, the larger the refresh threshold value is set so that the refresh process is not executed frequently. In addition, the refresh threshold is set to a large value because it is not necessary to frequently execute the refresh process for clean data that may be lost in the worst case.

FIG. 10 shows a logical configuration of the history table 216. The history table 216 is used to manage the usage status of each block group when managing a plurality of blocks for each attribute as a block group. Specifically, the history table 216 includes an attribute number column 217, a current capacity column 218, and a maximum capacity column 219.

In the attribute number column 217, an attribute number that uniquely identifies a combination of RT time and information indicating clean or dirty is stored. The current capacity column 218 stores the current capacity for each attribute. The maximum capacity column 219 stores the maximum capacity for each attribute.

Note that the capacity of each block group to be prepared depends on the characteristics of the application program executed in the information processing system 1. In the case of an appliance server system or the like that executes specific processing, the application may instruct the flash memory system 103 in advance of the capacity ratio between block groups. The instruction command and the processing flow will be described later.

If the capacity ratio cannot be specified in advance, the flash memory system 103 may determine the capacity ratio by observing the usage history of the application.

FIG. 11 shows a conceptual configuration of the physical block management list group 220. The physical block management list group 220 is used to manage block groups divided for each attribute. Specifically, the physical block management list group 220 includes a write destination selection list 221, a refresh destination selection list 223, and a refresh determination list 226 for each attribute. Further, a reserve list 229 for registering blocks not registered in any management list and a defect list 230 for registering defective blocks are provided.

In the write destination selection list 221, data is stored in some pages (valid) among blocks belonging to the block group having any attribute, and data is not stored in some pages and is empty. Active (invalid) blocks are registered. That is, a block including a partially valid / invalid page is registered. The blocks registered in the write destination selection list 221 are managed so that they are always sorted in ascending order of error rate calculated at the time of previous reading.

The write destination selection list 221 belongs to a block group corresponding to the attribute of the data to be written when a data write instruction is received from the host CPU 101, and can be written (some pages are empty). Used to select the page with the lowest error rate. By selecting the block with the lowest error rate, dynamic wear leveling at the time of writing is realized.

For wear leveling, various methods using the number of times of writing and the elapsed time after writing are known regardless of the error rate. Here, for the sake of simplicity, it is assumed that sorting is performed based only on the error rate. However, the writing destination selection list 221 may be sorted by combining the above information, and the writing destination may be selected.

In the refresh destination selection list 223, blocks in which all pages are free among the blocks belonging to the block group of any attribute are registered. That is, a block including all invalid pages is registered. The blocks registered in the refresh destination selection list 223 are managed so that they are always sorted in ascending order of error rates calculated at the time of previous reading.

The refresh destination selection list 223 belongs to the block group corresponding to the attribute of the data to be refreshed when the processor 113 executes the refresh process, and all data of the refresh source can be written (all pages). Used to select the page with the lowest error rate.

In the refresh determination list 226, among blocks belonging to a block group having any attribute, a block in which data is stored in some pages and a block in which data is stored in all pages are registered. That is, a block including some or all valid pages is registered. The blocks registered in the refresh determination list 226 are managed so that they are always sorted in the order of physical block numbers.

In this refresh determination list 226, since blocks including partially valid pages are registered, blocks registered in the write destination selection list 221 (blocks including partially valid and partially invalid data) are included. Duplicate registration may occur.

FIG. 12 shows the internal structure of the management list 231. Since the internal configuration of each management list (221, 223, 226, 229, 230) in FIG. 11 is the same, each management list is generically described as the management list 231.

The management list 231 includes a plurality of block information 232 including a pointer 232A, a physical block number 232B, and a previous error rate 232C, and has a list structure in which a plurality of block information 232 is linked by the pointer 232A. The physical block number 232B stores a physical block number corresponding to each management list, and the previous error rate 232C stores an error rate calculated at the previous read time. In the case of the preliminary list 229, the previous error rate 232C is empty.

(1-4) Command Configuration FIG. 13 shows an internal configuration of a command issued by the host CPU 101. As commands issued by the host CPU 101, an attribute instruction command 304, a write instruction command 305, a read instruction command 306, and an invalidation instruction command 307 will be described here. These commands are issued by the host CPU 101 and then received by the flash memory system 103.

The attribute instruction command 304 is a command for instructing the attribute of data to be read / written, and is composed of a plurality of areas 304A to 304F. The area 304A is an area for declaring an attribute instruction command, the area 304B is an area for designating a range (logical address of the flash memory 119), and the area 304D is an area for designating a size. In addition, the area 304E and the area 304F are areas for designating attributes (RT time, clean or dirty) for data of a designated range and size.

The write instruction command 305 is a command for instructing data writing, and includes a plurality of areas 305A to 305D. The area 305A is an area for declaring that it is a write instruction command, the area 305B is an area for designating a write destination range (logical address of the flash memory 119), and the area 305C is a write source (main memory). 102 is a region for designating a data size of a write instruction target.

The read instruction command 306 is a command for instructing data reading, and includes a plurality of areas 306A to 306D. The area 306A is an area that declares that it is a read instruction command, the area 306B is an area that specifies a read source range (logical address of the flash memory 119), and an area 306C is a read destination range ( The area 306D is an area for designating the data size of the read instruction target.

The invalidation instruction command 307 is a command for instructing a range that may be invalidated, and includes a plurality of areas 307A to 307D. The area 307A is an area that declares an invalidation instruction command, the area 307B is an area that designates a range to be invalidated (logical address of the flash memory 119), and an area 307D is an invalidation target. This area specifies the data size.

FIG. 14 shows the internal structure of another command. These commands are commands used in the third embodiment to be described later, and are points that specify attributes in the write instruction command 302 without using the attribute instruction command 304 (points having an area 301E and an area 301F). Different from the command of FIG. Details of processing executed using this command will be described later (FIGS. 23A and 23B).

FIG. 15 shows the internal structure of another command. This command is a command used in a second embodiment to be described later, and is a capacity ratio instruction command 308 used in addition to the command of FIG. The capacity ratio instruction command 308 is a command for instructing the flash memory system 103 in advance with a capacity ratio between block groups, and includes a plurality of areas 308A to 308D.

An area 308A is an area for declaring that it is a capacity ratio instruction command, an area 308B and an area 308C are areas for specifying attributes of data to be read / written, and an area 308D is a capacity ( This is an area for specifying the capacity for each attribute. Details of processing executed using the capacity ratio instruction command 308 will be described later (FIG. 22).

(1-5) Process Flow Hereinafter, the process for improving the number of writable times by the flash memory controller 111 when the command of FIG. 13 is issued will be described with reference to FIGS.

FIG. 16A and FIG. 16B show the processing procedure of the writable count improvement process. This writeable frequency improvement process is executed by the flash memory controller 111 when, for example, a command to start processing is issued from the host CPU 101.

In this embodiment, since the capacity ratio for each block group is not given in advance, the processing of each command is executed using only attribute number 1 while monitoring the usage history of each attribute until step S1013 is reached. To do. Note that the attribute of attribute number 1 is the attribute with the smallest bad block determination threshold.

First, the flash memory controller 111 initializes the logical address table 201 (FIG. 7), the physical address table 206 (FIG. 8), the threshold table 211 (FIG. 9), and the history table 216 (FIG. 10). A management list (221, 223, 226), a spare list 229, and a defect list 230 are created (S1001).

Specifically, the flash memory controller 111 sets invalid bits in all of the page valid /

invalid fields

203 and 208, and initializes the logical address table 201 and the physical address table 206.

The flash memory controller 111 sets a predetermined value (cycle) in the refresh determination cycle field 213 and sets a predetermined threshold (allowable error rate) in the refresh determination threshold field 214 and the defective block determination threshold field 215. Then, the threshold value table 211 is initialized. The flash memory controller 111 initializes the history table 216 by setting 0 in the current capacity column 218 and the maximum capacity column 219.

Also, the flash memory controller 111 creates a spare list 229 by registering a predetermined number of blocks among the plurality of blocks of the flash memory 119 in the spare list 229, and blocks defective at the time of shipment in the defect list 230. The defect list 230 is created by registration.

Further, the flash memory controller 111 registers blocks other than the blocks registered in the spare list 229 and the defect list 230 in the refresh destination selection list 223 of attribute number 1 to create and register the refresh destination selection list 223 of attribute number 1. The write destination selection list 221 and the refresh determination list 226 with the attribute number 1 are created in a state where no block exists.

Next, the flash memory controller 111 determines whether or not the attribute instruction command 304 has been received (S1002). If the flash memory controller 111 obtains a negative result in the determination at step S1002, the flash memory controller 111 proceeds to step S1004.

On the other hand, when the flash memory controller 111 obtains a positive result in the determination at step S1002, the flash memory controller 111 registers the attribute number corresponding to the specified attribute in the logical address table 201, and stores the capacity corresponding to the specified size in the history. The data is updated in the table 216 (S1003).

Next, the flash memory controller 111 determines whether or not the write instruction command 305 has been received (S1004). If the flash memory controller 111 obtains a negative result in the determination at step S1004, the flash memory controller 111 proceeds to step S1006.

On the other hand, if the flash memory controller 111 obtains a positive result in the determination at step S1004, it refers to each management list (221, 223, 226) of attribute number 1 and writes from the block group of attribute number 1. The previous page is selected, and data is written to the selected page (S1005).

The flash memory controller 111 writes the data and updates the logical address table 201 and the physical address table 206 so that the logical address corresponds to the physical address where the data is written. In addition, since some valid / partial invalid blocks or all valid blocks exist due to data writing, the block information 232 is moved between the management lists (221, 223, 226) of attribute number 1 to The management list is updated (S1005).

Next, the flash memory controller 111 determines whether or not the read instruction command 306 has been received (S1006). If the flash memory controller 111 obtains a negative result in the determination at step S1006, the flash memory controller 111 proceeds to step S1008.

On the other hand, when the flash memory controller 111 obtains a positive result in the determination at step S1006, it reads data from the physical address corresponding to the designated logical address with reference to the logical address table 201 (S1007).

In step S1007, the refresh determination process may be executed with reference to the error rate.

Next, the flash memory controller 111 determines whether or not the invalidation instruction command 307 has been received (S1008). If the flash memory controller 111 obtains a negative result in the determination at step S1008, the flash memory controller 111 proceeds to step S1010.

On the other hand, when the flash memory controller 111 obtains a positive result in the determination at step S1008, it refers to the logical address table 201 and the physical address table 206 and invalidates the page of the specified logical address and the corresponding physical address. The logical address table 201 and physical address table 206 are updated (S1009).

Since the flash memory controller 111 has all invalid blocks due to the invalidation, the block information 232 is moved between the management lists (221, 223, 226) of attribute number 1 and the respective management lists. Update. Also, the history table 216 is updated by reflecting the invalidated capacity phenomenon in the current capacity column 218 of the corresponding attribute (S1009).

Next, the flash memory controller 111 refers to the threshold table 211 to determine whether or not the block group having the attribute indicated by the attribute number 1 is the execution timing of the refresh determination process (S1010).

If the flash memory controller 111 obtains a negative result in the determination at step S1010, it proceeds to step S1012. On the other hand, when the flash memory controller 111 obtains a positive result in the determination in step S1010, it sequentially reads all the blocks registered in the refresh determination list 226 of attribute number 1 and executes a refresh determination process. In this case, refresh processing is executed (S1011).

In the refresh determination process, the flash memory controller 111 refers to the threshold value table 211, and determines the refresh determination threshold value (first allowable error rate) corresponding to the attribute number 1 and the previous error rate of the block read from the refresh determination list 226. Compare with 232C. If the previous error rate is equal to or higher than the refresh determination threshold, it is determined that the refresh process needs to be executed.

In the refresh process, the flash memory controller 111 selects the refresh destination block from the refresh destination selection list 223 with the attribute number 1, and writes the block data read from the refresh determination list 226 to the selected block.

In addition, the flash memory controller 111 refers to the threshold table 211 during the refresh determination process, and determines the bad block determination threshold (second allowable error rate) corresponding to the attribute number 1 and the previous block read from the refresh determination list 226. The error rate 232C is compared. If the previous error rate is equal to or higher than the defective block determination threshold, it is determined that the read block is defective, and this block is registered in the defect list 230 together with the read error rate.

Next, the flash memory controller 111 determines whether the history monitoring period has elapsed (S1012). If the flash memory controller 111 obtains a negative result in the determination at step S1012, the flash memory controller 111 proceeds to step S1002 and repeats the processing described above.

On the other hand, when the flash memory controller 111 obtains a positive result in the determination at step S1012, the flash memory controller 111 proceeds to step S1015 and enables the processing described above for all the attributes other than the attribute number 1 to be executed. Each management list (221, 223, 226) with numbers 2 to 6 is created, the attribute data indicated by the attribute numbers 2 to 6 is written to the corresponding block group block, the logical address table 201, the physical address table 206 and each management list (221, 223, 226) are updated (S1015).

Specifically, the flash memory controller 111 first refers to the maximum capacity column 219 of the history table 216 and acquires the used capacity ratio of each attribute. Next, a refresh destination selection list 223 with attribute numbers 2 to 6 is created, and block information 232 is moved according to the capacity ratio acquired from the refresh destination selection list 223 with attribute number 1.

Further, the flash memory controller 111 refers to the logical address table 201 and transfers data to all blocks in the refresh determination list 226 with attribute number 1 to blocks in the refresh destination selection list 223 with attribute numbers 2 to 6. In order to reflect the transferred result, the logical address table 201 and the physical address table 206 are updated, and the block information 232 is added to the write destination selection list 221 and the refresh determination list 226 with the attribute numbers 2 to 6.

As a result of this transfer, blocks in which all pages are invalid are generated among the block information 232 in the write destination selection list 221 of attribute number 1 and the refresh determination list 226, and these are attributed according to the used capacity ratio for each attribute. It is distributed to the refresh destination selection list 223 of numbers 2-6.

In addition, even if the block with the attribute number 1 is determined to be a bad block in step S1011, the other attribute numbers 2 to 6 may not be a bad block. The blocks determined as defective blocks are moved to the refresh destination selection lists 223 of 2 to 6.

In the present embodiment, the data of all blocks in the refresh determination list 226 with attribute number 1 are transferred at once to the blocks in the refresh destination selection list 223 with original attribute numbers 2 to 6, but this is not restrictive. Alternatively, the write data may be moved little by little to the original write destination selection list 221 and the refresh determination list 226 of the attribute numbers 2 to 6 when the write instruction command 305 is received and when the refresh determination process is executed.

The processing of steps S1016 to S1023 does not update the history table 216 in step S1017. In step S1019, the management list (221, 223, 226) is written in the block group of original attribute numbers 2 to 6 instead of attribute number 1. Is different from steps S1002 to S1009 in that the management list (221, 223, 226) of the original attribute numbers 2 to 6 is updated instead of the attribute number 1 in step S1023.

After executing the processing of steps S1016 to S1023, the flash memory controller 111 refers to the threshold value table 211 and determines whether the block group having the attribute indicated by the attribute number M (2 to 6) is the execution timing of the refresh determination processing. If it is determined whether or not (S1024) and an affirmative result is obtained, a refresh determination process, a refresh process or a defective block determination process is executed (S1025), and a series of processes in this process is terminated.

In the process of step S1025, even if the attribute number M (any one of 2 to 6) is determined to be a bad block in the bad block determination process, any other attribute number (any one of 2 to 6 other than M) is bad. If not determined, step S1011 is different in that a process of moving to a block group with another attribute number is executed. Details will be described later (FIG. 21B).

FIG. 17 shows a processing procedure of attribute instruction command reception processing. This attribute instruction command receiving process is a process that is executed when the flash memory controller 111 receives the attribute instruction command 304. Specifically, the attribute instruction command receiving process is a detailed process in steps S1003 and S1017 of FIGS. 16A and 16B. is there.

First, when the flash memory controller 111 receives the attribute instruction command 304, it registers any one of the attribute numbers 1 to 6 specified in the corresponding logical address range of the logical address table 201 (S1102). Next, the flash memory controller 111 determines whether or not history monitoring has elapsed (S1103).

If the flash memory controller 111 obtains a negative result in the determination at step S1103, it ends this attribute instruction command receiving process. On the other hand, when the flash memory controller 111 obtains a positive result in the determination at step S1103, it adds the capacity of the logical address range specified in the current capacity column 218 of the corresponding attribute of the history table 216 to add the history table 216 to the history table 216. Update (S1104).

Next, the flash memory controller 111 refers to the history table 216 to determine whether the maximum capacity of each attribute is larger than the current capacity (S1105). If the flash memory controller 111 obtains a negative result in the determination at step S1105, it ends this attribute instruction command reception processing. On the other hand, when the flash memory controller 111 obtains a positive result in the determination at step S1105, it updates the value of the corresponding maximum capacity column 219 (S1106), and ends this attribute instruction command receiving process.

FIG. 18 shows the processing procedure of the write instruction command reception process. This write instruction command receiving process is a process that is executed when the flash memory controller 111 receives the write instruction command 305, and specifically, is a detailed process in steps S1005 and S1019 of FIGS. 16A and 16B. is there.

First, the flash memory controller 111 assigns the attribute number (attribute number indicating the original attribute of the write data) to be registered in the attribute number column 205 of the logical address table 201 to the variable L (S1202). Next, the flash memory controller 111 determines whether or not the history monitoring period has elapsed (S1203).

If the flash memory controller 111 obtains a positive result in the determination at step S1203, it substitutes the variable L (any one of 2 to 6) for the variable K to execute processing for the attribute numbers 2 to 6 after the history monitoring period has elapsed. (S1204). In contrast, if the flash memory controller 111 obtains a negative result in the determination at step S1203, it substitutes 1 for the variable K to execute the process for attribute number 1 before the history monitoring period elapses (S1205).

Next, the flash memory controller 111 determines whether or not the write destination selection list 221 with the attribute number K is not empty (S1206). If the flash memory controller 111 obtains a positive result in the determination at step S1206, it selects a write destination page from the block groups classified in the write destination selection list 221 with the attribute number K (S1207).

At this time, the flash memory controller 111 selects the first block information (block information with the lowest error rate) from among the block information registered in the write destination selection list 221 with the attribute number K, thereby writing the write destination. Select the page. Then, the flash memory controller 111 writes data to the selected page (S1211).

On the other hand, if the flash memory controller 111 obtains a negative result in the determination at step S1206, it determines whether or not the refresh destination selection list 223 with the attribute number K is not empty (S1208). If the flash memory controller 111 obtains a positive result in the determination at step S1208, it selects a write destination page from the block group classified in the refresh destination selection list 223 with the attribute number K (S1209), and selects the selected page. Data is written (step S1211).

If the flash memory controller 111 obtains a negative result in the determination at step S1208, it selects a write destination page from the block group classified in the preliminary list 229 (S1210), and writes the data to the selected page (step S1210). S1211). In step S1211, data is written to the pages classified in any management list (221, 223, 229).

Next, the flash memory controller 111 is instructed to overwrite a logical address that has already been written by the write instruction command 305 and data has been written. It is determined whether or not an old physical page address is registered (S1214).

If the flash memory controller 111 obtains a negative result in the determination at step S1214, the flash memory controller 111 proceeds to step S1218. On the other hand, when the flash memory controller 111 obtains a positive result in the determination at step S1214, it invalidates the old physical page of the logical address table 201 (S1215).

The flash memory controller 111 determines whether all pages in the physical block including the invalidated physical page have been invalidated by the invalidation process in step S1215 (S1216). If the flash memory controller 111 obtains a negative result in the determination at step S1216, the flash memory controller 111 proceeds to step S1218.

On the other hand, when the flash memory controller 111 obtains a positive result in the determination at step S1216, it moves the block information 232 between the management lists (221, 223, 226) of the attribute number K and updates each management list. . Specifically, the block information 232 regarding the old physical block is deleted from the refresh determination list 226, deleted from the write destination selection list 221 (if registered), and registered in the refresh destination selection list 223 (S1217).

Next, the flash memory controller 111 registers a new physical page address corresponding to the page selected in step S1207, S1209, or S1210 in the logical address table 201, and also registers a logical address corresponding to the new physical page address in the physical address table 206. (S1218).

Next, the flash memory controller 111 determines whether or not a page is selected from the refresh destination selection list 223 or the spare list 229 in step S1209 or S1210 (S1219). If the flash memory controller 111 obtains a negative result in the determination at step S1219, the flash memory controller 111 proceeds to step S1221.

On the other hand, if the flash memory controller 111 obtains a positive result in the determination at step S1219, a part of the block including the page selected at step S1209 or S1210 becomes valid, so the block information 232 of this block is updated to the refresh destination. It is deleted from the selection list 223 or the reserve list 229, while being registered in the refresh determination list 226 with the attribute number K (S1220).

Next, the flash memory controller 111 determines whether there is an empty page in a part of the block including the page selected in step S1209 or S1210 (S1221). When the flash memory controller 111 obtains a positive result in the determination at step S1221, the block information of the block including the page selected at step S1209 or S1210 (if not registered) is written to the write destination selection list 221 with the attribute number K. (S1222), and the write instruction command receiving process is terminated.

In contrast, if the flash memory controller 111 obtains a negative result in the determination at step S1221, the flash memory controller 111 determines that all the pages are valid as a result of writing data to the page selected at step S1209 or S1210. Is deleted from the write destination selection list 221 of the attribute number K (if registered) (S1223), and the write instruction command receiving process is terminated.

FIG. 19 shows a processing procedure for reading instruction command reception processing. This read instruction command receiving process is a process that is executed when the flash memory controller 111 receives the read instruction command 306. Specifically, the read instruction command receiving process is a detailed process in steps S1007 and S1021 of FIGS. 16A and 16B. is there.

The flash memory controller 111 reads the data from the physical page address corresponding to the designated logical address with reference to the logical address table 201 (S1302), and ends the read instruction command receiving process.

FIG. 20 shows the processing procedure of the invalidation instruction command reception processing. This invalidation instruction command receiving process is a process that is executed when the flash memory controller 111 receives the invalidation instruction command 307. Specifically, the details are detailed in steps S1009 and S1023 of FIGS. 16A and 16B. It is processing.

First, the flash memory controller 111 refers to the logical address table 201 and the physical address table 206 to invalidate the old physical page address corresponding to the designated logical address (S1305).

The flash memory controller 111 determines whether all pages in the physical block including the invalidated physical page have been invalidated by the invalidation process in step S1305 (S1306). If the flash memory controller 111 obtains a negative result in the determination at step S1306, the flash memory controller 111 proceeds to step S1312.

On the other hand, if the flash memory controller 111 obtains a positive result in the determination at step S1305, it substitutes the attribute number registered in the attribute number column 205 of the logical address table 201 for the variable L (S1307). Next, the flash memory controller 111 determines whether or not the history monitoring period has elapsed (S1308).

If the flash memory controller 111 obtains a positive result in the determination at step S1308, the flash memory controller 111 executes processing for any of the attribute numbers 2 to 6 after the history monitoring period elapses. ) Is substituted (S1309). On the other hand, when the flash memory controller 111 obtains a negative result in the determination at step S1308, it substitutes 1 for the variable K in order to execute the process for the attribute number 1 before the history monitoring period elapses (S1310).

Next, the flash memory controller 111 moves the block information 232 between each management list (221, 223, 226) of the attribute number K and updates each management list. Specifically, the block information 232 relating to the old physical block is deleted from the refresh determination list 262, deleted from the write destination selection list 221 (if registered), and registered in the refresh destination selection list 223 (S1311).

Next, the flash memory controller 111 determines whether or not the history monitoring period has elapsed (S1312). If a negative result is obtained in this determination, the invalidation instruction command receiving process is terminated. On the other hand, if the flash memory controller 111 obtains a positive result in this determination, it subtracts the capacity in the range of the logical address designated from the current capacity column 218 of the corresponding attribute of the history table 216, thereby subtracting the history table 216 from the history table 216. It is updated (S1313), and the invalidation instruction command receiving process is terminated.

21A and 21B show a processing procedure for the refresh determination process and the bad block determination process. This refresh determination process and bad block determination process are processes executed by the flash memory controller 111 when the block group of any attribute is the execution timing of the refresh determination process. Specifically, FIG. And detailed processing in S1011 and S1025 of FIG. 16B.

First, the flash memory controller 111 refers to the threshold value table 211 and determines whether or not the block group having the attribute indicated by the attribute number M (any one of 1 to 6) is the execution timing of the refresh determination process (S1402). ). If the flash memory controller 111 obtains a negative result in this determination, it ends this refresh determination processing and bad block determination processing.

On the other hand, when the flash memory controller 111 obtains a positive result in the determination at step S1402, the flash memory controller 111 selects one physical block from the block information 232 registered in the refresh determination list 226 with the attribute number M, and selects the selected physical block. The data is read out to calculate the error rate (S1403).

Next, the flash memory controller 111 refers to the threshold table 211 to determine whether or not the calculated error rate is equal to or higher than the corresponding refresh determination threshold (first allowable error rate) (S1405). If the flash memory controller 111 obtains a positive result in this determination, it first determines whether or not the refresh destination selection list 223 with the attribute number M is not empty in order to execute the refresh process (S1406).

If the flash memory controller 111 obtains a positive result in the determination at step S1406, it selects the block to be refreshed from the refresh destination selection list 223 with the attribute number M (S1407). At this time, the block of the block information 232 at the head (the error rate is minimum) in the management list is selected. On the other hand, if the flash memory controller 111 obtains a negative result in the determination at step S1406, it selects a block to be refreshed from the preliminary list 229 (S1408).

Next, the flash memory controller 111 writes all the data read in step S1403 to the selected physical block (refresh processing), registers the corresponding new physical page address in the logical address table 201, and stores the corresponding logical address in the physical address table. It registers in 206.

Further, the physical block from which the physical address table 206 is read is invalidated, the selected physical block is deleted from the refresh destination selection list 223 or the spare list 229 with the attribute number M, and registered in the refresh determination list 226 with the attribute number M (S1409). ). In addition, when registering in the refresh determination list 226, the error rate calculated in step S1403 is included in a sortable position in the block information 232 before registration.

Then, the flash memory controller 111 determines whether there is still an empty page in the write destination block written by the refresh process (S1410). If the block read in step S1403 has no space, a negative result is obtained because there is no space in the write destination block. If some of the blocks are free, a positive result is obtained because the write destination block is also free. It will be.

If the flash memory controller 111 obtains a negative result in the determination at step S1410, the process proceeds to step S1423. On the other hand, if the flash memory controller 111 obtains a positive result in the determination at step S1410, it registers the block information 232 of the write destination block in the write destination selection list 221 with the attribute number M (S1411), and proceeds to step S1423. Transition.

Returning to step S1405, if the flash memory controller 111 obtains a negative result in the determination of step S1405, it determines that the execution of the refresh process is not necessary, and updates the corresponding error rate in the refresh determination list 226 for attribute number M. (S1412).

Next, the flash memory controller 111 determines whether or not the block information 232 corresponding to the physical block selected in step S1403 is registered in the write destination selection list 221 with the attribute number M (S1413).

If the flash memory controller 111 obtains a negative result in the determination at step S1413, the process proceeds to step S1429. On the other hand, when the flash memory controller 111 obtains a positive result in the determination at step S1413, it updates the error rate of the block information 232 registered in the write destination selection list 221 with the attribute number M (S1414). The process shifts to S1429.

Next, since all pages in the read-source physical block selected in step S1403 are invalidated by the refresh process, the flash memory controller 111 receives the block information 232 for the old read-source physical block from the refresh determination list 226 with the attribute number M. Delete (if registered) from the write destination selection list 221 (S1423).

Next, the flash memory controller 111 refers to the threshold table 211 and determines whether or not the error rate calculated in step S1403 is equal to or higher than the corresponding defective block determination threshold (second allowable error rate) (S1424).

If the flash memory controller 111 obtains a negative result in this determination, it determines that the old physical block to be read is not a bad block, and registers the block information 232 of this physical block in the refresh destination selection list 223 with the attribute number M (S1425), the process proceeds to step S1429. When registering in the refresh destination selection list 223, the error rate calculated in step S1403 is included in a sortable position in the block information 232 before registration.

On the other hand, if the flash memory controller 111 obtains a positive result in the determination at step S1424, the block having the attribute indicated by the attribute number M is a bad block, but the block having another attribute may not be a bad block. Therefore, with reference to the threshold table 211, it is determined whether there is an attribute number J of a defective block determination threshold smaller than the error rate calculated in step S1403 (S1426).

Note that the bad block determination threshold corresponding to attribute number 1 is smaller than the bad block determination threshold corresponding to other attribute numbers (2 to 6). Therefore, when the process of step S1424 is executed only for attribute number 1 before the history monitoring period elapses, the process proceeds to step S1428 without proceeding to step S1426.

If the flash memory controller 111 obtains a positive result in the determination at step S1426, it registers the block information of the old physical block of the read source in the refresh destination selection list 223 with the attribute number J (S1427), and proceeds to step S1429. In this case, the registration is performed after the error rate is included in a sortable position in the block information 232.

On the other hand, if the flash memory controller 111 obtains a negative result in the determination at step S1426, the flash memory controller 111 determines that the read-out physical block is a bad block in any attribute indicated by any attribute number (1 to 6). The physical block is registered in the defect list 230 (S1428), and the process proceeds to step S1429.

The flash memory controller 111 determines whether or not the processing described above has been executed for all block information registered in the refresh determination list 226 with the attribute number M (S1429). If the flash memory controller 111 obtains a negative result in this determination, it proceeds to step S1403 in order to repeatedly execute the above-described processing for other physical blocks having the same attribute. On the other hand, when the flash memory controller 111 obtains a positive result in this determination, it ends the refresh determination process and the defective block determination process.

(2) Second Embodiment In the second embodiment, in an appliance server system or the like that executes a specific process, an application running on the host CPU 101 stores a capacity ratio between block groups in the flash memory system 103 in advance. It differs from the first embodiment in that it is instructed. The information processing system in the second embodiment will be described below. The description of the same configuration as that of the first embodiment is omitted, and a different configuration will be described.

(2-1) Processing Flow FIG. 22 shows the processing procedure of the second writable count improvement processing. The second writable count improvement process is executed by the flash memory controller 111 when a command to start processing is issued from the host CPU 101, for example. In the second embodiment, a capacity ratio instruction command 308 in FIG. 15 is used in addition to the commands in FIG.

First, the flash memory controller 111 initializes the logical address table 201, the physical address table 206, and the threshold table, initializes the history table 216 based on the capacity ratio instruction command 308, and manages each management list (221, Attribute Number 1 to 6). 223, 226), the preliminary list 229 and the defect list 230 are created (S1515).

invalid fields

Further, the flash memory controller 111 sets a predetermined determination period in the refresh determination period column 213 for each attribute of the attribute numbers 1 to 6, and is predetermined in the refresh determination threshold field 214 and the defective block determination threshold field 215. A threshold value (allowable error rate) is set, and the history table 216 is initialized.

The flash memory controller 111 initializes the history table 216 based on the designated capacity because the capacity for each of the attribute numbers 1 to 6 is designated by the capacity ratio instruction command 308.

Further, the flash memory controller 111 registers the blocks other than the blocks registered in the spare list 229 and the defect list 230 in the refresh destination selection list 223 having the attribute numbers 1 to 6 based on the capacity ratio registered in the history table 216. A refresh destination selection list 223 with numbers 1 to 6 is created. In addition, the write destination selection list 221 and the refresh determination list 226 with the attribute numbers 1 to 6 are created in a state where there is no block to be registered.

Since the processing in steps S1516 to S1525 is the same as the processing in steps S1016 to S1026 after the history monitoring organization in FIG. 16B, description thereof is omitted here.

(3) Third Embodiment The third embodiment is different from the first embodiment in that the attribute of data is designated for each writing using the write instruction command 301 of FIG. 14 without using the attribute instruction command 304. This is different from the embodiment. Hereinafter, description of the same configuration as that of the first embodiment will be omitted, and a different configuration will be described.

Note that when the host CPU 101 uses the flash memory system 103, it may not be determined in advance how much data with a certain attribute is read or written. In this case, since the host CPU 101 cannot issue the attribute instruction command 304 in FIG. 13, the attribute of the data to be written every time writing is performed using the write instruction command 301 in FIG. 14 instead of the attribute instruction command 304. specify.

(3-1) Processing Flow FIGS. 23A and 23B show a processing procedure of the third writable number improvement processing. This third writable count improvement process is executed by the flash memory controller 111 when the host CPU 101 issues a process start instruction command, for example. In the third embodiment, each command in FIG. 15 is used.

The third writable number improvement process shown in FIGS. 23A and 23B is performed in the write instruction command reception process without performing the attribute instruction command reception process (FIG. 16A: S1002, S1003, FIG. 16B: S1016, S1017). This is different from the first embodiment in that an instruction command receiving process is executed. The write command reception process (S1604, S1605, S1618, S1619) will be described below.

First, steps S1604 and S1605 will be described. When the flash memory controller 111 receives the write instruction command 301 before the attribute monitoring organization has elapsed (S1604: YES), refer to each management list (221, 223, 226) of attribute number 1. Then, a write destination page is selected from the block group with attribute number 1, and data is written to the selected page (S1605).

The flash memory controller 111 writes the data and updates the logical address table 201 and the physical address table 206 so that the logical address corresponds to the physical address where the data is written. Further, based on the attribute specified by the write instruction command 301, the attribute number is registered in the attribute number column 205 of the logical address table 201 (S1605).

The flash memory controller 111 has a block information between the management lists (221, 223, and 226) of attribute number 1 because there is a partly valid / invalid block or a whole valid block by writing data. 232 is moved and each management list is updated. Further, the size instructed by the write instruction command is added to the corresponding current capacity column 218 of the history table 216, and when the current capacity becomes larger than the maximum capacity, the maximum capacity field is also updated (S1605).

Next, steps S1618 and S1619 will be described. When the flash memory controller 111 receives the write instruction command 301 after the attribute monitoring period has elapsed (S1618: YES), the flash memory controller 111 selects the write destination from any of the block groups of attribute numbers 2 to 6. A page is selected, and data is written to the selected page (S1619).

Further, the flash memory controller 111 writes the data and updates the logical address table 201 and the physical address table 206 so that the logical address corresponds to the newly written physical address. In addition, since the data is written in the block groups of the original attribute numbers 2 to 6 instead of the attribute number 1, the block information 232 is moved by the management lists (221, 223, 226) of the attribute numbers 2 to 4, and each management list is moved. Update. The history table 216 is not updated.

(4) Fourth Embodiment In the fourth embodiment, a program on the host CPU 101 instructs data attributes (RT time, clean or dirty) according to the method of using the flash memory system 103 and information in the program. A configuration using the flash memory system 103 will be described in detail with reference to FIGS.

(4-1) Internal Configuration FIG. 24 shows the internal configuration of the main memory 102. The main memory 102 includes an application 401, middleware 402, file system 403, device driver 404, and interfaces 402A, 403A, and 404A. These programs are executed by the host CPU 101.

The device driver 404 accesses the flash memory system 103 using each command shown in FIGS. A file system 403 is provided on the device driver 404. The application 401 and the middleware 402 can access the flash memory system 103 as a high-speed file system via the interface 403A.

Further, the middleware 402 can directly access the device driver 404 via the interface 404A and use the flash memory system 103 as if it were an extended area of the main memory 102, instead of a file system. Further, the application 401 uses the interface 402A, which is a special interface provided from the middleware 402, so that the flash memory system 103 is used as if it is an extended area of the main memory 102 via the middleware without going through the file system. can do.

FIG. 25 shows a data arrangement configuration in the information processing system 1. Each data is arranged in the storage system 104, the flash memory system 103, and the main memory 102. Specifically, files E and F are arranged in the storage system 104. Files C and D are arranged in the flash memory system 103, and areas A and B used as a main memory expansion area are arranged.

The main memory 102 also periodically stores a transfer buffer 405 for transferring data between the storage system 104 and the flash memory system 103, a work area 406 for the host CPU 101 to perform calculations, and data being calculated. The checkpoint data 409 for writing to the flash memory system 103 is stored. A configuration in which a program on the host CPU 101 uses the flash memory system 103 using these data will be described below with reference to FIGS.

(4-2) Processing Flow FIG. 26 shows a first processing flow by the application 401. This first processing flow is processing when the application 401 uses the file C on the flash memory system 103 as a high-speed file system via the file system 403. Note that the processing is actually executed in cooperation with the host CPU 101 and the application 401, but here, for convenience of explanation, the processing entity will be described as the application 401.

First, the application 401 declares that the file C on the flash memory system 103 is to be used and secures the file C (S2001). Since it is used as a permanent file in the declaration, for example, one month is specified as the RT time, and since it is used as a main body file instead of a copy of the storage system 104, dirty is specified.

Next, the application 401 reads the file E in the storage system 104 onto the work area 406 of the main memory 102, and writes the read file E into the file C as an initial value (S2002). Next, the application 401 determines whether or not the data of the file C is necessary (S2003).

If the application 401 obtains a negative result in the determination at step S2003, the application 401 proceeds to step S2005. On the other hand, when the application 401 obtains a positive result in the determination at step S2003, the application 401 reads a part of the file C onto the work area 406 of the main memory 102 (S2004). The application 401 executes processing on the work area 406 and writes the execution result in the file C (S2005).

Next, the application 401 determines whether or not the processing is completed (S2006). If the application 401 obtains a negative result in this determination, it proceeds to step S2003 and repeats the processing described above. On the other hand, if the application 401 obtains a positive result in this determination, it ends this first processing flow.

FIG. 27 shows a second processing flow by the middleware 402. This second processing flow is processing when the middleware 402 (database system) uses the file C on the flash memory system 103 via the file system 403 as a high-speed database system. Note that the processing is actually executed in cooperation with the host CPU 101 and the middleware 402, but here, for convenience of explanation, the processing entity will be described as the middleware 402.

First, the middleware 402 declares that the file C on the flash memory system 103 is to be used and secures the file C (S2101). In the declaration, since it is used as a permanent database, for example, one month is specified as the RT time, and since it is used as a main body file instead of a copy of the storage system 104, dirty is specified.

Next, the middleware 402 reads the original database (file E) in the storage system 104 onto the transfer buffer 405 of the main memory 102, and writes the read file E into the file C as an initial value (S2102). Next, the middleware 402 determines whether or not the transfer of all data to the file C has been completed (S2103).

If the middleware 402 obtains a negative result in the determination at step S2103, it proceeds to step S2102 and repeats the above processing. On the other hand, when the middleware 402 obtains a positive result in the determination in step S2103, it notifies the application 401 of the completion of initialization (S2104). Next, the middleware 402 determines whether or not a reference type query from the application 401 has been received (S2105).

When the middleware 402 obtains a positive result in the determination in step S2105, the middleware 402 reads a part of the reference target file C onto the work area 406 of the main memory 102, processes the reference type query on the work area 406, and obtains the processing result. After the processing result is committed to the file C, it is returned to the application 401 (S2106).

On the other hand, when the middleware 402 obtains a negative result in the determination at step S2105, it determines whether an update type query from the application 401 has been received (S2105). If the middleware 402 obtains a negative result in this determination, it moves to step S2105 and repeats the above processing. On the other hand, when the middleware 402 obtains a positive result in this determination, it executes a process for the update type query.

Specifically, the middleware 402 reads a part of the file C to be updated onto the work area 406 of the main memory 102, processes the update type query on the work area 406, writes the processing result to the file C, and outputs the processing result. After committing to the file C, it is returned to the application 401 (S2108).

FIG. 28 shows a third processing flow by the middleware 402. In the third processing flow, although the middleware 402 (database system) uses the file E in the storage system 104 as a database, it is a very complicated and large-scale query. This is a process for securing a temporary area necessary for the query process on the high-speed flash memory system 103 when the data cannot be stored and the file access must be repeated. Note that the processing is actually executed in cooperation with the host CPU 101 and the middleware 402, but here, for convenience of explanation, the processing entity will be described as the middleware 402.

First, the middleware 402 determines whether or not a reference-type large-scale query from the application 401 has been received (S2201). If the middleware 402 obtains a positive result in this determination, it secures the area A on the flash memory system 103 (S2202). If the power interruption occurs during the process, the query process may be discarded without being completed, so the RT time is designated as 0. Also, since this is a reference type query and the original data is in the storage system 104, clean is designated.

Next, the middleware 402 sequentially transfers and writes a part of the data of the file E necessary for the query processing to the area A via the transfer buffer 405 on the main memory 102 (S2203). Next, the middleware 402 writes all the data of the file E into the area A, and determines whether or not the data transfer is completed (S2204).

If the middleware 402 obtains a negative result in the determination at step S2204, the middleware 402 proceeds to step S2203 and repeats the above processing. On the other hand, when the middleware 402 obtains a positive result in the determination at step S2204, it sequentially reads all data in the area A into the work area 406 of the main memory 102, executes query processing on the work area 406, and obtains the processing result. Data is written on the work area 406 (S2205).

Next, the middleware 402 executes query processing for all data in the area A and determines whether the processing is completed (S2206). If the middleware 402 obtains a negative result in this determination, it moves to step S2205 and repeats the above processing. On the other hand, when the middleware 402 obtains a positive result in this determination, it releases the area A and returns the processing result to the application 401 (S2207).

Here, for simplicity, it is assumed that all data is once transferred from the file E to the area A and then read and processed little by little into the work area 406. However, the present invention is not limited to this. It is also possible to execute a part of the query processing by reading out to.

Returning to step S2201, when the middleware 402 obtains a negative result in the determination of step S2201, it determines whether a simple query that does not require the area A has been received (S2208). If the middleware 402 obtains a negative result in this determination, it moves to step S2201 and repeats the above processing. On the other hand, when the middleware 402 obtains a positive result in this determination, it reads necessary data from the file E in the storage system 104 onto the work area 406 of the main memory 102, and executes query processing (S2209).

29 and 30 show a fourth processing flow by the application 401 and a fifth processing flow by the middleware 402. The fourth and fifth processing flows are processes when the middleware 402 such as a large-scale data analysis framework provides the application 401 with an environment in which the flash memory system 103 is used as the main memory expansion area. Hereinafter, description will be made with reference to FIGS. 29 and 30 alternately.

First, the application 401 notifies the middleware 402 of the number of data to be processed. Further, the middleware 402 is notified of the files E and F in the storage system 104 storing the original data G and H used for the calculation (S2401).

When the middleware 402 receives these notifications, it estimates the total capacity of the data G and H based on the number of data to be processed. As a result of estimation, if it is found that the total capacity of the data G and H does not fit in the main memory 102, the data G and H are divided into a plurality of partial areas in consideration of the main storage capacity. Then, areas A and B corresponding to the total capacity of the data G and H are secured on the flash memory system 103 (S2501).

Since these areas are used as main memory expansion areas, it is not necessary to guarantee the data in the same way as the main memory 102 if a power interruption occurs. “Clean” is designated, and “Dirty” is designated for the area B. Here, it is assumed that the middleware 402 itself knows that the data G is clean and the data H is dirty because of the function provided to the application 401 by the large-scale data analysis framework.

Next, the middleware 402 transfers all data of the file E to the area A via the main memory 102 (S2502, S2503), and transfers all data of the file F to the area B (S2504, S2505). Further, according to the determined division, the middleware 402 reads the partial areas of the data G and H from the areas A and B onto the work area 406 of the main memory 102, and notifies the application 401 of the completion of partial calculation preparation (S2506).

When the application 401 receives the partial calculation preparation completion notification (S2402: YES), the application 401 executes the calculation using the data G and H on the work area 406, and updates the data H on the work area 406. When the partial calculation for one time is completed, the middleware is notified (S2403).

When the middleware 402 receives the partial calculation completion notification from the application 401 (S2507: YES), the middleware 402 writes the data H on the main memory 102 to the area B (S2508), and unless it receives a total calculation end notification from the application 401 (S2509: NO), reading the next partial area from the areas A and B to the main memory 102 is repeated. Here, it is assumed that when the last partial areas of the areas A and B are read out to the main memory 102, the process is repeated from the first partial areas of the areas A and B.

When the application 401 repeats the partial calculation and all the calculations are completed (S2404: YES), the application 401 notifies the middleware 402 of the completion of all the calculations (S2405).

When the middleware 402 receives the notification of completion of all calculations from the application 401, the middleware 402 transfers the entire area B to the file F in the storage system 104 (S2510), and when the transfer is completed (S2511: YES), notifies the application 401 (S2512). ). When the application 401 receives a file output completion notification from the middleware 402 (S2406: YES), the application 401 ends the process.

FIG. 31 shows a sixth processing flow by the application 401 or the middleware 402. This sixth processing flow is performed when a middleware 402 such as a large-scale data analysis framework or an application 401 such as a large-scale scientific calculation executes an analysis calculation that takes a very long time, and the intermediate result of the calculation is used as a checkpoint file in the flash memory. This is a process for storing on the system 103.

Note that such large-scale calculation often requires a large-capacity calculation area, so it may be used together with the processing flow of FIGS. 29 and 30 using the flash memory system 103 as the main memory expansion area. Here, a case where they are not used together will be described.

First, the middleware 402 or the application 401 estimates the total execution time of the program and the amount of checkpoint data based on the number of data to be processed (S2301). The time required for the checkpoint (stored in the flash memory system 103) is estimated from the checkpoint data amount, and the checkpoint cycle is determined so that the estimated time does not impose the execution time of the entire program (S2301).

The checkpoint is for restarting the calculation from the previous checkpoint when an analysis calculation that takes a long time is interrupted due to a power failure, etc., so the checkpoint data is retained for a long time longer than the total execution time of the program. It doesn't make sense. The reason is that the program can be re-executed from the beginning if that time is available. Therefore, the middleware 402 or the application 401 determines the RT time based on the total execution time of the program. In this example, it is 1 day (S2301).

When the checkpoint cycle is reached (S2302: YES), the middleware 402 or the application 401 creates checkpoint data on the main memory 102 (S2303), and secures a file C on the flash memory system 103 as a checkpoint file. The RT time designates one day determined as described above, and since the checkpoint file is stored only on the flash memory system 103, the dirty is designated. Then, the middleware 402 or the application 401 writes the checkpoint data on the main memory 102 to the file C (S2304: YES, S2305).

When the next checkpoint cycle is reached (S2302: YES), the middleware 402 or the application 401 creates checkpoint data on the main memory 102 (S2303), and performs a new check on the flash memory system 103 as a checkpoint file. A point file D is secured. Then, the middleware 402 or the application 401 writes the checkpoint data on the main memory 102 to the file D, and then releases the file C (S2304: NO, S2306).

Thereafter, the middleware 402 or the application 401 executes the checkpoint by alternately using the file C and the file D until the execution of the program is completed.

In this example, the two files C and D are used to explicitly indicate the release timing of the files C and D to the flash memory system 103. However, the second checkpoint is performed using only one file C. Sometimes writing may be performed from the top of file C. Although the checkpoint data is created on the main memory 102 here, when the processing flows of FIGS. 29 and 30 are used together, the data in the region B of FIG. 30 may be used as the checkpoint data.

(5) Effects of this Embodiment As described above, according to the information processing system and the flash memory system of this embodiment, a plurality of physical blocks in the flash memory are assigned data attributes (RT time and type of clean or dirty). ), And on the other hand, a different refresh determination period, refresh determination threshold, and bad block determination threshold are managed for each attribute, and based on a different refresh determination period, refresh determination threshold, and bad block determination threshold for each attribute. Since the refresh determination process and the bad block determination process are executed for the physical block with the corresponding attribute, the refresh determination process and the bad block determination process are performed with an appropriate cycle and threshold for data that requires a long-term guarantee. Can run and also for a short time Since it is possible to prevent unnecessary refresh determination processing and bad block determination processing from being executed for data that can be guaranteed, the number of writable times in the entire system can be improved while maintaining data guarantee.

Specifically, for data that can be guaranteed for a short period of time or clean data, it is possible to use more physical blocks by setting a large bad block determination threshold and managing it. The number of possible times can be improved.

Even if it is determined to be a bad block in the bad block determination process, it can be used as a physical block for writing data of other attributes, so that the number of times the entire system can be written can be improved accordingly. .

In addition, when writing data, the physical block with the lowest error rate is selected from the physical blocks with the corresponding attribute and written, and the leveling of deterioration accompanying the writing (wear leveling) can be executed for each attribute. Therefore, the number of writable times in the entire system can be improved.

In the refresh determination process, when it is determined that it is necessary to execute the refresh process, data is read from or written to the physical block. However, according to the present embodiment, unnecessary refresh process can be reduced. Therefore, the overhead at this time can be reduced.

101 Host CPU
102 Main memory 103 Flash memory system 104 Storage system 111 Flash controller 113 Processor in flash controller 119 Flash memory 201 Logical address table 206 Physical address table 211 Threshold table 216 History table 220 Physical block management list group 221 Write destination selection list 223 Refresh destination Selection list 226 Refresh determination list 304

Attribute instruction command

305, 301

Write instruction command

306, 302

Read instruction command

307, 303 Invalidation instruction command 308 Capacity ratio instruction command

Claims

In a nonvolatile memory system comprising a nonvolatile memory and a nonvolatile memory controller,
The nonvolatile memory controller is
A plurality of physical blocks in the non-volatile memory are classified and managed for each data attribute, while a different refresh determination threshold or bad block determination threshold is managed for each attribute, and data is written to the physical block when writing A non-volatile memory system, wherein a physical block classified into the same attribute as that of the target data is selected as a write destination.
The nonvolatile memory controller is
When reading data from the physical block, the error rate of the physical block is calculated, and when the calculated error rate is equal to or higher than the bad block determination threshold associated with the attribute of the physical block classification destination, the read data Is written in another physical block classified into the same attribute as the physical block, and the physical block from which data is read out is classified and managed as another attribute with a higher bad block determination threshold. The nonvolatile memory system according to claim 1.
The nonvolatile memory controller is
3. The read-out physical block is determined to be a bad block when the calculated error rate is equal to or higher than a bad block determination threshold associated with all attributes of a classification destination. 4. Non-volatile memory system.
The nonvolatile memory controller is
When reading data from the physical block, the error rate of the physical block is calculated, and when the calculated error rate is equal to or higher than the refresh determination threshold associated with the attribute of the physical block classification destination, the read data is The nonvolatile memory system according to claim 1, wherein writing is performed to another physical block classified into the same attribute as the physical block.
The nonvolatile memory controller is
The calculated error rate is equal to or higher than a bad block determination threshold or a refresh determination threshold associated with the physical block classification destination attribute, and the read data is classified into the same attribute as the physical block. When writing to another physical block, the other physical block having the smallest error rate calculated when reading data from the other physical block is selected as the write destination. The nonvolatile memory system according to claim 2.
The attribute of the data includes information indicating the guaranteed time of the data,
The nonvolatile memory controller is
When there is a first data guarantee time and a second data guarantee time shorter than the first data guarantee time, the second data guarantee time is shorter than the first data guarantee time. The nonvolatile memory system according to claim 1, wherein the refresh determination threshold value or the bad block determination threshold value associated with the non-volatile memory is set to be higher and managed.
The attribute of the data includes information indicating the type of clean or dirty,
The nonvolatile memory controller is
The nonvolatile memory system according to claim 1, wherein the refresh determination threshold value or the defective block determination threshold value that is associated more cleanly than dirty is set and managed higher.
The nonvolatile memory controller is
Managing a different refresh determination cycle for each attribute,
2. The nonvolatile memory system according to claim 1, wherein data is read from the physical block at a different timing for each attribute based on the refresh determination period.
In an information processing system comprising a computer system and a nonvolatile memory system,
The computer system is
Issuing an attribute instruction indicating an attribute of data to the nonvolatile memory system;
The nonvolatile memory system includes:
Upon receipt of the attribute instruction, based on the received attribute instruction, a plurality of physical blocks in the non-volatile memory are classified and managed for each data attribute, while a different refresh determination threshold value or bad block for each attribute An information processing system that manages a determination threshold and selects a physical block that is classified into the same attribute as the attribute of data to be written when writing data to the physical block.