WO2015145620A1

WO2015145620A1 - Computer, and address conversion method

Info

Publication number: WO2015145620A1
Application number: PCT/JP2014/058566
Authority: WO
Inventors: 直也服部; 貴之今田; 俊臣森木
Original assignee: 株式会社日立製作所
Priority date: 2014-03-26
Filing date: 2014-03-26
Publication date: 2015-10-01

Abstract

[Problem] To provide a computer and an address conversion method capable of limiting deteriorations in memory performance. [Solution] A computer equipped with a physical memory and a physical CPU is characterized in that: the physical memory is provided with one or more virtual computers, and a hypervisor which operates a guest OS on each virtual computer; the physical CPU is provided with a duplexed paging virtualization support function which uses two tables to perform address conversion between a virtual memory allocated to a program operating on the guest OS, a guest physical memory allocated to the virtual computer, and the physical memory; and the hypervisor is provided with a program analysis unit which recognizes the program operating on the guest OS, a characteristic table which holds characteristics of the program operating on the guest OS, and a scheme switching unit which enables or disables the duplexed paging virtualization support function depending on the characteristics of the program operating on the guest OS.

Description

Computer and address conversion method

The present invention relates to a computer and an address conversion method, and is particularly suitable for application to a computer and an address conversion method for converting a virtual memory address used by a program on a virtual computer into a physical memory address.

In recent years, with the improvement of performance and expansion of functions of open servers equipped with x86 CPUs, hypervisors responsible for server virtualization functions are widely used as methods for effectively utilizing CPU cores installed in servers. The hypervisor is system software that creates a plurality of virtual machines using resources such as a CPU, a memory, and an IO device mounted on one physical server, and runs an OS and an application program on each virtual machine.

Server virtualization technology using hypervisors has improved safety and memory performance as the virtualization support function by the CPU has been strengthened, and it is not limited to servers, but also for integration of multiple functions and multi-tenants for embedded applications such as control devices. Used for containment purposes.

As the virtualization support function by the CPU, AMD-V of AMD and VT-x (Virtualization Technology) of Intel that appeared around 2005 are known. In these virtualization support functions, management data formats such as AMD-V VMCB (Virtual Machine Control Block) and Intel VMCS (Virtual Machine Control Structure) are defined.

In this management data format, the CPU directly executes instructions of an OS running on the virtual machine (hereinafter referred to as a guest OS) or a program running on the guest OS, while executing instructions designated by the hypervisor, When an event such as a timer interrupt occurs, an “intercept” is provided that interrupts the execution of the guest OS or program and calls the hypervisor.

The hypervisor uses intercepts to handle (emulate) only events that require hypervisor intervention, such as fault notification, and directly control the CPU to execute other instructions, thereby suppressing memory performance degradation caused by hypervisor operations. Like to do.

Around 2007, the virtualization support function was further strengthened, and memory virtualization performance was improved by AMD's NPT (Nested Page Table) and Intel's EPT (Extended Page Table). In memory virtualization, a virtual physical address starting from 0 (hereinafter referred to as a guest physical address) is assigned to the memory of each virtual machine, and a guest OS designed on the assumption that all the memory starting from address 0 can be used is virtualized. It is running on a computer.

By the way, as a memory address conversion function provided by a CPU before NPT and EPT appear, there is a paging function that converts a virtual address into a physical address exclusively by referring to a page table.

In this paging function, the hypervisor creates a guest page table (hereinafter referred to as GPT) for the guest OS to convert a virtual address into a guest physical address, and refers to this GPT to convert the virtual address into a host physical address (actual A shadow page table (hereinafter referred to as SPT) to be converted into (physical address) is created, and this SPT is passed to the CPU.

A paging function using SPT (hereinafter referred to as an SPT method) realizes memory address conversion corresponding to two-stage conversion of virtual address to guest physical address and guest physical address to host physical address. be able to. However, this SPT method needs to maintain consistency with the GPT, and when the guest OS updates the GPT, the hypervisor needs to update the SPT. At this time, the memory performance is degraded.

The decrease in memory performance in the SPT method becomes remarkable when a change in state such as program generation and termination or memory swap-out occurs on the guest OS. In order to solve this problem, the virtualization support function of AMD and Intel uses a memory address conversion table (NPT or EPT) that converts a guest physical address to a host physical address independently of GPT. (Hereinafter referred to as EPT method).

Since the EPT method does not need to maintain consistency with the GPT, the hypervisor does not need to perform table update processing even when the guest OS updates the GPT. Therefore, the problem of memory performance degradation in the SPT method is solved.

Patent Document 1 and Non-Patent Document 1 disclose EPT technology, and Patent Document 2 discloses SPT technology.

US Patent No. 7886126 US Pat. No. 7,734,893

However, the EPT method is not universal, and the memory performance is degraded by the process of referring to the NPT or EPT at the time of memory address conversion. The CPU is equipped with a high-speed, small-capacity TLB (Translation Lookaside Buffer) that stores part of the contents of the page table, NPT, and EPT. This TLB reduces memory performance degradation. However, for a program that operates a wide range of memories that do not fit in the TLB capacity, the NPT or EPT is read repeatedly. At this time, the memory performance is degraded.

That is, when the SPT method is used in which address conversion is performed using an SPT in which two tables are combined into one, it is necessary to update the SPT when the GPT is updated. On the other hand, if the EPT method that performs address conversion using NPT or EPT which is an address conversion table independent of GPT is adopted, memory performance may be deteriorated for a program that operates a memory exceeding the capacity of the TLB. is there.

The present invention has been made in consideration of the above points, and proposes a computer and an address conversion method capable of suppressing a decrease in memory performance during address conversion.

In order to solve such a problem, in the present invention, in a computer equipped with a physical memory and a physical CPU, the physical memory includes one or more virtual machines and a hypervisor that operates a guest OS on each virtual machine. The physical CPU uses two tables to perform address conversion between the virtual memory allocated to the program running on the guest OS, the guest physical memory allocated to the virtual machine, and the physical memory using two tables. The hypervisor has a support function, and the hypervisor corresponds to a program analysis unit that recognizes a program running on the guest OS, a characteristic table that holds characteristics of the program running on the guest OS, and a characteristic of the program that runs on the guest OS. A method switching unit for enabling or disabling the double paging virtualization support function. Characterized in that it obtain.

In order to solve such a problem, in the present invention, in the address conversion method for a computer equipped with a physical memory and a physical CPU, the physical memory operates one or more virtual machines and a guest OS on each virtual machine. The physical CPU performs address conversion between the virtual memory allocated to the program running on the guest OS, the guest physical memory allocated to the virtual machine, and the physical memory using two tables. A first step having a dual paging virtualization support function, in which the hypervisor recognizes a program running on the guest OS, a second step holding characteristics of the program running on the guest OS, and on the guest OS Enables the paging virtualization support function according to the characteristics of the program running on Characterized in that it comprises a third step of disabled.

According to the present invention, it is possible to suppress a decrease in memory performance during address conversion.

It is a hardware block diagram of the physical computer in 1st Embodiment. It is a software block diagram of the physical computer in 1st Embodiment. It is a conceptual diagram of a memory map. It is a logic block diagram of a characteristic measurement value table. It is a logic block diagram of a characteristic fixed selection table. It is a logic block diagram of a mode selection table. It is a logical block diagram of a guest page table. It is a logical block diagram of an extended page table. It is a logical block diagram of a shadow page table. It is a logical block diagram of a physical CPU setting management table. It is a processing flowchart which shows the whole process by a hypervisor. It is a processing flowchart which shows the initialization process by a hypervisor. It is a processing flow figure showing event processing by a hypervisor. It is a processing flowchart which shows a virtual machine starting process. It is a processing flowchart which shows a virtual PT address register change process. It is a processing flow figure showing page exception processing. It is a processing flowchart which shows EPT exception processing. It is a processing flowchart which shows a timer interruption process. It is a processing flowchart which shows a virtual CPU switching process. It is a processing flowchart which shows a console input process. It is a processing flow figure showing self-report reception processing. It is a processing flowchart which shows a characteristic judgment process. It is a software block diagram of the physical computer in 2nd Embodiment. It is a logic block diagram of the characteristic measurement value table | surface in 2nd Embodiment. It is a logic block diagram of the characteristic fixed selection table in 2nd Embodiment. It is a processing flow figure of virtual machine starting processing in a 2nd embodiment. It is a processing flowchart of the virtual PT address register change processing in the second embodiment. It is a processing flow figure of processing of virtual CPU change in a 2nd embodiment. It is a software block diagram of the physical computer in 3rd Embodiment. It is a logic block diagram of the characteristic measurement value table | surface in 3rd Embodiment. It is a logic block diagram of the characteristic fixed selection table in 3rd Embodiment. It is a processing flow figure of page exception processing in a 3rd embodiment. It is a processing flow figure of return processing in a 3rd embodiment. It is a processing flow figure of physical CPU setting change processing in a 3rd embodiment. It is a processing flow figure of the characteristic judgment processing in a 3rd embodiment. It is a hardware block diagram of the physical computer in 4th Embodiment. It is a software block diagram of the physical computer in 4th Embodiment. It is a conceptual diagram of the memory map in 4th Embodiment.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

(1) First Embodiment In the first embodiment, when a guest OS operates as system software on a virtual machine and a plurality of guest processes are operated, the characteristics of the program are determined for each guest process. A configuration for enabling or disabling the double paging virtualization support function according to the characteristics of the program obtained as a determination result will be described.
(1-1) Hardware Configuration FIG. 1 shows a hardware configuration of the physical computer 10 in the first embodiment. The physical computer 10 includes one or more physical CPUs 70. These physical CPUs 70 are connected to the ChipSet 81 and the physical memory 90 via an interconnect 83 such as QPI (Quick Path Interconnect) or SMI (Scalable Memory Interconnect).

The ChipSet 81 is connected to the IO device 80 via a bus 82 such as PCI express. The IO device 80 includes a NIC (Network Interface Card) connected to the LAN 84, a storage device 85 and an HBA (Host Bus Adapter) connected to the SAN (Storage Area Network) 86, a graphic controller connected to the console 95, and the like. Configured.

The physical CPU 70 accesses the physical memory 90 via the interconnect 83. Further, the physical CPU 70 accesses the IO device 80 via the ChipSet 81 and performs predetermined processing. Similarly, the IO device 80 accesses the physical memory 90 via the ChipSet 81.

The physical memory 90 loads the hypervisor 20 and distributes a part of the physical memory 90 to the virtual machines 30. The virtual machine 30 operates by loading the guest OS 40 and the guest process 60.

(1-2) Software Configuration FIG. 2 shows a software configuration of the physical computer 10 in the first embodiment. On the physical computer 10, the hypervisor 20 that creates the virtual computer 30 operates. On the virtual machine 30, a guest OS 40 operates as system software. The guest OS 40 operates the guest process 60. The guest process 60 is an execution unit of a program having an independent memory address on the guest OS 40.

The physical computer 10 includes a physical CPU 70 and a physical memory 90. The virtual computer 30 includes a virtual CPU 32 and a guest physical memory 31 allocated by the hypervisor 20. The guest process 60 operates using the virtual memory 61 allocated by the guest OS 40.

The guest OS 40 creates a guest page table (GPT) 41 that holds the correspondence between the virtual memory 61 and the guest physical memory 31, and stores the address of the GPT 41 in the virtual PT address register 33 that the virtual CPU 32 has. The guest OS 40 generally creates a plurality of guest processes 60 and creates a GPT 41 for each guest process 60.

The guest OS 40 stores the address of the GPT 41 corresponding to the guest process 60 to be executed in the virtual PT address register 33 every time the guest process 60 to be executed using the virtual CPU 32 is switched.

The physical CPU 70 includes an EPT enable register 71, an EPT address register 72, a PT address register 73, a performance monitor function 74, an intercept condition register 75, and a TLB 76.

The EPT validation register 71 controls the validity or invalidity of the double paging virtualization support function (generic name of the virtualization support function using NPT or EPT). The EPT address register 72 stores the position of the table (EPT 111) referred to by the double paging virtualization support function. The PT address register 73 stores the position of the table (GPT41 or SPT121) referred to by the paging function.

Also, the performance monitor function 74 simultaneously measures two types of events such as TLB misses that occur on the physical CPU 70. The intercept condition register 75 holds the condition for generating an intercept that interrupts the execution of the guest OS 40 and the guest process 60 and calls the hypervisor 20. The TLB 76 stores information indicating the correspondence between the address of the virtual memory 61 and the address of the physical memory 90.

Here, the performance monitor function 74 measures the number of times the guest OS 40 has executed the TLB purge command and the number of TLB misses. The TLB purge command is a command for notifying the virtual CPU 32 of the change after the guest OS 40 changes the GPT 41. By measuring the number of TLB purge instructions, the number of updates of the GPT 41 can be estimated.

The TLB miss means that information indicating the correspondence between the address of the virtual memory 61 and the address of the physical memory 90 is not stored in the TLB. By measuring the number of TLB misses, it is possible to estimate the number of times the physical CPU 70 has referred to the GPT 41, EPT 111, or SPT 121 (table reference number). The performance monitor function 74 includes, for example, two registers for selecting an event type and two registers for holding the number of events.

The hypervisor 20 includes a program analysis unit 100, an EPT control unit 110, an SPT control unit 120, a method switching unit 130, and a virtual CPU scheduler 140.

The program analysis unit 100 analyzes the characteristics of each program while recognizing program switching, and determines whether the dual paging virtualization support function is valid or invalid. The EPT control unit 110 controls the double paging virtualization support function. The SPT control unit 120 controls the paging function.

In addition, the method switching unit 130 enables the double paging virtualization support function to use the EPT control unit 110, and disables the double paging virtualization support function to use the SPT control unit 120. Switch. The virtual CPU scheduler 140 operates or stops the virtual CPU 32 using the physical CPU 70.

The program analysis unit 100 further includes a performance monitor control unit 101, a GPT switching recognition unit 109, a GPT-specific characteristic table 106, and a mode selection table 104.

The performance monitor control unit 101 controls the performance monitor function 74 included in the physical CPU 70. The GPT switching recognition unit 109 recognizes that the value held in the virtual PT address register 33 has changed. The GPT-specific characteristics table 106 holds program characteristics for each GPT 41 whose address is stored in the virtual PT address register 33. The mode selection table 104 holds, for each virtual computer 30, a mode that measures the characteristics of the program or a mode that does not measure.

The GPT-specific characteristic table 106 is a kind of characteristic table that holds the characteristics of the program. Here, the characteristic measurement value table 102 that holds the characteristics measured for each GPT 41 and the characteristics given from the administrator or the guest process 60 are shown. And a characteristic fixed selection table 103 to be held. The contents of the mode selection table 104 and the characteristic fixed selection table 103 are updated by the console 95. Note that the property fixed selection table 103 may be updated from the guest process 60.

The EPT 111 controlled by the EPT control unit 110 is created for each virtual machine 30 and holds the correspondence between the guest physical memory 31 and the physical memory 90. When the EPT enable register 71 is set to be effective, the physical CPU 70 stores two tables of the GPT 41 whose address is stored in the PT address register 73 and the EPT 111 whose address is stored in the EPT address register 72. With reference to the address, the address of the virtual memory 61 is converted into the address of the physical memory 90.

The SPT 121 controlled by the SPT control unit 120 is created for each guest process 60 and holds the correspondence between the virtual memory 61 and the physical memory 90. The physical CPU 70 refers to the SPT 121 whose address is stored in the PT address register 73 and converts the address of the virtual memory 61 into the address of the physical memory 90 when the EPT enable register 71 is set to invalid. When part or all of the GPT 41 is updated, the hypervisor 20 updates the corresponding part of the SPT 121.

The method switching unit 130 holds a physical CPU setting management table 131 such as VMCB or VMCS that controls a register of the physical CPU 70.

(1-3) Memory Configuration FIG. 3 shows a memory map of the physical memory 90 managed by the hypervisor 20. The hypervisor 20 allocates an area where the hypervisor 20 is arranged on the physical memory 90 and an area used by the virtual machine 30. Then, the hypervisor 20 includes the program analysis unit 100, the EPT control unit 110, the SPT control unit 120, the method switching unit 130, and the virtual CPU scheduler 140 described above in the area allocated to itself.

Here, the hypervisor 20 assigns addresses AD0 to AD1 to itself and arranges each module, dynamically assigns addresses AD2 to AD3 to the virtual machine 30, and assigns addresses AD4 to AD5 to another virtual machine 30. Assign dynamically. The guest OS 40 allocates an area where the guest OS 40 is arranged on each virtual machine 30 and an area used by the guest process 60.

(1-4) Table Configuration FIG. 4 shows a logical configuration of the characteristic measurement value table 102 that holds the characteristics measured for each GPT 41. The characteristic measurement value table 102 stores a virtual machine number 401, a GPT address 402, a TLB purge count 404, a TLB miss count 405, and an application method 407.

The virtual machine number 401 is an identification number for identifying the virtual machine 30. The GPT address 402 is an address of the GPT 41 stored in the virtual PT address register 33. The TLB purge count 404 is the number of times the guest OS 40 has executed a TLB purge command during the most recent operation.

The TLB miss count 405 is the number of TLB misses made by the physical CPU 70 during the most recent operation. The application method 407 is information indicating a method to which one of the SPT method and the EPT method is applied. Note that for the program in which the virtual machine number 401 and the GPT address 402 are not included in the characteristic measurement value table 102, the EPT method is adopted as the application method 407.

FIG. 5 shows a logical configuration of the characteristic fixed selection table 103 that holds characteristics given by the administrator or the guest process 60 itself. In the characteristic fixed selection table 103, an application method 407 is stored for each combination of the virtual machine number 401 and the GPT address 402. Note that for a program in which the virtual machine number 401 and the GPT address 402 are included in the characteristic fixed selection table 103, the application method 407 of the characteristic fixed selection table 103 is adopted regardless of the contents of the characteristic measurement value table 102.

FIG. 6 shows a logical configuration of the mode selection table 104 that holds, for each virtual machine 30, a mode that measures the characteristics of the program or a mode that does not measure. The mode selection table 104 stores a runtime measurement option 502 that indicates whether or not the program characteristics are measured for the virtual machine number 401.

Note that the characteristic measurement value table 102 is referred to or updated only for the virtual machine 30 whose execution time measurement option 502 is “Yes”. An EPT method is adopted as an application method 407 for a program on the virtual machine 30 whose execution time measurement option 502 is “no” and whose characteristic fixed selection table 103 does not include the virtual machine number 401 and the GPT address 402. Is done.

FIG. 7 shows a logical configuration of the GPT 41 that associates the address of the virtual memory 61 with the address of the guest physical memory 31. The GPT 41 stores a virtual address 701, a guest physical address 702, a page size 704, a global flag 705, and an access right 706.

The virtual address 701 is an address of the virtual memory 61. The guest physical address 702 is an address of the guest physical memory 31. The page size 704 is information indicating an address range. The global flag 705 is information indicating that data common to all the GPTs 41 on the virtual machine 30 is held. The access right 706 is information indicating whether reading / writing / execution is permitted with user authority or kernel authority.

Kernel authority is authority when the guest OS 40 operates, and is distinguished from user authority when the guest process 60 operates. In addition, the global flag is usually set for a memory area for executing the guest OS 40. When an access prohibited by the access right 706 is detected, the physical CPU 70 generates a page exception.

FIG. 8 shows a logical configuration of the EPT 111 that associates the address of the guest physical memory 31 with the address of the physical memory 90. The EPT 111 stores a guest physical address 702, a host physical address 703, a page size 704, and an access right 706.

The guest physical address 702 is an address of the guest physical memory 31. The host physical address 703 is an address of the physical memory 90. The page size 704 is information indicating an address range. The access right 706 is information indicating whether reading / writing / execution is permitted.

When the access prohibited by the access right 706 is detected, the physical CPU 70 generates an EPT exception. The hypervisor 20 prohibits all read / write / execution with the access right 706 for all the guest physical addresses 702 not assigned to the virtual machine 30 and prevents illegal memory access by the guest OS 40 using the EPT exception. be able to.

FIG. 9 shows a logical configuration of the SPT 121 that associates the address of the virtual memory 61 with the address of the physical memory 90. The SPT 121 has the same format as the GPT 41 and stores a host physical address 703, a page size 704, a global flag 705, and an access right 706 for each virtual address 701.

When the access prohibited by the access right 706 is detected, the physical CPU 70 generates a page exception. When the hypervisor 20 finds a guest physical address 702 that is not assigned to the virtual machine 30 in the GPT 41, the hypervisor 20 prohibits all reading / writing / execution with the access right 706 corresponding to the corresponding virtual address 701, and generates a page exception. By using this, unauthorized memory access by the guest OS 40 can be prevented.

FIG. 10 shows a logical configuration of the physical CPU setting management table 131 that controls the registers of the physical CPU 70. The physical CPU setting management table 131 stores a physical CPU number 901, an EPT validation flag 902, a PT address register operation intercept flag 903, a page exception intercept flag 904, a PT address 905, and an EPT address 906.

The physical CPU number 901 is an identification number for identifying the physical CPU 70. The EPT validation flag 902 is a flag for controlling the EPT validation register 71. The PT address register operation intercept flag 903 and the page exception intercept flag 904 are flags for controlling the intercept condition register 75. The PT address 905 is an address for controlling the PT address register 73. The EPT address 906 is an address for controlling the EPT address register 72.

When the PT address register operation intercept flag 903 is “1”, the physical CPU 70 interrupts the execution of the guest OS 40 and calls the hypervisor 20 when the guest OS 40 attempts to change the value of the virtual PT address register 33. On the other hand, when the PT address register operation intercept flag 903 is “0”, even if the guest OS 40 updates the virtual PT address register 33, the hypervisor 20 is not called and the update is completed.

Similarly, when the page exception intercept flag 904 is “1”, the physical CPU 70 calls the hypervisor 20 when a page exception occurs during execution of the guest OS 40 or the guest process 60.

Here, the physical CPU 70 assigned to the virtual machine 30 that does not measure the program characteristics operates with the setting in which the physical CPU number 901 is stored in the entry “3”. Specifically, the EPT enable flag 902 is set to “1” and the double paging virtualization support function is used, and the PT address register operation intercept flag 903 and the page exception intercept flag 904 are cleared.

On the other hand, the physical CPU 70 assigned to the virtual machine 30 that measures the program characteristics has an entry with the physical CPU number 901 of “1” or “2” depending on which of the SPT method and the EPT method is applied. Operates with stored settings.

When the EPT method is applied, it operates with the setting stored in the entry with the physical CPU number “2”, and intercepts the update of the virtual PT address register 33 while enabling the double paging virtualization support function. To recognize the switching of GPT41. When the SPT method is applied, it operates with the setting stored in the entry with the physical CPU number “1”, invalidates the double paging virtualization support function, intercepts the page exception, and is illegal by the guest OS 40 Prevent excessive memory access.

(1-5) Flowchart Hereinafter, processing executed by the hypervisor 20 will be described with reference to a flowchart.

FIG. 11 shows a processing flow of overall processing including event processing that is the center of the operation of the hypervisor 20. When the physical computer 10 is powered on, the hypervisor 20 executes a hypervisor initialization process to initialize itself (S1100). Next, the hypervisor 20 shifts the processing to a loop that waits for the occurrence of an event. In the loop, the hypervisor 20 determines whether an event has occurred (S1110).

When the hypervisor 20 obtains a negative result in the determination at step S1110, the process proceeds to step S1130. On the other hand, when the hypervisor 20 obtains a positive result in the determination at step S1110, it executes event processing (S1120).

Next, the hypervisor 20 determines whether or not there is an operating virtual machine 30 (S1130). If there is no operating virtual machine 30, the process returns to step S1110 to wait for the occurrence of an event, and there is an operating virtual machine 30. If so, the program on the virtual machine 30 is executed (S1140). Thereafter, the hypervisor 20 returns to the loop.

FIG. 12 shows a processing flow of the hypervisor initialization process executed in step S1100 of FIG. The hypervisor 20 stores zero or an initial value stored in a file or the like in the characteristic fixed selection table 103, and initializes the characteristic fixed selection table 103 (S2100). Further, the hypervisor 20 stores zero or an initial value stored in a file or the like in the mode selection table 104, and initializes the mode selection table 104 (S2110).

Next, the hypervisor 20 changes the setting of the performance monitor function 74. Specifically, the hypervisor 20 selects the number of TLB misses as the first event counted by the performance monitor function 74 (S2120), and selects the number of TLB purges as the second event (S2130). These processes are realized by using event selection means provided by the performance monitor function 74.

Finally, the hypervisor 20 executes other initialization processing (S2140), and ends this hypervisor initialization processing.

FIG. 13 shows a process flow of the event process executed in step S1120 of FIG. The hypervisor 20 determines whether or not the generated event is an instruction to start the virtual machine 30 (S1200). If the hypervisor 20 obtains an affirmative result in this determination, it executes a virtual machine activation process (S1205). Note that the activation instruction for the virtual machine 30 may be generated in response to an input from the console 95, or may be automatically generated after the hypervisor initialization process is completed.

When the hypervisor 20 obtains a negative result in the determination at step S1200, the hypervisor 20 determines whether the generated event is an execution of a virtual PT address register change instruction by the guest OS 40 (S1210). If the hypervisor 20 obtains a positive result in this determination, it executes virtual PT address register change processing (S1215), and if it obtains a negative result, it proceeds to step S1220.

When the hypervisor 20 obtains a negative result in the determination at step S1210, it determines whether the event that has occurred is a page exception (S1220). If the hypervisor 20 obtains a positive result in this determination, it executes page exception processing (S1225), and if it obtains a negative result, it proceeds to step S1230.

When the hypervisor 20 obtains a negative result in the determination at step S1220, it determines whether the event that has occurred is an EPT exception (S1230). If the hypervisor 20 obtains a positive result in this determination, it executes EPT exception processing (S1235), and if it obtains a negative result, it proceeds to step S1240.

When the hypervisor 20 obtains a negative result in the determination at step S1230, it determines whether the event that has occurred is an input of an update instruction from the console 95 (S1240). If the hypervisor obtains a positive result in this determination, it executes console input processing (S1245), and if it obtains a negative result, it proceeds to step S1250.

When the hypervisor 20 obtains a negative result in the determination at step S1240, it determines whether the event that has occurred is an execution of a command for self-declaring characteristics to the hypervisor 20 from a program on the virtual machine 30 (S1250). . If the hypervisor 20 obtains a positive result in this determination, it executes self-report reception processing (S1255), and if it obtains a negative result, it proceeds to step S1260.

For the self-declaration of characteristics, an arbitrary instruction for calling the hypervisor 20 such as a VMMCALL instruction of an AMD CPU or a VMMCALL instruction of an Intel CPU is used.

When the hypervisor 20 obtains a negative result in the determination at step S1250, it determines whether or not the event that has occurred is a timer interrupt (S1260). If the hypervisor 20 obtains a positive result in this determination, it executes timer interrupt processing (S1265), and if it obtains a negative result, it executes other processing (S1270).

Finally, the hypervisor 20 executes a next process on the virtual machine 30 or executes a return process for resuming the process before the event detection (S1280), and ends this event process.

FIG. 14 shows a processing flow of the virtual machine activation process executed in step S1205 of FIG. The hypervisor 20 stores zero in the characteristic measurement value table 102 to clear the characteristic measurement value table 102 (S1300), and activates the double paging virtualization support function as the setting of the physical CPU 70 allocated to the virtual machine 30. The page exception intercept is invalidated (S1310).

According to the setting in step S1310, the program on the virtual machine 30 starts operating in a state where the EPT method is applied. Next, the hypervisor 20 refers to the mode selection table 104, confirms the runtime measurement option 502 of the virtual machine 30, and determines whether or not the virtual machine 30 is a virtual machine to be measured (S1320).

If the virtual machine 30 is not a measurement target, the hypervisor 20 invalidates the intercept when the PT address register 73 is changed (S1330), and if it is a measurement target, the hypervisor 20 enables the intercept when the PT address register is changed. (S1340), the virtual machine activation process is terminated. The initial value set here is transmitted to the physical CPU 70 through the physical CPU setting management table 131.

FIG. 15 shows a process flow of the virtual PT address register change process executed in step S1215 of FIG. The hypervisor 20 refers to the mode selection table 104, confirms the runtime measurement option 502 of the virtual machine 30, and determines whether the virtual machine 30 is a virtual machine to be measured (S1400).

The hypervisor 20 acquires the characteristic data of the TLB miss count and the TLB purge instruction execution count from the performance monitor function 74 only when the virtual computer 30 is a measurement target, and is registered in the virtual PT address register 33 before the change. The acquired characteristic data is stored in the TLB purge number 404 and the TLB miss number 405 of the characteristic measurement value table 102 in association with the GPT 41, and the characteristic of the guest process 60 is updated (S1405).

Next, the hypervisor 20 compares the value obtained by multiplying the TLB miss count 405 and the table reference unit price of the double paging virtualization support function with the value obtained by multiplying the TLB purge count 404 and the GPT update unit price. The SPT method is stored as the application method 407, and if the latter is larger, the EPT method is stored as the application method 407.

Note that the table reference unit price and the GPT update unit price of the dual paging virtualization support function are assumed to be held by the hypervisor 20 by a method such as measuring in advance. Further, the hypervisor 20 clears the number of TLB misses and the number of executions of the TLB purge instruction measured by the performance monitoring function 74 to the characteristics of the guest process 60 that operates using the GPT 41 registered in the virtual PT address register 33 after the change. Prepare for measurement (S1410).

The hypervisor 20 recognizes the change of the virtual PT address register 33 as program switching and determines a method to be applied. Therefore, the hypervisor 20 refers to the characteristic measurement value table 102 and determines the characteristic of the guest process 60 associated with the GPT 41 whose address is held by the virtual PT address register 33 after the change (S1420).

Next, the hypervisor 20 determines whether or not the application method 407 is the SPT method (S1430). When the application method 407 is the SPT method, the hypervisor 20 changes the setting of the physical CPU 70 for the SPT method in the following procedure.

The hypervisor 20 invalidates the double paging virtualization support function of the physical CPU 70 and enables page exception interception (S1435). Next, the hypervisor 20 searches for the SPT 121 corresponding to the GPT 41 registered in the virtual PT address register 33 after the change (S1440).

When the hypervisor 20 finds the corresponding SPT 121 (S1445: Yes), the hypervisor 20 registers the found SPT 121 in the PT address register 73 of the physical CPU 70 (S1455). On the other hand, when the corresponding SPT 121 is not found (S1445: No), the hypervisor 20 refers to the GPT 41 and the EPT 111 and creates the SPT 121 that associates the virtual address 701 with the host physical address 703 (S1450). Stored in association with the address.

At this time, in order to detect the update of the host physical address 703 where the referenced GPT 41 is arranged, the hypervisor 20 has access rights to write to the host physical address 703 for all the EPTs 111 and SPTs 121 held by the hypervisor 20. It is prohibited at 706. The hypervisor 20 registers the created address of the SPT 121 in the PT address register 73 of the physical CPU 70 (S1455), and ends this virtual PT address register change process.

Returning to step S1430, when the application method 407 is the EPT method, the hypervisor 20 changes the setting of the physical CPU 70 for the EPT method in the following procedure.

The hypervisor 20 enables the double paging virtualization support function of the physical CPU 70 and disables the page exception intercept (S1470). Next, the hypervisor 20 registers the address of the EPT 111 for the virtual computer 30 in the EPT address register 72 of the physical CPU 70, and registers the address of the GPT 41 held in the virtual PT address register 33 after the change in the PT address register 73 of the physical CPU 70. In step S1480, the virtual PT address register changing process is terminated.

FIG. 16 shows a processing flow of page exception processing executed in step S1225 of FIG. The hypervisor 20 refers to the GPT 41 in which the virtual PT address register 33 holds the address, and determines whether the page exception detected by the physical CPU 70 is an access prohibited by the GPT 41 (S1500).

When the access is prohibited by the GPT 41, the hypervisor 20 transmits a page exception to the guest OS 40 (S1550), and ends this page exception processing. On the other hand, if the access is not prohibited by the GPT 41, the hypervisor 20 determines whether this page exception is an update of the GPT 41 (S1510).

When updating the GPT 41, the hypervisor 20 updates the SPT 121 in accordance with the updated GPT 41 (S1530). When not updating the GPT 41, the hypervisor emulates the operation when the unallocated memory is operated on the virtual machine 30. (S1540), this page exception processing is terminated. As a method for determining whether or not the page exception is an update of the GPT 41, the GPT 41 associated with each of all the SPTs 121 may be examined one by one, or another method may be used.

FIG. 17 shows a processing flow of EPT exception processing executed in step S1235 of FIG. The hypervisor 20 determines whether or not the EPT exception (EPT Violation) is an update of the GPT 41 (S1510).

When the EPT exception is an update of the GPT 41, the hypervisor 20 updates the SPT 121 in accordance with the updated GPT 41 (S1530). When the EPT exception is not an update of the GPT 41, when an unallocated memory is operated on the virtual machine 30 Is emulated (S1540), and this EPT exception process is terminated.

FIG. 18 shows a process flow of the timer interrupt process executed in step S1265 of FIG. The hypervisor 20 determines whether or not this timer interrupt is an interrupt that occurs because the time slice used when the physical CPU 70 is allocated to the virtual CPU 32 in a time-sharing manner (S1700).

When the hypervisor 20 uses up the time slice, the hypervisor 20 selects the virtual CPU 32 to which the next time slice is assigned (S1710), and the program running on the physical CPU 70 is also switched. S1720), the timer interrupt process is terminated. On the other hand, when the time slice is not used up, the hypervisor 20 performs other processing (S1730) and ends the timer interrupt processing.

FIG. 19 shows a process flow of the virtual CPU switching process executed in step S1720 of FIG. The hypervisor 20 refers to the mode selection table 104 and determines whether or not the current virtual CPU 32 before switching belongs to the virtual computer 30 to be measured (S1800).

When the virtual CPU 32 before switching belongs to the virtual machine 30 to be measured, the hypervisor 20 acquires the characteristic data of the TLB miss count and the TLB purge instruction execution count from the performance monitor function 74, and the virtual PT address register 33 The acquired characteristic data is stored in the TLB purge number 404 and the TLB miss number 405 of the characteristic measurement value table 102 in association with the GPT 41 registered in the table, and the characteristic of the guest process 60 is updated (S1805).

Next, the hypervisor 20 refers to the mode selection table 104 and determines whether or not the virtual CPU 32 after switching belongs to the virtual machine 30 to be measured (S1810). When the virtual CPU 32 after switching belongs to the virtual machine 30 to be measured, the hypervisor 20 clears the TLB miss count and the TLB purge command execution count measured by the performance monitor function 74 to the next measurement. And intercepting PT address register operation (S1815).

On the other hand, when the virtual CPU 32 after switching belongs to the virtual computer 30 that is not the measurement target, the hypervisor 20 does not need to monitor the change of the GPT 41, and therefore invalidates the intercept of the PT address register operation (S1820).

Next, the hypervisor 20 refers to the characteristic measurement value table 102 and determines the characteristic of the guest process 60 associated with the GPT 41 in which the virtual PT address register 33 of the virtual CPU 32 after switching holds the address (S1830).

When the application method 407 is the SPT method, the hypervisor 20 changes the setting of the physical CPU 70 for the SPT method according to the following procedure. The hypervisor 20 invalidates the double paging virtualization support function of the physical CPU 70 and validates the page exception intercept (S1435). Next, the hypervisor 20 searches the SPT 121 corresponding to the GPT 41 registered in the virtual PT address register 33 of the virtual CPU 32 after switching (S1860).

Thereafter, the hypervisor 20 executes the same processing as steps S1445, S1450, and S1455 of FIG. 15 and registers the SPT 121 in the PT address register 73 of the physical CPU 70. When the application method 407 is the EPT method, the hypervisor 20 executes the same processing as steps S1470 and S1480 in FIG. 15 to change the setting of the physical CPU 70 to the EPT method.

FIG. 20 shows a processing flow of console input processing executed in step S1245 of FIG. The hypervisor 20 determines whether the update instruction received from the console 95 is an instruction for the mode selection table 104 or an instruction for the fixed characteristic selection table 103 (S2200).

When the hypervisor 20 is an instruction for the mode selection table 104, the hypervisor 20 updates the mode selection table 104 as instructed (S2220). On the other hand, when the instruction is for the characteristic fixed selection table 103, the hypervisor 20 updates the characteristic fixed selection table 103 as instructed (S2210). Although the mode selection table 104 and the characteristic fixed selection table 103 exist on the physical memory 90, the contents of the updated table may be stored in a file.

FIG. 21 shows a process flow of the self-report reception process executed in step S1255 of FIG. The hypervisor 20 updates the characteristic fixed selection table 103 in accordance with the contents reported from the guest process 60 (S2210). The characteristic fixed selection table 103 exists on the physical memory 90, but the updated table contents may be stored in a file.

FIG. 22 shows a process flow of the characteristic determination process executed in step S1420 in FIG. 15 and step S1830 in FIG. The hypervisor 20 refers to the characteristic fixed selection table 103 and determines whether or not information related to the currently running guest process 60 is stored (S2300).

When information is stored in the fixed characteristic selection table 103, the hypervisor 20 determines that the application method 407 stored in the fixed characteristic selection table 103 is valid, and the SPT method or the EPT method stored as the applicable method 407. Any one of these methods is adopted (S2310).

On the other hand, when information is not stored in the characteristic fixed selection table 103, the hypervisor 20 refers to the mode selection table 104 and determines whether or not the virtual computer 30 is a measurement target (S2320). When the virtual computer 30 is not a measurement target, the hypervisor 20 determines that the EPT method is appropriate and adopts the EPT method (S2350).

On the other hand, if the virtual computer 30 is a measurement target, the hypervisor 20 refers to the characteristic measurement value table 102 and determines whether or not information related to the currently running guest process 60 is stored (S2330). If the information is not stored, the hypervisor 20 determines that the EPT method is appropriate and adopts the EPT method (S2350).

On the other hand, when information is stored, the hypervisor 20 determines that the application method 407 stored in the characteristic measurement value table 102 is appropriate, and uses the SPT method or the EPT method stored as the application method 407. Either method is adopted (S2340).

(1-6) Effects According to First Embodiment As described above, according to the physical computer 10 in the first embodiment, the guest process 60 operated by the guest OS 40 on the virtual computer 30 is distinguished by the GPT 41, Since the characteristics of the guest process 60 are determined by the number of TLB misses and the number of TLB purges, an SPT method for disabling the double paging virtualization support function is adopted for the guest process 60 having a large number of TLB misses. It is possible to prevent a decrease in memory performance due to a table reference, while adopting an EPT method that enables the double paging virtualization support function for the guest process 60 having a large number of TLB purges, the GPT 41 and the SPT 121 It is possible to prevent the memory performance from being lowered due to the process of synchronizing the.

(2) Second Embodiment In the second embodiment, for each virtual CPU assigned to a virtual machine when a guest OS operates as system software on the virtual machine and operates a plurality of guest processes. A configuration for determining the characteristics of a program and enabling or disabling the double paging virtualization support function according to the characteristics of the program obtained as a determination result will be described.

In addition, about the structure similar to 1st Embodiment, the same code | symbol is attached | subjected, the description is abbreviate | omitted, and a different structure is demonstrated.

(2-1) Software Configuration FIG. 23 shows a software configuration of the physical computer 10 in the second embodiment. On the virtual machine 30, a guest OS 40 operates as system software. The guest OS 40 operates one or more guest processes 60 for each virtual CPU 32. Therefore, the guest OS 40 holds a GPT 41 for each virtual CPU 32.

The program analysis unit 100 includes a virtual CPU-specific characteristic table 107 that stores program characteristics for each virtual CPU 32. The characteristic table 107 for each virtual CPU is a kind of characteristic table for holding the characteristics of the program. Here, the characteristic measurement value table 112 for holding the characteristics measured for each virtual CPU 32 and the administrator or the guest process 60 itself are given. And a characteristic fixed selection table 113 that holds the characteristics.

(2-2) Table Configuration FIG. 24 shows a logical configuration of the characteristic measurement value table 112 that holds the characteristics measured for each virtual CPU 32. The characteristic measurement value table 112 stores a virtual computer number 401, a virtual CPU number 408 for identifying the virtual CPU 32, a TLB purge count 404, a TLB miss count 405, and an application method 407.

FIG. 25 shows a logical configuration of the characteristic fixed selection table 113 that holds the characteristics given by the administrator or the guest process 60 itself. In the characteristic fixed selection table 113, an application method 407 is stored for each combination of the virtual machine number 401 and the virtual CPU number 408.

In the second embodiment, the mode selection table 104, GPT41, EPT111, SPT121, and physical CPU setting management table 131 are the mode selection table 104 (FIG. 6), GPT41 (FIG. 7), and EPT111 in the first embodiment. (FIG. 8), SPT 121 (FIG. 9), and physical CPU setting management table 131 (FIG. 10) are the same, and the description thereof is omitted here.

(2-3) Flowchart Hereinafter, processing executed by the hypervisor 20 will be described with reference to a flowchart. In the second embodiment, the overall process, initialization process, and event process are the same as the overall process (FIG. 11), initialization process (FIG. 12), and event process (FIG. 13) in the first embodiment. Since it exists, description here is abbreviate | omitted.

FIG. 26 shows a processing flow of the virtual machine activation process executed in step S1205 of FIG. The hypervisor 20 stores zero in the characteristic measurement value table 102 to clear the characteristic measurement value table 102 (S1300), and activates the double paging virtualization support function as the setting of the physical CPU 70 allocated to the virtual machine 30. The page exception intercept is invalidated (S1310).

According to the setting in step S1310, the program on the virtual machine 30 starts operating in a state where the EPT method is applied. Next, the hypervisor 20 validates the intercept when the PT address register is changed (S1340), and ends this virtual machine activation process. The initial value set here is transmitted to the physical CPU 70 through the physical CPU setting management table 131.

FIG. 27 shows a processing flow of the virtual PT address register changing process executed in step S1215 of FIG. The hypervisor 20 searches for the SPT 121 corresponding to the GPT 41 registered in the virtual PT address register 33 after the change (S1440).

When the hypervisor 20 finds the corresponding SPT 121 (S1445: YES), the hypervisor 20 registers the found SPT 121 in the PT address register 73 of the physical CPU 70 (S1455).

On the other hand, when the corresponding SPT 121 is not found (S1445: No), the hypervisor 20 refers to the GPT 41 and the EPT 111 and creates the SPT 121 that associates the virtual address 701 with the host physical address 703 (S1450). Stored in association with the address.

At this time, the hypervisor 20 detects the update of the host physical address 703 where the referenced GPT 41 is arranged, and writes the access right 706 to the host physical address 703 for all the EPTs 111 and SPTs 121 held by the hypervisor 20. Is prohibited.

Finally, the hypervisor 20 registers the created address of the SPT 121 in the PT address register 73 of the physical CPU 70 (S1455), and ends this virtual PT address register change process.

In the second embodiment, page exception processing, EPT exception processing, and timer interrupt processing are the same as those in the first embodiment (FIG. 16), EPT exception processing (FIG. 17), and timer interrupt processing (FIG. 18). ), The description here is omitted. As for timer interrupt processing (FIG. 18), in the second embodiment, the guest process 60 running on the physical CPU 70 is switched only when the time slice is used up, and the hypervisor 20 recognizes this and recognizes the EPT method or The application of the SPT method is determined.

FIG. 28 shows a process flow of the virtual CPU switching process executed in step S1720 of FIG. Since the processes in steps S1800, S1805, and S1810 are the same as the processes in steps S1800, S1805, and S1810 of the virtual CPU switching process (FIG. 19) in the first embodiment, a description thereof is omitted here.

The hypervisor 20 clears the TLB miss count and the TLB purge command execution count measured by the performance monitor function 74 to zero only when the switched virtual CPU 32 belongs to the virtual machine 30 to be measured. (S1825).

Next, the hypervisor 20 refers to the characteristic measurement value table 112 and determines the characteristic of the guest process 60 associated with the virtual CPU 32 after switching (S1830).

When the application method 407 is the SPT method, the hypervisor 20 changes the setting of the physical CPU 70 for the SPT method according to the following procedure. Specifically, the hypervisor 20 invalidates the double paging virtualization support function of the physical CPU 70, validates the page exception intercept, and validates the intercept for the operation of the virtual PT address register 33 (S1850).

On the other hand, when the application method 407 is the EPT method, the hypervisor 20 changes the setting of the physical CPU 70 for the EPT method according to the following procedure. Specifically, the hypervisor 20 enables the double paging virtualization support function of the physical CPU 70, invalidates the page exception intercept, and invalidates the intercept for the operation of the virtual PT address register 33 (S1855).

The processes of steps S1860, S1445, S1450, S1455, and S1480 are the same as the processes of steps S1860, S1445, S1450, S1455, and S1480 of the virtual CPU switching process (FIG. 19) in the first embodiment. Description is omitted.

In the second embodiment, the console input process, the self-report reception process and the characteristic determination process are the console input process (FIG. 20), the self-report reception process (FIG. 21) and the characteristic determination process in the first embodiment. Since it is the same as (FIG. 22), description here is abbreviate | omitted.

(2-4) Effects According to Second Embodiment As described above, according to the physical computer 10 in the second embodiment, a set of guest processes 60 operated by the guest OS 40 on the virtual computer 30 is represented by the virtual CPU 32. Since the distinction is made and the characteristics of the guest process 60 are determined by the number of TLB misses and the number of TLB purges, the SPT for disabling the double paging virtualization support function for programs on the virtual CPU 32 with a large number of TLB misses The system can be used to prevent the memory performance from degrading due to the table reference. On the other hand, the program on the virtual CPU 32 with a large number of TLB purges adopts the EPT system that enables the double paging virtualization support function. Accordingly, it is possible to prevent a decrease in memory performance due to the process of synchronizing the GPT 41 and the SP 121.

(3) Third Embodiment In the third embodiment, a guest OS operates as system software on a virtual machine, and a kernel program that operates with kernel authority is operated in addition to a plurality of guest processes. A configuration for determining the characteristics of a program for each privilege level and enabling or disabling the double paging virtualization support function according to the characteristics of the program obtained as a determination result will be described.

(3-1) Software Configuration FIG. 29 shows a software configuration of the physical computer 10 in the third embodiment. On the virtual machine 30, a guest OS 40 operates as system software. In addition to the guest process 60, the guest OS 40 operates a kernel program 42 that operates with the same authority as the guest OS 40.

The kernel program 42 corresponds to a program closely associated with hardware such as control of the IO device 80, for example. The memory used by the kernel program 42 stores address conversion information common to all the GPTs 41 as with the memory used by the guest OS 40.

The virtual CPU scheduler 140 includes a privilege level history 141 that stores the last observed privilege level for each virtual CPU 32. The privilege level is a classification of user authority or kernel authority.

The program analysis unit 100 includes a privilege level-specific characteristic table 108 that holds the characteristics of a program for each privilege level of the virtual CPU 32. The privilege level-specific characteristic table 108 is a kind of characteristic table that holds the characteristics of a program. Here, a characteristic measurement value table 122 that holds characteristics of a program that operates with kernel authority measured for each virtual machine 30, and an administrator Or it is comprised from the characteristic fixed selection table 123 holding the characteristic given from guest process 60 itself.

(3-2) Table Configuration FIG. 30 shows a logical configuration of the characteristic measurement value table 122 that holds the characteristics of programs operating with kernel authority measured for each virtual machine 30. The characteristic measurement value table 122 stores a virtual computer number 401, a TLB purge count 404, a TLB miss count 405, and an application method 407.

FIG. 31 shows a logical configuration of the property fixed selection table 133 that retains properties given by the administrator or the guest process 60 itself. In the characteristic fixed selection table 133, an application method 407 is stored for each virtual machine number 401.

In the third embodiment, the mode selection table 104, GPT41, EPT111, SPT121, and physical CPU setting management table 131 are the mode selection table 104 (FIG. 6), GPT41 (FIG. 7), and EPT111 in the first embodiment. (FIG. 8), SPT 121 (FIG. 9), and physical CPU setting management table 131 (FIG. 10) are the same, and the description thereof is omitted here.

As for the SPT 121, in the third embodiment, since the SPT method is applied only to programs operating with kernel authority, the access right 706 of the virtual address 701 in which the global flag 705 of the GPT 41 is 0 is read / written / executed. Impossible is stored. As for the physical CPU setting management table 131, the PT address register operation intercept flag 903 is always 0 in the third embodiment.

(3-3) Flowchart Hereinafter, processing executed by the hypervisor 20 will be described with reference to a flowchart. In the third embodiment, the overall processing, initialization processing, and event processing are the same as the overall processing (FIG. 11), initialization processing (FIG. 12), and event processing (FIG. 13) in the first embodiment. Since it exists, description here is abbreviate | omitted. The virtual machine startup process is the same as the virtual machine startup process (FIG. 26) in the second embodiment, and a description thereof will be omitted here. In the third embodiment, since the PT address register operation intercept flag 903 is always 0, the virtual PT address register change process (FIG. 15) is not executed.

FIG. 32 shows a processing flow of page exception processing executed in step S1225 of FIG. The hypervisor 20 refers to the GPT 41 in which the virtual PT address register 33 holds the address, and determines whether the page exception detected by the physical CPU 70 is an access prohibited by the GP 41 (S1500).

When the hypervisor 20 is updating the GPT 41, the hypervisor 20 updates the SPT 121 in accordance with the updated GPT 41 (S1530), and ends this page exception processing. On the other hand, if the GPT 41 is not updated, the hypervisor 20 compares the contents of the current privilege level of the virtual CPU 32 and the privilege level history 141 to determine whether the kernel authority is changed to the user authority (S1560).

The hypervisor 20 ends the page exception process when a change is detected. On the other hand, when no change is detected, the hypervisor 20 emulates an operation when a memory unallocated to the virtual machine 30 is operated (S1540), and ends the page exception processing.

In the third embodiment, the EPT exception processing, timer interrupt processing, and virtual CPU switching processing are the same as the EPT exception processing (FIG. 17), timer interrupt processing (FIG. 18), and virtual CPU switching processing (FIG. 18) in the first embodiment. Since it is the same as FIG. 19), the description here is omitted.

In the virtual CPU switching process according to the third embodiment, in the process of step S1815, the TLB miss count and the TLB purge command execution count measured by the performance monitor function 74 are cleared to zero to prepare for the next measurement. This is different from the first embodiment.

In the third embodiment, the console input process and the self-report receiving process are the same as the console input process (FIG. 20) and the self-report receiving process (FIG. 21) in the first embodiment. Description is omitted.

FIG. 33 shows a processing flow of the return processing executed in step S1280 of FIG. The hypervisor 20 compares the current privilege level of the virtual CPU 32 with the contents of the privilege level history 141 (S1900).

The hypervisor 20 recognizes program switching only when the two do not match (S1910), and changes the setting of the physical CPU 70 in accordance with the change in privilege level (S1920). Thereafter, the hypervisor 20 records the current privilege level in the privilege level history 141 (S1930), and ends the return process.

FIG. 34 shows a processing flow of setting change processing of the physical CPU corresponding to the privilege level executed in step S1920 of FIG. The hypervisor 20 refers to the mode selection table 104 to determine whether or not the virtual CPU 32 belongs to the measurement target virtual computer 30 (S2000), and only when it belongs to the measurement target virtual computer 30. Then, it is determined whether the current privilege level is kernel authority (S2005).

If the current privilege level is not the kernel authority (S2005: NO), the hypervisor 20 acquires the characteristic data of the TLB miss count and the TLB purge instruction execution count when operating with the kernel authority from the performance monitor function 74. Then, the characteristic is stored in the TLB purge count 404 and the TLB miss count 405 of the characteristic measurement value table 102 in association with the virtual machine number 401 to update the program characteristics (S2010).

Further, the hypervisor 20 compares the value obtained by multiplying the TLB miss count 405 and the table reference unit price of the double paging virtualization support function with the value obtained by multiplying the TLB purge count 404 and the GPT update unit price. The SPT method is stored in the application method 407, and if the latter is larger, the EPT method is stored in the application method 407.

On the other hand, if the current privilege level is the kernel authority (S2005: YES), the hypervisor 20 clears the TLB miss count and the TLB purge command execution count measured by the performance monitor function 74 to the next measurement. Prepare (S2020).

Next, the hypervisor 20 refers to the characteristic measurement value table 102 and determines the characteristic of the guest program associated with the current privilege level (S2030).

When the application method 407 is the SPT method, the hypervisor 20 changes the setting of the physical CPU 70 for the SPT method according to the following procedure. Specifically, the hypervisor 20 invalidates the double paging virtualization support function of the physical CPU 70 and validates the page exception intercept (S1435). Here, since the SPT method is applied only to the kernel program 42, the hypervisor searches for the SPT 121 for the kernel program 42 (S2060). Since the process after step S1445 is the same as the process after step S1445 of FIG. 15, description here is abbreviate | omitted.

On the other hand, when the application method 407 is the EPT method, the hypervisor 20 executes processing similar to steps S1470 and S1480 in FIG. 15 to change the setting of the physical CPU 70 for the EPT method.

FIG. 35 shows a process flow of the characteristic determination process executed in step S1830 of FIG. The hypervisor 20 refers to the current privilege level and determines whether or not it is operating with kernel authority (S2360). If the hypervisor 20 is not operating with kernel authority, the hypervisor 20 determines that the EPT method is appropriate and adopts the EPT method (S2350). On the other hand, when the hypervisor 20 operates with the kernel authority, the hypervisor 20 executes a process similar to the characteristic determination process (FIG. 22) in the first embodiment.

(3-4) Effects of the Third Embodiment As described above, according to the physical computer 10 of the third embodiment, the kernel program 42 that is operated by the guest OS 40 on the virtual computer 30 operates with user authority. Distinguishing from the guest process 60, the characteristic of the kernel program 42 is determined by the number of TLB misses and the number of TLB purges. Therefore, the dual paging virtualization support function is disabled for the kernel program 42 having a large number of TLB misses. By adopting the SPT method, it is possible to prevent a decrease in memory performance due to table reference, while for the kernel program 42 having a large number of TLB purges, an EPT method for enabling the double paging virtualization support function is used. Adopted to prevent degradation of memory performance due to the process of synchronizing GPT41 and SP121 can do.

(4) Fourth Embodiment In the fourth embodiment, a guest OS having a function of creating an Lv2 virtual machine as system software on the virtual machine operates, and on the Lv2 virtual machine created by the guest OS, When the Lv2 guest OS that controls the Lv2 virtual machine is running and multiple guest processes are running, program characteristics are determined for each guest process, and double paging is performed according to the program characteristics obtained as a result of the determination. A configuration for enabling or disabling the virtualization support function will be described.

(4-1) Hardware Configuration FIG. 36 shows the hardware configuration of the physical computer 10 in the fourth embodiment.
The physical memory 90 loads the hypervisor 20 and distributes a part of the physical memory 90 to the virtual machines 30. The virtual machine 30 operates by loading the guest OS 40. The guest OS 40 distributes a part of the physical memory 90 to the Lv2 virtual computer 45. The Lv2 virtual computer 45 operates by loading the Lv2 guest OS 40 and the guest process 60.

(4-2) Software Configuration FIG. 37 shows the software configuration of the physical computer 10 in the fourth embodiment. On the physical computer 10, the hypervisor 20 that creates the virtual computer 30 operates. On the virtual machine 30, a guest OS 40 operates as system software. The guest OS 40 creates an Lv2 virtual computer 35 and operates the Lv2 guest OS 50 on each Lv2 virtual computer 45. The Lv2 guest OS 50 further operates the guest process 60.

The physical computer 10 includes a physical CPU 70 and a physical memory 90. Similarly, the virtual machine 30 includes a virtual CPU 32 and a guest physical memory 31 allocated by the hypervisor 20. Similarly, the Lv2 virtual computer 45 includes an Lv2 guest physical memory 46. The guest process 60 operates using the virtual memory 61 allocated by the Lv2 guest OS 50.

The Lv2 guest OS 50 creates an Lv2 guest page table (Lv2GPT) 51 that stores the correspondence between the virtual memory 61 and the Lv2 guest physical memory 46. The guest OS 40 creates a GPT 41 that associates the virtual memory 61 with the guest physical memory 31 with reference to the Lv2GPT 51, and stores the address of the GPT 41 in the virtual PT address register 33 in accordance with the operation of the guest process 60.

(4-3) Memory Configuration FIG. 38 shows a memory map of the physical memory 90 managed by the hypervisor 20. The hypervisor 20 allocates an area where the hypervisor 20 is arranged on the physical memory 90 and an area used by the virtual machine 30. The hypervisor 20 includes the program analysis unit 100, the EPT control unit 110, the SPT control unit 120, the method switching unit 130, and the virtual CPU scheduler 140 in the area allocated to itself.

Here, the hypervisor 20 allocates addresses AD0 to AD1 fixedly and arranges each module, dynamically assigns addresses AD2 to AD3 to the virtual machine 30, and assigns addresses AD4 to AD5 to another virtual machine 30. Assign dynamically. The guest OS 40 allocates an area where the guest OS 40 is arranged on each virtual machine 30 and an area used by the Lv2 guest OS 50 and the guest process 60.

Since each table configuration and processing executed by the hypervisor 20 are the same as those in the first embodiment, description thereof is omitted here. In the fourth embodiment, the guest OS 40 switches the GPT 41 in accordance with the operation of the guest process 60. Therefore, the hypervisor 20 can determine the characteristics of the guest process 60 on the Lv2 guest OS 50 by recognizing the switching of the GPT 41 and controlling the performance monitor function 74 by the mechanism in the first embodiment. Similarly, if either the SPT method or the EPT method is selected in accordance with the switching of the GPT 41, each method can be applied according to the operation of the guest process 60.

(4-4) Effects of the Fourth Embodiment As described above, according to the physical computer 10 of the fourth embodiment, the guest process operated by the Lv2 guest OS 50 operating on the guest OS 40 on the virtual computer 30 60 is differentiated by GPT41, and the characteristics of the guest process 60 are judged by the number of TLB misses and the number of TLB purges, so the double paging virtualization support function is disabled for the guest process 60 with many TLB misses By adopting the SPT method, it is possible to prevent the memory performance from being lowered due to the table reference. On the other hand, for the guest process 60 having a large number of TLB purges, the EPT method for enabling the double paging virtualization support function is used. Adopting it to prevent degradation of memory performance due to the process of synchronizing GPT41 and SP121 wear.

10 Physical computer 20 Hypervisor 30 Virtual computer 40 Guest OS
41 GPT (Guest Page Table)
45 Lv2 virtual machine 50 Lv2 guest OS
51 Lv2GPT
60 guest process 70 physical CPU
80 IO device 90 Physical memory 95 Console 100 Program analysis unit 110 EPT control unit 111 EPT (Extended Page Table)
120 SPT controller 121 SPT (shadow page table)
130 Method switching part

Claims

In computers equipped with physical memory and physical CPU,
The physical memory includes one or more virtual machines and a hypervisor that runs a guest OS on each virtual machine,
The physical CPU uses two tables to perform address conversion between a virtual memory allocated to a program running on the guest OS, a guest physical memory allocated to the virtual machine, and the physical memory. It has a paging virtualization support function,
The hypervisor is
A program analysis unit for recognizing a program running on the guest OS;
A characteristic table that holds characteristics of a program running on the guest OS;
A computer comprising: a method switching unit that enables or disables the double paging virtualization support function according to characteristics of a program running on the guest OS.
The virtual memory is given a first address,
The guest physical memory is given a second address,
The physical memory is given a third address,
The hypervisor is
The first table associating the first address and the second address and the second table associating the second address and the third address are combined into one, and the first address and An SPT control unit for creating a third table for associating the third address;
The method switching unit is
According to the characteristics of the program running on the guest OS, register the first table and the second table in the physical CPU, and refer to both the first table and the second table. By enabling the double paging virtualization support function by performing address conversion, or by registering the third table in the physical CPU and performing address conversion by referring to the third table The computer according to claim 1, wherein either one of the double paging virtualization support functions is disabled and the double paging virtualization support function is enabled or disabled.
The characteristic table is
The computer according to claim 2, wherein the computer is a GPT-specific characteristic table that holds characteristics of a program running on the guest OS for each address of the first table.
The characteristic table is
2. The computer according to claim 1, wherein each of the plurality of virtual CPUs included in the virtual computer is a virtual CPU-specific characteristic table that holds characteristics of a program running on the guest OS.
The characteristic table is
2. The computer according to claim 1, wherein the computer is a privilege level-specific characteristic table that retains characteristics of a program running on the guest OS with respect to a privilege level of a virtual CPU assigned to the virtual machine.
The characteristic table is
The computer according to claim 1, wherein the computer is a characteristic fixed selection table that holds the characteristics of the program declared from the program or the characteristics of the program input from an external terminal.
The characteristics of the program are:
The computer according to claim 2, comprising: a reference count of the first and second tables; and an execution count of an instruction for notifying update of the first table.
In an address conversion method for a computer equipped with a physical memory and a physical CPU,
The physical memory includes one or more virtual machines and a hypervisor that runs a guest OS on each virtual machine,
The physical CPU uses two tables to perform address conversion between a virtual memory allocated to a program running on the guest OS, a guest physical memory allocated to the virtual machine, and the physical memory. It has a paging virtualization support function,
The hypervisor is
A first step of recognizing a program running on the guest OS;
A second step of retaining the characteristics of a program running on the guest OS;
An address conversion method comprising: a third step of enabling or disabling the double paging virtualization support function according to the characteristics of a program running on the guest OS.
The virtual memory is given a first address,
The guest physical memory is given a second address,
The physical memory is given a third address,
The hypervisor is
The first table associating the first address and the second address and the second table associating the second address and the third address are combined into one, and the first address and A fourth step of creating a third table for associating the third address;
In the third step,
The hypervisor registers the first table and the second table in the physical CPU according to the characteristics of the program running on the guest OS, and both the first table and the second table are registered. The double paging virtualization support function is validated by referring to the address, or the third table is registered in the physical CPU, and the address conversion is performed by referring to the third table. 9. The method of enabling or disabling the double paging virtualization support function by selecting any one of disabling the double paging virtualization support function by performing The address conversion method described.
In the second step,
The address conversion method according to claim 9, wherein the hypervisor retains characteristics of a program running on the guest OS for each address of the first table.
In the second step,
The address conversion method according to claim 8, wherein the hypervisor holds characteristics of a program running on the guest OS for each of a plurality of virtual CPUs included in the virtual machine.
In the second step,
The address conversion method according to claim 8, wherein the hypervisor retains characteristics of a program running on the guest OS with respect to a privilege level of a virtual CPU assigned to the virtual machine.
In the second step,
The address conversion method according to claim 8, wherein the hypervisor retains the characteristics of a program declared from the program or the characteristics of the program input from an external terminal.
The characteristics of the program are:
The address conversion method according to claim 9, further comprising: a reference count of the first table and the second table; and an execution count of an instruction for notifying update of the first table.