WO2015144263A1 - Power converter with dynamic voltage scaling - Google Patents

Power converter with dynamic voltage scaling Download PDF

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Publication number
WO2015144263A1
WO2015144263A1 PCT/EP2014/076445 EP2014076445W WO2015144263A1 WO 2015144263 A1 WO2015144263 A1 WO 2015144263A1 EP 2014076445 W EP2014076445 W EP 2014076445W WO 2015144263 A1 WO2015144263 A1 WO 2015144263A1
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WO
WIPO (PCT)
Prior art keywords
power converter
supply voltage
input voltage
voltage
controller
Prior art date
Application number
PCT/EP2014/076445
Other languages
French (fr)
Inventor
Richard Maria Schmitz
Original Assignee
Zentrum Mikroelektronik Dresden Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zentrum Mikroelektronik Dresden Ag filed Critical Zentrum Mikroelektronik Dresden Ag
Priority to EP14808593.9A priority Critical patent/EP3123266A1/en
Priority to JP2016558321A priority patent/JP2017509305A/en
Publication of WO2015144263A1 publication Critical patent/WO2015144263A1/en

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0016—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters
    • H02M1/0022—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters the disturbance parameters being input voltage fluctuations

Definitions

  • the present invention relates to a power converter with dynamic voltage scaling (DVS) .
  • the present invention specifically relates to a standard DC DC power converter with dynamic voltage scaling.
  • Switched DC DC power conversion has been widely adopted to supply a point of load with power such as a device.
  • a supplied device such as microprocessor, FPGA or other digital circuit can run over a certain voltage range.
  • energy is wasted if the supplied device is running at a higher voltage than required for its performance, energy is wasted .
  • the supplied device is running a significant portion of time in a so called light load or medium load condition. Under these conditions the device does not need to run with the highest possible supply voltage. If, however the supplied device is running at a highest possible supply voltage under a light or medium load condidition, the energy consumption of the supplied device is higher than necessary. Instead the supply voltage can be lowered and therefore the energy consumption can also be lowered.
  • the present invention relates to a power converter generating an adjusted supply voltage according to the performance required by the supplied device.
  • the supplied device communicates its required supply voltage, i.e. the reference supply voltage, to the power converter. With the required supply voltage communicated to and an adjusted supply voltage generated by the power converter, the energy consumption of the device is optimized .
  • Fig. 1 shows a block diagram of a power converter and a supplied device that communicates its required supply voltage to the power converter using a low pass filter; shows a relationship between an input output voltage of the supplied device (V_IO) , a duty ratio of a PWM signal used to communicate a required supply voltage and an analog-to-digital (ADC) converter input voltage Vin; shows a selection procedure for the duty ratio of the PWM signal and a maximum ADC input voltage; shows a mapping of and ADC input voltage to a reference supply voltage; shows a block diagram for programming a PWM generator; shows a block diagram of a power converter and a supplied device that communicates its required supply voltage to the power converter using a resisitive divider;
  • Fig. 7 shows a block diagram of a power converter and a supplied device that communicates its required supply voltage to the power converter using a combined resisitive divider and low pass filter;
  • Fig. 8 shows a relationship between ADC input voltage and refe ⁇ rence supply voltage
  • Fig. 9 shows another block diagram for programming the PWM generator.
  • Fig. 10 shows a flow diagram showing a task flow in the supplied device and and the power converter
  • Fig. 1 shows a power converter 11 and a supplied device 12 that communicates its required supply voltage to the power converter 11.
  • the power converter 11 comprises a switchable power stage 15 for generating an output voltage for powering a supply domain of a supplied device 12, wherein the switchable power stage 15 is driven by a driver 16 controlled by a controller 17 generating a switching signal for driving the switchable power stage 15 according to a reference supply voltage.
  • the power converter can be a buck converter as shown in Fig. 1.
  • the switchable power stage 15 comprises a high-side switch 18, a low-side switch 19, an inductor 110 and a capacitor 111.
  • An analog to digital converter (ADC) 112 of the controller 17 of the power converter 11 is used as an communication interface.
  • a pulse width modulation (PWM) signal generated by PWM generator 13 can be used to generate an analog value by means of a low pass filter 14.
  • PWM pulse width modulation
  • This low pass filtered signal V in is then read by the ADC 112 of the controller 17 and mapped to the reference supply voltage Vsup the controller 17.
  • the ADC input voltage Vin can be translated into the reference supply voltage Vsu according to this equation:
  • Vmin is a minimum reference supply voltage
  • Vmax is a maximum supply voltage
  • Vin max is a maximum ADC input voltage
  • Vmax, Vmin and Vin, max and also a minimum ADC input voltage Vin,min may be stored in the DCDC controller memory.
  • V_IO 10 voltage
  • VADCmax maximum ADC voltage
  • the PWM has to be limited to VADCmax/V_IO*100% in order to avoid exceeding the voltage limit of the ADC.
  • V_IO, PWM and Vinmax are shown in Fig. 2. These are the maximum possible or allowed values for Vinmax and PWM. Any value below the straight line on the left side and below the hyperbola on the right side of the graph in Fig. 2 can be picked as the maximum values for PWM and Vinmax.
  • the selection procedure for PWM and Vinmax is illustrated in Fig. 3.
  • the PWM generator 53 can be easily programmed into any digital device as shown in Figure 5 according to the requirement of a user application 51. It can be done in software or hardware. It can also be based on a module 52 that is predefined and then is instantiated into the digtal device as a netlist or a module based on a HDL (hard ware description language) like Verilog or VHDL . Doing this the PWM generator 53 can be incorporated in any device like a FPGA, ASIC, uC or uP .
  • the HDL code or netlist 52 can be developed independently of the application of the supplied device. Only the interface to the PWM generator 53 needs to be specified. Input for the PWM generator 53 is a serial or parallel interface defining the desired PWM duty cycle and a clock. The output of the PWM generator is one external pin which is driving the PWM signal.
  • the highest flexibility can be achieved with a soft IP on HDL level. This way the number of bits required for the resolution of the PWM duty cycle can be specified during the design cycle of the user application. It is also possible to use a process specific layout based hard IP, in which case the flexibility for the PWM duty cycle resolution will be lost. It is not mandatory to use the IP based approach.
  • the PWM functionality can also be programmed in SW or in a state machine or together with any other HW that the supplied device is incorporating.
  • the low pass filter can be omitted because the PWM output will be logic low or logic high, i.e. it is a DC value.
  • V_IO > VADCmax a resistive divider is needed instead of the low pass to limit the ADC input voltage to VADCmax.
  • V_IO ⁇ VADCmax Vinmax needs to be set to V_IO .
  • Fig. 6 the modified block diagram with analogous reference signs as in Fig. 1 is shown.
  • the low pass filter has been replaced by the resistive divider 64. In this application Vsup can only have two values which in some applications are sufficient .
  • an additional resistor R2 as shown in Fig. 6 and 7 can be provided.
  • R2/(Rl+R2) has to be VADCmax/V_IO.
  • the filter 74 comprises a low pass filter and a resistive divider.
  • the controller 77 will hold in its memory (volatile or non volatile) the values for Vinmin, Vinmax, Vmin and Vmax and will adjust Vsup according to the equation as shown in Figure 8:
  • Vmax-Vmin is the dynamic range of the reference supply voltage and Vin, max-Vin, min is the dynamic range of the ADC input
  • a duty ratio of the PWM signal is limited such that at maximum a 100% duty ratio of the PWM signal corresponds to a maximum ADC input voltage that can be read by the ADC and wherein the ADC input voltage is mapped to the reference supply reference such that a dynamic range of the ADC input voltage corresponds to a dynamic range of the reference supply voltage.
  • the PWM generator 73 will generate a PWM output with a linear resolution of n bits between PWMmin and PWMmax.
  • the operating range of Vin can be influenced through Rl and R2 and with Clp together with Rl and R2 a low pass filter is formed to generate a DC value from the PWM signal.
  • Fig. 9 shows another block diagram for programming the PWM generator 93.
  • the PWM generator is a HDL module with the clock and the PWMdig signal as inputs and PWMmax and PWMmin as a parameter.
  • This IP can also be provided as a layout or netlist IP 92 according to a user application 91. In this case the
  • the PWM generator is part of the supplied device .
  • Fig. 10 illustrates the flow in the supplied device and in the DCDC controller.
  • the communication is a one way communication from the supplied device to the DCDC controller. This means that the maximum time from sending out the DVS signal (PWM change) to the time the output voltage reaches its desired value has to be calculated during the system design and a waiting period has to be implemented to wait for completion of the output voltage change. This is not important for the situation going from a high performance mode, i.e. high output voltage to a lower output voltage. But it is important when going from a low power mode to a high power mode, because the supplied device needs to wait the calculated maximum time to go into the high performance , i.e. high power, mode.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The present invention relates to a power converter generating an adjusted supply voltage according to the performance required by a supplied device. The supplied device communicates its required supply voltage, i.e. the reference supply voltage, to the power converter. With the required supply voltage communicated to and an adjusted supply voltage generated by the power converter, the energy consumption of the device is optimized.

Description

Power converter with dynamic voltage scaling
FIELD OF THE INVENTION
The present invention relates to a power converter with dynamic voltage scaling (DVS) . The present invention specifically relates to a standard DC DC power converter with dynamic voltage scaling.
BACKGROUND OF THE INVENTION
Switched DC DC power conversion has been widely adopted to supply a point of load with power such as a device. Typically, a supplied device such as microprocessor, FPGA or other digital circuit can run over a certain voltage range. The higher the supply voltage of a digital circuit the better is the performance of the device. However, if the supplied device is running at a higher voltage than required for its performance, energy is wasted .
Moreover, In many applications the supplied device is running a significant portion of time in a so called light load or medium load condition. Under these conditions the device does not need to run with the highest possible supply voltage. If, however the supplied device is running at a highest possible supply voltage under a light or medium load condidition, the energy consumption of the supplied device is higher than necessary. Instead the supply voltage can be lowered and therefore the energy consumption can also be lowered.
Hence, what is required is a power converter configured to optimize the energy consumption of the supplied device. SUMMARY OF THE INVENTION
The present invention relates to a power converter generating an adjusted supply voltage according to the performance required by the supplied device. The supplied device communicates its required supply voltage, i.e. the reference supply voltage, to the power converter. With the required supply voltage communicated to and an adjusted supply voltage generated by the power converter, the energy consumption of the device is optimized .
BRIEF DESCRIPTION OF THE DRAWINGS
Reference will be made to the accompanying drawings, wherein:
Fig. 1 shows a block diagram of a power converter and a supplied device that communicates its required supply voltage to the power converter using a low pass filter; shows a relationship between an input output voltage of the supplied device (V_IO) , a duty ratio of a PWM signal used to communicate a required supply voltage and an analog-to-digital (ADC) converter input voltage Vin; shows a selection procedure for the duty ratio of the PWM signal and a maximum ADC input voltage; shows a mapping of and ADC input voltage to a reference supply voltage; shows a block diagram for programming a PWM generator; shows a block diagram of a power converter and a supplied device that communicates its required supply voltage to the power converter using a resisitive divider;
Fig. 7 shows a block diagram of a power converter and a supplied device that communicates its required supply voltage to the power converter using a combined resisitive divider and low pass filter;
Fig. 8 shows a relationship between ADC input voltage and refe¬ rence supply voltage;
Fig. 9 shows another block diagram for programming the PWM generator; and
Fig. 10 shows a flow diagram showing a task flow in the supplied device and and the power converter;
DETAILED DESCRIPTION OF THE INVENTION
Fig. 1 shows a power converter 11 and a supplied device 12 that communicates its required supply voltage to the power converter 11. The power converter 11 comprises a switchable power stage 15 for generating an output voltage for powering a supply domain of a supplied device 12, wherein the switchable power stage 15 is driven by a driver 16 controlled by a controller 17 generating a switching signal for driving the switchable power stage 15 according to a reference supply voltage. The power converter can be a buck converter as shown in Fig. 1. Thus, the switchable power stage 15 comprises a high-side switch 18, a low-side switch 19, an inductor 110 and a capacitor 111. An analog to digital converter (ADC) 112 of the controller 17 of the power converter 11 is used as an communication interface. Assuming that the supplied device cannot output analog voltages, a pulse width modulation (PWM) signal generated by PWM generator 13 can be used to generate an analog value by means of a low pass filter 14.
This low pass filtered signal Vin is then read by the ADC 112 of the controller 17 and mapped to the reference supply voltage Vsup the controller 17.
Specifically, the ADC input voltage Vin can be translated into the reference supply voltage Vsu according to this equation:
Figure imgf000005_0001
wherein Vmin is a minimum reference supply voltage, Vmax is a maximum supply voltage and Vin, max is a maximum ADC input voltage .
This equation is illustrated in Fig. 4.
Vmax, Vmin and Vin, max and also a minimum ADC input voltage Vin,min may be stored in the DCDC controller memory.
A possible mismatch of the maximum ADC voltage VADCmax and the input output voltage V_IO of the supplied device is addressed.
In case the 10 voltage (V_IO) of the supplied device is lower than the maximum ADC voltage (VADCmax) the supplied device will have PWM values from 0% to 100% and the Vinmax is equivalent to the 10 voltage of the supplied device. For a PWM of 0% the input voltage of the ADC is 0 and for a PWM value of 100% Vin=V_IO=Vinmax .
In case the 10 voltage of the supplied device is higher than VADCmax, the PWM has to be limited to VADCmax/V_IO*100% in order to avoid exceeding the voltage limit of the ADC.
The relationship between V_IO, PWM and Vinmax is shown in Fig. 2. These are the maximum possible or allowed values for Vinmax and PWM. Any value below the straight line on the left side and below the hyperbola on the right side of the graph in Fig. 2 can be picked as the maximum values for PWM and Vinmax. The selection procedure for PWM and Vinmax is illustrated in Fig. 3.
The PWM generator 53 can be easily programmed into any digital device as shown in Figure 5 according to the requirement of a user application 51. It can be done in software or hardware. It can also be based on a module 52 that is predefined and then is instantiated into the digtal device as a netlist or a module based on a HDL (hard ware description language) like Verilog or VHDL . Doing this the PWM generator 53 can be incorporated in any device like a FPGA, ASIC, uC or uP .
The HDL code or netlist 52 can be developed independently of the application of the supplied device. Only the interface to the PWM generator 53 needs to be specified. Input for the PWM generator 53 is a serial or parallel interface defining the desired PWM duty cycle and a clock. The output of the PWM generator is one external pin which is driving the PWM signal. The highest flexibility can be achieved with a soft IP on HDL level. This way the number of bits required for the resolution of the PWM duty cycle can be specified during the design cycle of the user application. It is also possible to use a process specific layout based hard IP, in which case the flexibility for the PWM duty cycle resolution will be lost. It is not mandatory to use the IP based approach. The PWM functionality can also be programmed in SW or in a state machine or together with any other HW that the supplied device is incorporating.
In the case of a PWM resolution of 1 bit, the low pass filter can be omitted because the PWM output will be logic low or logic high, i.e. it is a DC value. For V_IO > VADCmax a resistive divider is needed instead of the low pass to limit the ADC input voltage to VADCmax. For V_IO < VADCmax Vinmax needs to be set to V_IO . In Fig. 6 the modified block diagram with analogous reference signs as in Fig. 1 is shown. The low pass filter has been replaced by the resistive divider 64. In this application Vsup can only have two values which in some applications are sufficient .
To overcome the limitation of the maximum PWM allowed in the system in Fig. 1, an additional resistor R2 as shown in Fig. 6 and 7 can be provided. The resistive divider R1/R2 in Fig. 6 and 7 limits the input voltage of the ADC to VADCmax. Therefore it must be ensured that R2/(Rl+R2) <= VADCmax/V_IO for a PWM output of 100%. To use the full input range of the ADC R2/(Rl+R2) has to be VADCmax/V_IO.
A flexible solution for the DVS implantation can be described using Fig. 7, Fig. 8 and Fig. 9 showing a block diagram with analogous reference signs as in Fig. 1. The filter 74 comprises a low pass filter and a resistive divider.
The controller 77 will hold in its memory (volatile or non volatile) the values for Vinmin, Vinmax, Vmin and Vmax and will adjust Vsup according to the equation as shown in Figure 8:
Figure imgf000007_0001
Vmax-Vmin is the dynamic range of the reference supply voltage and Vin, max-Vin, min is the dynamic range of the ADC input
voltage .
Thus, a duty ratio of the PWM signal is limited such that at maximum a 100% duty ratio of the PWM signal corresponds to a maximum ADC input voltage that can be read by the ADC and wherein the ADC input voltage is mapped to the reference supply reference such that a dynamic range of the ADC input voltage corresponds to a dynamic range of the reference supply voltage.
The PWM generator 73 will generate a PWM output with a linear resolution of n bits between PWMmin and PWMmax. In addition to that the operating range of Vin can be influenced through Rl and R2 and with Clp together with Rl and R2 a low pass filter is formed to generate a DC value from the PWM signal.
Fig. 9 shows another block diagram for programming the PWM generator 93. The PWM generator is a HDL module with the clock and the PWMdig signal as inputs and PWMmax and PWMmin as a parameter. This IP can also be provided as a layout or netlist IP 92 according to a user application 91. In this case the
flexibility to specify the PWMdig width and the parameters PWMmin and PWMmax is lost. The PWM generator is part of the supplied device .
A summary of features provided for the implementation of DVS in a standard DCDC controller inside a system is shown below.
Figure imgf000009_0001
Fig. 10 illustrates the flow in the supplied device and in the DCDC controller.
All of the above described configurations run in open loop. The communication is a one way communication from the supplied device to the DCDC controller. This means that the maximum time from sending out the DVS signal (PWM change) to the time the output voltage reaches its desired value has to be calculated during the system design and a waiting period has to be implemented to wait for completion of the output voltage change. This is not important for the situation going from a high performance mode, i.e. high output voltage to a lower output voltage. But it is important when going from a low power mode to a high power mode, because the supplied device needs to wait the calculated maximum time to go into the high performance , i.e. high power, mode.

Claims

What is claimed is:
1. Power converter comprising:
a switchable power stage for generating an output voltage for powering a supply domain of a supplied device, wherein the switchable power stage is driven by a driver controlled by a controller generating a switching signal for driving the switchable power stage according to a reference supply voltage, characterized in that
the reference supply voltage is communicated to the
controller by the supplied device.
2. Power converter according to claim 1, wherein the supplied device comprises or is connected to a PWM generator, wherein the reference supply voltage is communicated to the
controller via a PWM signal that is generated by the PWM generator and that corresponds to the reference supply voltage, wherein the supplied device communicates the PWM signal to the controller, and wherein the controller maps the PWM signal to the reference supply voltage.
3. Power converter according to claim 2, wherein the PWM signal is filtered by a filter to generate an ADC input voltage that is read by an ADC of the controller and wherein the controller maps the ADC input voltage to the reference supply voltage.
4. Power converter according to claim 3, wherein a duty ratio of the PWM signal is limited such that at maximum a 100% duty ratio of the PWM signal corresponds to a maximum ADC input voltage that can be read by the ADC and wherein the ADC input voltage is mapped to the reference supply reference such that a dynamic range of the ADC input voltage corresponds to a dynamic range of the reference supply voltage .
Power converter according to claim 3, wherein the filter comprises a resistive divider to filter the PWM signal such that the ADC input voltage is limited to a maximum ACD input voltage that can be read by the ADC.
Power converter according to claim 4 or 5, wherein
controller is configured to map the ADC input voltage Vin to the reference supply voltage Vsup, ref such that wherein Vmin is a minimum reference supply voltage, Vmax is a maximum supply voltage, Vmax-Vmin is the dynamic range of the reference supply voltage, Vin,min is a minimum ADC input voltage, Vin, max is a maximum ADC input voltage, and Vin, max- Vin, min is the dynamic range of the ADC input voltage.
Power converter according to claim 5 or 6, wherein the controller comprises a memory configured to store values for
Vin, min , Vin, max Vmin and Vmax .
Power converter according to any of claims 5 to 7, wherein the resistive divider comprises a first resistor Rl and a second resistor R2 and wherein R2/(R2-Rl) is chosen such that it equals to ( Vin, max-Vin, min) / ( Vmax-Vmin) .
Power converter according to any of claims 3 to 8, wherein the filter comprises a low pass filter.
10. Power converter according to any of claims 1 to 9, wherein the PWM generator of the supplied device is configurable with respect to the number of bits of a duty cycle resolution, a maximum duty ratio and a minimum duty ratio .
PCT/EP2014/076445 2014-03-25 2014-12-03 Power converter with dynamic voltage scaling WO2015144263A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP14808593.9A EP3123266A1 (en) 2014-03-25 2014-12-03 Power converter with dynamic voltage scaling
JP2016558321A JP2017509305A (en) 2014-03-25 2014-12-03 Power converter with dynamic voltage scaling

Applications Claiming Priority (2)

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US201461970046P 2014-03-25 2014-03-25
US61/970,046 2014-03-25

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0735656A2 (en) * 1995-03-31 1996-10-02 Space Systems / Loral Inc. Stabilized power converter having quantized duty cycle
EP1965496A2 (en) * 2007-03-02 2008-09-03 Yamaha Corporation Delta-sigma type ad converter, class-d amplifier, and dc-dc coverter
US20090039842A1 (en) * 2007-08-09 2009-02-12 Industrial Technology Research Institute Dc-dc converter
CN102931842A (en) * 2012-10-12 2013-02-13 华为技术有限公司 Chip dynamic voltage regulating circuit and terminal equipment

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5055083B2 (en) * 2007-10-19 2012-10-24 日立コンピュータ機器株式会社 Digital control power supply
WO2010059900A1 (en) * 2008-11-21 2010-05-27 Maxim Integrated Products, Inc. Digital compensator for power supply applications
GB0912745D0 (en) * 2009-07-22 2009-08-26 Wolfson Microelectronics Plc Improvements relating to DC-DC converters
US8779740B2 (en) * 2011-08-19 2014-07-15 Infineon Technologies Austria Ag Digital sliding mode controller for DC/DC converters
US8698475B2 (en) * 2011-10-20 2014-04-15 Monolithic Power Systems, Inc. Switching-mode power supply with ripple mode control and associated methods

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0735656A2 (en) * 1995-03-31 1996-10-02 Space Systems / Loral Inc. Stabilized power converter having quantized duty cycle
EP1965496A2 (en) * 2007-03-02 2008-09-03 Yamaha Corporation Delta-sigma type ad converter, class-d amplifier, and dc-dc coverter
US20090039842A1 (en) * 2007-08-09 2009-02-12 Industrial Technology Research Institute Dc-dc converter
CN102931842A (en) * 2012-10-12 2013-02-13 华为技术有限公司 Chip dynamic voltage regulating circuit and terminal equipment

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TW201537876A (en) 2015-10-01
TWI586086B (en) 2017-06-01
EP3123266A1 (en) 2017-02-01

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