WO2015134709A1 - Statistical overlay error prediction for feed forward and feedback correction of overlay errors, root cause analysis and process control - Google Patents

Statistical overlay error prediction for feed forward and feedback correction of overlay errors, root cause analysis and process control Download PDF

Info

Publication number
WO2015134709A1
WO2015134709A1 PCT/US2015/018884 US2015018884W WO2015134709A1 WO 2015134709 A1 WO2015134709 A1 WO 2015134709A1 US 2015018884 W US2015018884 W US 2015018884W WO 2015134709 A1 WO2015134709 A1 WO 2015134709A1
Authority
WO
WIPO (PCT)
Prior art keywords
profiles
wafer
overlay
training
overlay error
Prior art date
Application number
PCT/US2015/018884
Other languages
French (fr)
Inventor
Wei Chang
Krishna Rao
Joseph GUTIERREZ
Ramon Olavarria
Craig MACNAUGHTON
Amir Azordegan
Prasanna Dighe
Original Assignee
Kla-Tencor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kla-Tencor Corporation filed Critical Kla-Tencor Corporation
Priority to EP15758366.7A priority Critical patent/EP3114705B1/en
Priority to JP2016555779A priority patent/JP6490094B2/en
Priority to US15/123,980 priority patent/US10545412B2/en
Priority to KR1020167025800A priority patent/KR102179988B1/en
Publication of WO2015134709A1 publication Critical patent/WO2015134709A1/en

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/705—Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70591—Testing optical components
    • G03F7/706—Aberration measurement
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70681—Metrology strategies
    • G03F7/706833—Sampling plan selection or optimisation, e.g. select or optimise the number, order or locations of measurements taken per die, workpiece, lot or batch
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/706835—Metrology information management or control
    • G03F7/706837—Data analysis, e.g. filtering, weighting, flyer removal, fingerprints or root cause analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N5/00—Computing arrangements using knowledge-based models
    • G06N5/04—Inference or reasoning models
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

  • the present invention is directed generally toward semiconductor wafer fabrication and more particularly toward error identification and correction methods in fabrication,
  • a wafer generally goes through certain processes including deposition, etching., chemical- mechanical polishing (CMP) etc., before it is sent into a lithography scanner for exposure. Overlay errors are measured after the exposure using tools such as TWiNSCAN, Archer 500 or some other appropriate device.
  • CMP chemical- mechanical polishing
  • Lithography overlay and critical dimension uniformity are critical parameters in semiconductor manufacturing which can adversely affect integrated circuit performance and wafer yield.
  • Overlay errors can be caused by lithography scanner tools, mask or reticle, and process Induced wafer geometry changes during scan and expose operation or other similar sources. With shrinking logic and memory device dimensions, overlay errors increasingly consume a significant fraction of the total overlay budget for critical layers. Significant efforts have been expended to identify and minimize systematic sources of overlay errors.
  • One method of minimizing systematic overlay errors is to use high resolution wafer geometry measurements to Identify and monitor wafer fabrication processes and identify wafer geometry changes that can be fed forward to the scanner to counteract the impact of the wafer geometry changes (along with other correctible factors) during the scan and expose operation.
  • Analytical mechanics models, numerical finite-element models and other such methodologies have been used to make overlay predictions. However these methods suffer from the high complexity of the physical processes. Furthermore, they impact the wafer geometry that they seek to model and may not be usable to consistently predict reliable scanner corrections to counteract incoming wafer geometry changes.
  • the present invention is directed to a novel method and apparatus for consistently predicting overlay errors in a consistent wafer fabrication process and apply appropriate corrections to subsequent wafer fabrications.
  • an overlay prediction system accurately predicts corrections by determining wafer geometry changes based on measurements of the wafer before and after lithography processes, applying a plurality of predictive models and comparing the predictive models to actual overlay errors to determine which predictive model produces the most accurate result.
  • the identified predictive model is then used to predict overlay errors in subsequent wafer fabrication for the same batch of wafers.
  • a validation wafer is used to verify the identified predictive model
  • FIG. 1 shows a block diagram of a lithographic computer system useful for implementing at least one embodiment of the present Invention
  • FIG. 2 shows a flowchart of a method for error prediction in a semiconductor wafer fabrication process
  • FIG. 3 shows an exemplary output of an error prediction process according to at least one embodiment of the present invention
  • FIG. 4 shows a block diagram of a neural network according to at least one embodiment of the present invention
  • a computer system for scanning wafers and determining a predictive model of overlay errors in a wafer fabrication process includes a processor 100, memory 102 connected to the processor 100 for storing and executin computer executable program code and a camera 106 or other wafer scanning device for scanning a wafer 108 geometry and for analyzing overlay errors in a wafer 108 after an overlay exposure process.
  • the computer system may also include a data storage device 104 connected to the processor 100 for storing predictive models and the results of applying such predictive models to a scanned wafer 108 geometry.
  • one or more training wafers are selected 200 from a batch of productio wafers 214 produced by or during the same or substantially similar fabrication process.
  • the batch of wafers produced by or during the same fabrication process are also intended for the same scan-and-expose overlay procedures.
  • a dynamically smart sampling strategy may be employed to select training wafers.
  • Patterned wafer geometry parameters such as wafer shape and geometry are obtained 202 for the training wafers using a patterned wafer geometry metrology tool.
  • Training wafers may also undergo homogeneity testing, if the training wafers behave heterogeneously (for example due to different chambers of a multi-chamber process tool imparting different process signatures on the wafers in a single lot), statistical clustering techniques such as K -means and Gaussian mixture model may be applied to separate training wafers into several homogenous groups. Homogeneity is critical for determining a replicatable predictive model
  • a predictive modeling engine runs advanced predictive models including but not limited to neural network, random forest, boosted regression tree, support vector machine and generalized linear models.
  • Those models take a large number of process dependent variables, including a multitude of high spatial resolution wafer geometry parameters, as input variables such as but not limited to wafer flatness, thickness, shape, and their first or higher order derivatives, difference in shape (post- process minus pre-process), shape residual ⁇ post 2nd order removal) and other relevant process information (such as but not limited to chip layout, film-stack thickness and other properties, lithography scanner settings, etc.)
  • process dependent variables including a multitude of high spatial resolution wafer geometry parameters, as input variables such as but not limited to wafer flatness, thickness, shape, and their first or higher order derivatives, difference in shape (post- process minus pre-process), shape residual ⁇ post 2nd order removal) and other relevant process information (such as but not limited to chip layout, film-stack thickness and other properties, lithography scanner settings, etc.)
  • process information such as but
  • a overla process is performed on the one or more training wafers and the one or more training wafers are analyzed 204 for actual overlay errors.
  • the measured lithography overlay errors are used to develop complex highly non- linear relationships or predictive models intended to minimize overlay errors.
  • the actual overlay errors are then compared 206 to the predicted overlay errors based on the predictive models in real time to produce a candidate predictive model that most closely matches the actual overlay errors.
  • the prediction accuracy is measured by Pearson correlation between the predicted overlay errors and the actual overlay errors. The model with the best prediction accuracy will be retained as the candidate model.
  • the predictive methodology of the present invention Is point-to-point geometry information at a particular wafer coordinate corresponds to an overlay error at wafer coordinate.
  • the statisticall predictive models allow for flexible experimentation.
  • the number of training wafers and the number of sample locations on the training wafers can be gradually increased until reaching reliable prediction performance.
  • wafer geometry and process characteristics of interest are identified. Different sampling strategies based on those characteristics may be rapidly tested to converge to the most optimal prediction performance in terms of accuracy and reliability.
  • Optimal sampling may define the minimum number of points at whic wafer geometry changes need to be measured and thus reduce cycle time and increase tool productivity,
  • one or more validation wafers are selected 212 from the production wafers 214 and patterned wafer geometry parameters are obtained 202 for the validation wafers using a patterned wafer geometry metrology tool.
  • An overlay process is performed on the one or more validation wafers and the one or more validation wafers are analyzed 210 for actual overlay errors.
  • the candidate model predicts the overlay errors and compares them with the actual overlay errors on the validation wafers, if the prediction accuracy satisfies 207 certain thresholds based on the overlay budget and other considerations, the candidate model is considered to be valid and ready to be deployed 208 to predict overlay errors on other production wafers which share simitar processing conditions with the training and validation wafers.
  • the remaining production wafers 216 are scanned 218 with a patterned wafer geometry metrology tool to determine 220 wafer geometry parameters. Based on the wafer geometry parameters and the deployed predictive model 208, the system predicts 222 an overlay error for the remaining production wafers and adjusts 224 the lithography scanner to correct the predicted overlay error. Point-to-point prediction is crucial for feeding forward the predicted overlay, applying the adjustment 224 and hence reducing the actual overlay error after the exposure.
  • Methods according to the present invention may allow a lithography production process to preemptively correct for overlay errors without intensive processing of each individual wafer,
  • FIG. 3 an exemplary output of an error prediction process according to at least one embodiment of the present invention is shown.
  • Current linear regression prediction methodolog predicts an overlay error pattern 302 substantially different from an actual overlay error pattern 300.
  • methods according to the present invention using advanced predictive models generate an overlay error pattern 304 more closely correlated with the actual overlay error pattern 300.
  • the advanced predictive model utilized neural networks.
  • a neural network comprises a plurality of input variables 400, X2 402, X3 404, >Q 406 such as IPD, shape, slope etc.
  • the linear combination Zj - ⁇ 2 is passed as a stimulus to neuron Hi 408 in the hidden layer.
  • An activation function embedded in each neuron abstractly represents a biological rate of action potential firing in the neuron.
  • a commonly used activation function is the SIGMOID function O j TM _ . y where O j is the output from neuron H j .
  • the predicted overlay output cell Y 412 is the collection of the outcomes from all neurons Hi 408 .
  • the overlay output cell is defined by y TM ⁇ ;1 3 ⁇ 43 ⁇ 4- overlay output cell 412 and the input variable 400, 402, 404, 406 may exhibit highly non-linear structure.
  • Mathematical structure in a neural network can also suggest how the output behaves depending on certain input. Assuming a neural network with two input variables, for example X 400 and X 2 402, and three neurons 408, 410 in the hidden layer, the first derivative of output Y 412 with reference to the first input variable X1 400 is defined by:
  • the relative importance of each input variable in a predictive model is determined by a procedure in a statistical package, input variables are ranked based on the reduction in variance of the predicted overlay attributable to each variable, via a sensitivity analysis.
  • a prediction score may be defined by: cores / v(y) which is the ratio of expected variance of predicted overlay given certain variable value X. to the unconditional variance of the predicted overlay.
  • wafers may have characteristics that are non-uniform such as film stress and higher order in-plane displacement as a result of non-uniform variation in wafer geometry and process variations. Therefore, the correlatio between input variables such as wafer geometry and output such as overlay can exhibit convoluted non-linearity. In that case, a predictive model which models the non-linear correlation can improve prediction accuracy. Neural networks can therefore improve predictive accuracy over linear regression.
  • Methods according to at least one embodiment of the present invention may be employed to study a relationship between wafer geometry changes and overlay error, and identify dominant geometry components that affect lithography overlay and lithography critical dimension uniformity.
  • Methods according to at least one embodiment of the present invention may be used to identify a root cause of overlay errors. All process related parameters, such as wafer flatness, thickness, shape, and the first or higher order derivatives of those parameters, differences in shape, and shape residual may be considered using the predictive model process described herein. Some appropriate variable select algorithm, such as ElastlcNet, forward-stepwise regression or least angle regression, may systematically rule out non-essential or noisy parameters in the predictive model selection process and converge to the more impactful sources of overlay errors. Similar methods may be applied to other relevant process parameters such as chip layout, film-stack thickness and other film-stack properties, lithography scanner settings, including translation, rotation, magnification, orthogonality . , wafer tilt, etc.
  • ElastlcNet forward-stepwise regression or least angle regression
  • Methods according to at least one embodiment of the present invention may reveal process variations that can be used to monitor process excursions. Clustering techniques can separate wafers into different groups. Assuming a stable production process results in similar overlay maps within each group, engineers may identify a process excursion by monitoring the characteristics of each group. ⁇ 0032] Systems according to embodiments of the present invention may leverage statistically predictive models, which in addition to improved overlay correction prediction capability may also identify the impact of wafer fabrication unit processes such as scan-and-expose including reticle effects, chemical mechanical polishing, rapid thermal processing and other semiconductor processes that contribute to overlay errors.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Software Systems (AREA)
  • Geometry (AREA)
  • Data Mining & Analysis (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Artificial Intelligence (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Medical Informatics (AREA)
  • Computational Linguistics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

A method to collect data and train, validate and deploy statistical models to predict overlay errors using patterned wafer geometry data and other relevant information includes selecting a training wafer set, measuring at multiple lithography steps and calculating geometry differences, applying a plurality of predictive models to the training wafer geometry differences and comparing predicted overlay to the measured overlay on the training wafer set. The most accurate predictive model is identified and the results fed-forward to the lithography scanner tool which can correct for these effects and reduce overlay errors during the wafer scan-and-expose processes.

Description

STATISTICAL OVERLAY ERROR PREDICTION FOR FEED FORWARD AND FEEDBACK CORRECTION OF OVERLAY ERRORS, ROOT CAUSE ANALYSIS AND PROCESS CONTROL
PRIORITY
[00013 The present application claims the benefit under 35 U.S.C. § 119(e) of United States Provisional Application Serial Number 61 /949,022, filed March 6, 2014, which is incorporated herein by reference.
FIELD OF THE INVENTION
[00023 The present invention is directed generally toward semiconductor wafer fabrication and more particularly toward error identification and correction methods in fabrication,
BACKGROUND OF THE INVENTION
[0003] A wafer generally goes through certain processes including deposition, etching., chemical- mechanical polishing (CMP) etc., before it is sent into a lithography scanner for exposure. Overlay errors are measured after the exposure using tools such as TWiNSCAN, Archer 500 or some other appropriate device.
[0004] Lithography overlay and critical dimension uniformity (CDU) are critical parameters in semiconductor manufacturing which can adversely affect integrated circuit performance and wafer yield. Overlay errors can be caused by lithography scanner tools, mask or reticle, and process Induced wafer geometry changes during scan and expose operation or other similar sources. With shrinking logic and memory device dimensions, overlay errors increasingly consume a significant fraction of the total overlay budget for critical layers. Significant efforts have been expended to identify and minimize systematic sources of overlay errors.
[0005] One method of minimizing systematic overlay errors is to use high resolution wafer geometry measurements to Identify and monitor wafer fabrication processes and identify wafer geometry changes that can be fed forward to the scanner to counteract the impact of the wafer geometry changes (along with other correctible factors) during the scan and expose operation. [0006] Analytical mechanics models, numerical finite-element models and other such methodologies have been used to make overlay predictions. However these methods suffer from the high complexity of the physical processes. Furthermore, they impact the wafer geometry that they seek to model and may not be usable to consistently predict reliable scanner corrections to counteract incoming wafer geometry changes.
[0007] Consequently, it would be advantageous if a method and apparatus existed that is suitable for consistently predicting overlay errors in a consistent wafer fabrication process and apply appropriate corrections to subsequent wafer fabrications.
SUMMARY OF THE INVENTION
[0008] Accordingly, the present invention is directed to a novel method and apparatus for consistently predicting overlay errors in a consistent wafer fabrication process and apply appropriate corrections to subsequent wafer fabrications.
[0009] in at least one embodiment, an overlay prediction system accurately predicts corrections by determining wafer geometry changes based on measurements of the wafer before and after lithography processes, applying a plurality of predictive models and comparing the predictive models to actual overlay errors to determine which predictive model produces the most accurate result. The identified predictive model is then used to predict overlay errors in subsequent wafer fabrication for the same batch of wafers. In another embodiment, a validation wafer is used to verify the identified predictive model,
[0010] t is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles. BRIEF DESCRIPTION OF THE DRAWINGS
{001 1 ] The numerous advantages of the present invention may be better understood by those skilled in the art by reference to the accompanying figures in which:
FIG. 1 shows a block diagram of a lithographic computer system useful for implementing at least one embodiment of the present Invention;
FIG. 2 shows a flowchart of a method for error prediction in a semiconductor wafer fabrication process;
FIG. 3 shows an exemplary output of an error prediction process according to at least one embodiment of the present invention;
FIG. 4 shows a block diagram of a neural network according to at least one embodiment of the present invention;
DETAILED DESCRIPTION OF THE INVENTION
{00123 Reference will now be made in detail to the subject matter disclosed, which is illustrated in the accompanying drawings. The scope of the invention is limited only by the claims; numerous alternatives, modifications and equivalents are encompassed. For the purpose of clarity, technical material that is known in the technical fields related to the embodiments has not been described in detail to avoid unnecessarily obscuring the description.
[0013] Referring to FIG. 1 , a block diagram of a lithographic computer system useful for implementing at least one embodiment of the present invention is shown. In at least one embodiment of the present invention, a computer system for scanning wafers and determining a predictive model of overlay errors in a wafer fabrication process includes a processor 100, memory 102 connected to the processor 100 for storing and executin computer executable program code and a camera 106 or other wafer scanning device for scanning a wafer 108 geometry and for analyzing overlay errors in a wafer 108 after an overlay exposure process. The computer system may also include a data storage device 104 connected to the processor 100 for storing predictive models and the results of applying such predictive models to a scanned wafer 108 geometry.
{0014] Referring to FiG. 2, a flowchart of a method for error prediction in a semiconductor wafer fabrication process is shown. In at least one embodiment of the present invention, one or more training wafers are selected 200 from a batch of productio wafers 214 produced by or during the same or substantially similar fabrication process. In at least one embodiment, the batch of wafers produced by or during the same fabrication process are also intended for the same scan-and-expose overlay procedures.
[00153 A dynamically smart sampling strategy may be employed to select training wafers. Patterned wafer geometry parameters such as wafer shape and geometry are obtained 202 for the training wafers using a patterned wafer geometry metrology tool. Training wafers may also undergo homogeneity testing, if the training wafers behave heterogeneously (for example due to different chambers of a multi-chamber process tool imparting different process signatures on the wafers in a single lot), statistical clustering techniques such as K -means and Gaussian mixture model may be applied to separate training wafers into several homogenous groups. Homogeneity is critical for determining a replicatable predictive model
[00 63 A predictive modeling engine runs advanced predictive models including but not limited to neural network, random forest, boosted regression tree, support vector machine and generalized linear models. Those models take a large number of process dependent variables, including a multitude of high spatial resolution wafer geometry parameters, as input variables such as but not limited to wafer flatness, thickness, shape, and their first or higher order derivatives, difference in shape (post- process minus pre-process), shape residual {post 2nd order removal) and other relevant process information (such as but not limited to chip layout, film-stack thickness and other properties, lithography scanner settings, etc.) Different statistic models have different assumptions and restrictions on the function space .
[00173 The predictive results from statistical models help engineers understand the contribution of and correlation between various process factors to overlay errors at downstream scan-arid -expose operations. The fitting parameters of the predictive model can trigger further investigation of the relationship between the wafer geometry changes and overlay errors.
[0018] A overla process is performed on the one or more training wafers and the one or more training wafers are analyzed 204 for actual overlay errors. The measured lithography overlay errors are used to develop complex highly non- linear relationships or predictive models intended to minimize overlay errors. The actual overlay errors are then compared 206 to the predicted overlay errors based on the predictive models in real time to produce a candidate predictive model that most closely matches the actual overlay errors. The prediction accuracy is measured by Pearson correlation between the predicted overlay errors and the actual overlay errors. The model with the best prediction accuracy will be retained as the candidate model.
[0019] The predictive methodology of the present invention Is point-to-point geometry information at a particular wafer coordinate corresponds to an overlay error at wafer coordinate. The statisticall predictive models allow for flexible experimentation. The number of training wafers and the number of sample locations on the training wafers can be gradually increased until reaching reliable prediction performance. In the training phase, wafer geometry and process characteristics of interest are identified. Different sampling strategies based on those characteristics may be rapidly tested to converge to the most optimal prediction performance in terms of accuracy and reliability. Optimal sampling may define the minimum number of points at whic wafer geometry changes need to be measured and thus reduce cycle time and increase tool productivity,
[0020] Once a candidate model is determined, one or more validation wafers are selected 212 from the production wafers 214 and patterned wafer geometry parameters are obtained 202 for the validation wafers using a patterned wafer geometry metrology tool. An overlay process is performed on the one or more validation wafers and the one or more validation wafers are analyzed 210 for actual overlay errors. The candidate model predicts the overlay errors and compares them with the actual overlay errors on the validation wafers, if the prediction accuracy satisfies 207 certain thresholds based on the overlay budget and other considerations, the candidate model is considered to be valid and ready to be deployed 208 to predict overlay errors on other production wafers which share simitar processing conditions with the training and validation wafers.
[0021 ] Once the candidate model is validated 207, the remaining production wafers 216 are scanned 218 with a patterned wafer geometry metrology tool to determine 220 wafer geometry parameters. Based on the wafer geometry parameters and the deployed predictive model 208, the system predicts 222 an overlay error for the remaining production wafers and adjusts 224 the lithography scanner to correct the predicted overlay error. Point-to-point prediction is crucial for feeding forward the predicted overlay, applying the adjustment 224 and hence reducing the actual overlay error after the exposure.
[0022] Methods according to the present invention may allow a lithography production process to preemptively correct for overlay errors without intensive processing of each individual wafer,
[0023] Referring to FIG. 3, an exemplary output of an error prediction process according to at least one embodiment of the present invention is shown. Current linear regression prediction methodolog predicts an overlay error pattern 302 substantially different from an actual overlay error pattern 300. By contrast, methods according to the present invention using advanced predictive models generate an overlay error pattern 304 more closely correlated with the actual overlay error pattern 300. In this exemplary embodiment, the advanced predictive model utilized neural networks.
[0024] Referring to FIG, 4, a block diagram of a neural network according to at least one embodiment of the present invention is shown. In at least one embodiment,, a neural network comprises a plurality of input variables 400, X2 402, X3 404, >Q 406 such as IPD, shape, slope etc. The linear combination Zj -∑ 2
Figure imgf000008_0001
is passed as a stimulus to neuron Hi 408 in the hidden layer. An activation function embedded in each neuron abstractly represents a biological rate of action potential firing in the neuron. A commonly used activation function is the SIGMOID function Oj™ _ . y where Oj is the output from neuron Hj. The predicted overlay output cell Y 412 is the collection of the outcomes from all neurons Hi 408 . . . ¾i 410 in the hidden layer. In at least one embodiment, the overlay output cell is defined by y™∑ ;1 ¾¾- overlay output cell 412 and the input variable 400, 402, 404, 406 may exhibit highly non-linear structure.
[0025] Mathematical structure in a neural network can also suggest how the output behaves depending on certain input. Assuming a neural network with two input variables, for example X 400 and X2 402, and three neurons 408, 410 in the hidden layer, the first derivative of output Y 412 with reference to the first input variable X1 400 is defined by:
dY .
~rr ~ VjWjtf OiCl - i } + v2w-i">0->{i - 0<*) + t?3 (I - 0·¾) 0026] The result is a three mode curve, suggesting the overlay is sensitive to input variable X1 400 in three areas. An engineer may determine which conditions are most pertinent to overlay errors in a particular geometry and how an overlay reacts to geometry parameters.
£0027] In one embodiment, the relative importance of each input variable in a predictive model is determined by a procedure in a statistical package, input variables are ranked based on the reduction in variance of the predicted overlay attributable to each variable, via a sensitivity analysis. A prediction score may be defined by: cores /v(y) which is the ratio of expected variance of predicted overlay given certain variable value X. to the unconditional variance of the predicted overlay. Once the relative importance of each variable is determined, engineers can modify the production process or further Investigate why other variables affect overlay.
[0028] n a real world production system, wafers may have characteristics that are non-uniform such as film stress and higher order in-plane displacement as a result of non-uniform variation in wafer geometry and process variations. Therefore, the correlatio between input variables such as wafer geometry and output such as overlay can exhibit convoluted non-linearity. In that case, a predictive model which models the non-linear correlation can improve prediction accuracy. Neural networks can therefore improve predictive accuracy over linear regression.
[0029] Methods according to at least one embodiment of the present invention may be employed to study a relationship between wafer geometry changes and overlay error, and identify dominant geometry components that affect lithography overlay and lithography critical dimension uniformity.
[0030] Methods according to at least one embodiment of the present invention may be used to identify a root cause of overlay errors. All process related parameters, such as wafer flatness, thickness, shape, and the first or higher order derivatives of those parameters, differences in shape, and shape residual may be considered using the predictive model process described herein. Some appropriate variable select algorithm, such as ElastlcNet, forward-stepwise regression or least angle regression, may systematically rule out non-essential or noisy parameters in the predictive model selection process and converge to the more impactful sources of overlay errors. Similar methods ma be applied to other relevant process parameters such as chip layout, film-stack thickness and other film-stack properties, lithography scanner settings, including translation, rotation, magnification, orthogonality., wafer tilt, etc.
[0031 ] Methods according to at least one embodiment of the present invention may reveal process variations that can be used to monitor process excursions. Clustering techniques can separate wafers into different groups. Assuming a stable production process results in similar overlay maps within each group, engineers may identify a process excursion by monitoring the characteristics of each group. {0032] Systems according to embodiments of the present invention may leverage statistically predictive models, which in addition to improved overlay correction prediction capability may also identify the impact of wafer fabrication unit processes such as scan-and-expose including reticle effects, chemical mechanical polishing, rapid thermal processing and other semiconductor processes that contribute to overlay errors.
[0033] is believed that the present invention and many of its attendant advantages will be understood by the foregoing description of embodiments of the present invention, and it will be apparent that various changes may be made in the form, construction, and arrangement of the components thereof without departing from the scope and spirit of the invention or without sacrificing all of its material advantages. The form herein before described being merely an explanatory embodiment thereof, it is the intention of the following claims to encompass and include such changes.

Claims

CLAIMS What is claimed is:
Claim 1. A computer system comprising:
a processor;
memory connected to the processor; and
computer executable program code configured to execute on the processor, wherein the computer executable program code configures the processor to: receive one or more training wafer profiles corresponding to one or more geometry parameters of one or more training wafers;
apply a plurality of overlay error predictive models to the training wafer profiles to produce corresponding predicted overlay error profiles;
receive one or more training wafer error profiles;
compare the training wafer error profiles to the plurality of predicted overlay error profiles to determine a best fit overlay error predictive model from the plurality of overla error predictive models; and determine a correction to a lithographic overlay process based on the best fit overlay error predictive model.
Claim 2, The computer system of Claim 1 , wherein the computer executable program code further configures the processor to:
receive one or more validation wafer profiles corresponding to one or more geometry parameters of one or more validation wafers;
apply the best fit overlay error predictive model to the validation wafer profiles to produce one or more predicted valid overlay error profiles;
receive one or more validation wafer error profiles;
compare the validation wafer error profiles to the predicted valid overlay error profiles;
determine that the validation wafer error profiles differ from the predicted valid overlay error profiles by a quantity less than some threshold.
Claim 3. The computer system of Claim 1 , wherein the computer executable program code further configures the processor to apply the correction to subsequent lithographic overlay processes of one or more production wafers.
Claim 4. The computer system of Claim 1 , wherein applying the plurality of overlay error predictive models comprises executing a neural network based on the one or more geometry parameters.
Claim 5. The computer system of Claim 1 , wherein applying the plurality of overlay error predictive models comprises executing a random forest algorithm on the one or more geometry parameters.
Claim 6. The computer system of Claim 1 , wherein the computer executable program code f urther configures the processor to:
determine that the training wafer profiles represent heterogeneous geometry parameters; and
organize the training wafer profiles into homogeneous geometry parameters.
Claim 7. The computer system of Claim 1 , wherein the computer executable program code further configures the processor to analyze the one or more training wafer profiles to determine a primary geometry parameter responsible for an overlay error.
Claim 8. A metrology system comprising:
a processor;
a wafer scanning device connected to the processor;
memory connected to the processor; and
computer executable program code configured to execute on the processor, wherein the computer executable program code configures the processor to: scan one or more training wafers to determine one or more geometry parameters of the training wafers;
produce one or more training wafer profiles corresponding to the one or more geometry parameters of one or more training wafers; apply a plurality of overlay error predictive models to the training wafer profiles to produce corresponding predicted overlay error profiles;
scan the one or more training wafer to determine one or more training wafer error profiles error profiles;
compare the training wafer error profiles to the plurality of predicted overlay error profiles to determine a best fit overlay error predictive model from the plurality of overlay error predictive models; and determine a correction to a lithographic overlay process based on the best fit overlay error predictive model.
Claim 9. The metrology system of Claim S, wherein the computer executable program code further configures the processor to:
scan one or more validation wafers to determine one or more validation wafer profiles corresponding to one or more geometry parameters of one or more validation wafers;
apply the best fit overlay error predictive model to the validation wafer profiles to produce one or more predicted valid overlay error profiles;
scan one or more validation wafers to determine one or more validation wafer error profiles; compare the validation wafer error profiles to th predicted valid overlay error profiles;
determine that the validation wafer error profiles differ from the predicted valid overlay error profiles by a quantity less than some threshold.
Claim 10. The metrology system of Claim 8, further comprising a lithographic overlay exposure device connected to the processor, wherein the computer executable program code further configures the processor to apply the correction to the lithographic overlay exposure device during a subsequent lithographic overlay processes of one or more production wafers.
Claim 1 1. The metrology system of Claim 8, wherein applyin the plurality of overlay error predictive models comprises executing a neural network based on the one or more geometry parameters.
Claim 12. The metrology system of Claim 8, wherein applying the plurality of overlay error predictive models comprises executing a random forest algorithm on the one or more geometry parameters.
Claim 13. The metrology system of Claim 8, wherein the computer executable program code further configures the processor to:
determine that the training wafer profiles represent heterogeneous geometry parameters; and
organize the training wafer profiles into homogeneous geometry parameters.
Claim 14. The metrology system of Claim 8, wherein the computer executable program code further configures the processor to analyze the one or more training wafer profiles to determine a primary geometry parameter responsible for an overlay error.
Claim 5. A method for compensating for overlay errors comprising:
scanning one or more training wafers to determine one or more geometry parameters of the training wafers;
producing one or more training wafer profiles corresponding to the one or more geometry parameters of one or more training wafers;
applying a plurality of overlay error predictive models to the training wafer profiles to produce corresponding predicted overlay error profiles; scanning the one or more training wafer to determine one or more training wafer error profiles error profiles;
comparing the training wafer error profiles to the plurality of predicted overlay error profiles to determine a best fit overlay error predictive model from the plurality of overlay error predictive models; and
determining a correction to a lithographic overlay process based on the best fit overlay error predictive model.
Claim 16. The method of Claim 15, further comprising
scanning one or more validation wafers to determine one or more validation wafer profiles corresponding to one or more geometry parameters of one or more validation wafers;
applying the best fit overla error predictive model to the validation wafer profiles to produce one or more predicted valid overlay error profiles;
scanning one or more validation wafers to determine one or more validation wafer error profiles;
compare the validation wafer error profiles to the predicted valid overlay error profiles;
determine that the validation wafer error profiles differ from the predicted valid overlay error profiles by a quantity less than some threshold.
Claim 17. The method of Claim 15, wherein applying the plurality of overlay error predictive models comprises executing a neural network based on the one or more geometry parameters.
Claim 18, The method of Claim 15, wherein applying the plurality of overlay error predictive models comprises executing a random forest algorithm on the one or more geometry parameters.
Claim: 19. The method of Claim 15, further comprising:
determining that the training wafer profiles represent heterogeneous geometry parameters; and
organizing the training wafer profiles into homogeneous geometry parameters.
Claim 20. The method of Claim 15» further comprising analyzing the one or more training wafer profiles to determine a primary geometry parameter responsible for an overlay error.
PCT/US2015/018884 2014-03-06 2015-03-05 Statistical overlay error prediction for feed forward and feedback correction of overlay errors, root cause analysis and process control WO2015134709A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP15758366.7A EP3114705B1 (en) 2014-03-06 2015-03-05 Metrology system and method for compensating for overlay errors by the metrology system
JP2016555779A JP6490094B2 (en) 2014-03-06 2015-03-05 Overlay error feedforward and feedback correction, root cause analysis and process control statistical overlay error prediction
US15/123,980 US10545412B2 (en) 2014-03-06 2015-03-05 Statistical overlay error prediction for feed forward and feedback correction of overlay errors, root cause analysis and process control
KR1020167025800A KR102179988B1 (en) 2014-03-06 2015-03-05 Statistical overlay error prediction for feed forward and feedback correction of overlay errors, root cause analysis and process control

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201461949022P 2014-03-06 2014-03-06
US61/949,022 2014-03-06
US14/220,665 2014-03-20
US14/220,665 US9087176B1 (en) 2014-03-06 2014-03-20 Statistical overlay error prediction for feed forward and feedback correction of overlay errors, root cause analysis and process control

Publications (1)

Publication Number Publication Date
WO2015134709A1 true WO2015134709A1 (en) 2015-09-11

Family

ID=53540163

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2015/018884 WO2015134709A1 (en) 2014-03-06 2015-03-05 Statistical overlay error prediction for feed forward and feedback correction of overlay errors, root cause analysis and process control

Country Status (6)

Country Link
US (2) US9087176B1 (en)
EP (1) EP3114705B1 (en)
JP (1) JP6490094B2 (en)
KR (1) KR102179988B1 (en)
TW (1) TWI651789B (en)
WO (1) WO2015134709A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180110025A (en) * 2016-03-11 2018-10-08 에이에스엠엘 네델란즈 비.브이. METHOD FOR COMPUTING CALCULATIONS FOR CONTROLLING MANUFACTURING PROCESS, METERING DEVICE
US11954615B2 (en) 2019-10-16 2024-04-09 International Business Machines Corporation Model management for non-stationary systems

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5960198B2 (en) 2013-07-02 2016-08-02 キヤノン株式会社 Pattern forming method, lithographic apparatus, lithographic system, and article manufacturing method
US10379447B2 (en) * 2013-07-10 2019-08-13 Qoniac Gmbh Method and apparatus for simulation of lithography overlay
US11366397B2 (en) 2013-07-10 2022-06-21 Qoniac Gmbh Method and apparatus for simulation of lithography overlay
US10576603B2 (en) * 2014-04-22 2020-03-03 Kla-Tencor Corporation Patterned wafer geometry measurements for semiconductor process controls
EP3748669A1 (en) * 2014-06-24 2020-12-09 Kla-Tencor Corporation Predictive modeling based focus error prediction
US10430719B2 (en) 2014-11-25 2019-10-01 Stream Mosaic, Inc. Process control techniques for semiconductor manufacturing processes
KR102521159B1 (en) 2014-11-25 2023-04-13 피디에프 솔루션즈, 인코포레이티드 Improved process control techniques for semiconductor manufacturing processes
US10036964B2 (en) 2015-02-15 2018-07-31 Kla-Tencor Corporation Prediction based chucking and lithography control optimization
US10024654B2 (en) 2015-04-06 2018-07-17 Kla-Tencor Corporation Method and system for determining in-plane distortions in a substrate
US9779202B2 (en) 2015-06-22 2017-10-03 Kla-Tencor Corporation Process-induced asymmetry detection, quantification, and control using patterned wafer geometry measurements
US9916965B2 (en) * 2015-12-31 2018-03-13 Kla-Tencor Corp. Hybrid inspectors
KR20180115299A (en) * 2016-02-22 2018-10-22 에이에스엠엘 네델란즈 비.브이. Separation of contributions to measurement data
US10068323B2 (en) * 2016-04-10 2018-09-04 Kla-Tencor Corporation Aware system, method and computer program product for detecting overlay-related defects in multi-patterned fabricated devices
SG11201810017VA (en) * 2016-06-02 2018-12-28 Universal Instruments Corp Semiconductor die offset compensation variation
US10475712B2 (en) 2016-09-30 2019-11-12 Kla-Tencor Corporation System and method for process-induced distortion prediction during wafer deposition
JP6884855B2 (en) 2016-10-21 2021-06-09 エーエスエムエル ネザーランズ ビー．ブイ． Methods for determining corrections for the patterning process, device manufacturing methods, control systems for lithographic equipment, and lithographic equipment.
US10409171B2 (en) * 2017-01-25 2019-09-10 Kla-Tencor Corporation Overlay control with non-zero offset prediction
KR102432667B1 (en) 2017-05-15 2022-08-17 삼성전자주식회사 method for correcting overlay and control system
US11029673B2 (en) 2017-06-13 2021-06-08 Pdf Solutions, Inc. Generating robust machine learning predictions for semiconductor manufacturing processes
US11022642B2 (en) 2017-08-25 2021-06-01 Pdf Solutions, Inc. Semiconductor yield prediction
WO2019129485A1 (en) 2017-12-29 2019-07-04 Asml Netherlands B.V. Method and device for determining adjustments to sensitivity parameters
US11775714B2 (en) 2018-03-09 2023-10-03 Pdf Solutions, Inc. Rational decision-making tool for semiconductor processes
US11029359B2 (en) 2018-03-09 2021-06-08 Pdf Solutions, Inc. Failure detection and classsification using sensor data and/or measurement data
CN110365503B (en) * 2018-03-26 2022-08-19 华为技术有限公司 Index determination method and related equipment thereof
US10777470B2 (en) 2018-03-27 2020-09-15 Pdf Solutions, Inc. Selective inclusion/exclusion of semiconductor chips in accelerated failure tests
US11454949B2 (en) * 2018-03-28 2022-09-27 Kla Corporation Auto-correlation of wafer characterization data and generation of composite wafer metrics during semiconductor device fabrication
DE102018207880A1 (en) * 2018-05-18 2019-11-21 Carl Zeiss Smt Gmbh Method and apparatus for evaluating an unknown effect of defects of an element of a photolithography process
CN108897219B (en) * 2018-07-11 2021-02-09 杭州电子科技大学 Chemical uncertain industrial process constraint prediction control method
US11094053B2 (en) * 2018-10-08 2021-08-17 Kla Corporation Deep learning based adaptive regions of interest for critical dimension measurements of semiconductor substrates
KR20230130767A (en) * 2018-11-07 2023-09-12 에이에스엠엘 네델란즈 비.브이. Determining a correction to a process
US10990019B2 (en) * 2019-04-09 2021-04-27 Kla Corporation Stochastic reticle defect dispositioning
KR20210007275A (en) 2019-07-10 2021-01-20 삼성전자주식회사 Overlay correcting method, and photo-lithography method, semiconductor device manufacturing method and scanner system based on the correcting method
CN110470263A (en) * 2019-08-02 2019-11-19 天津大学 A kind of revolving body measurement system error compensation method based on gradient boosted tree
JP7545278B2 (en) 2020-09-25 2024-09-04 キヤノン株式会社 Method for determining set of sample shot areas, method for obtaining measurement values, information processing apparatus, lithography apparatus, program, and article manufacturing method
CN112257337B (en) * 2020-10-14 2022-09-16 上海工程技术大学 Prediction method for removal rate of wafer CMP (chemical mechanical polishing) material of GMDH (Gaussian mixture distribution) neural network
US11288115B1 (en) 2020-11-05 2022-03-29 International Business Machines Corporation Error analysis of a predictive model
US11829077B2 (en) * 2020-12-11 2023-11-28 Kla Corporation System and method for determining post bonding overlay
US11669079B2 (en) * 2021-07-12 2023-06-06 Tokyo Electron Limited Tool health monitoring and classifications with virtual metrology and incoming wafer monitoring enhancements
US11782411B2 (en) 2021-07-28 2023-10-10 Kla Corporation System and method for mitigating overlay distortion patterns caused by a wafer bonding tool
CN113591395B (en) * 2021-08-11 2024-01-30 重庆大学 Modeling method of thermal error prediction model and intelligent thermal error control system framework based on haze-edge-fog-cloud computing
JP2023053800A (en) * 2021-10-01 2023-04-13 キヤノン株式会社 Method for determining arrangement of a plurality of shot areas on substrate, exposure method, exposure device, article production method, program and information processing device
TWI790795B (en) * 2021-10-29 2023-01-21 財團法人資訊工業策進會 Model adjustment method, model adjustment system and non-transitory computer readable medium
CN114999182B (en) * 2022-05-25 2023-07-04 中国人民解放军国防科技大学 Traffic flow prediction method, device and equipment based on LSTM feedback mechanism

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030223630A1 (en) * 2002-02-15 2003-12-04 Kla-Tencor Corporation Overlay metrology and control method
US7042552B1 (en) 2004-11-17 2006-05-09 Asml Netherlands B.V. Alignment strategy optimization method
US20090063378A1 (en) * 2007-08-31 2009-03-05 Kla-Tencor Technologies Corporation Apparatus and methods for predicting a semiconductor parameter across an area of a wafer
US20110154272A1 (en) * 2009-12-17 2011-06-23 Industrial Technology Research Institute Method for designing two-dimensional array overlay target sets and method and system for measuring overlay errors using the same
US20130060354A1 (en) * 2011-09-01 2013-03-07 Kla-Tencor Corporation Method and system for detecting and correcting problematic advanced process control parameters
WO2013178404A2 (en) * 2012-05-29 2013-12-05 Asml Netherlands B.V. A method to determine the usefulness of alignment marks to correct overlay, and a combination of a lithographic apparatus and an overlay measurement system

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8017411B2 (en) * 2002-12-18 2011-09-13 GlobalFoundries, Inc. Dynamic adaptive sampling rate for model prediction
US7525638B2 (en) * 2005-03-23 2009-04-28 Asml Netherlands B.V. Lithographic apparatus and device manufacturing method
US8136068B2 (en) * 2008-09-30 2012-03-13 Cadence Design Systems, Inc. Methods, systems, and computer program products for implementing compact manufacturing models in electronic design automation
US8260449B2 (en) * 2008-11-06 2012-09-04 Micron Technology, Inc. Photolithography systems and associated methods of overlay error correction
DE102011078927B4 (en) * 2010-07-12 2019-01-31 Carl Zeiss Sms Ltd. Method for correcting errors of a photolithographic mask
KR101815975B1 (en) * 2011-07-27 2018-01-09 삼성전자주식회사 Apparatus and Method for Detecting Object Pose
US9354526B2 (en) 2011-10-11 2016-05-31 Kla-Tencor Corporation Overlay and semiconductor process control using a wafer geometry metric

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030223630A1 (en) * 2002-02-15 2003-12-04 Kla-Tencor Corporation Overlay metrology and control method
US7042552B1 (en) 2004-11-17 2006-05-09 Asml Netherlands B.V. Alignment strategy optimization method
US20090063378A1 (en) * 2007-08-31 2009-03-05 Kla-Tencor Technologies Corporation Apparatus and methods for predicting a semiconductor parameter across an area of a wafer
US20110154272A1 (en) * 2009-12-17 2011-06-23 Industrial Technology Research Institute Method for designing two-dimensional array overlay target sets and method and system for measuring overlay errors using the same
US20130060354A1 (en) * 2011-09-01 2013-03-07 Kla-Tencor Corporation Method and system for detecting and correcting problematic advanced process control parameters
WO2013178404A2 (en) * 2012-05-29 2013-12-05 Asml Netherlands B.V. A method to determine the usefulness of alignment marks to correct overlay, and a combination of a lithographic apparatus and an overlay measurement system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3114705A4

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180110025A (en) * 2016-03-11 2018-10-08 에이에스엠엘 네델란즈 비.브이. METHOD FOR COMPUTING CALCULATIONS FOR CONTROLLING MANUFACTURING PROCESS, METERING DEVICE
CN108713166A (en) * 2016-03-11 2018-10-26 Asml荷兰有限公司 Calculate method, measuring equipment, device making method and the modeling method of the correction for controlling manufacturing process
KR102162174B1 (en) 2016-03-11 2020-10-07 에이에스엠엘 네델란즈 비.브이. Method of calculating corrections to control manufacturing process, measurement apparatus, device manufacturing method and modeling method
US11022896B2 (en) 2016-03-11 2021-06-01 Asml Netherlands B.V. Mark position determination method
US11954615B2 (en) 2019-10-16 2024-04-09 International Business Machines Corporation Model management for non-stationary systems

Also Published As

Publication number Publication date
EP3114705B1 (en) 2022-11-23
TW201539602A (en) 2015-10-16
EP3114705A1 (en) 2017-01-11
JP6490094B2 (en) 2019-03-27
US10545412B2 (en) 2020-01-28
KR20160130243A (en) 2016-11-10
KR102179988B1 (en) 2020-11-17
EP3114705A4 (en) 2017-11-08
TWI651789B (en) 2019-02-21
JP2017514294A (en) 2017-06-01
US9087176B1 (en) 2015-07-21
US20170017162A1 (en) 2017-01-19

Similar Documents

Publication Publication Date Title
US9087176B1 (en) Statistical overlay error prediction for feed forward and feedback correction of overlay errors, root cause analysis and process control
US11520238B2 (en) Optimizing an apparatus for multi-stage processing of product units
CN107004060B (en) Improved process control techniques for semiconductor manufacturing processes
US9707660B2 (en) Predictive wafer modeling based focus error prediction using correlations of wafers
US20200050180A1 (en) Methods &amp; apparatus for controlling an industrial process
US10539882B2 (en) Methods and apparatus for obtaining diagnostic information, methods and apparatus for controlling an industrial process
KR102637430B1 (en) Signal-domain adaptation for instrumentation
JP2009075110A (en) Determination of profile parameter of structure using dispersion function for making process parameter associate with dispersion
JP6641372B2 (en) Determining important parameters using a high-dimensional variable selection model
JP7436589B2 (en) Method and apparatus for restoring the position of semiconductor components on a wafer
JP2024500887A (en) Prediction of electrical properties of semiconductor samples
US10481592B2 (en) Selecting manufacturing settings based on historical data from manufacturing tools
US12111355B2 (en) Semiconductor substrate yield prediction based on spectra data from multiple substrate dies
CN115795254A (en) Method and device for reconstructing the position of a semiconductor component on a wafer

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15758366

Country of ref document: EP

Kind code of ref document: A1

REEP Request for entry into the european phase

Ref document number: 2015758366

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2015758366

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2016555779

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 15123980

Country of ref document: US

ENP Entry into the national phase

Ref document number: 20167025800

Country of ref document: KR

Kind code of ref document: A