WO2015134638A1 - Integrated device comprising high density interconnects and redistribution layers - Google Patents

Integrated device comprising high density interconnects and redistribution layers Download PDF

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Publication number
WO2015134638A1
WO2015134638A1 PCT/US2015/018784 US2015018784W WO2015134638A1 WO 2015134638 A1 WO2015134638 A1 WO 2015134638A1 US 2015018784 W US2015018784 W US 2015018784W WO 2015134638 A1 WO2015134638 A1 WO 2015134638A1
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WIPO (PCT)
Prior art keywords
die
interconnects
implementations
integrated device
base portion
Prior art date
Application number
PCT/US2015/018784
Other languages
French (fr)
Inventor
Dong Wook Kim
Hong Bok We
Jae Sik Lee
Shiqun Gu
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Priority to EP15710373.0A priority Critical patent/EP3114707A1/en
Priority to CN201580011603.4A priority patent/CN106068558A/en
Priority to JP2016555342A priority patent/JP2017507495A/en
Publication of WO2015134638A1 publication Critical patent/WO2015134638A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Definitions

  • Various features relate to an integrated device that includes high density interconnects and redistributions layers.
  • FIG. 1 illustrates a conventional integrated package 100 that includes a substrate 102, a first die 106, a second die 108, a first set of solder bails 1 16, a second set of solder bails 1 18, and a third set of solder balls 120.
  • the first die 106 is coupled to the substrate 102 through the first set of solder balls 116.
  • the second die 108 is coupled to the substrate 1 02 through the second set of solder bails 1 18.
  • the third set of solder bails 120 is coupled to the substrate 102.
  • the third set of solder balls 120 is coupled to a printed circuit board (PCB) (not shown).
  • PCB printed circuit board
  • the substrate 102 of the integrated package 100 of FIG. I is typically made of an organic laminate (e.g., rigid or flexible), or a silicon (Si) interposer.
  • organic laminate e.g., rigid or flexible
  • Si silicon
  • solder bails as a coupling method between a die and a substrate limits the density of the connection that can exist between a die and a substrate, as the minimum spacing required between solder balls is often greater than the minimum spacing required between traces and/or vias on a substrate.
  • tool alignment tolerances and the shifting of dies can cause inaccuracy hi the placement of dies on a substrate.
  • big landing pads must be provided to ensure that there is proper connection of the dies. These big landing pads can take up valuable space in the integrated device and. add unnec unfairy cost to the manufacturing of axi integrated device.
  • a first example provides axi integrated device that includes a base portion for the integrated device, a first die coupled to a first surface of the base portion, and an underfill between the first die and the base portion.
  • the base portion includes a dielectric layer, axid a set of redistribution metal layers.
  • the integrated device further includes an encapsulation material that encapsulates the first die.
  • the integrated device further includes a second die coupled to the first surface of the base portion.
  • the integrated device further includes a set of interconnects on the base portion, the set of interconnects electrically coupling the first die and the second die.
  • the first die includes a first set of interconnect pillars and the second die includes a second set of interconnect pillars.
  • the set of interconnects is coupled to the first set of interconnects pillars and the second set of interconnect pillars while bypassing a bump pad and/or landing pad.
  • the set of interconnects has a first pitch that is about 40 microns ( ⁇ ) or less.
  • the underfill is also between the second die and. the base portion, [0012]
  • the first die is a first wafer level die.
  • the first die includes a first set of interconnect pillars, the first die is coupled to the set of redistribution metal layers through the first set of interconnect pillars.
  • the first set of interconnect pillars has a first pitch that is about 40 microns ( ⁇ ) or less.
  • the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a srnartphone, a personal digital assistant, a fixed location terminal, a tablet, computer, and/or a laptop computer.
  • a second example provides an apparatus that includes a base portion for an integrated device.
  • the base portion includes a dielectric layer, and a redistribution means.
  • the apparatus further includes a first die coupled to a first surface of the base portion, a means for encapsulating an area between the first die and the base portio .
  • the apparatus further includes an encapsulation means that encapsulates the first die.
  • the apparatus further includes a second die coupled to the first surface of the base portion.
  • the apparatus further includes a set of interconnects on the base portion.
  • the set of interconnects electrically couples the first die and the second die.
  • the first die includes a first set. of interconnect, pillars.
  • the second die includes a second set of interconnect pillars.
  • the set of interconnects is coupled to the first set of interconnects pillars and the second set of interconnect pillars while bypassing a landing pad.
  • the set. of interconnects includes a first, pitch that is about. 40 microns ( ⁇ ) or less.
  • the first die is a first wafer level die.
  • the first, die includes a first set of interconnect pillars.
  • the first die is coupled to the redistribution means through the first set of interconnect pillars.
  • the first set of interconnect pillars includes a first pitch that is about 40 microns (fim) or less.
  • the apparatus is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a srnartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.
  • a third example provides a method for providing an integrated device.
  • the method forms a base portion for the integrated device, where forming the base portion includes forming a dielectric layer, and. forming a set of redistribution metal layers.
  • the method provides a first die on a first surface of the base portion.
  • the method forms an underfill between the first die and the base portion.
  • the method further forms an encapsulation material that encapsulates the first die.
  • the method provides a second die on the first surface of the base portion.
  • the method forms a set of interconnects on the base portion.
  • the set of interconnects electrically coupling the first die and the second die.
  • the first die includes a first set of interconnect pillars and the second die includes a second set of interconnect pillars.
  • the set of interconnects is coupled to the first set of interconnects pillars and the second set of interconnect pillars while bypassing a landing pad.
  • the set of interconnects includes a first pitch that is about 40 microns ( ⁇ ) or less.
  • the first die is a first wafer level die
  • the first die includes a first set of interconnect pillars.
  • the first die is coupled to the set of redistribution metal layers through the first set of interconnect pillars.
  • the first set of interconnect pillars includes a first pitch that is about 40 microns ( ⁇ ) or less.
  • the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.
  • FIG, 1 illustrates a profile view of a conventional integrated device.
  • FIG. 2 illustrates an example of an integrated device.
  • FIG. 3 illustrates an example of a die.
  • FIG. 4 illustrates an example of a die that includes a through substrate via.
  • FIG. 5 illustrates an example of an integrated device.
  • FIG. 6 illustrates an example of an integrated device.
  • FIG. 7A illustrates part of an exemplary sequence for providing / manufacturing an integrated device.
  • FIG. 7B illustrates part of an exemplary sequence for providing / ma ufacturing an integrated device.
  • FIG. 7C illustrates part of an exemplar ⁇ ' sequence for providing / manufacturing an integrated device.
  • FIG. 7D illustrates part of an exemplary sequence for providing / manufacturing an integrated device.
  • FIG. 8A illustrates part of an exemplary sequence for providing / manufacturing an integrated device.
  • FIG. 8B illustrates part of an exemplar ⁇ ' sequence for providing / manufacturing an integrated device.
  • FIG. 8C illustrates part of an exemplary sequence for providing / manufacturing an integrated device.
  • FIG. 8D illustrates part of an exemplary sequence for providing / manufacturing an integrated device.
  • FIG. 9 illustrates an exemplary method for providing / manufacturing an integrated device.
  • FIG. I OA illustrates part of an exemplary sequence for providing / manufacturing an integrated device.
  • FIG. 10B illustrates part of an exemplary sequence for providing / manufacturing an integrated device.
  • FIG. IOC illustrates part of an exemplary sequence for providing / manufacturing an integrated device.
  • FIG. 1 1 illustrates various electroxiic devices that may integrate a semiconductor device, a die, an integrated circuit and/or PCB described herein.
  • an integrated device e.g., integrated package
  • a first die e.g., first wafer level die
  • the base portion includes a dielectric layer, and a set of redistribution metal layers.
  • the integrated device further includes an encapsulation material thai encapsulates the first die.
  • the integrated device further includes a second die (e.g., second wafer level die) coupled to the first surface of the base portio .
  • the integrated device further includes a set of interconnects on the base portion, the set of interconnects electrically coupling the first die and the second die.
  • the first, die includes a first set of interconnect pillars and the second die includes a second set of interconnect pillars.
  • the set of interconnects is coupled, to the first set of interconnects pillars and the second set of interconnect pillars while bypassing a landing pad (e.g., bump pad).
  • the set of interconnects has a first pitch of about 40 microns ( a m) or less.
  • the underfill is also between the second die and. the base portion.
  • FIG. 2 conceptually illustrates an example of a side view of an integrated device (e.g., semiconductor device, integrated package) thai includes several dies.
  • FIG. 2 illustrates an integrated device 200 (e.g., integrated package) that includes a dielectric layer 202, a first set of solder balls 204, a first die 206, a second die 208, an encapsulation material 220, and an underfill 222.
  • the encapsulation material 220 may include one of at least a mold, an epoxy and/or a polymer fill.
  • the dies may represent different types of dies, such as memory dies, and/or processors.
  • the first die 206 and/or the second die 208 are wafer level dies. Dies are further described in detail below with reference to FIGS. 3-4.
  • the dielectric layer 202 may include one dielectric layer or several dielectric layers.
  • the dielectric layer 202 is an insulation layer.
  • FIG. 2 illustrates that the dielectric layer 202 includes a set of metal layers.
  • the dielectric layer 202 includes a first set of redistribution interconnects 230, a first under bump metallization (UBM) layer 232, a second set of redistribution interconnects 240, a second under bump metallization (UBM) layer 242, a third set of redistribution interconnects 250, a third under bump metallization (UBM) layer 252, a fourth set of redistribution interconnects 260, a fourth under bump metallization (UBM) layer 262, and a fifth set of redistribution interconnects 280,
  • the first, second, third, and fourth sets of redistribution interconnects 230. 240, 250, and 260 are redistribution layers hi the dielectric layer 202.
  • the redis is redistribution layers
  • the fifth set of redistribution interconnects 280 is a metal layer on the dielectric layer 202 (e.g., on surface of dielectric layer 202).
  • the first, second, third, and fourth sets of redistribution interconnects 230, 240, 250, and 260 have respectively, a first pitch, a second pitch, a third pitch, and a fourth pitch.
  • the fifth set of redistribution interconnects 280 has a fifth pitch that is different than the first pitch, the second pitch, the third pitch, and/or the fourth pitch. In some implementations, the fifth pitch is less than the first pitch, the second pitch, the third pitch, and/or the fourth pitch.
  • the fifth set of redistribution interconnects 280 is coupled to the first set of interconnects 216 and the second set of interconnects 218.
  • the fifth set of redistribution interconnects 280 includes a set of high density interconnects.
  • the fifth set of interconnects 280 includes a first pitch that is about 40 microns ( ⁇ ) or less.
  • the first die 206 is coupled to a first surface of the dielectric layer 202 through the first set of interconnects 216,
  • the first set of interconnects 216 are metal pillars (e.g., metal layers).
  • the metal pillars are copper pillars.
  • the first die 206 is electrically coupled to at least one of the set of solder bails 204 through the first set of interconnects 216, the first set of redistribution interconnects 230, the first UBM layer 232, the second set of redistribution interconnects 240, and/or the second UBM layer 242.
  • the second die 208 is coupled to the first surface of the dielectric layer 202 through the second set of interconnects 218.
  • the second set of interconnects 218 are metal pillars (e.g., metal layers).
  • the metal pillars are copper pillars.
  • the second die 208 is electrically coupled to at least one of the set of solder bails 204 through the second set of interconnects 218, the third set of redistribution interconnects 250, and/or the third UBM layer 252.
  • the first die 206 may be electrically coupled to the second die 208 through the fifth set of redistribution interconnects 280.
  • FIG. 2 also illustrates that the first set of interconnects 21 6 and the second set of interconnects 218 are encapsulated by the underfill 222.
  • the underfill 222 is optional in some instances.
  • FIG. 3 conceptually illustrates an example of a die 300 (which is a form of an integrated device).
  • FIG. 3 illustrates a generalization of a die. As such, not all the components of a die are shown in FIG. 3.
  • the die 300 may correspond to at least one of the dies 206, and/or 208 of FIG. 2,
  • the die 300 e.g., integrated device
  • the die 300 includes a substrate 301 , several lower level metal layers and dielectric layers 302, a set of interconnects 311-316 (e.g., bumps, pillar interconnects), and an encapsulation material 320 (e.g., mold, epoxy, polymer fill).
  • the encapsulation material 320 may be optional.
  • the die 300 includes a front side region (e.g., active region) and a back side region. In some implementations, the die 300 is wafer level die.
  • the die 300 may also include pads, a passivation layer, a first insulation layer, a first under bump metallization (UBM) layer, and a second under bump metallization (UBM) layer.
  • the pad may be coupled to the lower level metal layers and dielectric layers 302.
  • a passivation layer may be positioned between the lower level metal layers and dielectric layers 302 and. the encapsulation material 320.
  • a first bump layer may be coupled to the pad and one of the interconnects 31 1-316.
  • a die may also include one or more through substrate vias (TSVs).
  • FIG. 4 conceptually illustrates an example of a die 400 (which is a form of an integrated device) that includes at least one TSV.
  • FIG. 4 illustrates a generalization of a die. As such, not all the components of a die are shown in FIG. 4.
  • the die 400 may correspond to at least one of the dies 206, and/or 208 of FIG. 2. As shown in FIG.
  • the die 400 (e.g., integrated device) includes a substrate 401 , several lower level metal layers and dielectric layers 402, a set of interconnects 41 1 -416 (e.g., bumps, pillar interconnects), and an encapsulation material 420 (e.g., mold, epoxy, polymer fill). In some implementations, the encapsulation material 420 may be optional.
  • the die 400 includes a front side region (e.g., active region) and a back side region.
  • the die 400 is a wafer level die.
  • the die 400 includes a first through substrate via (TSV) 421, a second TSV 422, a third TSV 423, and a fourth TSV 424.
  • the first TSV 421 and the second TSV 422 traverse the substrate 401 and the lower level metal layers and dielectric layers 402, That is, the first TSV 421 and the second TSV 422 traverse the active region (e.g., front side) and the back side region of the die 400.
  • the third TSV 433 and the fourth TSV 434 traverse the substrate 401. That is, the third TSV 433 and the fourth TSV 434 traverse the active region (e.g., front side) of the die 400.
  • the die 400 may also include pads, a passivation layer, a first insulation layer, a first under bump metallization (UBM) layer, and a second under bump metallization (UBM) layer.
  • the pad may be coupled to the lower level metal layers and dielectric layers 402.
  • a passivation layer may be positioned between the lower level metal layers and dielectric layers 402 and. the encapsulation material 420.
  • a first bump layer may be coupled to the pad and one of the interconnects 41 1-416.
  • FIG. 5 conceptually illustrates an example of a side view of an integrated device (e.g., semiconductor device, integrated package) that includes several dies.
  • a integrated device 500 e.g., integrated package
  • the encapsulation material 520 may include one of at least a mold, an epoxy and/or a polymer fill.
  • the dies may represent different types of dies, such as memory dies, and/or processors.
  • the first die 506 and/or the second die 508 are wafer level dies. Dies are described in detail with reference to FIGS. 3-4,
  • the dielectric layer 502 may include one dielectric layer or several dielectric layers. In some implementations, the dielectric layer 502 is an insulation layer.
  • FIG. 5 illustrates that the dielectric layer 502 includes a set of metal layers.
  • the dielectric layer 502 includes a first set of redistribution interconnects 530, a first under bump metallization (UBM) layer 532, a second set of redistribution interconnects 540, a second under bump metallization (UBM) layer 542, a third set of redistribution interconnects 550, a third under bump metallization (UBM) layer 552, a fourth set of redistribution interconnects 560, a fourth under bump metallization (UBM) layer 562, and a fifth set of redistribution interconnects 580.
  • UBM under bump metallization
  • UBM under bump metallization
  • the first, second, third, fourth, and fifth set of redistribution interconnects 530, 540, 550, 560, and 580 are redistribution layers.
  • the redistribution layers may include vias. Different implemexitations may have different number of redistribution metal layers (e.g., 1 , 5 or more metal layers).
  • the first die 506 is coupled to a first surface of the dielectric layer 502 through a first set of interconnects 516.
  • the first set of interconnects 16 are metal pillars (e.g., metal layers).
  • the metal pillars are copper pillars.
  • the first die 506 is electrically coupled to at least one of the set of solder bails 504 through the first set of interconnects 516, the first set of redistribution interconnects 530, the first UBM layer 532, the second set of redistribution interconnects 540, and/or the second UBM layer 542,
  • the second die 508 is coupled to the first surface of the dielectric layer 502 through a second set of interconnects 518.
  • the second set of interconnects 18 are metal pillars (e.g., metal layers).
  • the metal pillars are copper pillars, in some implementations, the seco d die 508 is electrically coupled to at least one of the set of solder bails 504 through the second set of interconnects 518, the third set of redistribution interconnects 550, and/or the third UBM layer 552,
  • the first die 506 may be electrically coupled to the second die 508 through the fifth set of redistribution interconnects 580.
  • FIG. 5 also illustrates that the first set of i terconnects 516 and the second set of interconnects 518 is encapsulated by the underfill 522.
  • the underfill 522 is optional in some instances.
  • FIG. 6 conceptually illustrates an example of a side view of an integrated device (e.g., semiconductor device, integrated package) that includes several dies.
  • a integrated device 600 e.g., integrated package
  • the encapsulation material 620 may include one of at least a mold, an epoxy and/or a polymer fill.
  • the dies e.g., first die 606, second die 608) may represent different types of dies, such as memory dies, and/or processors.
  • the first die 606 and/or the second die 608 are wafer level dies. Dies are described in detail with reference to FIGS. 3-4.
  • the dielectric layer 602 may include one dielectric layer or several dielectric layers. In some implementations, the dielectric layer 602 is an insulation layer.
  • FIG. 6 I I illustrates that the dielectric layer 602 includes a set of metal layers.
  • the dielectric layer 602 includes a first set of redistribution interconnects 630, a first under bump metallization (UBM) layer 632, a second set of redistribution interconnects 640, a second under bump metallization (UBM) layer 642, a third, set of redistribution interconnects 650, a third under bump metallization (UBM) layer 652.
  • UBM under bump metallization
  • UBM under bump metallization
  • the first, second, third, and fourth sets of redistribution interconnects 630, 640, 650, and 660 are redistribution layers.
  • the redistribution layers may include vias. Different implementations may have different number of redistribution metal layers (e.g., 1 , 6 or more metal layers).
  • the first die 606 is coupled to a first surface of the dielectric layer 602 through a first set of interconnects 616.
  • the first set of interconnects 616 are metal pillars (e.g., metal layers).
  • the metal pillars are copper pillars.
  • the first die 606 is electrically coupled to at least one of the set of solder bails 604 through the first set of interconnects 616, the first set of redistribution interconnects 630, the first UBM layer 632, the second set of redistribution interconnects 640, and/or the second UBM layer 642,
  • the second die 608 is coupled to the first surface of the dielectric layer 602 through a second set of interconnects 618.
  • the second set of interconnects 618 are metal pillars (e.g., metal layers).
  • the metal pillars are copper pillars.
  • the second die 608 is electrically coupled to at least one of the set of solder bails 604 through the second set of interconnects 618, the third set of redistribution interconnects 650, and/or the third UBM layer 652.
  • the first die 606 may be electrically coupled to the second die 608 through the fifth set of redistribution interconnects 680.
  • FIGS. 7A-7D illustrate an exemplar ⁇ ' sequence for providing an mtegrated device.
  • the sequence of FIGS. 7A-7D may be used to provide / manufacture the integrated device of FIGS. 2 and/or 5-6, and/or other integrated, devices described in the presen! disclose.
  • FIGS. 7A-7D may be used to provide / manufacture integrated devices that also include circuit elements. It should further be noted that the sequence of FIGS. 7A-7D may combine one or more stages in order to simplify and/or clarity the sequence for providing an integrated device that includes several dies.
  • the process of FIGS. 7A-7D illustrates a novel process that provides an integrated device with high density interconnects (e.g., pitch between interconnects is about 40 microns or less) and/or an integrated device that bypasses the use of unnecessary big landing pads (e.g., big bump pads).
  • high density interconnects e.g., pitch between interconnects is about 40 microns or less
  • an integrated device that bypasses the use of unnecessary big landing pads e.g., big bump pads
  • a carrier e.g., carrier 700
  • a first set of interconnects 702 e.g., first set of traces
  • a second set of interconnects 704 e.g., second set of traces
  • the carrier is a substrate.
  • Different implementations may use different materials for the carrier (e.g., silicon substrate, glass substrate, ceramic substrate).
  • a first die 712 and a second die 714 are provided on the earner 700. Specifically, the front sides (active sides) of the first die 712 and the second die 714 are coupled to the carrier 700. Examples of dies are described in FIGS. 3-4.
  • the first die 712 includes a first set of interconnects 722 (e.g., bumps, copper pillar).
  • the second die 714 includes a second set of interconnects 724 (e.g., bumps, copper pillar).
  • the first set of interconnects 722 of the first die 712 is coupled to the first set of interconnects 702 of the carrier 700.
  • the second set of interconnects 724 of the second die 714 is coupled to the second set of interconnects 704 of the earner 700.
  • the first die 712 and/or the second die 714 are wafer level dies.
  • an underfill 730 is provided on the carrier 700.
  • the underfill 730 is provided such that the underfill 730 covers the first set of interconnects 702, the second set of interconnects 704, the first set of interconnects 722, and. the second set of interconnects 724.
  • providing the underfill 730 is optional.
  • an encapsulation material 740 is provided.
  • the encapsulation material 740 substantially or completely surrounds or encapsulates the first die 712 and the second die 714.
  • the integrated device is flipped and coupled to a temporary carrier 742. That is, the encapsulation material 740 is coupled to the temporary carrier 742.
  • the carrier 742 may use different materials (e.g., substrate, silicon, glass, ceramic) for the carrier 742.
  • an adhesive layer (not shown) may be used to couple the encapsulation material 740 of the integrated device to the temporary carrier 742.
  • Different implementations may use different materials for the adhesion layer.
  • the temporary carrier 742 is a bonding tape.
  • a first surface of the integrated device is removed (e.g., polished, grinded).
  • the surface that includes the carrier 700 is removed (e.g., polished, grinded).
  • polishing the integrated, device may include polishing and/or grinding the carrier 700, the first set of interconnects 702, the second set of interconnects 704, the first set of interconnects 722, the second set of interconnects 724, the underfill 730, and/or the encapsulation material 740.
  • polishing the integrated device may leave behind portions of the first set of interconnects 702, the second set of interconnects 704, the first set of interconnects 722, the second set of interconnects 724, the underfill 730, and/or the encapsulation material 740.
  • a first dielectric layer 750 and several redistribution interconnects are provided on the front side of the first die 712 and the second, die 714. Specifically, several interconnects are provided on the first set of interconnect 722 and the second set of interconnects 724.
  • the redistribution mterconnects 751 -755 are formed on a first redistribution metal layer.
  • the redistribution interconnects 755-755 may include at least one via.
  • the redistribution interconnects 751-755 bypasses the use of unnecessary landing pads (e.g., big bump pads) when coupling to the first set of interconnect 722 and/or the second set of interconnects 724. In some implementations, the redistribution interconnects 751-755 are directly coupled to the first set of interconnect 722 and/or the second set of interconnects 724.
  • unnecessary landing pads e.g., big bump pads
  • a second dielectric layer 760 and several redistribution interconnects are provided on the first dielectric layer 750 and the redistribution interconnects 751 - 754.
  • the redistribution interconnects 761-764 are formed on a second redistribution metal layer.
  • the redistribution interconnects 761 -764 may include at least one via.
  • a third dielectric layer 770 and several redistribution interconnects are provided on the second dielectric layer 760 and the redistribution interconnects 761-764.
  • the redistribution interconnects 771-774 is formed on a third redistribution metal layer.
  • the redistribution interconnects 771 -774 may include at least one via.
  • At stage 10 at least one under bump metallization (UBM) layer is provided. Specifically, a first under bump metallization (UBM) layer 781, a second UBM layer 782, a third UBM layer 783, and a fourth UBM layer 784 are provided. The UBM layers are provided, on the fourth dielectric layer 780. In some implementations, providing the UBM layer is optional
  • At stage 1 1 as shown in FIG. 7D, at least one solder ball is provided on the UBM layer. Specifically, a first solder bail 791 is coupled to the first UBM layer 781 , a second solder ball 792 is coupled to the second UBM layer 782, a third solder ball 793 is coupled to the third UBM layer 783, and a fourth solder bail 794 is coupled to the fourth UBM layer 784.
  • Stage 1 1 illustrates the set of dielectric layers 790.
  • the set of dielectric layers 790 includes the dielectric layers 750, 760, 770 and. 780.
  • the solder ball may be coupled to the redistribution interconnects instead of a UBM layer.
  • a portion of the integrated device is removed (e.g., polished). As shown at stage 12, at least a portion of the carrier 742 is removed (e.g., entire carrier 742 is removed). In some implementations, at least a portion of the encapsulation material 740 is also removed.
  • FIGS. 8A-8D illustrate an exemplar ⁇ ' sequence for providing an integrated device.
  • the sequence of FIGS. 8A-8D may be used to provide / manufacture the integrated device of FIGS. 2 and/or 5-6, and/or other integrated devices described in the presen ! disclose.
  • FIGS. 8A-8D may be used to provide / manufacture integrated devices that also include circuit elements. It should further be noted that the sequence of FIGS. 8A-8D may combine one or more stages in order to simplify and/or clarity the sequence for providing an integrated device that includes several dies.
  • the process of FIGS. 8A-8D illustrates a novel process thai provides an integrated device with high density interconnects (e.g., pitch between interconnects is about 40 microns or less) and/or an integrated device that bypasses the use of unnecessary big landing pads (e.g., big bump pads).
  • high density interconnects e.g., pitch between interconnects is about 40 microns or less
  • an integrated device that bypasses the use of unnecessary big landing pads e.g., big bump pads
  • a carrier e.g., carrier 800
  • a first set of interconnects 802 e.g., first set of traces
  • a second set of interconnects 804 e.g., second set of traces
  • the carrier is a substrate.
  • Different implementations may use different materials for the carrier (e.g., silicon substrate, glass substrate, ceramic substrate).
  • a first die 812 and a second die 814 are provided on the carrier 800. Specifically, the front side (active side) of the first die 812 and the second die 814 are coupled to the carrier 800. Examples of dies are described in FIGS. 3-4.
  • the first die 812 includes a first set of interconnects 822 (e.g., bumps, copper pillar).
  • the second die 814 includes a second set of interconnects 824 (e.g., bumps, copper pillar).
  • the first set of interconnects 822 of the first die 812 is coupled to the first set of interconnects 802 of the carrier 800.
  • the second set of interconnects 824 of the second die 814 is coupled to the second set of interconnects 804 of the carrier 800.
  • the first die 812 and/or the second die 814 are wafer level dies.
  • an underfill 830 is provided on the carrier 800.
  • the underfill 830 is provided such that the underfill 830 covers the first set of interconnects 802, the second set of interconnects 804, the first set of interconnects 822, and. the second set of interconnects 824.
  • providing the underfill 830 is optional.
  • an encapsulation material 840 is provided.
  • the encapsulation material 840 substantially or completely surrounds or encapsulates the first die 812 and the second die 814.
  • the integrated device is flipped and coupled to a temporary carrier 842. That is, the encapsulation material 840 is coupled to the temporary carrier 842.
  • the carrier 842 may use different materials (e.g., substrate, silicon, glass, ceramic) for the carrier 842.
  • an adhesive layer (not shown) may be used to couple the encapsulation material 840 of the integrated device to the temporary carrier 842.
  • Different implementations may use different materials for the adhesion layer.
  • the temporary carrier 842 is a bonding tape.
  • a first surface of the integrated device is removed (e.g., polished, grinded).
  • the surface that includes the carrier 800 is removed (e.g., polished, grinded).
  • polishing the integrated, device may include polishing and/or grinding the carrier 800, the first set of interconnects 802, the second set of interconnects 804, the first set of interconnects 822, the second set of interconnects 824, the underfill 830, and/or the encapsulation material 840.
  • polishing the integrated device may leave behind portions of the first set of interconnects 802, the second set of interconnects 804, the first set of interconnects 822, the second set of interconnects 824, the underfill 830, and/or the encapsulation material 840.
  • polishing the integrated device includes creating at least o e cavity (e.g., cavities 825) in the integrated device.
  • the cavity 825 may be created in the underfill 830 and/or the encapsulation material 840.
  • a metal layer is provided in the cavity 825.
  • the metal layer defines an interconnect from a set of interconnects 826.
  • the set of interconnects 826 electrically couples the first set of interconnects 822 and the second set of interconnects 824.
  • the set of interconnects 826 electrically couples the first die 812 and the second die 814.
  • the set of interconnects 826 bypasses the use of unnecessary landing pads (e.g., big bump pads) when coupling to the first set of interconnects 822 and/or the second set of interconnects 824.
  • the set of interconnects 826 is directly coupled to the first set of interconnects 822 and the second set of interconnects 824. In some implementations, the set of interconnects 826 is coupled to the side surface of the first set of interconnects 822 and the side surface of the second set of interconnects 824. In some implementations, the set of interconnects 826 is coupled to the top surface of the first set of interconnects 822 and the top surface of the second set of interconnects 824. In some implementations, the set of interconnects 826 are high density interconnects. In some implementations, a pitch of the set of interconnects 826 is about 40 microns ( ⁇ ) or less.
  • a first dielectric layer 850 and several redistribution interconnects are provided on the front side of the first die 812 and the second die 814. Specifically, several interconnects are provided on the first set of interconnect 822 and the second set of interconnects 824.
  • the redistribution mierconnects 851 -854 are formed on a first redistribution metal layer.
  • the redistribution interconnects 855-854 may include at least one via.
  • the redistribution interconnects 851 -854 bypasses the use of unnecessary landing pads (e.g., big bump pads) when coupling to the first set of interconnect 822 and/or the second set of interconnects 824. In some implementations, the redistribution interconnects 851-854 are directly coupled to the first set of interconnects 822 and'Or the second set of interconnects 824.
  • unnecessary landing pads e.g., big bump pads
  • a second dielectric layer 860 and several redistribution interconnects are provided on the first dielectric layer 850 and the redistribution interconnects 851-854.
  • the redistribution interconnects 861-864 is formed on a second redistribution metal layer.
  • the redistribution interconnects 861 -864 may include at least one via.
  • a third dielectric layer 870 and several redistribution interconnects are provided on the second dielectric layer 860 and the redistribution interconnects 861-864.
  • the redistribution interconnects 871 -874 is formed on a third redistribution metal layer.
  • the redistribution interconnects 871-874 may include at least one via.
  • UBM under bump metallization
  • a first under bump metallization (UBM) layer 881 a first under bump metallization (UBM) layer 881 , a second UBM layer 882, a third UBM layer 883, and a fourth XJBM layer 884 are provided.
  • the UBM layers are provided, on the fourth dielectric layer 880. In some implementations, providing the UBM layer is optional
  • At stage 12 as shown in FIG. 8D, at least one solder ball is provided on the XJBM layer. Specifically, a first solder bail 891 is coupled to the first UBM layer 881 , a second solder ball 892 is coupled to the second UBM layer 882, a third solder ball 893 is coupled to the third UBM layer 883, and a fourth solder bail 894 is coupled to the fourth UBM layer 884.
  • Stage 12 illustrates the set of dielectric layers 890.
  • the set of dielectric layers 890 includes the dielectric layers 850, 860, 870 and. 880.
  • the solder ball may be coupled to the redistribution interconnects instead of the UBM layer.
  • a portion of the integrated device is removed (e.g., polished).
  • at least a portion of the carrier 842 is removed (e.g., entire carrier 842 is removed).
  • at least a portion of the encapsulation material 840 is also removed.
  • FIG. 9 illustrates an exemplary method for providing an integrated device (e.g., integrated package).
  • the method of FIG. 9 may be used to provide / manufacture the integrated device of FIGS. 2 and/or 5-6, and/or other integrated devices (e.g., die package) described in the present disclose.
  • the method provides (at 805) a first carrier (e.g., carrier 800) and interconnects (e.g., traces).
  • a first carrier e.g., carrier 800
  • interconnects e.g., traces
  • the first earner is a sacrificial carrier.
  • the first carrier is a substrate. Different implementations may use different materials for the first carrier (e.g., silicon substrate, glass substrate, ceramic substrate).
  • the method then provides (at 910) at. least one integrated device (e.g., die) on the carrier.
  • providing (at 810) at least one integrated device includes providing a first die on the first carrier and providing a second die on the first carrier.
  • the dies that are provided are wafer level dies. Examples of providing at least one die is shown in FIG. 8A (see e.g.. stage 2).
  • the method optionally provides (at 815) an underfill and an encapsulation material
  • the underfill is provided, between the dies and the first carrier.
  • the interconnects 802, 804, 822, and 824 are covered by the underfill
  • the encapsulation material substantially or completely suirounds or encapsulates the dies (e.g., first die 812, the second die 814).
  • the method couples (at 920) the integrated device that includes the first carrier and. the first and second dies, to a second carrier.
  • the second carrier is a temporary carrier. Different implementations may use different materials for the second carrier.
  • the second carrier is a bonding tape.
  • the method further removes (at 925) at least a portion of the integrated device.
  • removing at least a portion of the integrated device includes removing (e.g., polishing, grinding) at least the first carrier, portions of the underfill, potions of the encapsulation layer, and/or the interconnects (e.g., interconnects 802, 804, 822, 824).
  • at least one metal layer may be provided, in a cavity.
  • the metal layer in the cavity may define an interconnect (e.g., high density interconnect between two dies).
  • the method further provides (at 930) at least one dielectric layer (e.g., dielectric layers 850, 860, 870. 880).
  • dielectric layers 850, 860, 870. 880 Different implementations may use different materials for the dielectric layers.
  • first and second insulation layers (which are a form of a dielectric layer) may be a Poiybenzoxazole (FbO) layer and/or a polymer layer.
  • the method also provides (at 935) several metal redistribution layers.
  • providing several redistribution layers includes providing several redistribution interconnects (e.g., redistribution interconnects 851 -854) and/or vias.
  • the method of providing (at 930) at least one dielectric layer, and providing (at 935) the metal redistribution layers may be performed sequentially back and forth. That is, in some implementations, the method may provide a first dielectric layer, a first redistribution layer, a second dielectric layer, a second redistribution layer, and so on and so forth.
  • the method then optionally provides (at 940) an under bump metallization (UBM) layer.
  • UBM under bump metallization
  • providing (at 940) the UBM layer includes coupling the UBM layer to a metal redistribution layer.
  • the UBM layer is a copper layer.
  • the method further provides (at. 945) a solder bail on the UBM layer.
  • the method further removes (at 950 ⁇ at least a portion of the integrated device.
  • removing a portion of the integrated device includes removing (e.g., polishing, grinding) at least a portion of the carrier 842.
  • at least a portion of the encapsulation material 840 is also removed.
  • providing an integrated device that includes redistribution layers includes several processes.
  • FIGS. 1 OA- IOC illustrate an exemplary sequence for providing an integrated device that includes several redistribution layers.
  • the sequence of FIGS. 1 OA- IOC may be used to provide / manufacture the integrated device of FIGS. 2 and/or 5-6. and/or other integrated devices (e.g., dies) described in the present disclose.
  • the sequence of FIGS. 1 OA- IOC may be used to provide / manufacture integrated devices that also include circuit elements.
  • the sequence of FIGS. 10A ⁇ IOC may combine one or more stages in order to simplify and/or clarify the sequence for providing an integrated device that includes redistribution layers.
  • FIGS. lOA-lOC a more specific process for providing one or more redistribution layers.
  • a substrate e.g., substrate 1001
  • the substrate 1 001 is a wafer.
  • Different implementations may use different materials for the substrate (e.g., silicon substrate, glass substrate, ceramic substrate).
  • lower level metal layers and dielectric layers are provided on the substrate 1001 .
  • Different implementations may provide different number of lower level metal layers and dielectric layers (e.g., Ml metal layer, M2 metal layer, M3 metal layer, M4 metal layer, M5 metal layer, M6 metal layer, M7 metal layer).
  • circuits, routes and/or interconnects are also provided.. However, for the purpose of simplification and clarity, circuits, routes and/or interconnects are not shown in the lower level metal layers and dielectric layers 1002.
  • at stage 1 at least one pad (e.g., pads 1004, 1025, 1029 ⁇ is provided on the lower level metal layers and dielectric layers 1002.
  • the pad 1004 is coupled to one of the lower level metal layer (e.g., the top lower level metal layer, M7 metal layer).
  • the pad 1004 is an aluminum pad..
  • different implementations may use different materials for the pad 1004. Different implementations may use different processes for providing the pad on the lower level metal layers and dielectric layers 1002. For example, in some implementations, a lithography and/or etching process may be use to provide the pad 1004 on the lower level metal layers and dielectric layers 1002.
  • a passivation layer (e.g., passivation layer 1006) is provided, on the lower level metal layers and dielectric layers 1002.
  • a passivation layer e.g., passivation layer 1006
  • Different implementations may use different materials for the passivation layer 1006.
  • the passivation layer 1006 is provided on the lower level metal layers and dielectric layers 1002 such that at least a portion of the pad 1004 is exposed.
  • a first insulation layer (e.g., first insulation layer 1008) is provided on the passivation layer 1006 and the pads 1004, 1025 and 1029.
  • the first insulation layer 1008 is a dielectric layer.
  • the first insulation layer 1008 may be a Polybenzoxazole (FbO) layer or a polymer layer.
  • stage 3 several cavities (e.g., cavity, trench) is provided. / created in the first insulation layer 1008. As further shown in stage 3, the cavity 1009 is created over the pad 1004. Similarly, a cavity 1011 is created over the pad 1025, and a cavity 1013 is created over the pad 1029. Different implementations may create the cavities (e.g., cavity 1009) differently. For example, the cavity 1009 may be provided / created by etching the first insulation layer 1008.
  • a first metal redistribution layer is provided. Specifically, a first metal redistribution layer 1010 is provided over the pad 1 004 and the first insulation layer 1008. As shown in stage 4, the first metal redistribution layer 1010 is coupled to the pad 1004.
  • the first metai redistribution layer 1010 also inciudes a first metal layer 1030 and a second metal layer 1032. That is, in some implementations, the first metal layer 1030 and the second metal layer 1032 is on the same layer as the first metai redistribution layer 1010. In some implementations, the first and second metal layers 1030 and 1032 are vias. In some impiemeniations, the first metal redistribution layer 1010 is a copper layer.
  • a second insulation layer 1014 and a third insulation layer 1016 are provided.
  • a second metal redistribution layer 1020 is provided.
  • several metal layers (1040, 1050, 1042, 1052) are provided.
  • the metal layers are part of the redistribution layers.
  • some of the metal layers include vias.
  • metal layers 1042, and 1052 are vias and metal layers 1040 and 1050, are traces in some implementations.
  • a cavity 1017 is provided in the insulation layer 1 016.
  • the cavity 1017 in the insulation layer 1016 is over a portion of the second metal redistribution layer 1020 (e.g., interconnect).
  • an under bump metallization (XJBM) layer is provided.
  • an under bump metallization (UBM) layer 1070 is provided in the cavity 101 7 of the insulation layer 1016,
  • the UBM layer 1070 is a copper layer.
  • a solder ball is provided on the UBM layer. Specifically, a solder ball 1080 is coupled to the UBM layer 1070.
  • FIG. 1 1 illustrates various electronic devices that may be integrated with any of the aforementioned semiconductor device, integrated circuit, die, interposer or package.
  • a mobile telephone 1102, a laptop computer 1 104, and a fixed location terminal 1 106 may include an integrated circuit (IC) 1100 as described herein.
  • the IC 1 100 may be, for example, any of the integrated circuits, dice or packages described herein.
  • the devices 1 102, 1 104, 1 106 illustrated in FIG. 11 are merely exemplary.
  • IC 1 100 may also feature the IC 1 100 including, but not limited to, mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, GPS enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers or any other device that stores or retrieves data or computer instructions, or any combination thereof.
  • PCS personal communication systems
  • portable data units such as personal digital assistants
  • GPS enabled devices GPS enabled devices
  • navigation devices set top boxes
  • music players video players
  • entertainment units fixed location data units
  • fixed location data units such as meter reading equipment
  • communications devices smartphones, tablet computers or any other device that stores or retrieves data or computer instructions, or any combination thereof.
  • FIGS. 2, 3, 4, 5, 6, 7A-7D, 8A-8D, 9, 1 OA- IOC and/or 1 1 may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps, or functions.
  • FIGS. 2, 3, 4, 5, 6, 7A-7D, 8A-8D, 9, iOA-iOC and/or 11 and its corresponding description in the present disclosure is not limited to dies and/or ICs.
  • 2, 3, 4, 5, 6, 7A-7D, 8A-8D, 9, lOA-lOC and/or 11 and its corresponding description may be used to manufacture, create, provide, and/or produce integrated, devices.
  • an integrated, device may include a die package, an integrated circuit (IC), a wafer, a semiconductor device, and/or an interposer.
  • the embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed ixi parallel or coxicurrexitly. Ixi addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed.

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Abstract

An integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (206) coupled to a first surface of the base portion, and an underfill (222) between the first die and the base portion. The base portion includes a dielectric layer (202), and a set of redistribution metal layers (230-260). In some implementations, the integrated device further includes an encapsulation material (220) that encapsulates the first die. In some implementations, the integrated device further includes a second die (208) coupled to the first surface of the base portion. In some implementations, the integrated device further includes a set of interconnects (280) on the base portion, the set of interconnects coupling the first die and the second die. In some implementations, the first die includes a first set of interconnect pillars (216) and the second die includes a second set of interconnect pillars (218).

Description

CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims priority to and the benefit of U.S. Non-Provisional Patent Application No, 14/196,817 filed in the United. States Patent and Trademark Office on March 4. 2014, the entire content of which is incorporated herein by
Figure imgf000003_0001
[0002] Various features relate to an integrated device that includes high density interconnects and redistributions layers.
Background
Θ003] FIG. 1 illustrates a conventional integrated package 100 that includes a substrate 102, a first die 106, a second die 108, a first set of solder bails 1 16, a second set of solder bails 1 18, and a third set of solder balls 120. The first die 106 is coupled to the substrate 102 through the first set of solder balls 116. The second die 108 is coupled to the substrate 1 02 through the second set of solder bails 1 18. The third set of solder bails 120 is coupled to the substrate 102. Typically, the third set of solder balls 120 is coupled to a printed circuit board (PCB) (not shown).
Θ004] Conventional integrated packages, such as the one described in FIG. 1, have certain limitations and downsides. For example, the substrate 102 of the integrated package 100 of FIG. I is typically made of an organic laminate (e.g., rigid or flexible), or a silicon (Si) interposer. The use of such materials as a substrate creates design problems when attempting to manufacture low profile integrated package. That is, these materials create substantial design penalty due to their manufacturing limitations, in particular, these materials make it impossible or cost-prohibitive to provide a low profile integrated package.
[0005] Moreover, the use of solder bails as a coupling method between a die and a substrate limits the density of the connection that can exist between a die and a substrate, as the minimum spacing required between solder balls is often greater than the minimum spacing required between traces and/or vias on a substrate. [0006] In addition, during the manufacturing process of an integrated device, tool alignment tolerances and the shifting of dies can cause inaccuracy hi the placement of dies on a substrate. To account for these issues, big landing pads must be provided to ensure that there is proper connection of the dies. These big landing pads can take up valuable space in the integrated device and. add unnecessaiy cost to the manufacturing of axi integrated device.
[0007] Therefore, there is a need for a cost effective integrated package that has a low profile hut also takes up a little real estate as possible. Ideally, such an integrated package will also provide higher density connections with the dies.
SUMMARY
[Θ008] Various features, apparatus and methods described herein provide an integrated device that includes high density interconnects redistributions layers.
[0009] A first example provides axi integrated device that includes a base portion for the integrated device, a first die coupled to a first surface of the base portion, and an underfill between the first die and the base portion. The base portion includes a dielectric layer, axid a set of redistribution metal layers.
[00iO] According to an aspect, the integrated device further includes an encapsulation material that encapsulates the first die.
[0011 ] According to one aspect, the integrated device further includes a second die coupled to the first surface of the base portion. Ixi some implementations, the integrated device further includes a set of interconnects on the base portion, the set of interconnects electrically coupling the first die and the second die. In some implementations, the first die includes a first set of interconnect pillars and the second die includes a second set of interconnect pillars. The set of interconnects is coupled to the first set of interconnects pillars and the second set of interconnect pillars while bypassing a bump pad and/or landing pad. In some implementations, the set of interconnects has a first pitch that is about 40 microns (μχη) or less. In some implementations, the underfill is also between the second die and. the base portion, [0012] According to an aspect, the first die is a first wafer level die.
[0013] According to an aspect, the first die includes a first set of interconnect pillars, the first die is coupled to the set of redistribution metal layers through the first set of interconnect pillars. In some implementations, the first set of interconnect pillars has a first pitch that is about 40 microns (μτη) or less. [0014] According to one aspect, the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a srnartphone, a personal digital assistant, a fixed location terminal, a tablet, computer, and/or a laptop computer.
[0015] A second example provides an apparatus that includes a base portion for an integrated device. The base portion includes a dielectric layer, and a redistribution means. The apparatus further includes a first die coupled to a first surface of the base portion, a means for encapsulating an area between the first die and the base portio .
[0016] According to an aspect, the apparatus further includes an encapsulation means that encapsulates the first die.
[0017] According to one aspect, the apparatus further includes a second die coupled to the first surface of the base portion. In some implementations, the apparatus further includes a set of interconnects on the base portion. The set of interconnects electrically couples the first die and the second die. Tn some implementations, the first die includes a first set. of interconnect, pillars. The second die includes a second set of interconnect pillars. The set of interconnects is coupled to the first set of interconnects pillars and the second set of interconnect pillars while bypassing a landing pad. In some implementations, the set. of interconnects includes a first, pitch that is about. 40 microns (μηι) or less.
[0018] According to an aspect, the first die is a first wafer level die.
[0019] According to one aspect, the first, die includes a first set of interconnect pillars. The first die is coupled to the redistribution means through the first set of interconnect pillars.
[0020] According to an aspect, the first set of interconnect pillars includes a first pitch that is about 40 microns (fim) or less.
[0021] According to one aspect, the apparatus is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a srnartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.
[0022] A third example provides a method for providing an integrated device. The method forms a base portion for the integrated device, where forming the base portion includes forming a dielectric layer, and. forming a set of redistribution metal layers. The method provides a first die on a first surface of the base portion. The method forms an underfill between the first die and the base portion. [0023] According to an aspect, the method further forms an encapsulation material that encapsulates the first die.
[0024] According to one aspect, the method provides a second die on the first surface of the base portion. In some implementations, the method forms a set of interconnects on the base portion. The set of interconnects electrically coupling the first die and the second die. In some implementations, the first die includes a first set of interconnect pillars and the second die includes a second set of interconnect pillars. The set of interconnects is coupled to the first set of interconnects pillars and the second set of interconnect pillars while bypassing a landing pad. In some implementations, the set of interconnects includes a first pitch that is about 40 microns (μιη) or less.
[0025] According to an aspect, the first die is a first wafer level die,
[0026] According to one aspect, the first die includes a first set of interconnect pillars. The first die is coupled to the set of redistribution metal layers through the first set of interconnect pillars. In some implementations, the first set of interconnect pillars includes a first pitch that is about 40 microns (μη ) or less.
[0027] According to an aspect, the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.
DRAWINGS
[0028] Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identity correspondingly throughout.
[0029] FIG, 1 illustrates a profile view of a conventional integrated device.
[0030] FIG. 2 illustrates an example of an integrated device.
[0031 ] FIG. 3 illustrates an example of a die.
[0032] FIG. 4 illustrates an example of a die that includes a through substrate via.
[0033] FIG. 5 illustrates an example of an integrated device.
[0034] FIG. 6 illustrates an example of an integrated device.
[003S] FIG. 7A illustrates part of an exemplary sequence for providing / manufacturing an integrated device.
[0036] FIG. 7B illustrates part of an exemplary sequence for providing / ma ufacturing an integrated device. [0037] FIG. 7C illustrates part of an exemplar}' sequence for providing / manufacturing an integrated device.
[0038] FIG. 7D illustrates part of an exemplary sequence for providing / manufacturing an integrated device.
[0039] FIG. 8A illustrates part of an exemplary sequence for providing / manufacturing an integrated device.
[0040] FIG. 8B illustrates part of an exemplar^' sequence for providing / manufacturing an integrated device.
[0041] FIG. 8C illustrates part of an exemplary sequence for providing / manufacturing an integrated device.
[0042] FIG. 8D illustrates part of an exemplary sequence for providing / manufacturing an integrated device.
[0043] FIG. 9 illustrates an exemplary method for providing / manufacturing an integrated device.
[0044] FIG. I OA illustrates part of an exemplary sequence for providing / manufacturing an integrated device.
[0045] FIG. 10B illustrates part of an exemplary sequence for providing / manufacturing an integrated device.
[0046] FIG. IOC illustrates part of an exemplary sequence for providing / manufacturing an integrated device.
[0047] FIG. 1 1 illustrates various electroxiic devices that may integrate a semiconductor device, a die, an integrated circuit and/or PCB described herein.
DETAILED DESCRIPTION
[0048] In the following description, specific details are given to provide a thorough understanding of the various aspects of the disclosure. However, it will be understood by one of ordinary skill in the art that the aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams in order to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the aspects of the disclosure.
Overview [0049] Some novel features pertain to an integrated device (e.g., integrated package) that nicludes a base portion for the integrated device, a first die (e.g., first wafer level die) coupled to a first surface of the base portion, and an underfill between the first die and the base portion. The base portion includes a dielectric layer, and a set of redistribution metal layers. In some implementations, the integrated device further includes an encapsulation material thai encapsulates the first die. In some implementations, the integrated device further includes a second die (e.g., second wafer level die) coupled to the first surface of the base portio . In some implementations, the integrated device further includes a set of interconnects on the base portion, the set of interconnects electrically coupling the first die and the second die. In some implementations, the first, die includes a first set of interconnect pillars and the second die includes a second set of interconnect pillars. The set of interconnects is coupled, to the first set of interconnects pillars and the second set of interconnect pillars while bypassing a landing pad (e.g., bump pad). In some implementations, the set of interconnects has a first pitch of about 40 microns ( a m) or less. In some implementations, the underfill is also between the second die and. the base portion.
Exemplary Integrated Device That Includes Redistribution Layers
Θ050] FIG. 2 conceptually illustrates an example of a side view of an integrated device (e.g., semiconductor device, integrated package) thai includes several dies. Specifically, FIG. 2 illustrates an integrated device 200 (e.g., integrated package) that includes a dielectric layer 202, a first set of solder balls 204, a first die 206, a second die 208, an encapsulation material 220, and an underfill 222. Different implementations may use different materials for the encapsulation material 220. For example, the encapsulation material 220 may include one of at least a mold, an epoxy and/or a polymer fill. The dies (e.g., first die 206, second die 208) may represent different types of dies, such as memory dies, and/or processors. In some implementations, the first die 206 and/or the second die 208 are wafer level dies. Dies are further described in detail below with reference to FIGS. 3-4.
[0051] The dielectric layer 202 may include one dielectric layer or several dielectric layers. In some implementations, the dielectric layer 202 is an insulation layer. FIG. 2 illustrates that the dielectric layer 202 includes a set of metal layers. In particular, the dielectric layer 202 includes a first set of redistribution interconnects 230, a first under bump metallization (UBM) layer 232, a second set of redistribution interconnects 240, a second under bump metallization (UBM) layer 242, a third set of redistribution interconnects 250, a third under bump metallization (UBM) layer 252, a fourth set of redistribution interconnects 260, a fourth under bump metallization (UBM) layer 262, and a fifth set of redistribution interconnects 280, In some implementations, the first, second, third, and fourth sets of redistribution interconnects 230. 240, 250, and 260 are redistribution layers hi the dielectric layer 202. The redistribution layers may include vias. Different implementations may have different number of redistribution metal layers (e.g., I , 2 or more metal layers).
|C>052] The fifth set of redistribution interconnects 280 is a metal layer on the dielectric layer 202 (e.g., on surface of dielectric layer 202). In some implementations, the first, second, third, and fourth sets of redistribution interconnects 230, 240, 250, and 260 have respectively, a first pitch, a second pitch, a third pitch, and a fourth pitch. In some implementations, the fifth set of redistribution interconnects 280 has a fifth pitch that is different than the first pitch, the second pitch, the third pitch, and/or the fourth pitch. In some implementations, the fifth pitch is less than the first pitch, the second pitch, the third pitch, and/or the fourth pitch. The fifth set of redistribution interconnects 280 is coupled to the first set of interconnects 216 and the second set of interconnects 218. In some implementations, the fifth set of redistribution interconnects 280 includes a set of high density interconnects. In some implementations, the fifth set of interconnects 280 includes a first pitch that is about 40 microns (μτή) or less.
Θ053] The first die 206 is coupled to a first surface of the dielectric layer 202 through the first set of interconnects 216, In some implementations, the first set of interconnects 216 are metal pillars (e.g., metal layers). In some implementations, the metal pillars are copper pillars. In some implementations, the first die 206 is electrically coupled to at least one of the set of solder bails 204 through the first set of interconnects 216, the first set of redistribution interconnects 230, the first UBM layer 232, the second set of redistribution interconnects 240, and/or the second UBM layer 242.
[0054] The second die 208 is coupled to the first surface of the dielectric layer 202 through the second set of interconnects 218. In some implementations, the second set of interconnects 218 are metal pillars (e.g., metal layers). In some implementations, the metal pillars are copper pillars. In some implementations, the second die 208 is electrically coupled to at least one of the set of solder bails 204 through the second set of interconnects 218, the third set of redistribution interconnects 250, and/or the third UBM layer 252. [0055] As shown in FIG. 2, the first die 206 may be electrically coupled to the second die 208 through the fifth set of redistribution interconnects 280. FIG. 2 also illustrates that the first set of interconnects 21 6 and the second set of interconnects 218 are encapsulated by the underfill 222. The underfill 222 is optional in some instances.
[0056] FIG. 3 conceptually illustrates an example of a die 300 (which is a form of an integrated device). For purpose of clarity, FIG. 3 illustrates a generalization of a die. As such, not all the components of a die are shown in FIG. 3. In some implementations, the die 300 may correspond to at least one of the dies 206, and/or 208 of FIG. 2, As shown in FIG. 3, the die 300 (e.g., integrated device) includes a substrate 301 , several lower level metal layers and dielectric layers 302, a set of interconnects 311-316 (e.g., bumps, pillar interconnects), and an encapsulation material 320 (e.g., mold, epoxy, polymer fill). In some implementations, the encapsulation material 320 may be optional.
[0057] The die 300 includes a front side region (e.g., active region) and a back side region. In some implementations, the die 300 is wafer level die.
[0058] In some implementations, the die 300 may also include pads, a passivation layer, a first insulation layer, a first under bump metallization (UBM) layer, and a second under bump metallization (UBM) layer. In such instances, the pad may be coupled to the lower level metal layers and dielectric layers 302. A passivation layer may be positioned between the lower level metal layers and dielectric layers 302 and. the encapsulation material 320. A first bump layer may be coupled to the pad and one of the interconnects 31 1-316.
[0059] In some implementations, a die may also include one or more through substrate vias (TSVs). FIG. 4 conceptually illustrates an example of a die 400 (which is a form of an integrated device) that includes at least one TSV. For purpose of clarity, FIG. 4 illustrates a generalization of a die. As such, not all the components of a die are shown in FIG. 4. In some implementations, the die 400 may correspond to at least one of the dies 206, and/or 208 of FIG. 2. As shown in FIG. 4, the die 400 (e.g., integrated device) includes a substrate 401 , several lower level metal layers and dielectric layers 402, a set of interconnects 41 1 -416 (e.g., bumps, pillar interconnects), and an encapsulation material 420 (e.g., mold, epoxy, polymer fill). In some implementations, the encapsulation material 420 may be optional.
[0060] The die 400 includes a front side region (e.g., active region) and a back side region. In some implementations, the die 400 is a wafer level die. [0061] As shown in FIG. 4, the die 400 includes a first through substrate via (TSV) 421, a second TSV 422, a third TSV 423, and a fourth TSV 424. The first TSV 421 and the second TSV 422 traverse the substrate 401 and the lower level metal layers and dielectric layers 402, That is, the first TSV 421 and the second TSV 422 traverse the active region (e.g., front side) and the back side region of the die 400. The third TSV 433 and the fourth TSV 434 traverse the substrate 401. That is, the third TSV 433 and the fourth TSV 434 traverse the active region (e.g., front side) of the die 400.
[0062] In some implementations, the die 400 may also include pads, a passivation layer, a first insulation layer, a first under bump metallization (UBM) layer, and a second under bump metallization (UBM) layer. In such instances, the pad may be coupled to the lower level metal layers and dielectric layers 402. A passivation layer may be positioned between the lower level metal layers and dielectric layers 402 and. the encapsulation material 420. A first bump layer may be coupled to the pad and one of the interconnects 41 1-416.
[0063] FIG. 5 conceptually illustrates an example of a side view of an integrated device (e.g., semiconductor device, integrated package) that includes several dies. Specifically, FIG. 5 illustrates a integrated device 500 (e.g., integrated package) that includes a dielectric layer 502, a first set of solder bails 504, a first die 506, a second die 508, an encapsulation material 520, and an underfill 522. Different implementations may use different materials for the encapsulation material 520. For example, the encapsulation material 520 may include one of at least a mold, an epoxy and/or a polymer fill. The dies (e.g., first die 506, second die 508) may represent different types of dies, such as memory dies, and/or processors. In some implementations, the first die 506 and/or the second die 508 are wafer level dies. Dies are described in detail with reference to FIGS. 3-4,
Θ064] The dielectric layer 502 may include one dielectric layer or several dielectric layers. In some implementations, the dielectric layer 502 is an insulation layer. FIG. 5 illustrates that the dielectric layer 502 includes a set of metal layers. In particular, the dielectric layer 502 includes a first set of redistribution interconnects 530, a first under bump metallization (UBM) layer 532, a second set of redistribution interconnects 540, a second under bump metallization (UBM) layer 542, a third set of redistribution interconnects 550, a third under bump metallization (UBM) layer 552, a fourth set of redistribution interconnects 560, a fourth under bump metallization (UBM) layer 562, and a fifth set of redistribution interconnects 580. In some implementations, the first, second, third, fourth, and fifth set of redistribution interconnects 530, 540, 550, 560, and 580 are redistribution layers. The redistribution layers may include vias. Different implemexitations may have different number of redistribution metal layers (e.g., 1 , 5 or more metal layers).
Θ065] The first die 506 is coupled to a first surface of the dielectric layer 502 through a first set of interconnects 516. In some implementations, the first set of interconnects 16 are metal pillars (e.g., metal layers). In some implementations, the metal pillars are copper pillars. In some implementations, the first die 506 is electrically coupled to at least one of the set of solder bails 504 through the first set of interconnects 516, the first set of redistribution interconnects 530, the first UBM layer 532, the second set of redistribution interconnects 540, and/or the second UBM layer 542,
Θ066] The second die 508 is coupled to the first surface of the dielectric layer 502 through a second set of interconnects 518. In some implementations, the second set of interconnects 18 are metal pillars (e.g., metal layers). In some implementations, the metal pillars are copper pillars, in some implementations, the seco d die 508 is electrically coupled to at least one of the set of solder bails 504 through the second set of interconnects 518, the third set of redistribution interconnects 550, and/or the third UBM layer 552,
Θ067] As shown in FIG. 5, the first die 506 may be electrically coupled to the second die 508 through the fifth set of redistribution interconnects 580. FIG. 5 also illustrates that the first set of i terconnects 516 and the second set of interconnects 518 is encapsulated by the underfill 522. The underfill 522 is optional in some instances.
[0068] FIG. 6 conceptually illustrates an example of a side view of an integrated device (e.g., semiconductor device, integrated package) that includes several dies. Specifically, FIG. 6 illustrates a integrated device 600 (e.g., integrated package) that includes a dielectric layer 602, a first set of solder balls 604, a first die 606, a second die 608, and an encapsulation material 620. Different implementations may use different materials for the encapsulation material 620. For example, the encapsulation material 620 may include one of at least a mold, an epoxy and/or a polymer fill. The dies (e.g., first die 606, second die 608) may represent different types of dies, such as memory dies, and/or processors. In some implementations, the first die 606 and/or the second die 608 are wafer level dies. Dies are described in detail with reference to FIGS. 3-4.
Θ069] The dielectric layer 602 may include one dielectric layer or several dielectric layers. In some implementations, the dielectric layer 602 is an insulation layer. FIG. 6 I I illustrates that the dielectric layer 602 includes a set of metal layers. In particular, the dielectric layer 602 includes a first set of redistribution interconnects 630, a first under bump metallization (UBM) layer 632, a second set of redistribution interconnects 640, a second under bump metallization (UBM) layer 642, a third, set of redistribution interconnects 650, a third under bump metallization (UBM) layer 652. a fourth set of redistribution interconnects 660, a fourth under bump metallization (UBM) layer 662. and a fifth set of redistribution interconnects 680. In some implementations, the first, second, third, and fourth sets of redistribution interconnects 630, 640, 650, and 660 are redistribution layers. The redistribution layers may include vias. Different implementations may have different number of redistribution metal layers (e.g., 1 , 6 or more metal layers).
Θ070] The first die 606 is coupled to a first surface of the dielectric layer 602 through a first set of interconnects 616. In some implementations, the first set of interconnects 616 are metal pillars (e.g., metal layers). In some implementations, the metal pillars are copper pillars. In some implementations, the first die 606 is electrically coupled to at least one of the set of solder bails 604 through the first set of interconnects 616, the first set of redistribution interconnects 630, the first UBM layer 632, the second set of redistribution interconnects 640, and/or the second UBM layer 642,
[0071] The second die 608 is coupled to the first surface of the dielectric layer 602 through a second set of interconnects 618. In some implementations, the second set of interconnects 618 are metal pillars (e.g., metal layers). In some implementations, the metal pillars are copper pillars. In some implementations, the second die 608 is electrically coupled to at least one of the set of solder bails 604 through the second set of interconnects 618, the third set of redistribution interconnects 650, and/or the third UBM layer 652.
[0072] As shown in FIG. 6, the first die 606 may be electrically coupled to the second die 608 through the fifth set of redistribution interconnects 680.
[0073] Having described several integrated devices, a sequence for providing / manufacturing an integrated device (e.g., semiconductor device) will now be described below.
Exemplary Sequence for Providing / Manufacturing an Integrated Device That Includes a Redistribution Layer [0074] In some implementations, providing an integrated device (e.g., integrated package) that includes redistribution layers includes several processes. FIGS. 7A-7D illustrate an exemplar}' sequence for providing an mtegrated device. In some implementations, the sequence of FIGS. 7A-7D may be used to provide / manufacture the integrated device of FIGS. 2 and/or 5-6, and/or other integrated, devices described in the presen! disclose.
[0075] It should also be noted that the sequence of FIGS. 7A-7D may be used to provide / manufacture integrated devices that also include circuit elements. It should further be noted that the sequence of FIGS. 7A-7D may combine one or more stages in order to simplify and/or clarity the sequence for providing an integrated device that includes several dies.
[Θ076] In some implementations, the process of FIGS. 7A-7D illustrates a novel process that provides an integrated device with high density interconnects (e.g., pitch between interconnects is about 40 microns or less) and/or an integrated device that bypasses the use of unnecessary big landing pads (e.g., big bump pads).
[0077] As shown in stage 1 of FIG. 7 A, a carrier (e.g., carrier 700), a first set of interconnects 702 (e.g., first set of traces) and a second set of interconnects 704 (e.g., second set of traces) are provided. In some implementations, the carrier is a substrate. Different implementations may use different materials for the carrier (e.g., silicon substrate, glass substrate, ceramic substrate).
[0078] At stage 2, several dies are provided on the carrier. As shown in stage 2, a first die 712 and a second die 714 are provided on the earner 700. Specifically, the front sides (active sides) of the first die 712 and the second die 714 are coupled to the carrier 700. Examples of dies are described in FIGS. 3-4. The first die 712 includes a first set of interconnects 722 (e.g., bumps, copper pillar). The second die 714 includes a second set of interconnects 724 (e.g., bumps, copper pillar). As shown at stage 2, the first set of interconnects 722 of the first die 712 is coupled to the first set of interconnects 702 of the carrier 700. Similarly, the second set of interconnects 724 of the second die 714 is coupled to the second set of interconnects 704 of the earner 700. In some implementations, the first die 712 and/or the second die 714 are wafer level dies.
[0079] At stage 3, an underfill 730 is provided on the carrier 700. In some implementations, the underfill 730 is provided such that the underfill 730 covers the first set of interconnects 702, the second set of interconnects 704, the first set of interconnects 722, and. the second set of interconnects 724. In some implementations, providing the underfill 730 is optional.
[0080] At stage 4, an encapsulation material 740 is provided. The encapsulation material 740 substantially or completely surrounds or encapsulates the first die 712 and the second die 714.
[0081 ] At stage 5, as shown in FIG. 7B, the integrated device is flipped and coupled to a temporary carrier 742. That is, the encapsulation material 740 is coupled to the temporary carrier 742. Different implementations may use different materials (e.g., substrate, silicon, glass, ceramic) for the carrier 742. in some implementations, an adhesive layer (not shown) may be used to couple the encapsulation material 740 of the integrated device to the temporary carrier 742. Different implementations may use different materials for the adhesion layer. In some implementations, the temporary carrier 742 is a bonding tape.
[0082] At stage 6, a first surface of the integrated device is removed (e.g., polished, grinded). In this example, the surface that includes the carrier 700 is removed (e.g., polished, grinded). In some implementations, polishing the integrated, device may include polishing and/or grinding the carrier 700, the first set of interconnects 702, the second set of interconnects 704, the first set of interconnects 722, the second set of interconnects 724, the underfill 730, and/or the encapsulation material 740. In some implementations, polishing the integrated device may leave behind portions of the first set of interconnects 702, the second set of interconnects 704, the first set of interconnects 722, the second set of interconnects 724, the underfill 730, and/or the encapsulation material 740.
[0083] At stage 7, a first dielectric layer 750 and several redistribution interconnects (e.g., redistribution interconnects 751-755) are provided on the front side of the first die 712 and the second, die 714. Specifically, several interconnects are provided on the first set of interconnect 722 and the second set of interconnects 724. In some implementations, the redistribution mterconnects 751 -755 are formed on a first redistribution metal layer. In some implementations, the redistribution interconnects 755-755 may include at least one via. In some implementations, the redistribution interconnects 751-755 bypasses the use of unnecessary landing pads (e.g., big bump pads) when coupling to the first set of interconnect 722 and/or the second set of interconnects 724. In some implementations, the redistribution interconnects 751-755 are directly coupled to the first set of interconnect 722 and/or the second set of interconnects 724.
[0084] At stage 8, as shown in FIG, 7C, a second dielectric layer 760 and several redistribution interconnects (e.g., redistribution interconnects 761-764) are provided on the first dielectric layer 750 and the redistribution interconnects 751 - 754. In some implementations, the redistribution interconnects 761-764 are formed on a second redistribution metal layer. In some implementations, the redistribution interconnects 761 -764 may include at least one via.
[Θ085] At stage 9, a third dielectric layer 770 and several redistribution interconnects (e.g., redistribution interconnects 771 -774) are provided on the second dielectric layer 760 and the redistribution interconnects 761-764. In some implementations, the redistribution interconnects 771-774 is formed on a third redistribution metal layer. In some implementations, the redistribution interconnects 771 -774 may include at least one via.
[0086] At stage 10, at least one under bump metallization (UBM) layer is provided. Specifically, a first under bump metallization (UBM) layer 781, a second UBM layer 782, a third UBM layer 783, and a fourth UBM layer 784 are provided. The UBM layers are provided, on the fourth dielectric layer 780. In some implementations, providing the UBM layer is optional
[0087] At stage 1 1 , as shown in FIG. 7D, at least one solder ball is provided on the UBM layer. Specifically, a first solder bail 791 is coupled to the first UBM layer 781 , a second solder ball 792 is coupled to the second UBM layer 782, a third solder ball 793 is coupled to the third UBM layer 783, and a fourth solder bail 794 is coupled to the fourth UBM layer 784. Stage 1 1 illustrates the set of dielectric layers 790. In some implementations, the set of dielectric layers 790 includes the dielectric layers 750, 760, 770 and. 780. In some implementations, the solder ball may be coupled to the redistribution interconnects instead of a UBM layer.
[0088] At stage 12, a portion of the integrated device is removed (e.g., polished). As shown at stage 12, at least a portion of the carrier 742 is removed (e.g., entire carrier 742 is removed). In some implementations, at least a portion of the encapsulation material 740 is also removed.
Exemplary Sequence for Providing / Manufacturing an Integrated Device That includes a Redistribution Layer [0089] In some implementations, providing an integrated device (e.g., integrated package) that includes redistribution layers mcludes several processes. FIGS. 8A-8D illustrate an exemplar}' sequence for providing an integrated device. In some implementations, the sequence of FIGS. 8A-8D may be used to provide / manufacture the integrated device of FIGS. 2 and/or 5-6, and/or other integrated devices described in the presen ! disclose.
[0090] It should also be noted that the sequence of FIGS. 8A-8D may be used to provide / manufacture integrated devices that also include circuit elements. It should further be noted that the sequence of FIGS. 8A-8D may combine one or more stages in order to simplify and/or clarity the sequence for providing an integrated device that includes several dies.
[0091] In some implementations, the process of FIGS. 8A-8D illustrates a novel process thai provides an integrated device with high density interconnects (e.g., pitch between interconnects is about 40 microns or less) and/or an integrated device that bypasses the use of unnecessary big landing pads (e.g., big bump pads).
[0092] As shown in stage 1 of FIG. 8A, a carrier (e.g., carrier 800), a first set of interconnects 802 (e.g., first set of traces) and a second set of interconnects 804 (e.g., second set of traces) are provided. In some implementations, the carrier is a substrate. Different implementations may use different materials for the carrier (e.g., silicon substrate, glass substrate, ceramic substrate).
[0093] At stage 2, several dies are provided on the carrier. As shown in stage 2, a first die 812 and a second die 814 are provided on the carrier 800. Specifically, the front side (active side) of the first die 812 and the second die 814 are coupled to the carrier 800. Examples of dies are described in FIGS. 3-4. The first die 812 includes a first set of interconnects 822 (e.g., bumps, copper pillar). The second die 814 includes a second set of interconnects 824 (e.g., bumps, copper pillar). As shown at stage 2, the first set of interconnects 822 of the first die 812 is coupled to the first set of interconnects 802 of the carrier 800. Similarly, the second set of interconnects 824 of the second die 814 is coupled to the second set of interconnects 804 of the carrier 800. In some implementations, the first die 812 and/or the second die 814 are wafer level dies.
[0094] At stage 3, an underfill 830 is provided on the carrier 800. In some implementations, the underfill 830 is provided such that the underfill 830 covers the first set of interconnects 802, the second set of interconnects 804, the first set of interconnects 822, and. the second set of interconnects 824. In some implementations, providing the underfill 830 is optional.
[0095] At stage 4, an encapsulation material 840 is provided. The encapsulation material 840 substantially or completely surrounds or encapsulates the first die 812 and the second die 814.
[0096] At stage 5, as shown in FIG. 8B, the integrated device is flipped and coupled to a temporary carrier 842. That is, the encapsulation material 840 is coupled to the temporary carrier 842. Different implementations may use different materials (e.g., substrate, silicon, glass, ceramic) for the carrier 842. In some implementations, an adhesive layer (not shown) may be used to couple the encapsulation material 840 of the integrated device to the temporary carrier 842. Different implementations may use different materials for the adhesion layer. In some implementations, the temporary carrier 842 is a bonding tape.
[0097] At stage 6, a first surface of the integrated device is removed (e.g., polished, grinded). In this example, the surface that includes the carrier 800 is removed (e.g., polished, grinded). In some implementations, polishing the integrated, device may include polishing and/or grinding the carrier 800, the first set of interconnects 802, the second set of interconnects 804, the first set of interconnects 822, the second set of interconnects 824, the underfill 830, and/or the encapsulation material 840. In some implementations, polishing the integrated device may leave behind portions of the first set of interconnects 802, the second set of interconnects 804, the first set of interconnects 822, the second set of interconnects 824, the underfill 830, and/or the encapsulation material 840.
[0098] In some implementations, polishing the integrated device includes creating at least o e cavity (e.g., cavities 825) in the integrated device. For example, the cavity 825 may be created in the underfill 830 and/or the encapsulation material 840.
Θ099] At stage 7, a metal layer is provided in the cavity 825. The metal layer defines an interconnect from a set of interconnects 826. When several cavities are created, several metal layers may be provided i some implementations. The set of interconnects 826 electrically couples the first set of interconnects 822 and the second set of interconnects 824. In some implementations, the set of interconnects 826 electrically couples the first die 812 and the second die 814. In some implementations, the set of interconnects 826 bypasses the use of unnecessary landing pads (e.g., big bump pads) when coupling to the first set of interconnects 822 and/or the second set of interconnects 824. In some implementations, the set of interconnects 826 is directly coupled to the first set of interconnects 822 and the second set of interconnects 824. In some implementations, the set of interconnects 826 is coupled to the side surface of the first set of interconnects 822 and the side surface of the second set of interconnects 824. In some implementations, the set of interconnects 826 is coupled to the top surface of the first set of interconnects 822 and the top surface of the second set of interconnects 824. In some implementations, the set of interconnects 826 are high density interconnects. In some implementations, a pitch of the set of interconnects 826 is about 40 microns (μηι) or less.
[00100] At stage 8, a first dielectric layer 850 and several redistribution interconnects (e.g., redistribution interconnects 851-854) are provided on the front side of the first die 812 and the second die 814. Specifically, several interconnects are provided on the first set of interconnect 822 and the second set of interconnects 824. In some implementations, the redistribution mierconnects 851 -854 are formed on a first redistribution metal layer. In some implementations, the redistribution interconnects 855-854 may include at least one via. In some implementations, the redistribution interconnects 851 -854 bypasses the use of unnecessary landing pads (e.g., big bump pads) when coupling to the first set of interconnect 822 and/or the second set of interconnects 824. In some implementations, the redistribution interconnects 851-854 are directly coupled to the first set of interconnects 822 and'Or the second set of interconnects 824.
[00101] At stage 9, as shown in FIG. 8C, a second dielectric layer 860 and several redistribution interconnects (e.g., redistribution interconnects 861-864) are provided on the first dielectric layer 850 and the redistribution interconnects 851-854. In some implementations, the redistribution interconnects 861-864 is formed on a second redistribution metal layer. In some implementations, the redistribution interconnects 861 -864 may include at least one via.
Θ0102] At stage 1 0, a third dielectric layer 870 and several redistribution interconnects (e.g., redistribution interconnects 871-874) are provided on the second dielectric layer 860 and the redistribution interconnects 861-864. In some implementations, the redistribution interconnects 871 -874 is formed on a third redistribution metal layer. In some implementations, the redistribution interconnects 871-874 may include at least one via. [00103] At stage 11, at least one under bump metallization (UBM) layer is provided. Specifically, a first under bump metallization (UBM) layer 881 , a second UBM layer 882, a third UBM layer 883, and a fourth XJBM layer 884 are provided. The UBM layers are provided, on the fourth dielectric layer 880. In some implementations, providing the UBM layer is optional
[00104] At stage 12, as shown in FIG. 8D, at least one solder ball is provided on the XJBM layer. Specifically, a first solder bail 891 is coupled to the first UBM layer 881 , a second solder ball 892 is coupled to the second UBM layer 882, a third solder ball 893 is coupled to the third UBM layer 883, and a fourth solder bail 894 is coupled to the fourth UBM layer 884. Stage 12 illustrates the set of dielectric layers 890. In some implementations, the set of dielectric layers 890 includes the dielectric layers 850, 860, 870 and. 880. In some implementations, the solder ball may be coupled to the redistribution interconnects instead of the UBM layer.
[00105] At stage 13, a portion of the integrated device is removed (e.g., polished). As shown at stage 12, at least a portion of the carrier 842 is removed (e.g., entire carrier 842 is removed). In some implementations, at least a portion of the encapsulation material 840 is also removed.
[00106] Having described, a sequence for providing / manufacturing an integrated device (e.g., semiconductor device), a method for providing / manufacturing an integrated device (e.g., semiconductor device) will now be described below.
Exemplary Method for Providing / Manufacturing an Integrated Device
[00107] FIG. 9 illustrates an exemplary method for providing an integrated device (e.g., integrated package). In some implementations, the method of FIG. 9 may be used to provide / manufacture the integrated device of FIGS. 2 and/or 5-6, and/or other integrated devices (e.g., die package) described in the present disclose.
[00108] The method provides (at 805) a first carrier (e.g., carrier 800) and interconnects (e.g., traces). In some implementations, the first earner is a sacrificial carrier. In some implementations, the first carrier is a substrate. Different implementations may use different materials for the first carrier (e.g., silicon substrate, glass substrate, ceramic substrate).
[00109] The method then provides (at 910) at. least one integrated device (e.g., die) on the carrier. In some implementations, providing (at 810) at least one integrated device includes providing a first die on the first carrier and providing a second die on the first carrier. In some implementations, the dies that are provided are wafer level dies. Examples of providing at least one die is shown in FIG. 8A (see e.g.. stage 2).
[00110] The method optionally provides (at 815) an underfill and an encapsulation material In some implementations, the underfill is provided, between the dies and the first carrier. In some implementations, the interconnects 802, 804, 822, and 824 are covered by the underfill In some implementations, the encapsulation material substantially or completely suirounds or encapsulates the dies (e.g., first die 812, the second die 814).
[00111] The method couples (at 920) the integrated device that includes the first carrier and. the first and second dies, to a second carrier. In some implementations, the second carrier is a temporary carrier. Different implementations may use different materials for the second carrier. In some implementations, the second carrier is a bonding tape.
[001 2] The method further removes (at 925) at least a portion of the integrated device. In some implementations, removing at least a portion of the integrated device includes removing (e.g., polishing, grinding) at least the first carrier, portions of the underfill, potions of the encapsulation layer, and/or the interconnects (e.g., interconnects 802, 804, 822, 824). In some implementations, after removing a portion of the integrated device, at least one metal layer may be provided, in a cavity. In some implementations, the metal layer in the cavity may define an interconnect (e.g., high density interconnect between two dies).
[00113] The method further provides (at 930) at least one dielectric layer (e.g., dielectric layers 850, 860, 870. 880). Different implementations may use different materials for the dielectric layers. For example, first and second insulation layers (which are a form of a dielectric layer) may be a Poiybenzoxazole (FbO) layer and/or a polymer layer.
[00114] The method also provides (at 935) several metal redistribution layers. In some implementations, providing several redistribution layers includes providing several redistribution interconnects (e.g., redistribution interconnects 851 -854) and/or vias. It should be noted that in some implementations, the method of providing (at 930) at least one dielectric layer, and providing (at 935) the metal redistribution layers may be performed sequentially back and forth. That is, in some implementations, the method may provide a first dielectric layer, a first redistribution layer, a second dielectric layer, a second redistribution layer, and so on and so forth. [00115] The method then optionally provides (at 940) an under bump metallization (UBM) layer. In some implementations, providing (at 940) the UBM layer includes coupling the UBM layer to a metal redistribution layer. In some implementations, the UBM layer is a copper layer. The method further provides (at. 945) a solder bail on the UBM layer.
[00116] The method further removes (at 950} at least a portion of the integrated device. In some implementations, removing a portion of the integrated device includes removing (e.g., polishing, grinding) at least a portion of the carrier 842. In some implementations, at least a portion of the encapsulation material 840 is also removed.
Exemplary Sequence for Providing / Manufacturing Redistribution Layers
[00117] In some implementations, providing an integrated device that includes redistribution layers includes several processes. FIGS. 1 OA- IOC illustrate an exemplary sequence for providing an integrated device that includes several redistribution layers. In some implementations, the sequence of FIGS. 1 OA- IOC may be used to provide / manufacture the integrated device of FIGS. 2 and/or 5-6. and/or other integrated devices (e.g., dies) described in the present disclose. It should also be noted that the sequence of FIGS. 1 OA- IOC may be used to provide / manufacture integrated devices that also include circuit elements. It should further be noted that the sequence of FIGS. 10A~ IOC may combine one or more stages in order to simplify and/or clarify the sequence for providing an integrated device that includes redistribution layers. FIGS. lOA-lOC a more specific process for providing one or more redistribution layers.
[00118] As shown in stage 1 of FIG. 10A, a substrate (e.g., substrate 1001) is provided. In some implementations, the substrate 1 001 is a wafer. Different implementations may use different materials for the substrate (e.g., silicon substrate, glass substrate, ceramic substrate).
[00119] In addition, at stage 1 , several lower level metal layers and dielectric layers (e.g., lower level metal and dielectric layers 1002) are provided on the substrate 1001 . Different implementations may provide different number of lower level metal layers and dielectric layers (e.g., Ml metal layer, M2 metal layer, M3 metal layer, M4 metal layer, M5 metal layer, M6 metal layer, M7 metal layer).
[00120] In some implementations, circuits, routes and/or interconnects are also provided.. However, for the purpose of simplification and clarity, circuits, routes and/or interconnects are not shown in the lower level metal layers and dielectric layers 1002. [00121] Moreover, at stage 1, at least one pad (e.g., pads 1004, 1025, 1029} is provided on the lower level metal layers and dielectric layers 1002. In some implementations, the pad 1004 is coupled to one of the lower level metal layer (e.g., the top lower level metal layer, M7 metal layer). In some implementations, the pad 1004 is an aluminum pad.. However, different implementations may use different materials for the pad 1004. Different implementations may use different processes for providing the pad on the lower level metal layers and dielectric layers 1002. For example, in some implementations, a lithography and/or etching process may be use to provide the pad 1004 on the lower level metal layers and dielectric layers 1002.
[00122] Additionally, at stage 1, a passivation layer (e.g., passivation layer 1006) is provided, on the lower level metal layers and dielectric layers 1002. Different implementations may use different materials for the passivation layer 1006. As shown in stage 4, the passivation layer 1006 is provided on the lower level metal layers and dielectric layers 1002 such that at least a portion of the pad 1004 is exposed.
[00123] At stage 2, a first insulation layer (e.g., first insulation layer 1008) is provided on the passivation layer 1006 and the pads 1004, 1025 and 1029. In some implementations, the first insulation layer 1008 is a dielectric layer. Different implementations may use different materials for the first insulatio layer 1008. For example, the first insulation layer 1008 may be a Polybenzoxazole (FbO) layer or a polymer layer.
[00 24] At stage 3, several cavities (e.g., cavity, trench) is provided. / created in the first insulation layer 1008. As further shown in stage 3, the cavity 1009 is created over the pad 1004. Similarly, a cavity 1011 is created over the pad 1025, and a cavity 1013 is created over the pad 1029. Different implementations may create the cavities (e.g., cavity 1009) differently. For example, the cavity 1009 may be provided / created by etching the first insulation layer 1008.
[00125] At stage 4 of FIG. 10B, a first metal redistribution layer is provided. Specifically, a first metal redistribution layer 1010 is provided over the pad 1 004 and the first insulation layer 1008. As shown in stage 4, the first metal redistribution layer 1010 is coupled to the pad 1004. The first metai redistribution layer 1010 also inciudes a first metal layer 1030 and a second metal layer 1032. That is, in some implementations, the first metal layer 1030 and the second metal layer 1032 is on the same layer as the first metai redistribution layer 1010. In some implementations, the first and second metal layers 1030 and 1032 are vias. In some impiemeniations, the first metal redistribution layer 1010 is a copper layer.
[00126] At stage 5, several insulation layers and several redistribution layers are provided. Specifically, a second insulation layer 1014 and a third insulation layer 1016 are provided. Moreover, a second metal redistribution layer 1020 is provided.. In addition, several metal layers (1040, 1050, 1042, 1052) are provided. In some implementations, the metal layers are part of the redistribution layers. In some implementations, some of the metal layers include vias. For example, metal layers 1042, and 1052 are vias and metal layers 1040 and 1050, are traces in some implementations.
[00127] At stage 6, a cavity 1017 is provided in the insulation layer 1 016. The cavity 1017 in the insulation layer 1016 is over a portion of the second metal redistribution layer 1020 (e.g., interconnect).
[00128] At stage 7 of FIG. IOC, an under bump metallization (XJBM) layer is provided. Specifically, an under bump metallization (UBM) layer 1070 is provided in the cavity 101 7 of the insulation layer 1016, In some implementations, the UBM layer 1070 is a copper layer.
[00129] At stage 8, a solder ball is provided on the UBM layer. Specifically, a solder ball 1080 is coupled to the UBM layer 1070.
Exemplary Electronic Devices
[00130] FIG. 1 1 illustrates various electronic devices that may be integrated with any of the aforementioned semiconductor device, integrated circuit, die, interposer or package. For example, a mobile telephone 1102, a laptop computer 1 104, and a fixed location terminal 1 106 may include an integrated circuit (IC) 1100 as described herein. The IC 1 100 may be, for example, any of the integrated circuits, dice or packages described herein. The devices 1 102, 1 104, 1 106 illustrated in FIG. 11 are merely exemplary. Other electronic devices may also feature the IC 1 100 including, but not limited to, mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, GPS enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers or any other device that stores or retrieves data or computer instructions, or any combination thereof. [00131] One or more of the components, steps, features, and/or functions illustrated, in FIGS. 2, 3, 4, 5, 6, 7A-7D, 8A-8D, 9, 1 OA- IOC and/or 1 1 may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from the disclosure. It should also be noted that FIGS. 2, 3, 4, 5, 6, 7A-7D, 8A-8D, 9, iOA-iOC and/or 11 and its corresponding description in the present disclosure is not limited to dies and/or ICs. In some implementations, 2, 3, 4, 5, 6, 7A-7D, 8A-8D, 9, lOA-lOC and/or 11 and its corresponding description may be used to manufacture, create, provide, and/or produce integrated, devices. In some an integrated, device may include a die package, an integrated circuit (IC), a wafer, a semiconductor device, and/or an interposer.
[Θ0132] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspects" does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term "coupled" is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C may still be considered coupled to one another even if they do not directly physically touch each other.
[00133] Also, it is noted that the embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed ixi parallel or coxicurrexitly. Ixi addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed.
[00134] The various features of the disclosure described herein can be implemented in different systems without departing from the disclosure. It should be noted, that the foregoing aspects of the disclosure are merely examples and are not to be construed as limiting the disclosure. The description of the aspects of the present disclosure is intended to be illustrative, and not to limit the scope of the ciaims. As such, the present teachings can be readily applied to other types of apparatuses and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

CLAIMS WHAT IS CLAIMED IS:
1. An integrated device comprising:
a base portion for the integrated device, the base portion comprising;
a dielectric layer; and
a set of redistribution metal layers;
a first die coupled to a first surface of the base portion; and.
an underfill between the first die and the base portion.
2. The mtegrated device of claim 1, further comprising an encapsulation material that encapsulates the first die.
3. The integrated device of claim 1 , further comprising a second die coupled to the first surface of the base portion.
4. The integrated device of claim 3, further comprising a set of interconnects on the base portion, the set of interconnects electrically coupling the first die and the second die.
5. The integrated device of claim 4, wherein the first die comprises a first set of interconnect pillars and the second, die comprises a second set of interconnect pillars, the set of interconnects being coupled to the first set of interconnects pillars and the second set of interconnect pillars while bypassing a landing pad.
6. The integrated device of claim 4. wherein the set of interconnects comprises a first pitch that is about 40 microns (μπι) or less.
7. The integrated device of claim 1 , wherein the first die is a first wafer level die.
8. The integrated device of claim 1 , wherein the first die comprises a first set of interconnect pillars, the first die being coupled to the set of redistribution metal layers through the first set of interconnect pillars.
9. The integrated device of claim 8, wherein the first set of interconnect pillars comprises a first pitch that is about 40 microns (um) or less.
10. The integrated device of claim 1 , wherein the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.
1 1. An apparatus comprising:
a base portion for an integrated, device, the base portion comprising:
a dielectric layer; and
a redistribution means;
a first die coupled to a first surface of the base portion; and
a means for encapsulating an area between the first die and the base portion.
12. The apparatus of claim 11, further comprising an encapsulation means that encapsulates the first die,
13. The apparatus of claim 11 . further comprising a second die coupled to the first surface of the base portion.
14. The apparatus of claim 13, further comprising a set of interconnects on the base portion, the set of interconnects electrically coupling the first die and the second die.
15. The apparatus of claim 14, wherein the first die comprises a first set of interconnect pillars and the second die comprises a second set of interconnect pillars, the set of interconnects being coupled to the first set of interconnects pillars and the second set of interconnect pillars while bypassing a la ding pad.
16. The apparatus of claim 14, wherein the set of interconnects comprises a first pitch that is about 40 microns (μηι) or less.
17. The apparatus of claim 11 . wherein the first die is a first wafer level die.
18. The apparatus of claim 1 1. wherein the first die comprises a first set of ix erconnect pillars, the first die being coupled to the redistribution means through the first set of interconnect pillars.
19. The apparatus of claim 18, wherein the first set of interconnect pillars comprises a first pitch that is about 40 microns (μχη) or less.
20. The apparatus of claim 1 1 , wherein the apparatus is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.
21. A method for providing an integrated device, comprising:
forming a base portion for the i tegrated device, wherein forming the base portion comprises:
forming a dielectric layer; axid
forming a set of redis rib tion metal layers;
providing a first die on a first surface of the base portion; and.
forming an underfill between the first die and the base portion.
22. The method of claim 21, farther comprising forming an encapsulation material that encapsulates the first die.
23. The method of claim 21, further comprising providing a second die on the first surface of the base portion.
24. The method of claim 23, further comprising forming a set of interconnects on the base portion, the set of interconnects electrically coupling the first die and. the second die.
25. The method of claim 24, wherein the first die comprises a first set of interconnect pillars and the second die comprises a second, set of interconnect pillars, the set of interconnects being coupled to the first set of interconnects pillars and the second set of interconnect pillars while bypassing a landing pad.
26. The method of claim 24, wherein the set of interconnects comprises a first pitch that is about 40 microns (μ ι) or less.
27. The method of claim 21, wherein the first die is a first wafer level die.
28. The method of claim 21 , wherein the first die comprises a first set of ixiterconnect pillars, the first die being coupled to the set of redistribution metal layers through the first set of interconnect pillars.
29. The method of claim 28, wherein the first set of interconnect pillars comprises a first pitch that is about 40 microns (μτη) or less.
30. The method of claim 21, wherein the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018009145A1 (en) * 2016-07-08 2018-01-11 Agency For Science, Technology And Research A semiconductor package and methods of forming the same
US10727185B2 (en) * 2016-09-30 2020-07-28 Intel Corporation Multi-chip package with high density interconnects
US9799618B1 (en) * 2016-10-12 2017-10-24 International Business Machines Corporation Mixed UBM and mixed pitch on a single die
US11152274B2 (en) 2017-09-11 2021-10-19 Advanced Semiconductor Engineering, Inc. Multi-moldings fan-out package and process
US10181449B1 (en) * 2017-09-28 2019-01-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure
US11217555B2 (en) * 2017-09-29 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Aligning bumps in fan-out packaging process
KR102124892B1 (en) * 2017-09-29 2020-06-22 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Aligning bumps in fan-out packaging process
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10867954B2 (en) 2017-11-15 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect chips
US10679946B2 (en) * 2018-04-10 2020-06-09 Wispry, Inc. Methods and devices for solderless integration of multiple semiconductor dies on flexible substrates
US10665673B2 (en) 2018-06-28 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure with non-gated well tap cell
US11832391B2 (en) * 2020-09-30 2023-11-28 Qualcomm Incorporated Terminal connection routing and method the same
CN112420531B (en) * 2020-11-27 2021-11-30 上海易卜半导体有限公司 Semiconductor packaging method, semiconductor assembly and electronic equipment comprising semiconductor assembly
CN113169075B (en) * 2021-02-08 2022-06-03 广东省科学院半导体研究所 Chip interconnection packaging structure and method
US11869833B2 (en) * 2021-09-15 2024-01-09 Qualcomm Incorporated Package comprising a substrate with a via interconnect coupled to a trace interconnect and method of fabricating the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110316156A1 (en) * 2010-06-24 2011-12-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect
US20110316146A1 (en) * 2010-06-24 2011-12-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Anisotropic Conductive Film Between Semiconductor Die and Build-Up Interconnect Structure

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
JP3728847B2 (en) * 1997-02-04 2005-12-21 株式会社日立製作所 Multi-chip module and manufacturing method thereof
US8574959B2 (en) * 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
JP2008091638A (en) * 2006-10-02 2008-04-17 Nec Electronics Corp Electronic equipment, and manufacturing method thereof
US20080142946A1 (en) * 2006-12-13 2008-06-19 Advanced Chip Engineering Technology Inc. Wafer level package with good cte performance
JP2009059771A (en) * 2007-08-30 2009-03-19 Kyushu Institute Of Technology Wafer level chip-size package and manufacturing method thereof
US10074553B2 (en) * 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
KR101214746B1 (en) * 2008-09-03 2012-12-21 삼성전기주식회사 Wafer level package and method of manufacturing the same
JP5173758B2 (en) * 2008-11-17 2013-04-03 新光電気工業株式会社 Manufacturing method of semiconductor package
US8406004B2 (en) * 2008-12-09 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system and method of manufacture thereof
US8110926B2 (en) * 2009-01-30 2012-02-07 Broadcom Corporation Redistribution layer power grid
US8378383B2 (en) * 2009-03-25 2013-02-19 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer between stacked semiconductor die
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
TWI528514B (en) * 2009-08-20 2016-04-01 精材科技股份有限公司 Chip package and fabrication method thereof
US8742561B2 (en) * 2009-12-29 2014-06-03 Intel Corporation Recessed and embedded die coreless package
US8901724B2 (en) * 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US20110186960A1 (en) 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates
US8426961B2 (en) * 2010-06-25 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded 3D interposer structure
US8691626B2 (en) * 2010-09-09 2014-04-08 Advanced Micro Devices, Inc. Semiconductor chip device with underfill
US8435834B2 (en) * 2010-09-13 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP
US8786066B2 (en) * 2010-09-24 2014-07-22 Intel Corporation Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
US8384225B2 (en) 2010-11-12 2013-02-26 Xilinx, Inc. Through silicon via with improved reliability
US8754514B2 (en) * 2011-08-10 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip wafer level package
JP2013153122A (en) * 2011-10-20 2013-08-08 Nitto Denko Corp Method for manufacturing semiconductor device
US9786622B2 (en) * 2011-10-20 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package
US20130099371A1 (en) * 2011-10-21 2013-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having solder jointed region with controlled ag content
US9748203B2 (en) 2011-12-15 2017-08-29 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with conductive pillars and method of manufacture thereof
US8558395B2 (en) 2012-02-21 2013-10-15 Broadcom Corporation Organic interface substrate having interposer with through-semiconductor vias
US8878360B2 (en) * 2012-07-13 2014-11-04 Intel Mobile Communications GmbH Stacked fan-out semiconductor chip

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110316156A1 (en) * 2010-06-24 2011-12-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect
US20110316146A1 (en) * 2010-06-24 2011-12-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Anisotropic Conductive Film Between Semiconductor Die and Build-Up Interconnect Structure

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