WO2015132958A1

WO2015132958A1 - Input/output matching circuit

Info

Publication number: WO2015132958A1
Application number: PCT/JP2014/055981
Authority: WO
Inventors: 健治古後; 高司川本
Original assignee: 株式会社日立製作所
Priority date: 2014-03-07
Filing date: 2014-03-07
Publication date: 2015-09-11

Abstract

Provided is an input/output matching circuit, which maintains electrostatic resistance by means of ESD elements, and which, at the same time, has high-speed communication performance without being affected by noise. In the present invention, a plurality of ESD elements having different frequency characteristics, and elements thereof are connected to each other by means of coils, thereby constituting a matching circuit of the ESD elements and the coils.

Description

I / O matching circuit

The present invention relates to an electrostatic discharge element in a portion where a signal is input or output in a semiconductor chip that performs high-speed transmission in the Gbit / s band, and relates to a technique for suppressing communication deterioration due to this element.

In the information and communication field, with the spread of the Internet and smartphones and the progress of cloud computing, the amount of data to be processed by servers and routers in the data center has increased dramatically, and the need for large-scale information processing has expanded. In order to increase the data processing speed of these servers and routers, it is necessary to increase the signal transmission speed between the CPU (Central Processing Unit) and the memory and between the devices in addition to increasing the operating speed of the device alone. .

In recent years, devices such as servers and routers are required to have a throughput of Tbit / s class, and in order to satisfy this requirement, it is necessary to increase the speed of transmission between the CPU and the memory. Currently, there are several high-speed I / O (Input / Output) communication standards, such as PCI express and Ethernet, but the maximum communication speed exceeds 20 Gbit / s in any communication standard. In this way, as the transmission speed increases, the loss of the board and cable connecting the CPU-memory increases. Therefore, the wiring can be shortened by changing the application of the low-loss board and changing the device structure. Yes.

Simultaneously with such material development and structural studies, development of a waveform equalization technique for increasing the bandwidth using an LSI having a reverse characteristic of transmission loss is also in progress. Furthermore, when performing wired transmission, it is necessary to consider not only signal loss but also loss due to reflection caused by impedance discontinuity. Therefore, in order to reduce deterioration due to reflection, the transmission is such that the output impedance ZT of the transmission LSI, the line impedance ZL, and the input impedance ZR of the reception LSI become ZT = ZL = ZR = Z, as shown in FIG. It is required to align.
This Z is generally set to 50Ω for single-phase wiring and 100Ω for differential wiring, but the conductor width of the conductor is widened to reduce the conductor loss of the wiring and designed to have a differential of 85Ω. There is also a case. Thus, various measures are taken to reduce the loss of the signal transmission line.

Also, active elements such as transistors and diodes are provided inside the transmission LSI and the reception LSI that perform such communication. Therefore, when a high voltage such as static electricity is applied from the outside of the circuit, the active element is destroyed, causing a failure. Therefore, in order to protect the active element, an electrostatic protection circuit as shown in FIG. 25 is configured, and a termination resistor 15 and an ESD element 11 are provided between the pad 10 and the first stage transistor 13.

Note that 14 is a pad capacitance, and 16 is an input capacitance of a transistor. In an ESD (Electro Static Discharge) element, one diode is connected between the VDD voltage and the signal line, and between the signal line and the GND. By these two diodes, high voltage noise input from the outside is connected to VDD or GND with a low resistance to prevent a high voltage from being applied to the input of the transistor 13. Both diodes have the same allowable current tolerance and the same discharge current.

Thus, when the

capacitors

14 and 16 are connected in parallel to the signal line, the pass characteristic from the pad 10 to the transistor 13 becomes a low-pass characteristic. As a result, as shown in FIG. 26, as the frequency increases, the signal strength deteriorates, which causes a problem in high-speed transmission. For this reason, the input / output pads for high-speed signals are minimized to the extent that there is no problem in assembly, and measures such as setting a metal wiring prohibited area under the pads are taken to reduce the pad capacitance 14. In addition, by selecting a transistor having a small parasitic capacitance, the input capacitance 16 is reduced, and measures are taken so that the transistor 13 can operate with a high-speed signal.

However, when an element with a small PN junction area (details will be described later) is used to reduce the capacitance, the ESD element 11 also deteriorates the resistance to high voltage due to a disturbance and fulfills its original purpose. I can't. For this reason, it is impossible to take measures by changing the PN junction area or the like. Therefore, compared with the pad capacitance 14 and the input capacitance 16 of the transistor, the characteristic deterioration of high-speed transmission by the ESD element 11 becomes dominant.

Therefore, conventionally, in order to improve the high-speed transmission characteristic deterioration due to the ESD element, as shown in Patent Document 1 and Non-Patent Document 1, a coil is added and the ESD element and the coil are arranged symmetrically in the signal transmission direction. There is a technique for configuring a transmission line to increase the speed of signal passage.

US Patent Application Publication No. 2012 / 0314328A1

Conventionally, an ESD element is provided to protect an active element in an LSI. However, since this ESD element has a low-pass characteristic as described above, it causes deterioration of communication quality particularly in high-speed communication, and high-speed communication performance. Decreases.

On the other hand, the techniques disclosed in Patent Document 1 and Non-Patent Document 1 for improving the high-speed communication performance need to connect many ESD elements and coils, and increase the area and form three or more layers to form the coils. This results in a complicated shape requiring a large number of wiring layers. As the number of coil wiring layers increases, even the lower signal wiring area is used, so a wiring layer with a thin electrode thickness is used, which increases the resistance value of the coil and increases the passage loss in the coil. Let

Further, since the techniques disclosed in both documents have high transmission performance over a wide band including a high-frequency noise region, there is a disadvantage that it is easy to pick up unnecessary noise at the input / output portion of the LSI.
Accordingly, an object of the present invention is to realize an input / output matching circuit having high-speed communication performance that maintains electrostatic resistance by an ESD element and is not affected by noise.

In an LSI having a plurality of transistors on a semiconductor substrate, in order to exchange data with the outside of the LSI, a plurality of transistors are provided between the input / output pads in the LSI and the input / output transistors. A diode, a resistor, and a plurality of coils are arranged, and the LSI has at least two potentials, that is, a ground potential GND and a circuit drive power supply voltage. As a signal wiring from the pad to the transistor, the first coil, Are connected in this order, and between the first coil and the second coil, one end is connected to the signal wiring, the other end is connected to the power supply voltage, and one end is connected to the signal wiring. In addition, a second diode having the other end connected to GND is disposed, and the first diode has an anode connected to the signal wiring side and a cathode connected to the power supply voltage side so as to be reverse-biased. The second diode has a cathode connected to the signal wiring side and an anode connected to the GND side so as to be reverse-biased, and one end connected to the signal wiring and the other end connected to the power supply voltage between the second coil and the transistor. And a fourth diode having one end connected to the signal line and the other end connected to the GND. The third diode has an anode and a power supply on the signal line side so as to be reverse-biased. The cathode is connected to the voltage side, the cathode of the fourth diode is connected to the signal wiring side and the anode is connected to the GND side so as to be reverse-biased, and a resistor is arranged in parallel with the third diode or the fourth diode. The PN junction area of the first diode is larger than the PN junction area of the third diode, and the PN junction area of the second diode is larger than the PN junction area of the fourth diode. The diode is arranged such that the PN junction area of the first diode is smaller than the PN junction area of the third diode and the PN junction area of the second diode is smaller than the PN junction area of the fourth diode. Is done.

According to the present invention, it is possible to realize an LSI having input / output characteristics with low loss without being affected by noise even in a high-speed signal while maintaining the resistance to electrostatic discharge by the ESD element.

FIG. 3 is an equivalent circuit model diagram of the input matching circuit according to the first embodiment and its impedance characteristic diagram. FIG. 12 is another example of an equivalent circuit model diagram of the input matching circuit according to the first embodiment. The characteristic at the time of performing an electrostatic discharge test at the time of using Example 1 is shown. 3 is a frequency characteristic of a transmission signal according to the first embodiment. FIG. 3 is a schematic diagram of a metal wiring layer in an LSI according to the first embodiment. It is a figure which shows the layout pattern of the coil which concerns on Example 1. FIG. It is a figure which shows the layout pattern of the coil which concerns on Example 1. FIG. 4 shows another layout pattern of the coil according to the first embodiment. It is a figure which shows an example of the octagonal layout pattern of the coil which concerns on Example 1. FIG. It is a figure which shows an example of the circular layout pattern of the coil which concerns on Example 1. FIG. It is a figure which shows an example of the layout pattern miniaturized using the wiring of the coil which concerns on Example 1 using two layers. It is a figure which shows an example of the layout pattern created in order to reduce resistance with the coil which concerns on Example 1. FIG. It is a figure which shows an example of the layout pattern of the coil corresponding to the differential signal which concerns on Example 2. FIG. FIG. 10 is a diagram illustrating LSI control corresponding to a multi-protocol, multi-rate including a speed detection circuit inside or outside the LSI according to the third embodiment. FIG. 10 is a circuit diagram of an input matching circuit for performing band change according to a third embodiment. It is a frequency characteristic concerning the circuit of FIG. It is a figure which shows the layout pattern of the coil which concerns on the circuit of FIG. 7 is a cross-sectional view of an LSI mounting structure according to Embodiment 4. FIG. It is a figure which shows the upper surface structure of the LSI mounting structure based on the circuit of FIG. FIG. 10 is an equivalent circuit model diagram of the input matching circuit according to the fourth embodiment. FIG. 10 is a diagram illustrating a cross-sectional structure of an LSI mounting structure according to a fifth embodiment. FIG. 22 is a top view of the LSI mounting structure according to FIG. 21. FIG. 10 is an equivalent circuit model diagram of the input matching circuit according to the fifth embodiment. It is a figure which shows an example of the scene which uses LSI of an Example. It is a figure which shows the conventional input circuit. This is a conventional pass frequency characteristic. 1A is a top layout view and a cross-sectional view of an ESD element according to Example 1. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

The input / output matching circuit according to the first embodiment of the present invention will be described.
FIG. 1A is an equivalent circuit of the input circuit of the present invention. An ESD element having a large PN junction area is arranged on the PAD side, and an ESD element having a small PN junction area is arranged on the transistor side.

Coils

12 a and 12 b are inserted in series between the pad 10 and the input transistor 13.

ESD elements

11a and 11b are disposed between the coils. Further, a termination resistor 15 and

ESD elements

11c and 11d are arranged between the coil 12b and the input transistor 13. Elements having different PN coupling areas of these four ESD elements are used.

Fig. 1 (b) shows the characteristics of the ESD element. The horizontal axis represents frequency and the vertical axis represents impedance. Focusing on one ESD element, it can be largely divided into three regions. In the first region, the dominant factor that determines the impedance is the C component, and in the second region, the impedance decreases in inverse proportion to the frequency. In the second region, the dominant factor that determines the impedance is the R component, and the impedance is constant regardless of the frequency. The third region is a region where the dominant factor that determines the impedance is the L component, and the impedance increases in proportion to the frequency.

Using a plurality of ESD elements, the region in which R having the smallest impedance is the dominant factor is distributed in different frequency bands. By doing so, it is possible to widen the frequency region for electrostatic discharge. One method of using ESD element groups having different frequency characteristics is to change the PN junction area.

FIG. 27A shows an example of the top surface layout of the ESD element. The diode has a p-electrode and an n-electrode, and the n-electrode is formed so as to surround the p-electrode concavely. FIG. 27B shows a cross-sectional view of the ESD element taken along the line AA ′. An n-well is formed in the p-substrate, and a p + region and an n + region are provided in the n-well to perform a PN junction. The p + region and the n + region are connected to the p electrode and the n electrode, respectively. The product of the electrode width, the electrode length, and the number of electrodes of the p-electrode differs depending on the manufacturing process used. The product of the electrode width, the electrode length, and the number of electrodes is slightly different from the PN junction area. It is a measure of the bonding area.
That is, the

ESD elements

11a, 11b, 11c, and 11d can change the PN junction area between the ESD elements by providing a difference in the electrode width or electrode length, or both the electrode width and electrode length.

For example, if the electrode length of the ESD element 11a is 500 nm, a difference of about 10 times from the electrode length of 50 nm of 11c is provided. In addition, in order to equalize the resistance due to the positive side and the negative side due to static electricity, the discharge currents of the ESD element connected to the power supply side and the ESD element connected to GND are made uniform. Therefore, in the ESD element arranged on the GND side, the electrode length of the ESD element 11b is 250 μm, the electrode length of the ESD element 11d is 2.5 μm, the electrode length of the ESD element 11a> the electrode length of the ESD element 11c, and the ESD element The electrode length of 11b> the electrode length of the ESD element 11d, the magnitude relationship among the

ESD elements

11a and 11b and the

ESD elements

11c and 11d is aligned between the power supply side and the GND side.

As a result, the ESD capacitance on the pad side constituted by the

ESD elements

11a and 11b becomes larger than the ESD capacitance on the transistor side constituted by 11c and 11d, so that the low impedance band can be widened and electrostatic discharge can be prevented. The band to be suppressed can be widened.
When the ESD element 11 is inserted into the input portion of the circuit, resistance against static electricity and the like is increased. However, a mismatch occurs between the line connected to the LSI and the input or output impedance of the LSI, and the characteristics in the high frequency band are remarkably increased. It will be deteriorated.

Therefore, a coil is arranged between the pad and the

ESD elements

11a and 11b and between the

ESD elements

11a and 11b and the

ESD elements

11c and 11d, and a matching circuit is configured by the inductance of the coil and the capacitance of the ESD element. In the present invention, the pad capacitance 14, the input capacitance 16 of the input transistor, the combined capacitance of the

ESD elements

11a and 11b pair, and the combined capacitance of the

ESD elements

11c and 11d pair are different. The inductance of the

coils

12a and 12b is determined in consideration of the element characteristics.

When a plurality of ESD elements having different PN junction areas are arranged, in FIG. 1, an ESD element having a large PN junction area is arranged on the pad side, and an ESD element having a small PN junction area is arranged on the transistor side. By disposing an ESD element having a large PN junction area on the pad side, it is possible to maintain ESD resistance by reducing electrostatic discharge noise of a relatively high strength low frequency component.
In FIG. 2, contrary to FIG. 1, an ESD element having a small PN junction area is arranged on the PAD side, and an ESD element having a large PN junction area is arranged on the transistor side. This is because an ESD element with a large PN junction area, which is effective for reducing electrostatic discharge noise of low frequency components, is arranged in the subsequent stage, and the noise source is reduced due to the resistance component of the coil. Therefore, the size of the large low-frequency ESD element can be greatly reduced. Compared with FIG. 1, one coil is added. However, when an ESD element having a large capacity is arranged on the transistor side, the input capacity of the transistor is equivalently increased and the transistor cannot operate at high speed. Therefore, a high-frequency matching circuit is made by inserting a coil at this position.
Also, in order to increase the PN junction area on the pad side and reduce the PN junction area on the transistor side, the electrode length of the ESD element 11a <the electrode length of the ESD element 11c and the ESD element 11b, contrary to FIG. <The electrode length of the ESD element 11d.

FIG. 3 shows the characteristics when an electrostatic discharge test is performed when Example 1 is used. FIG. 3A is a circuit diagram of a human body model used in the test. Electric charge is supplied to a 100 pF capacitor through a 1 MΩ resistor. After the charge is sufficiently charged, the switch is connected to the resistance 1.5 kΩ side to inject the charge into the circuit. The waveform of the injected current is shown in FIG. The voltage applied to the transistor 13 when this current is injected is shown in FIG. In the first embodiment, the maximum applied voltage of the transistor is smaller than that in the conventional method (FIG. 25) due to the broadening of the electrostatic discharge suppression region and the increase in wiring resistance due to the coil insertion. That is, it can be seen that even when voltages of the same strength are applied, the voltage applied to the transistor is smaller in Example 1 and the electrostatic resistance is maintained.

FIG. 4 shows the frequency characteristics of the transmission signal of the first embodiment. FIG. 4A shows reflection characteristics when viewed from the pad 10. Compared with the conventional method (FIG. 25) which does not use a coil, Example 1 can reduce reflection to a high frequency of about 20 GHz. By improving the reflection characteristic, the pass characteristic from the pad 10 to the transistor 13 can pass a signal having a high frequency of 10 GHz or more as shown in FIG. However, in the first embodiment, the resistance due to the wiring increases due to the addition of the coil, and the pass characteristic is deteriorated in the low frequency region as compared with the conventional method. Since this resistance is a component connected in series with the signal path, it is desirable to reduce it as much as possible in order to increase the loss of pass characteristics in the entire frequency band.

FIG. 5 shows a schematic diagram of a metal wiring layer in the LSI according to the first embodiment. It has a total of nine wiring layers including the pads. Each layer is connected by VIA. In this wiring structure, two types of wiring conductor thicknesses are used: a thin layer of wiring conductors M1 to M6 and a thick layer of wiring conductors M7 and M8. A layer having a thin wiring conductor thickness has a small change in the wiring width in the thickness direction, so that the wiring width can be reduced, so that wiring can be performed at a high density. However, since the width is narrow and the thickness is thin, the wiring resistance becomes high, which is suitable as a short distance wiring. For this reason, a pattern having a narrow wiring width is used for M1 to M4 for connecting the transistors in the block at a very short distance. Furthermore, for M5 and M6 used as connections between adjacent blocks, high-density wiring is not required for M1 to M4, so although the wiring conductor layer is thin, the wiring width is made wider than M1 to M4 to lower the wiring resistance. To use. The wiring layers M7 and M8 are used for connection between power supply wiring and long-distance blocks. Since the wiring layer is thick and the wiring width is large, high-density wiring cannot be performed, but wiring resistance can be reduced. Therefore, a thick layer of M7 and M8 wiring conductors is suitable for reducing the conductor loss of the coil. Since the pad layer is also thick, the pad layer may be formed including the pad layer.

FIG. 6 shows a coil layout pattern (only the coil 12a is described) used in the first embodiment. The pad and M8 are connected, and the M8 layer is wired spirally from the outside to the inside. Finally, M8 and M7 are connected inside by VIA78 and pulled out from M7, and a signal is input to the circuit. At this time, by drawing out the lead lines of M8 and M7 in the opposite side direction, the coil can be disposed between the front-stage circuit and the rear-stage circuit relatively easily.

In Example 1, two

coils

12a and 12b are used. However, since the coil is easily affected by surrounding circuits and metal arrangements, in order to have the desired characteristics, metal wiring is prohibited within a certain distance including other wiring layers from M1 to M6 around the coil. An area to do is required. Therefore, in order to create a coil, a relatively large area is required on the LSI, so it is desirable that the number of coils be small.

Therefore, as shown in FIG. 7A, a layout pattern in which the

coils

12a and 12b are created by one coil will be described. First, a coil having an inductance value obtained by combining the two is created. An extraction wiring for connecting an ESD element is provided in the middle of the coil to connect the ESD element. By doing so, it is possible to consolidate the wiring prohibited areas around the coil and reduce the required area of the coil. At this time, the portion from the pad 10 to the lead wires of the

ESD elements

11a and 11b can be the coil 12a, and the portion from the lead wire of the

ESD elements

11a and 11b to the lead wires of the

ESD elements

11c and 11d can be the coil 12b. Further, as shown in FIG. 7B, the inductance values of the

coils

12a and 12b can be arbitrarily adjusted by changing the positions of the lead wires of the

ESD elements

11a and 11b.

FIG. 8 shows another layout pattern of the coil according to the first embodiment. The coils up to FIG. 7 formed a spiral pattern in the M8 single layer, but there is a problem even if the M7 single layer forms a spiral pattern from the outer periphery to the inner periphery and is connected in the M8 from the innermost periphery. Absent. Further, in this case, when the connection destination of the signal after the coil extracted from the inner circumference is connected to a component arranged in the lower layer such as a transistor, the lead-out line from the innermost circumference is drawn from the lower layer such as M1 to M6. It is also possible to pull it out. However, in the case of pulling out in the lower layer, in order to reduce the loss due to wiring, it is necessary to connect to the subsequent transistor as close as possible to the coil.

Fig. 9 shows an example of an octagonal layout pattern of coils. One of the coil performance indexes is a Q value. This is a characteristic determined by the ratio of the inductance component and the resistance component of the coil. A higher Q value indicates a smaller resistance component and an ideal inductance. This Q value is determined by various factors such as a wiring width, a wiring interval, and a coil pattern. Since the Q value is generally higher as it is closer to a circle, the Q value is higher in the case where the inductance is formed by the octagonal coil pattern of FIG. 9 than in the case of the quadrangular shape. At this time, the

coils

12a and 12b may be integrated into one coil, and a lead-out wiring for connecting the

ESD elements

11a and 11b may be provided from the middle of the coil.

FIG. 10 shows another example of the coil layout pattern of the first embodiment. This is a case of creating a circle in order to further improve the Q value compared to the octagon. At this time, the

coils

ESD elements

11a and 11b may be provided from the middle of the coil.

FIG. 11 shows another example of the coil layout pattern of the first embodiment. Since the LSI area is limited, it is desirable to make the coil area as small as possible. For this reason, the two layers of the coils M7 and M8 are formed as spiral wiring. As a result, when using only one layer as shown in FIGS. 7 to 10, the inductance value that required three turns as a spiral was used, and the number of turns per layer was 2 by using two layers M7 and M8. This can be achieved with less than the winding, leading to a reduction in area.

FIG. 12 shows an example of a layout pattern created for the purpose of reducing resistance by the coil according to the first embodiment. Since the resistance due to the coil wiring is connected in series with the transmission signal, it directly affects the passage loss of the matching circuit of the present invention. Therefore, it is required to reduce the wiring resistance as much as possible. Therefore, a coil is formed by virtually increasing the wiring layer thickness of one VIA layer of VIA 78 connecting M7, M8 and M7, M8. Since wiring cannot be drawn in the VIA portion, M7 and M8 are connected with low impedance by arranging VIA in high density as shown in the portion surrounded by ◯. As a result, it is possible to make the wiring thickness even thicker than wiring with two layers of M7 and M8, and by reducing the resistance due to the wiring of the coil, the passing loss of the matching circuit can be reduced.

Example 2 is an example in which the input of an LSI is realized as a differential signal.

FIG. 13 shows a coil layout of the second embodiment. Differential wiring is used in electrical wire transmission such as electrical interconnection technology. This is because noise resistance is higher than that of a single phase. In the differential line, two wirings are always arranged close to each other, so that the wiring area is increased as compared with a single phase. However, since these two wirings are similarly affected by disturbances such as electromagnetic noise, the influence of the disturbances can be canceled out by taking the difference between the lines, and the resistance to the disturbances is enhanced. Accordingly, it is required to provide an arrangement with excellent noise resistance that can cancel the influence of disturbance even in the arrangement of the coils. In the differential case, current flows in opposite directions by injection and outflow. Therefore, if the coils are wound in the same direction, the magnetic field generated by the coils is generated in the opposite direction between the differentials, and the noise is reduced by canceling the differential common mode noise.

Example 3 is an example in which an optimum high-speed performance is realized by detecting a transmission speed. As shown in FIG. 24, there are various standards such as PCI express and Ethernet for communication from IC to IC. Further, even in the same Ethernet standard, there are various communication speeds in the same standard as 100 GKR4 (25.78125 Gbit / s) and 10 GKR (10.3125 Gbit / s). Each transmission speed has an optimum bandwidth. If the bandwidth is insufficient, a signal on the high frequency side cannot be received, leading to deterioration of characteristics. On the other hand, if the band is too wide, the received noise band is widened, so that the intensity of the noise amount is increased. Accordingly, measures such as increasing the output amplitude of transmission are required, leading to an unnecessary increase in power. Therefore, there is an optimum band depending on the communication rate, and optimum performance can be derived by changing the amplitude of the matching circuit and the amplifier according to the communication speed.

FIG. 14 shows a block diagram of the third embodiment. FIG. 14A is a block diagram showing speed control corresponding to multiprotocol and multirate by providing a speed detection circuit in an LSI alone. A matching circuit 141 in which the ESD element of the present invention and a coil are combined is disposed at the input and output portions of the LSI. Since the transmitted signal is attenuated, it is amplified by the amplifier 142 in the LSI. The attenuation of the line increases as the frequency increases.

Therefore, an amplifier 142 having a peaking characteristic 144 that increases the gain as the frequency becomes higher and lowers the gain at a high frequency where the signal component is small and the noise component is large is used so that the characteristics are opposite to those of the line. A speed detection circuit 143 for detecting the data speed is provided after the amplifier. In this circuit, the current transmission speed is discriminated, and the matching circuit characteristics, the amplifier frequency characteristics, and the output amplitude corresponding to the communication speed are controlled. By operating each in the optimum state, unnecessary power can be reduced and interference with other circuits and LSIs can be reduced. When the transmission speed to be handled is changed, the signal is received with the maximum speed at which the LSI can operate. Using the signal, the speed detection circuit 143 detects the communication protocol and the communication speed. When the speed detection is completed, a control signal is sent to the matching circuit 141 and the amplifier 142 to change the setting.

FIG. 14B is a block diagram showing multi-protocol, multi-rate compatible speed control when the LSI does not have a speed detection circuit. Since the speed cannot be detected inside the LSI, communication protocol and communication speed information is input from the LSI 146 or the like of the I2C serial communication system that controls the information at the upper level of the apparatus. The settings of the matching circuit 141 and the amplifier 142 are changed according to this information.

FIG. 15 shows a configuration diagram of a matching circuit for changing the band. As a method of changing the band, there is a method of changing the L value of the coil. The L value of a single coil cannot be varied, but if another coil is placed near the coil, magnetic coupling (mutual) occurs between the coils. At this time, the combined inductance L can be expressed by Equation 1 by the inductance L1 of the coil 17a for transmitting a signal, the inductance L2 of the coil 17b for generating a mutual, and the mutual inductance M generated between the coils.
L = L1 + L2 ± 2M Formula (1)
The sign of M depends on whether the magnetic flux directions of L1 and L2 are the same or opposite. Therefore, L can be changed by changing M. In order to change M, a method of changing the current flowing through the coil 17b is used. Since the amount of magnetic flux generated changes depending on the flowing current, the coupling amount M can be changed, so that the combined inductance L can be changed. A frequency source of the matching circuit is adjusted by providing a current source 18 in the coil and controlling the current value.

FIG. 16 shows a schematic diagram of the frequency characteristic change of the matching circuit in which the value of the current flowing through the coil 17b of FIG. 15 is varied. 16A shows reflection characteristics, and FIG. 16B shows transmission characteristics. When the communication speed is low, there is no need to pass a signal up to a high frequency. Therefore, M can be reduced to improve reflection within the band, and pass characteristics can be improved. Further, in a high-speed signal, reflection at a low frequency is deteriorated and a loss of a passing characteristic is increased. However, a wideband characteristic can be obtained by increasing M at a high frequency to reduce the loss.

Fig. 17 shows the layout pattern of the coils connected in a mutual manner. The coil 17a to which the signal is transmitted forms a coil with M7 and M8 having a thick wiring layer thickness to reduce the loss of the transmission line. When the coils are coupled at physically close positions, the influence on M becomes larger, so that a wide variable range can be obtained with a small change in current. Further, the coil 17b for adjusting the mutual is not on the signal transmission line, so there is no need to consider signal degradation. Therefore, the coil 17b is created by M5 and M6 immediately below the coils created by M7 and M8. Thus, by creating and adjusting the variable inductance, it is possible to create a matching circuit that supports multi-protocol and multi-rate.

Example 4 is an example of a mounting structure.
18 is a cross-sectional view of a mounting structure of an LSI chip 18 to which the input matching circuit of the present invention is applied, and FIG. 19 is a top view. Since the LSI chip 18 cannot be directly mounted on the printed circuit board 22 to ensure reliability, it must be mounted on the package 25. The package substrate 20 has a high-speed signal wiring 23 to which a signal input / output pad of the LSI chip 18 is connected. At this time, the LSI chip 18 is mounted face down with the circuit surface facing the package substrate 20. The high-speed signal wiring 23 is connected to a through hole 26 that connects the front and back surfaces of the package substrate 20, and is connected to the high-speed signal wiring 24 on the printed circuit board 22 through the solder 21, from the LSI chip to the printed circuit board. Input / output signals.

By mounting the LSI chip 18 face-down, only the bumps 19 are connected to the package substrate 20 and parasitic components can be suppressed. As a result, impedance mismatch can be suppressed and good high frequency characteristics can be obtained.
FIG. 19B shows an enlarged view of the connection portion A (◯ portion) between the LSI chip 18 and the package substrate 20 in FIG. When performing face-down mounting, it is necessary to increase the area of the bump portion in order to ensure the adhesive strength of the bump from the viewpoint of ensuring reliability. Basically, this width is wider than the high-speed signal wiring 23 designed for impedance. Therefore, a parasitic capacitance is generated at this connection portion.

Fig. 20 shows the equivalent circuit model of LSI including the mounting structure. Between the LSI chip pad 10 and the high-speed signal wiring 23, there are an inductance 27 by the bump 19 and a capacitor 28 by a wiring width expansion pattern provided for disposing the bump 19. A better high frequency characteristic can be obtained by performing input / output matching including the inductance 27 and the capacitor 28. Therefore, the parasitic inductance 27 can have a part or all of the coil 12a of the input matching circuit. As a result, the inductance value of the coil can be reduced, and the coil area on the LSI chip 18 can be reduced.

The fifth embodiment is an example applied to a QFN LSI chip.
21 is a cross-sectional view of the mounting structure of the LSI chip 18 to which the input matching circuit of the present invention is applied, and FIG. 22 is a top view. When the chip is packaged in a general-purpose package 25 such as a QFN (Quad For Non-Lead Package), it is connected to the pad of the package with a wire 29 by face-up mounting. The pads of the package are connected to the high-speed signal wiring 24 of the printed circuit board 22 through the solder 21 and input / output signals from the LSI chip 18 to the printed circuit board 22.

FIG. 22B shows an enlarged view of the connection portion between the pad of the package in the portion A (◯ portion) in FIG. 22A and the printed circuit board 22. When a general-purpose product package is used, the pad positions are arranged at regular intervals according to the standard. Therefore, a discontinuous point of impedance occurs at this connection position due to the parasitic capacitance and the parasitic inductance due to the pad. Further, in order to ensure the adhesive strength of the solder 21, the solder connection portion needs a wiring width wider than the wiring width of the high-speed signal wiring 24. For this reason, a parasitic capacitance is generated in this connection portion. As a countermeasure for this parasitic capacitance, a parasitic pattern is obtained by removing the GND pattern immediately below the portion of the printed circuit board 22 of the multilayer substrate from the location where the second layer package pad and the high-speed signal wiring 24 are connected from the surface where the package 25 is mounted. There is also a means to relieve capacity.

However, even if it can be mitigated, the parasitic capacitance cannot be completely eliminated. Therefore, the equivalent circuit model when including the mounting structure of the LSI chip 18 has the configuration shown in FIG. Between the LSI chip pad 10 and the high-speed signal wiring 24, there exists a capacitance 31 due to the wiring width expansion performed for providing the inductance 30 by the wire 29 and the solder 21 for arranging the package pad. A better high frequency characteristic can be obtained by performing input / output matching including the inductance 30 and the capacitor 31. At this time, the parasitic inductance 30 and the coil 12a of the input matching circuit can complement the characteristics as a matching circuit. Therefore, part or all of the role of the coil 12a can be shared by the wire 29, and the inductance value of the coil 12a can be reduced. As a result, the coil area on the LSI chip 18 can be reduced.

By using the configuration described above, it is possible to provide an LSI that performs high-speed operation while maintaining resistance to electrostatic radiation in an LSI that performs high-speed transmission.

11a 11b 11c 11d: ESD element 12a 12b: coil 10: pad capacitance 13: LSI first stage transistor 15: termination resistor 16: parasitic capacitance of LSI first stage transistor

Claims

In an LSI having a plurality of transistors on a semiconductor substrate,
In order to exchange data with the outside of the LSI, a plurality of diodes, resistors, and coils are arranged between the input / output pads inside the LSI and the input / output transistors.
The LSI has at least two potentials, that is, a ground potential GND and a circuit drive power supply voltage.
As the signal wiring from the pad to the transistor, the first coil and the second coil are connected in this order,
A first diode having one end connected to the signal wiring and the other end connected to the power supply voltage, one end connected to the signal wiring and the other end connected to the GND between the first coil and the second coil. Two diodes, and
The first diode has an anode on the signal line side and a cathode on the power supply voltage side so as to be reverse-biased, and the second diode has a cathode on the signal line side and an anode on the GND side so as to be reverse-biased. Connected,
Between the second coil and the transistor, a third diode having one end connected to the signal line, the other end connected to the power supply voltage, one end connected to the signal line, and the other end connected to the GND A diode is arranged, an anode on the signal wiring side and a cathode on the power supply voltage side are connected so that the third diode is reverse-biased, and a fourth diode is a cathode on the signal wiring side so as to be reverse-biased , The anode is connected to the GND side,
A resistor is arranged in parallel with the third diode or the fourth diode,
The PN junction area of the first diode is larger than the PN junction area of the third diode, and the PN junction area of the second diode is larger than the PN junction area of the fourth diode.
An input / output matching circuit characterized by that.
In an LSI having a plurality of transistors on a semiconductor substrate,
The LSI includes a plurality of diodes, resistors, and a plurality of coils between an input / output pad and a transistor for exchanging data with the outside of the LSI. The LSI includes at least a ground potential. There are two or more potentials of GND and circuit drive power supply voltage, and the first coil, the second coil, and the third coil are connected in this order as signal wiring from the pad to the transistor,
A first diode having one end connected to the signal wiring and the other end connected to the power supply voltage, one end connected to the signal wiring and the other end connected to the GND between the first coil and the second coil. Two diodes, and
Between the second coil and the third coil, a third diode having one end connected to the signal wiring, the other end connected to the power supply voltage, one end connected to the signal wiring, and the other end connected to the GND 4 diodes are arranged, the anode of the third diode is connected to the signal wiring side so as to be reverse bias, the cathode is connected to the power supply voltage side, and the fourth diode is connected to the signal wiring side so as to be reverse biased. Are connected to the cathode, and the anode is connected to the GND side.
Between the third coil and the transistor, a resistor is disposed between the signal line and the power supply voltage, or between the signal line and GND,
The PN junction area of the first diode is smaller than the PN junction area of the third diode, and the PN junction area of the second diode is smaller than the PN junction area of the fourth diode.
An input / output matching circuit characterized by that.
The LSI has a plurality of wiring layers,
There are two or more thicknesses of the wiring layer,
There are at least two consecutive layers other than the thinnest layer,
The input / output matching circuit according to claim 1, wherein the first coil and the second coil are formed in a spiral shape in the two continuous layers.
The LSI has a plurality of wiring layers,
There are two or more thicknesses of the wiring layer,
There are at least two consecutive layers other than the thinnest layer,
3. The input / output matching circuit according to claim 2, wherein the first coil, the second coil, and the third coil are formed in a spiral shape in the two continuous layers.
The first coil and the second coil are composed of one spiral wire,
A lead wiring is provided at an arbitrary position of the spiral wiring,
The input / output matching circuit according to claim 1, wherein a first diode and a second diode are connected to the lead-out wiring.
The first coil, the second coil, and the third coil are composed of one spiral wire,
Two lead wires are provided at an arbitrary position of the spiral wire,
A first diode and a second diode are connected to the lead wiring close to the pad,
3. The input / output matching circuit according to claim 2, wherein a third diode and a fourth diode are connected to the lead wiring close to the transistor.
7. The input / output matching circuit according to claim 3, wherein the spiral wiring has a quadrangular shape.
7. The input / output matching circuit according to claim 3, wherein the spiral wiring is octagonal.
7. The input / output matching circuit according to claim 3, wherein the spiral wiring has a circular shape.
2. The LSI signal is a differential signal, and each differential signal has an input / output matching circuit, and the winding direction of the coil is the same between both differential signals. The input / output matching circuit according to any one of Items 9 to 9.
11. The LSI according to claim 1, wherein the LSI has a speed detection circuit for input / output signals, and adjusts the input / output frequency characteristics in accordance with the speed detected by the speed detection circuit. The input / output matching circuit described.
The LSI is mounted on one side of a first substrate having a wiring pattern on both sides,
The pad and the wiring pattern on one side of the substrate are fixed with a conductive adhesive,
There is a conductive adhesive on the back side of the LSI mounting surface of the substrate for bonding to the second substrate,
The LSI input / output matching circuit according to claim 1, wherein the first substrate and the second substrate are electrically connected.
The LSI is arranged in a central portion of a package surrounded by a metal pattern,
The LSI pad is connected to the metal pattern with a metal wire,
3. The input / output matching circuit according to claim 1, wherein the metal pattern is fixed to a substrate having a wiring pattern formed of metal on at least one surface by a conductive adhesive.
3. The input / output matching circuit according to claim 1, wherein a data rate passing through the input / output matching circuit is 20 Gbit / s or more. 4.