WO2015128648A1

WO2015128648A1 - Joint sparse graph design for multiple access systems

Info

Publication number: WO2015128648A1
Application number: PCT/GB2015/050549
Authority: WO
Inventors: Lei WEN; Pei XIAO; Muhammad Ali IMRAN; Rahim Tafazolli
Original assignee: University Of Surrey
Priority date: 2014-02-26
Filing date: 2015-02-26
Publication date: 2015-09-03
Also published as: GB2542499B; GB2542499A; GB201614502D0; GB201403382D0

Abstract

A joint sparse graph (208) includes several single sparse graphs (204) and (206). Multiple accessing and channel coding are combined in the joint sparse graph, where joint multi-user detection and channel decoding can be performed by message passing algorithm. Design guidelines of the joint sparse graph are derived through EXIE chart analysis. The joint sparse graph not only leads to improved BER performance, but also reduces the detection complexity.

Description

JOINT SPARSE GRAPH DESIGN FOR MULTIPLE ACCESS SYSTEMS

Field of the Invention

The present invention relates to wireless communication systems, and more specifically to wireless multiple access systems.

Background to the Invention

Multiple access systems, such as multi-carrier code division multiple access (MC- CDMA) and orthogonal frequency division multiple access (OFDMA), are widely used in wireless communications (i.e ., 3GPP-LTE and WiMAX) . The transmission uncertainty in multiple access system is caused by multipath fading, multi-user interference (MUI) and channel noise . Orthogonalized sub-carrier methods are able to minimise the negative effect of multipath fading. The problems arising from MUI can be overcome by multi-user detection. Channel coding, in particular sparse graph coding, is an effective way to combat channel noise .

However, these conventional techniques are usually carried out as several independent functions, which can lead to a number of problems. First, due to the high complexity of implementation of optimum detection, sub-optimum algorithms such as minimum mean square error (MMSE) are employed. If the number of modulated symbols exceeds that of available chips (i.e. the number of sub-carriers), which results in an overloaded condition, the bit error rate (BER) performance of the MMSE detector is poor. Although group-orthogonal MC-CDM (GO-MC-CDMA) and low density signature orthogonal frequency division multiplex (LDS-OFDM) have been proposed to deal with the problem of overloaded conditions, their performances are still not satisfactory and their receiver complexities are relatively high.

Furthermore, processing of detection and decoding functions jointly can improve the performance . For instance, information can be exchanged iteratively between detector and decoder in the receiver of turbo structured LDS-OFDM. Although turbo structured LDS-OFDM can improve performance, it is very limited in performance improvement, and its receiver complexity is relatively high. Therefore, designing a receiver to achieve satisfactory performance, and in the meantime, keeping the complexity to a minimum, is a challenging task. Summary of the Invention

The present invention provides a receiver for a multiple access telecommunications system, the receiver comprising a demodulator arranged to extract received data, which may be in the form of chips, from a received RF signal, and processing means arranged to extract data, for example by processing the chips. The processing means defines a graph, typically a sparse graph, having first, second and third sets of nodes. The first set of nodes may be arranged to receive the chips and to process the chips to generate a first set of messages. The second set of nodes may be arranged to receive the first set of messages and from them to generate soft values of the data. The second set of nodes may be arranged to iteratively to exchange messages with the first set of nodes and the third set of nodes to update the soft values of the data. The sparse graph may therefore be arranged to perform multi-user detection and channel decoding thereby to output channel decoded data for each of a plurality of users. The present invention may therefore provide joint sparse graph (JSG) means for a multiple access system, the JSG providing joint multi-user detection and channel decoding (JMUDD) for interference cancellation.

The chips may each comprise a pulse or section of code modulated onto a sub-carrier. There may be a set of different chips each having a respective sub-carrier frequency.

The receiver may define one or more variable parameters of the sparse graph, whereby the receiver can be set to one of a plurality of different settings. The variable parameters may be stored as a lookup table . The parameters of the sparse graph in the receiver may be switchable between different values, and the receiver arranged to switch to the optimum parameters in response to an input indicating the parameters of the signal which is to be received.

The present invention further provides a communications system comprising a transmitter and a receiver wherein the receiver is a receiver according to the invention. The telecommunications system may be arranged to implement a spreading sequence or orthogonalized sub-carriers, whereby multiplexing can be involved, and the negative effects arising from multipath fading can be overcome. The telecommunications system may be arranged to implement sparse graph code such as low density parity check (LDPC) code, Luby transform (LT) code and raptor code, whereby channel coding can be involved. The use of a low density graph to combine multiple access and channel coding means that graph theory can be used to conduct the system research and optimization.

The system may be arranged to support overloaded conditions well while maintaining affordable complexity and satisfactory performance .

The system may incorporate any multiple access systems, such as code division multiple access (CDMA), MC-CDMA, orthogonal frequency division multiple (OFDM) and filter bank multi-carrier (FBMC). The processing means may be arranged to reduce the MUI by performing multi-user detection.

The processing means may be arranged to combat the channel noise by decoding of the sparse graph code .

The processing means may be arranged to terminate the joint iteration of detection and decoding by syndrome computing, thus the iteration number of message passing can be minimised. The processing means may be arranged to carry out multi-user detection and channel decoding simultaneously, so the low complexity of receiver can be achieved.

The processing means may be arranged to apply the message passing algorithm to any types of JSG.

The present invention further provides a system for the construction and optimization of the receiver, or the JSG according to the invention. This can allow optimization of the performance of the receiver while reducing the JMUDD complexity. The construction system may be arranged to design a whole sparse graph which contains at least two single sparse graphs. The construction system may comprise a computer system having software stored thereon which defines a joint sparse graph having a number of variable parameters. The construction system may further be arranged to simulate operation of the JSG using different values of each of the variable parameters, and to test its performance .

The construction means may be arranged to analyse the extrinsic information transfer (EXIT) chart for the JSG, hence the trajectory of JMUDD can be predicted, and the convergence behaviour of message passing can be evaluated.

The construction means may be arranged to design degree distributions of different nodes in JSG (including chip nodes, variable nodes and parity check nodes), therefore, the BER performance of JSG can be optimized, and the density of the JSG can be reduced.

The construction means may be arranged to optimize cycle structure, and to avoid short cycles in JSG, hence the performance of message passing can be improved. The construction means may be arranged to optimize the performance of JSG, meanwhile reduce the complexity of JMUDD.

The construction means may provide design guidelines for any types of JSG. Some embodiments of the invention have the potential to provide key techniques for the next generation of mobile networks such as LTE-Advance and fifth-generation (5G) mobile system. Moreover, some embodiments have the potential to play a key role in many wireless systems including satellite, terrestrial or broadcast and military systems.

The receiver, or the telecommunications system, may further comprise, in any combination, any one or more features of the preferred embodiments of the invention, which will now be described by way of example only with reference to the accompanying drawings. Brief Description of the Drawings

Figure 1 is a block diagram of a transmitter of a multiple access system according to an embodiment of the invention;

Figure 2 is a block diagram of a receiver of the multiple access system of Figure 1 ;

Figure 3(a) shows updating of a chip node in the system of Figure 2;

Figure 3(b) shows updating of a parity check node in the system of Figure 2;

Figure 3(c) shows updating of a variable node in the system of Figure 2; Figure 4 is a block diagram of the iterative structure of the system of Figure

2;

Figure 5 shows the degree distribution of the system of Figure 2; Figure 6 shows a matrix representation of the system of Figure 2; Table 1 shows the system parameters as an example of the system of Figure 2;

Table 2 shows several schemes of degree distributions for the system of Figure 2;

Figure 7 shows the EXIT charts of different degree distributions for the system of Figure 2 over a channel with multipath fading;

Figure 8 shows the EXIT charts of different cycle structures for the system of Figure 2over a channel with multipath fading;

Table 3 shows several scenarios for the system of Figure 2;

Figure 9 shows the BER performance for 200% system loading over a channel with multipath fading;

Figure 10 shows the BER performance for 300% system loading over a channel with multipath fading;

Figure 11 shows the average number of detection iterations for 200% system loading over a channel with multipath fading, and

Figure 12 is a schematic illustration of a construction system for constructing and optimising the receiver of Figure 2.

Description of the Preferred Embodiments

Referring to Figure 1 , a transmitter of a joint sparse graph (JSG) system for uplink transmission, is arranged for use by a number of users K_lds (where Ids indicates the use of a low density signature), using data symbols M_lds, a number of chips N_lds and a number of parity check equations for channel coding M_ldpc (where Idpc indicates the use of a low density parity check). Moreover, V^_m and c„ stand for the m^th data symbol of user k and the n^th chip, respectively. As shown in Figure 1 , the system provides an independent link for each user, provided over multiple-access channels. On each channel there is a channel encoder 100 providing channel encoding of the data from the user, and a symbol mapper 102 providing symbol mapping of the encoded data to form symbols 14. A different set of symbols is used for each user. A symbol spreader is provided in which the data symbols 14 are multiplied with a spreading signature 106 and spread between a number of chips 18, where each chip is a pulse of code modulated onto a sub-carrier frequency. A modulator 1 10 is arranged to modulate the chips 18 output from the spreader onto respective sub-carrier frequencies. Each chip 18 is transmitted over an orthogonal sub-carrier. Inter symbol interference can be avoided by the insertion of a cyclic prefix into each symbol. Data on the channels for the different users are therefore modulated onto a number if different sub-carrier frequencies in a way determined by the spreading signature for the user, but the same sub-carrier frequencies are potentially used for all users. The signals for all the channels are summed together and transmitted over an additive white Gaussian noise (AWGN) channel.

Due to the low density of spreading signature 106, each data symbol 14 is only spread over a limited number (the effective spreading factor) of chips 18. Meanwhile, each chip 18 is only used by a limited number of data symbols 14 that may belong to different users. Each user, transmitting on given sub-carriers, will experience interference from only a small number of other users' data symbols. Therefore, the number of users' modulated symbols 14 that superimposed on each chip 18 is much less than the total number of modulated symbols 14, and the number of chips 18 that spread by each symbol 14 is much less than the total number of chips 18. Referring to Figure 2 a receiver of the JSG system for uplink transmission comprises a single base station in practical systems. The receiver is arranged to process the received signals and comprises a demodulator 200 which is arranged to receive the RF signal and extract the chips from it on the basis of their subcarrier frequency. A joint sparse graph is arranged to process the chips from the received signal to reconstitute the transmitted data. The joint sparse graph is defined by an algorithm, typically in software, and comprises nodes arranged to pass data or messages from one to another. There are three types of nodes in this figure: chip nodes 108, variable nodes 104 and parity check nodes 202. A single sparse graph, as illustrated in the left dash box 204, represents the low density signature (LDS) system (R. Hoshyar, R. Razavi, and M. Al- Imari, "LDS-OFDM an efficient multiple access technique," in IEEE 71^st Vehicular Technology Conference, May 2010, pp. 1-5). The other single sparse graph, as illustrated in the right dash box 206, represents the low density parity check matrix due to channel codes. These two types of single sparse graph 204, 206 belong to the techniques of multiple access and channel coding, respectively. Variable nodes 104 are used to connect other two types of nodes (chip nodes 108 and parity check nodes 202) through low density edges (204 and 206). Therefore, it becomes a joint low density graph, which is marked by the long dash box 208.

There is one chip node 108 for each chip 18, therefore where there are Ni_ds chips that is also the number of chip nodes 108. There is one group of variable nodes 104 for each of the Ki_ds users, and in each group of variable nodes 104, there is one node for each of the Mi_ds symbols, i.e. are Mi_ds nodes in each group. Therefore each of the variable nodes 104 is specific to a unique combination of one user and one symbol. There is one group of parity check nodes 202 for each of the Ki_ds users, and in each group of parity check nodes 202, there is one node for each of the Mi_dpc parity check equations.

Each of the chip nodes 108 is arranged to send a message, to each of a number of the variable nodes 104 that are connected to it, and each of the variable nodes 104 is arranged to send a message to each of a number of the chip nodes 108 that are connected to it. Theses connections are non-symmetrical so that the number of variable nodes 104 connected to each chip node 108 is typically different from the number of chip nodes 108 connected to each variable node 104. Also each chip node 104 is arranged to receive messages from a set of variable nodes 108 which is different from the set of variable nodes 108 to which it is arranged to send messages. Similarly each variable node 108 is arranged to receive messages from a set of chip nodes 104 which is different from the set of chip nodes 104 to which it is arranged to send messages. In a corresponding manner each of the parity check nodes 202 is arranged to send a message, to each of a number of the variable nodes 104 that are connected to it, and each of the variable nodes 104 is arranged to send a message to each of a number of the parity check nodes 202 that are connected to it. Theses connections are non-symmetrical so that the number of variable nodes 104 connected to each parity check node 202 is typically different from the number of parity check nodes 202 connected to each variable node 104. Also each parity check node 202 is arranged to receive messages from a set of variable nodes 104 which is different from the set of variable nodes 104 to which it is arranged to send messages. Similarly each variable node 104 is arranged to receive messages from a set of parity check nodes 202 which is different from the set of parity check nodes 202 to which it is arranged to send messages.

The number of other nodes to which each of the nodes is connected (i.e. arranged to receive messages from) is significantly less than the total number of possible nodes, and hence the joint graph is a sparse graph. In operation each of the messages sent is a 'soft' value of the data that is being received, and each node is arrange to receive messages from a number of nodes and combine them to generate the message that it then sends out to a different set of nodes. Specifically the chip nodes 108 store soft values of the data in the received chips 18, and update these on the basis of the messages received from the variable nodes 104, and the variable nodes 104 store soft values of the channel data, i.e. the data symbols 14 for each of the users, and update those values on the basis of the messages they receive from the chip nodes, and on the basis of the messages they receive from the parity check nodes. The choice of the nodes from which messages are received, the way they are combined, and the choice of nodes to which the messages are sent, are arranged to converge the soft data towards the most likely values of the data that is received, during the iterative exchange of messages.

As such, the LDS structure 204 and channel code structure are well linked together in the JSG 208. The JSG 208 is therefore arranged to perform joint multi-user detection and channel decoding (JMUDD). In the JSG 208, users' signals that are using the same chip 18 will be superimposed, and the number of symbols 14 that interfere with each other at one chip 18 is much less than the total number of symbols 14, so it can perform well in overload conditions. It should be noted that the JSG 208 performs not only multi-user detection, but also channel decoding at the same time. Furthermore, it is different from the turbo structured LDS system (R. Razavi, M. Al-Imari, Muhammad Ali Imran, R. Hoshyar and Dageng Chen, "On Receiver Design for Uplink Low Density Signature OFDM LDS-OFDM," IEEE Transactions on Communications , vol. 60, no. 1 1 , pp . 3499-3508, November 2012), as there is no outer-inner turbo style iteration in JSG 208. Hence, the JSG system is a novel sparse graph system which combines multiple access and channel coding techniques. Based on message passing algorithm, multi-user detection and channel decoding can be performed jointly on the JSG 208.

The JMUDD performed on the JSG 208 is an iterative process of extracting the data from the signal, i.e. the channel information, that is received. The iterative process comprises the following four steps: /^') initialization of channel information to chip nodes; /^'/^') updating of chip nodes and parity check nodes; /^'/^'/^') updating of variable nodes; and iv) estimation and syndrome computing. Figure 3(a) shows chip node updating which is carried out at each iterative step. Each of the nodes 108, 202, 104 is arranged to receive a number of messages and to generate from them one or more messages which it outputs. The message 300 from demodulator and the extrinsic messages 302 and 304 from variable nodes 104 are fed to chip node 108 which is arranged to compute information 306 from those messages and output that information 306 as a further message.

Figure 3(b) shows parity check node updating. The extrinsic messages 308 and 3 10 from variable nodes 104 are delivered to parity check node 202 which is arranged to compute information 3 12 from those messages and output that information 3 12 as a further message.

Figure 3 (c) shows variable node updating. Extrinsic messages (3 14, 3 16, 3 18, 320, 322 and 324) from both chip nodes 108 and parity check nodes 202 are delivered into variable node 104 which is a arranged to compute information 326 and 328 from those messages and output that information as further messages, one of which 326 is output to one of the chip nodes 108 and one of which is output to one of the parity check nodes 202. The processing of detection and decoding are well joined by variable nodes 104. In the single graph of LDS-OFDM, a posterior probability of the transmitted symbol 104 can only be calculated after a fixed number of iterations, as there is no criterion to determine whether the iteratively updated message has converged. However, in the case of the JSG system of Figure 2, parity check nodes 202 are available, thus it is possible to terminate the iterative JMUDD process promptly with syndrome computing. Figure 4 shows the iterative structure of the JSG system 208 which enables it to perform JMUDD. The structure is shown as functional blocks, but it will be appreciated that these functions are all defined in, and performed by, software . To evaluate the transformation of extrinsic information for JSG, the sets of chip nodes 108, variable nodes 104 and parity check nodes 202 are referred to as chip nodes detector 400 (CND), variable node detector and decoder 404 (VNDD) and parity check node decoder 408 (PND), respectively. The extrinsic messages that have been output by one of the detectors or decoders and passed on to another of the detectors or decoders, are considered as a priori information by the other detector or decoder that receives them. Each of the detectors or decoders 400, 404, 406 therefore includes all of the respective type of nodes 108, 104, 202. A first pair of edge interleavers 402 connects the chip node detector 400 to the variable node detector and decoder 404. A second pair of edge interleavers 406 connects the parity check node detector 408 to the variable node detector and decoder 404. The first pair of interleavers 402 represents a sparse spreading signature (or low density signature - Ids), and the second pair of interleavers 406 represents a sparse parity check matrix (or low density parity check - ldpc). Such iterative structure is more complicated than any previous single sparse graph which only has the long dash box (LDS system) or the dash box (sparse graph code) in Figure 4. In operation, the demodulator 200 is arranged to extract a series of chips from the received signal, each of which comprises a pulse of code encoding data. That data in each chip itself partially encodes a number of data symbols which are spread onto the chip. The 'soft' values of the data within each received chip (which will be the originally transmitted values modified by the channel effects of transmission) are input to the chip node detector 400. The CND 400 is arranged to exchange a set of messages to the VNDD 404 via the interleavers 402, and the VNDD 404 is arranged to exchange a set of messages with the PCD 408 via the interleavers 406. The exchange of messages between the CND 400 and the VNDD 404 is arranged to extract the individual symbols encoded in the chips, and the exchange of messages between the VNDD and the PCND is arranged to provide channel decoding of the data. The VNDD 404 is arranged to extract soft values for the data symbols for each user channel from the exchange of messages and perform syndrome computing on that data. Depending on the result of the syndrome computing, the VNDD 404 is arranged to update the soft values the data symbols and then exchange a further round of messages with the CND 400 and the PCD 408, or to terminate the iteration and output the latest values of the data for each channel onto the respective channel for receipt by the relevant user.

Figure 5 shows the degree distribution of the JSG system of Figure 2. It can be seen that the chip nodes 108 and the parity check nodes 202 are shown on one side of the diagram, while the variable nodes 104 are shown on the other side. The chip nodes 108 are connected to variable nodes 104 through low density edges 204, which are marked by bold lines. The parity check nodes 202, belonging to different users, are connected to corresponding groups of variable nodes 104 through sparse edges 206, which are marked by independent groups of dash lines. Multiple access, channel coding and the combination of several single sparse graphs, are clearly depicted in the figure. Due to the fact that the parity check nodes 202 do not receive information directly from the demodulator, but instead receive it only from the variable nodes 104, the proportion of the edges related to parity check nodes 202 can be reduced properly.

Figure 6 shows a matrix representation of the JSG system of Figure 2. The upper rows of the matrix each correspond to one of the parity check nodes of different users, and the lower rows each correspond to one of the chip nodes. Columns of the matrix each represent one of the variable nodes of different users. In Figure 6, each user has an independent parity check matrix (600, 602 and 604) for channel coding, while all of the parity check matrices are linked to each other through the spreading matrix 606. Hence, parity matrices and spreading matrix form a whole joint matrix. The girth of a graph is the length of the shortest cycle. Usually, short cycles are avoided in a single graph. For example, in the parity check matrix 600 that belongs to the first user, length-4 cycles are deleted and the local girth of such single graph is 6 (marked by bold lines 608). Nevertheless, in the whole matrix, length-4 cycles are easy to be regenerated (marked by dash lines 610). Therefore, the restriction of cycle length has to be applied in the joint matrix rather than any single sub-matrix. Table 1 shows an example of the system parameters used for simulation of the system of Figure 2.

Table 2 shows several schemes of degree distributions for JSG. Let D_CND(X), D_pnd(X) and D_VNDD(x) denote the degree distribution polynomials of chip nodes, parity check nodes and variable nodes in the joint sparse raph, respectively. In the polynomial

where P_CND, P_PND and P_VNDD are the fractions of all edges connected to corresponding nodes. We can see that the Deg_a is a case of regular JSG, whereas other schemes are cases of irregular JSG.

Figure 7 shows the EXIT charts for different degree distributions of JSG, over ITU Pedestrian Channel B at E_b/N₀ = 13 dB. In Table 2, Deg_c and Deg_d slightly decrease the weight of PND, then the polynomials of VNDD are altered accordingly. Consequently, as seen in Figure 7, the average mutual information between the bits and the extrinsic values of CND & PND are both increased for Deg_c and Deg_d. Furthermore, their intersection point become higher, which means better performance can be achieved. By contrast, Deg_b increases the density of edges, but its average mutual information and intersection point are both dropped. Therefore, degree distribution is a key factor to the performance of JSG. Note that the curves of Deg_c and Deg_d almost overlap, Deg_d can be regarded as a more suitable choice because it has the lowest density among these schemes.

Figure 8 shows the EXIT charts of different girth for the JSG, over ITU Pedestrian Channel B at E_b/N₀ = 13 dB. It should be emphasized that the restriction of girth is applied to the whole matrix rather than any single sub-matrix in Fig. 6. Optimized Deg_d is chosen to be the degree distribution. The curves of matrices with girth 4 and 6 are very close to each other, whereas matrix with girth 8 outperforms the others. Therefore, in order to improve system performance, cycles of length-4 and length-6 should be removed during the construction of the JSG.

Table 3 shows several scenarios for the JSG. Based on the analysis of degree distribution and short cycle, three scenarios which have different degree distribution and girth for the JSG are proposed.

Figure 9 shows BER performance for 200% system loading over ITU Pedestrian Channel B . For fair comparisons, the number of iterations is limited to a maximum of 6 for all the systems. According to Figure 9, JSG-OFDM outperforms LDS-OFDM. Furthermore, based on the optimized degree distribution (Deg_d) and cycle structure (girth of 8), JSG-OFDM scenario-3 achieves the best performance . Its performance improvements at BER= 10^~4 are 0.7 dB over JSG-OFDM scenario-1 , 1 . 1 dB over JSG- OFDM scenario-2 and 2 dB over LDS-OFDM, respectively.

Figure 10 shows BER performance for 300% system loading over ITU Pedestrian Channel B . For fair comparisons, the number of iterations is limited to a maximum of 6 for all the systems. JSG-OFDM scenario-3 still achieves the best performance . Figure 1 1 shows the average number of detection iterations for 200% system loading over multipath fading channel. As we can see that LDS-OFDM needs more iterations than JSG-OFDM (including scenario-1 and scenario-3). It is noteworthy that, in the case of JSG-OFDM, the detection complexity of scenario-3 is even less than that of scenario-1 , since the density of JSG of scenario-3 is lower than that of scenario-1.

Referring to Figure 12, a system for constructing the joint sparse graph comprises a computer 1200 comprising a display screen 1202, a user input in the form of a keyboard 1204 and a processor 1206 with associated memory. The computer memory has stored, in its memory, construction software defining the JSG of the receiver of Figure 2 including a large number of parameters of the JSG, in particular all of the parameters in Table 1. These parameters include the internal parameters of the JSG itself, including the number of each type of node, the degrees of the nodes as defined by the distribution polynomials of the chip nodes, parity check nodes and variable nodes, and the maximum number of iterations, as well as 'external' parameters of the signal being received including the number of users, the number of sub-carrier frequencies, and the code rate. The software enables each of these parameters to be modified, and the performance of the JSG tested using a simulation of the receiver. This allows the optimum parameters of the JSG to be identified for each of a number of sets of external parameters. The software is then arranged to create a lookup table indicating the optimum parameters of the JSG for each of a number of sets of external parameters. This lookup table may then be stored within the receiver and the parameters of the JSG in the receiver may be switchable between different values, and the receiver arranged to switch to the optimum parameters in response to an input indicating the parameters of the signal which is to be received.

Claims

A receiver for a multiple access telecommunications system, the receiver comprising a demodulator arranged to extract chips from a received RF signal, and processing means arranged to process the chips to extract data, the processing means defining a sparse graph having first, second and third sets of nodes, wherein: the first set of nodes are arranged to receive the chips and to process the chips to generate a first set of messages, and the second set of nodes is arranged to receive the first set of messages and from them to generate soft values of the data, and then iteratively to exchange messages with the first set of nodes and the third set of nodes to update the soft values of the data, whereby the sparse graph is arranged to perform multi-user detection and channel decoding thereby to output channel decoded data for each of a plurality of users.

A receiver according to claim 1 wherein the first and second sets of nodes form a single sparse graph arranged to perform multi-user detection and the second and third sets of nodes form a single sparse graph arranged to perform channel decoding.

A receiver according to claim 1 of claim 2 wherein the iterative exchange of messages comprises a sequence of iterations, each iteration comprising an exchange of messages between the second set of nodes and the third set of nodes, and an exchange of messages between the second set of nodes and the first set of nodes.

A receiver according to any preceding claim wherein after each iteration the processing means is arranged to check the updated soft values of the data for convergence, and if convergence has been reached, to output the data.

A receiver according to any preceding claim wherein the data is encoded in a plurality of symbols, each of the symbols is spread over a plurality of the chips, and each data symbol is only spread over a limited number of chips which is less than the total number of chips.

6. A receiver according to any preceding claim in which the multi-user detection comprises one of CDMA, MC-CDMA, OFDM and FBMC.

7. A receiver according to any preceding claim wherein the processing means is arranged to use one of LDPC code, LT code and raptor code .

8. A receiver according to any preceding claim wherein the processing means is arranged to use belief propagation whereby the messages can be passed through low density edges.

9. A receiver according to any foregoing claim wherein the nodes form a sparse graph which, when represented as a matrix, has no cycles of length six or less.

10. A system for designing a receiver according to any foregoing claim, the system comprising a model of the receiver wherein the model defines a plurality of variable parameters of the sparse graph, whereby the model of the sparse graph can be modified and its performance simulated and tested.

1 1. A system according to claim 10 in which an EXIT chart is arranged to facilitate the analysis of the convergence behaviour of the sparse graph.

12. A system according to claim 1 1 , in which two factors of graph theory, including degree distribution and short cycle length of the model, can be varied to influence the sparse graph performance.

13. A system according to claim 1 1 or claim 12, in which degree distributions of different nodes in the sparse graph can be optimized thereby to optimize the BER performance of sparse graph.

14. A system according to claim 12 or claim 13, in which performance of message passing can be improved by eliminating length-4 and length-6 cycles in the sparse graph.