WO2015101281A1 - 一种五电平逆变器 - Google Patents

一种五电平逆变器 Download PDF

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Publication number
WO2015101281A1
WO2015101281A1 PCT/CN2014/095527 CN2014095527W WO2015101281A1 WO 2015101281 A1 WO2015101281 A1 WO 2015101281A1 CN 2014095527 W CN2014095527 W CN 2014095527W WO 2015101281 A1 WO2015101281 A1 WO 2015101281A1
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Prior art keywords
branch
switch tube
period
inverter
turned
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PCT/CN2014/095527
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English (en)
French (fr)
Inventor
张彦虎
周灵兵
薛丽英
胡兵
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阳光电源股份有限公司
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Publication of WO2015101281A1 publication Critical patent/WO2015101281A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0095—Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

Definitions

  • the present invention relates to the field of power electronics, and more particularly to a five-level inverter.
  • the inverter is used to convert the DC voltage output from the DC power supply into an AC voltage and output it to the load circuit. It is widely used in photovoltaic, wind power generation and other fields. However, due to the presence of parasitic capacitance to the ground by a DC power source (such as a solar panel), leakage current may occur during operation of the inverter. The leakage current problem not only damages the output power quality, reduces the working efficiency of the inverter, but also causes harm to the human body and reduces the reliability of the inverter.
  • FIG. 1 is a conventional five-level inverter.
  • a DC power supply DC positive pole has a power frequency jump with respect to an output negative pole, that is, a power frequency jump, and the power frequency jumps.
  • the voltage acts on the parasitic capacitance between the positive (or negative) DC of the DC power supply and the ground, which can cause leakage current spikes.
  • the technical problem solved by the present invention is to provide a five-level inverter to overcome the leakage current problem, thereby improving the working efficiency and reliability of the inverter.
  • the present invention provides a five-level inverter, the inverter comprising: a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a first branch, a second branch, The third branch, the fourth branch, a first capacitor unit, a second capacitor unit, a third capacitor unit, a fourth capacitor unit, a first inductor and a second inductor;
  • Each of the first branch, the second branch, the third branch, and the fourth branch has a first conductive path and a second conductive path, the first When the conduction path is turned on, current can flow from the first end of the branch to the second end, and when the second conductive path is turned on, current can flow from the second end of the branch to the first end, When both the first conduction path and the second conduction path are turned off, the branch is turned off, and current is prohibited from flowing from one end of the branch to the other end;
  • a cathode of the DC power source connected to the second switch a first end of the tube, a first end of the fourth switch tube, and a second end of the second capacitor unit;
  • the second end of the first switch tube is connected to the second end of the second switch tube and the first end of the first branch; the second end of the third switch tube is connected to the fourth switch tube a second end and a first end of the second branch;
  • the second end of the first branch is connected to the first end of the first inductor and the first end of the third branch; the second end of the second branch is connected to the second inductor One end and a first end of the fourth branch;
  • the second end of the first capacitor is connected to the first end of the third capacitor unit, and the second end of the second inductor is connected to the second end of the fourth capacitor unit;
  • the second end of the third capacitor unit is connected to the first end of the fourth capacitor unit, the second end of the third branch, the second end of the fourth branch, and the first capacitor unit a second end and a first end of the second capacitor unit;
  • the second end of the first inductor and the second end of the second inductor are alternating current outputs of the inverter.
  • any of the branches includes a fifth switch tube and a sixth switch tube connected in series and having opposite conduction directions;
  • the conducting direction of the fifth switching tube is such that a current flows from the first end of the branch to the second end, and the conducting direction of the sixth switching tube causes current to flow from the second end of the branch to the first end;
  • the anti-parallel diodes of the fifth switch tube and the sixth switch tube are the first conduction path of the branch, and the anti-parallel diodes of the sixth switch tube and the fifth switch tube are The second conduction path of the branch.
  • any one of the first branch, the second branch, the third branch, and the fourth branch includes a seventh switch tube, an eighth switch tube, and a first a diode and a second diode;
  • the first diode and the seventh switch tube are connected in series, in parallel with the series circuit of the second diode and the eighth switch tube, the first diode and the seventh switch
  • the conduction direction of the tube is such that current flows from the first end to the second end of the branch, and the conduction directions of the second diode and the eighth switch tube both cause current from the second end of the branch
  • the first diode and the seventh switch tube are the first conduction path of the branch
  • the second diode and the eighth switch tube are the branch The second conduction path.
  • any one of the first branch, the second branch, the third branch, and the fourth branch includes a third diode, a fourth diode, a fifth diode, a sixth diode, and a ninth switch tube;
  • a positive electrode of the third diode is connected to a negative electrode of the fourth diode, and a positive electrode of the fifth diode is connected to a negative electrode of the sixth diode as a first end of the branch a second end of the branch; a cathode of the third diode and a cathode of the fifth diode connected to a first end of the ninth switch, a positive pole of the fourth diode
  • the positive pole of the sixth diode is connected to the second end of the ninth switch tube, and the conduction direction of the ninth switch tube is such that current flows from the first end to the second end of the ninth switch tube;
  • the third diode, the ninth switch tube and the sixth diode are the first conduction path of the branch; the fourth diode, the ninth switch tube and The fifth diode is the second conduction path of the branch.
  • the inverter has six active working modes, which are a first working mode, a second working mode, a third working mode, a fourth working mode, a fifth working mode, and a first Six working modes;
  • the first switch tube, the fourth switch tube, and the The first conduction path of the first branch and the second conduction path of the second branch are turned on, the second switch tube, the third switch tube, the third branch, and the fourth The branch is closed;
  • the inverter When the inverter is in the second working mode, the inverter is in a first sub-working mode or a second sub-working mode; when the inverter is in the first sub-working mode The first switch tube, the first conductive path of the first branch, and the first conductive path of the fourth branch are turned on, the second switch tube, the third switch tube, and the fourth The switch tube, the second branch, and the third branch are turned off, the second end of the first capacitor unit is in a charging state; when the inverter is in the second sub-mode, the The fourth switch tube, the second conductive path of the second branch, and the second conductive path of the third branch are turned on, the first switch tube, the second switch tube, and the third switch tube The first branch and the fourth branch are turned off, and the second end of the first capacitor unit is in a discharged state;
  • the inverter When the inverter is in the third working mode, the second conductive path of the third branch and the first conductive path of the fourth branch are turned on, the first switch tube, The second switch tube, the third switch tube, the fourth switch tube, the first branch and the second branch are turned off;
  • the second switch tube, the third switch tube, the second conduction path of the first branch, and the first guide of the second branch The through path is turned on, and the first switch tube, the fourth switch tube, the third branch, and the fourth branch are turned off;
  • the inverter When the inverter is in the fifth working mode, the inverter is in a third sub working mode or a fourth sub working mode; when the inverter is in the third sub working mode The third switch tube, the first conductive path of the second branch, and the first conductive path of the third branch are turned on, the first switch tube, the second switch tube, and the fourth The switch tube, the first branch and the fourth branch are turned off, the second end of the first capacitor unit is in a charging state; when the inverter is in the fourth sub-mode, the The second switch tube, the second conductive path of the first branch, and the second conductive path of the fourth branch are turned on, the first switch tube, the third switch tube, and the fourth switch tube The second branch and the third branch are turned off, and the second end of the first capacitor unit is in a discharged state;
  • the inverter When the inverter is in the sixth working mode, the first conduction path of the third branch and the second conduction path of the fourth branch are turned on, the first switch tube, The second switch tube, the third switch tube, the fourth switch tube, the first branch, and the second branch are turned off.
  • the periodic signal output by the inverter is divided into a first time period, a second time period, a third time period, a fourth time period, a fifth time period, and a sixth time period in one cycle;
  • the inverter is alternately in a second working mode and a third working mode
  • the inverter In the second period, the inverter is alternately in a first working mode and a second working mode;
  • the inverter is alternately in a fifth working mode and a sixth working mode
  • the inverter is alternately in a fourth working mode and a fifth working mode.
  • a charge and discharge state of the second end of the first capacitor unit is the same; in the fourth time period, the fifth time period And the sixth period of time, the charge and discharge states of the second end of the first capacitor unit are the same, and the first capacitor unit of the first period, the second period, and the third period The charge and discharge states of the second end are opposite;
  • And charging and discharging states of the second end of the first capacitor unit are the same in the first period, the second half of the second period, the fourth period, and the second half of the fifth period;
  • the first half of the second period, the third period, the first half of the fifth period, and the sixth period, the charge and discharge states of the second end of the first capacitor unit are the same, and the first period, The charge and discharge states of the second end of the first capacitor unit in the second half of the second period, the fourth period, and the fifth period are opposite;
  • And charging and discharging states of the second end of the first capacitor unit are the same in the first period, the second half of the second period, the first half of the fifth period, and the sixth period; Second period a charge and discharge state of the second end of the first capacitor unit is the same, and the first period, the first period, the third period, the fourth period, and the second half of the fifth period The charge and discharge states of the second half of the second period, the first half of the fifth period, and the second end of the first period are opposite.
  • the inverter has three reactive working modes, which are a seventh working mode, an eighth working mode, and a ninth working mode:
  • the first switch tube, the fourth switch tube, the first and second conduction paths of the first branch, and the second branch when the inverter is in the seventh working mode The first and second conduction paths are turned on, and the second switch tube, the third switch tube, the third branch, and the fourth branch are turned off;
  • the inverter When the inverter is in the eighth working mode, the first and second conduction paths of the third branch, and the first and second conduction paths of the fourth branch are turned on, The first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the first branch, and the second branch are turned off;
  • the second switch tube, the third switch tube, the first and second conduction paths of the first branch, and the second branch The first and second conduction paths are turned on, and the first switching transistor, the fourth switching transistor, the third branch, and the fourth branch are turned off.
  • the second end of the first inductor is further connected to the anode of the AC grid through a third inductor, and the second end of the second inductor is further connected to the cathode of the AC grid through the fourth inductor.
  • the third capacitor unit and the fourth capacitor unit are output filter circuits of the inverter, and the second end of the first capacitor unit is in the DC bus. And the common end of the third capacitor unit and the fourth capacitor unit are connected to the second end of the first capacitor unit such that the midpoint of the DC bus (or the positive or negative DC power source) is relative to the midpoint of the output filter circuit
  • the potential is relatively stable, there is no trip voltage, so there is no leakage current problem, which improves the efficiency and reliability of the inverter.
  • 1 is a circuit diagram of a conventional five-level inverter
  • FIG. 2 is a circuit diagram of a five-level inverter according to an embodiment of the present invention.
  • FIG. 3 is a circuit diagram of any branch according to an embodiment of the present invention.
  • 5a is a circuit conduction diagram of a first operational mode of the inverter shown in FIG. 2;
  • Figure 5b is a circuit diagram of the first sub-operation mode of the inverter shown in Figure 2;
  • Figure 5c is a circuit diagram of the second sub-operation mode of the inverter shown in Figure 2;
  • Figure 5d is a circuit diagram of the third operating mode of the inverter shown in Figure 2;
  • 5e is a circuit conduction diagram of a fourth operating mode of the inverter shown in FIG. 2;
  • Figure 5f is a circuit conduction diagram of the third sub-operation mode of the inverter shown in Figure 2;
  • Figure 5g is a circuit conduction diagram of the fourth sub-operation mode of the inverter shown in Figure 2;
  • 5h is a circuit conduction diagram of a sixth operational mode of the inverter shown in FIG. 2;
  • FIG. 6 is a modal switching control diagram corresponding to a first distribution mode of a DC bus midpoint charging and discharging
  • FIG. 7 is a modal switching control diagram corresponding to a second distribution mode of a DC bus midpoint charging and discharging
  • FIG. 8 is a modal switching control diagram corresponding to a third distribution mode of a DC bus midpoint charging and discharging
  • 9a is a circuit conduction diagram of a seventh operational mode of the inverter shown in FIG. 2;
  • Figure 9b is a circuit diagram of the eighth operational mode of the inverter shown in Figure 2;
  • Figure 9c is a circuit diagram of the ninth mode of operation of the inverter shown in Figure 2;
  • Figure 10 is a preferred circuit diagram of the inverter shown in Figure 2.
  • the DC power supply When the inverter is working, the DC power supply may have a power frequency or high frequency trip voltage with respect to the output negative pole (potential with earth), and the possibility of parasitic capacitance to the ground due to the DC power supply (such as solar panel) may result in There will be leakage current problems.
  • the leakage current problem not only damages the output power quality, reduces the working efficiency of the inverter, but also causes harm to the human body and reduces the reliability of the inverter.
  • FIG. 1 is a conventional five-level inverter.
  • the DC power supply DC has a power frequency jump relative to the output negative pole, that is, at point C, which can also be said to be a midpoint of the bus.
  • the DC power supply DC negative pole has a power frequency jump with respect to the output negative pole.
  • the output negative pole is often connected to the N-line of the power grid, and the N-line of the power grid is close to the ground potential. Therefore, the jump voltage acts on the parasitic capacitance between the DC positive (or negative) DC power source and the ground, which may cause leakage current spikes.
  • the invention provides a five-level inverter to solve the leakage current problem, thereby improving the working efficiency of the inverter and improving the reliability.
  • the present invention provides a specific embodiment of a five-level inverter.
  • the five-level inverter includes: a first switch tube Q L1 , a second switch tube Q L2 , and a third The switch tube Q L3 , the fourth switch tube Q L4 , the first branch 201 , the second branch 202 , the third branch 203 , the fourth branch 204 , the first capacitor unit C 1 , the second capacitor unit C 2 , The third capacitor unit C 3 , the fourth capacitor unit C 4 , the first inductor L 1 and the second inductor L 2 .
  • Each of the first branch 201, the second branch 202, the third branch 203, and the fourth branch 204 has a first conductive path and a second conductive path, wherein the first conductive path When conducting, current can flow from the first end of the branch to the second end, and when the second conductive path is turned on, current can flow from the second end of the branch to the first end, the first conduction path and When the second conduction path is turned off, the branch is turned off, and current is prohibited from flowing from either end of the branch to the other end.
  • the anode of the DC power source DC is connected to the first end of the first switch tube Q L1 , the first end of the third switch tube Q L3 and the first end of the first capacitor unit C 1 ; the cathode of the DC power source DC is connected to the second switch tube Q a first end of L2, a first end of the fourth switching transistor Q L4 and a second end of the second capacitive unit C 2 .
  • the second end of the first switch tube Q L1 is connected to the second end of the second switch tube Q L2 and the first end of the first branch; the second end of the third switch tube Q L3 is connected to the fourth switch tube Q L4 The first end of the two ends and the second branch.
  • the second end of the first branch is connected to the first end of the first inductor L 1 and the first end of the third branch; the second end of the second branch is connected to the first end and the fourth end of the second inductor L 2 The first end of the road.
  • the second end of the first capacitor L 1 is connected to the first end of the third capacitor unit C 3 , and the second end of the second inductor L 2 is connected to the second end of the fourth capacitor unit C 4 .
  • the second end of the third capacitor unit C 3 is connected to the first end of the fourth capacitor unit C 4 , the second end of the third branch, the second end of the fourth branch, and the second end of the first capacitor unit C 1 . And a first end of the second capacitor unit C 2 .
  • the second end of the first inductor L 1 and the second end of the second inductor L 2 are the AC output terminals of the five-level inverter of the embodiment.
  • the AC output can be connected to an AC grid.
  • the second end of the third capacitor unit C 3 is connected to the first end of the fourth capacitor unit C 4 , the second end of the first capacitor unit C 1 , and the second capacitor
  • the first end of the unit C 2 can be seen that the common end of the third capacitor unit C 3 and the fourth capacitor unit C 4 is connected to the midpoint of the DC bus (ie, the second end of the first capacitor unit C 1 ), thereby making the DC bus
  • the potential of the midpoint relative to the common terminal of the third capacitor unit C 3 and the fourth capacitor unit C 4 is relatively stable, that is, the anode or cathode of the DC power source DC is relative to the third capacitor unit C 3 and the fourth capacitor unit C 4 .
  • the potential at the common terminal is relatively stable, and there is no power frequency or high frequency jump.
  • the third capacitor unit C 3 and the fourth capacitor unit C 4 are output filter circuits of the inverter, and the output filter circuit is generally connected to the N line of the power grid, and the N line of the power grid is close to the earth potential, so the DC in this embodiment
  • the power supply DC positive (or negative) does not have a power frequency or high frequency transition between the ground and the ground, so there is no leakage current problem, thereby improving the efficiency and reliability of the inverter.
  • the five-level inverter in this embodiment is a dual buck circuit with five-level output and high efficiency, which is suitable for applications such as photovoltaic power generation.
  • an AC grid u g can be connected between the two outputs of the inverter.
  • the inverter in this embodiment can be used in the field of photovoltaic power generation, etc., so the DC power source DC can be a PV (Photo Voltaics) power source or the like.
  • the first switching transistor Q L1 , the second switching transistor Q L2 , the third switching transistor Q L3 , and the fourth switching transistor Q L4 can be any type of switching transistor, such as an IGBT, a MOS transistor, or the like.
  • each device of the switch tube has a reverse diode connected in parallel, that is, an anti-parallel diode is connected in parallel.
  • the switching tubes included in each of the first branch 201, the second branch 202, the third branch 203, and the fourth branch 204 are also connected with a reverse diode in parallel.
  • the first switching transistor Q L1 when the first switching transistor Q L1 is turned on, current flows from the first end of the first switching transistor Q L1 to the second end, that is, the positive connection of the reverse diode of the first switching transistor Q L1 in parallel
  • the second end of the first switch tube Q L1 and the negative end are connected to the first end of the first switch tube Q L1 .
  • the third switching transistor Q L3 When the third switching transistor Q L3 is turned on, current flows from the first end to the second end of the third switching transistor Q L3 .
  • the second switching transistor Q L2 When the second switching transistor Q L2 is turned on, current flows from the second end of the second switching transistor Q L2 to the first end, that is, the anode of the reverse diode connected in parallel with the second switching transistor Q L2 is connected to the second switching transistor Q.
  • the first end of L2 is connected to the second end of the second switch tube Q L2 .
  • the fourth switching transistor Q L4 When the fourth switching transistor Q L4 is turned on, current flows
  • each of the first branch 201, the second branch 202, the third branch 203, and the fourth branch 204 includes two conductive paths, that is, a first conductive path and The second conduction path.
  • the corresponding control current can flow from one end of the branch to the other end.
  • any branch may be as shown in FIG.
  • the first branch includes switching transistors Q H1 and Q H2 connected in series and having opposite conduction directions.
  • the second branch comprises switching transistors Q H3 and Q H4 connected in series and in opposite directions.
  • the third branch comprises switching transistors Q H5 and Q H6 connected in series and in opposite directions.
  • the fourth branch includes switching transistors Q H7 and Q H8 connected in series and in opposite directions.
  • the switch tube Q H1 and the switch tube Q H2 are connected in series on the first branch, and the conduction direction of the switch tube Q H1 and the switch tube Q H2 is opposite, and the conduction direction of the switch tube Q H1 is such that the current flows from the first branch The first end flows to the second end of the first branch, and the conduction direction of the switch Q H2 causes current to flow from the second end of the first branch to the first end of the first branch.
  • the switch tube Q H1 and the switch tube Q H2 can be connected as shown in FIG. 2, the switch tube Q H1 is connected to the first end of the first branch, and the switch tube Q H2 is connected to the second end of the first branch.
  • the positions of the switch tube Q H1 and the switch tube Q H2 are also interchangeable, that is, the switch tube Q H2 is connected to the first end of the first branch, and the switch tube Q H1 is connected to the second end of the first branch, which does not affect the present Implementation of the invention.
  • the positions of the switch tube Q H3 and the switch tube Q H4 shown in FIG. 2 are also interchangeable, and the positions of the switch tube Q H5 and the switch tube Q H6 are also interchangeable, and the switch tube Q H7 and the switch tube Q H8 are also interchangeable.
  • the locations are also interchangeable.
  • any of the first branch 201, the second branch 202, the third branch 203, and the fourth branch 204 may be replaced with other circuits without affecting the implementation of the present invention.
  • any of the branches may include a seventh switching transistor Q H9 , an eighth switching transistor Q H10 , a first diode D 1 , and a second diode D 2 .
  • the first diode D 1 and the seventh switching transistor Q H9 are connected in series, in parallel with the series circuit of the second diode D 2 and the eighth switching transistor Q H10 , the first diode D 1 and the seventh switching transistor Q
  • the conduction direction of H9 causes current to flow from the first end to the second end of the branch, and the conduction directions of the second diode D 2 and the eighth switch Q H10 both cause current from the second end of the branch
  • the first diode D 1 and the seventh switching transistor Q H9 are the first conduction paths of the branch
  • the second diode D 2 and the eighth switching transistor Q H10 are the first of the branches Two conduction paths.
  • the first conduction path when the first conduction path is turned on, it indicates that the seventh switch tube Q H9 of the branch is turned on, and when the second conductive path is turned on, it indicates that the eighth switch tube Q H10 of the branch is turned on.
  • the first conduction path and the second conduction path are both turned off, that is, when the branch is turned off, it is indicated that the seventh switch tube Q H9 and the eighth switch tube Q H10 of the branch are all turned off.
  • the positions of the first diode D 1 and the seventh switch tube Q H9 in FIG. 3 may be interchanged, and the positions of the second diode D 2 and the eighth switch tube Q H10 may also be interchanged.
  • a first branch 201 and second branch 202, the third branch 203 and the fourth branch 204 may comprise any of a path: a third diode D 3, a fourth diode
  • the anode of the third diode D 3 is connected to the cathode of the fourth diode D 4 as the first end of the branch, and the anode of the fifth diode D 5 is connected to the cathode of the sixth diode D 6 As the second end of the branch; the anode of the third diode D 3 and the cathode of the fifth diode D 5 are connected to the first end of the ninth switch tube Q H11 , and the anode of the fourth diode D 4 and a second end of the positive sixth diode D 6 is connected to a ninth switch Q H11 of the ninth switching transistor Q is turned on so that the current direction of the H11 from the ninth to the second end of the switch Q H11 of the first end.
  • the third diode D 3 , the ninth switch tube Q H11 and the sixth diode D 6 are the first conduction path of the branch; the fourth diode D 4 , the ninth switch tube Q H11 and the fifth Diode D 5 is the second conduction path for the branch. Therefore, when the first conduction path is turned on, it indicates that the ninth switch tube Q H11 of the branch is turned on, and when the second conductive path is turned on, it indicates that the ninth switch tube Q H11 of the branch is turned on. When both the first conduction path and the second conduction path are turned off, it is indicated that the ninth switching transistor Q H11 of the branch is turned off.
  • the first switch tube Q L1 , the second switch tube Q L2 , the third switch tube Q L3 , and the fourth switch tube Q L4 may be low frequency switch tubes, that is, power frequency switch tubes, and thus in the inverter During operation, the first switching transistor Q L1 , the second switching transistor Q L2 , the third switching transistor Q L3 , and the fourth switching transistor Q L4 operate at a low frequency.
  • the switch tube on each branch can be a high frequency switch tube. Therefore, when the inverter is in operation, the switch tube on each branch has a high frequency switching action.
  • the high frequency referred to in the present invention generally refers to a frequency greater than 1 khz, and the low frequency Generally refers to frequencies below 1khz (typically power frequency, such as 50hz).
  • the first capacitor unit, the second capacitor unit, the third capacitor unit, and the fourth capacitor unit may each be a unit composed of a capacitor.
  • the number of capacitors included in each capacitor unit is not limited.
  • the capacitance values of the first capacitor unit and the second capacitor unit may be equal or the difference between the capacitance values is within the first preset threshold, and the capacitance values of the third capacitor unit and the fourth capacitor unit may also be made.
  • the equal or capacitance difference is within a second predetermined threshold.
  • the first preset threshold and the second preset threshold may be set according to circuit requirements, and may or may not be equal.
  • the inductance values of the first inductor and the second inductor may also be equal or different within a threshold range.
  • the inverter provided by the embodiment of the present invention can be applied not only to the occasion where the active power is required, but also to the occasion where the reactive power and the active power are required at the same time. Introduce.
  • the inverter in this embodiment has six active working modes, which are a first working mode, a second working mode, a third working mode, and a fourth working mode, respectively.
  • the fifth working mode and the sixth working mode are a first working mode, a second working mode, a third working mode, and a fourth working mode, respectively.
  • the inverter of the embodiment when the inverter of the embodiment is in the first operating mode, the inverter outputs a positive 2 level.
  • the first switch tube Q L1 , the fourth switch tube Q L4 , the first conduction path of the first branch, and the second conduction path of the second branch are turned on, and the second switch tube Q L2 , the third The switch tube Q L3 , the third branch and the fourth branch are turned off.
  • the current flows in sequence: the first switch tube Q L1 ⁇ the switch tube Q H1 ⁇ the switch tube Q H2 anti-parallel diode ⁇ first inductance L 1 ⁇ AC grid u g ⁇ second inductor L 2 ⁇ switch tube Q H4 ⁇ reverse parallel diode of switch tube Q H3 ⁇ fourth switch tube Q L4 ⁇ second capacitor Cell C 2 ⁇ first capacitor cell C 1 .
  • the conduction state of the switch tube Q H2 and the switch tube Q H3 is not limited, that is, the switch tube Q H2 can be turned on or off, and the switch tube Q H3 can be turned on or off.
  • two reverse series connected switches ie, switch tube Q H5 and switch tube Q H6
  • switch tube Q H5 and switch tube Q H6 on the third branch can prevent current from flowing from the first end to the third branch of the third branch.
  • the two reverse series connected switches on the fourth branch ie, the switch tube Q H7 and the switch tube Q H8
  • the switch tube Q H7 and the switch tube Q H8 can prevent current from flowing from the second end of the fourth branch to the first of the fourth branch end.
  • the connection between the common end of the first capacitive unit C 1 and the second capacitive unit C 2 and the common end of the third capacitive unit C 3 and the fourth capacitive unit C 4 There is also a small amount of current flowing through it. If the capacitance values of the third capacitor unit C 3 and the fourth capacitor unit C 4 are similar, the capacitance values of the first capacitor unit C 1 and the second capacitor unit C 2 are similar, and the inductances of the first inductor L 1 and the second inductor L 2 are When the values are close, the current is small.
  • the inverter of this embodiment When the inverter of this embodiment is in the second working mode, the inverter outputs a positive 1 level. At this time, the inverter may be in the first sub-operation mode or in the second sub-operation mode. The following are explained separately.
  • the first switch tube Q L1 when the inverter of the embodiment is in the first sub-operation mode, the first switch tube Q L1 , the first conduction path of the first branch, and the first conduction path of the fourth branch Turning on, the second switch tube Q L2 , the third switch tube Q L3 , the fourth switch tube Q L4 , the second branch and the third branch are turned off. In this case, the second terminal of the first capacitor C 1 (i.e., the first capacitor C 1 and the second common terminal of capacitor C 2) in a charged state.
  • the first capacitor C 1 i.e., the first capacitor C 1 and the second common terminal of capacitor C 2
  • the current flows in sequence: the first switch tube Q L1 ⁇ the switch tube Q H1 ⁇ the switch tube Q H2 anti-parallel diode ⁇ first inductance L 1 ⁇ alternating current grid u g ⁇ second inductance L 2 ⁇ switching tube Q H8 ⁇ reverse parallel diode of switching tube Q H7 ⁇ first capacitive unit C 1 .
  • the conduction state of the switch tube Q H2 and the switch tube Q H7 is not limited, that is, the switch tube Q H2 can be turned on or off, and the switch tube Q H7 can be turned on or off.
  • two reverse-series switching tubes on the third branch can prevent current from flowing from the first end of the third branch to the second end of the third branch.
  • the fourth switch tube Q L4 , the second conduction path of the second branch, and the second conduction path of the third branch are turned on, A switching transistor Q L1 , a second switching transistor Q L2 , a third switching transistor Q L3 , a first branch and a fourth branch are turned off.
  • the second terminal of the first capacitor C 1 i.e., the first capacitor C 1 and the second common terminal of capacitor C 2 in a discharged state.
  • the current flows sequentially through: the reverse parallel diode of the switch tube Q H6 ⁇ the switch tube Q H5 ⁇ First inductance L 1 ⁇ AC grid u g ⁇ Second inductor L 2 ⁇ Switching tube Q H4 ⁇ Reverse parallel diode of switching transistor Q H3 ⁇ Fourth switching transistor Q L4 ⁇ Second capacitor unit C 2 .
  • the conduction state of the switch tube Q H3 and the switch tube Q H5 is not limited, that is, the switch tube Q H3 can be turned on or off, and the switch tube Q H5 can be turned on or off.
  • two reverse-series switching tubes on the fourth branch can prevent current from flowing from the second end of the fourth branch to the first end of the fourth branch.
  • the inverter When the inverter is in the first sub-operation mode or the second sub-operation mode, the common ends of the first capacitor unit C 1 and the second capacitor unit C 2 and the third capacitor unit C 3 and the fourth capacitor unit C 4 Current flows through the connection circuit between the common terminals.
  • the inverter outputs a positive 1 level, but the difference between the two word working modes is that in the first sub-working mode, the first capacitive unit C The second end of 1 is in a charged state, and in the second sub-operating mode, the second end of the first capacitive unit C 1 is in a discharged state.
  • the inverter of the embodiment when the inverter of the embodiment is in the third operating mode, the inverter outputs a positive 0 level.
  • the second conduction path of the third branch and the first conduction path of the fourth branch are turned on, the first switch tube Q L1 , the second switch tube Q L2 , the third switch tube Q L3 , and the fourth The switch tube Q L4 , the first branch and the second branch are turned off.
  • the current flows in sequence: the first inductor L 1 ⁇ the AC grid u g ⁇ the second inductor L 2 ⁇ switch tube Q H8 ⁇ reverse parallel diode of switch tube Q H7 ⁇ switch tube Q H6 ⁇ reverse parallel diode of switch tube Q H5 .
  • the conduction state of the switch tube Q H5 and the switch tube Q H7 is not limited, that is, the switch tube Q H5 can be turned on or off, and the switch tube Q H7 can be turned on or off.
  • the inverter When the inverter is in the third operating mode, there is also a small amount of current in the connection between the common terminal of the third branch and the fourth branch and the common terminal of the third capacitor unit C 3 and the fourth capacitor unit C 4 flow past. If the capacitance values of the third capacitor unit C 3 and the fourth capacitor unit C 4 are similar, the capacitance values of the first capacitor unit C 1 and the second capacitor unit C 2 are similar, and the inductances of the first inductor L 1 and the second inductor L 2 are When the values are close, the current is small.
  • the inverter of the embodiment when the inverter of the embodiment is in the fourth operating mode, the inverter outputs a negative 2 level.
  • the second switch tube Q L2 , the third switch tube Q L3 , the second conduction path of the first branch, and the first conduction path of the second branch are turned on, the first switch tube Q L1 , the fourth The switch tube Q L4 , the third branch and the fourth branch are turned off.
  • the current flows sequentially: the third switch Q L3 ⁇ the switch Q H3 ⁇ Reverse parallel diode of switch tube Q H4 ⁇ second inductor L 2 ⁇ AC grid u g ⁇ first inductor L 1 ⁇ switch transistor Q H2 ⁇ reverse parallel diode of switch transistor Q H1 ⁇ second switch transistor Q L2 ⁇
  • the second capacitor unit C 2 ⁇ the first capacitor unit C 1 .
  • the conduction state of the switch tube Q H1 and the switch tube Q H4 is not limited, that is, the switch tube Q H1 can be turned on or off, and the switch tube Q H4 can be turned on or off.
  • two reverse series connected switches on the third branch can prevent current from flowing from the second end of the third branch to the first end of the third branch, and two on the fourth branch.
  • the reverse series connected switch prevents current from flowing from the first end of the fourth branch to the second end of the fourth branch.
  • the connection between the common end of the first capacitive unit C 1 and the second capacitive unit C 2 and the common end of the third capacitive unit C 3 and the fourth capacitive unit C 4 There is also a small amount of current flowing through it. If the capacitance values of the third capacitor unit C 3 and the fourth capacitor unit C 4 are similar, the capacitance values of the first capacitor unit C 1 and the second capacitor unit C 2 are similar, and the inductances of the first inductor L 1 and the second inductor L 2 are When the values are close, the current is small.
  • the inverter of this embodiment When the inverter of this embodiment is in the fifth working mode, the inverter outputs a negative 1 level. At this time, the inverter may be in the third sub-operation mode or in the fourth sub-operation mode. The following are explained separately.
  • the third switch tube Q L3 when the inverter of the embodiment is in the third sub-operation mode, the third switch tube Q L3 , the first conduction path of the second branch, and the first conduction path of the third branch Turning on, the first switching transistor Q L1 , the second switching transistor Q L2 , the fourth switching transistor Q L4 , the first branch and the fourth branch are turned off. In this case, the second terminal of the first capacitor C 1 (i.e., the first capacitor C 1 and the second common terminal of capacitor C 2) in a charged state.
  • the current flows in sequence: the third switching tube Q L3 ⁇ the switching tube Q H3 ⁇ the switching tube Q H4 anti-parallel diode ⁇ second inductor L 2 ⁇ AC grid u g ⁇ first inductor L 1 ⁇ switch transistor Q H5 ⁇ reverse parallel diode of switch transistor Q H6 ⁇ first capacitor unit C 1 .
  • the conduction state of the switch tube Q H4 and the switch tube Q H6 is not limited, that is, the switch tube Q H4 can be turned on or off, and the switch tube Q H6 can be turned on or off.
  • two reverse-series switching tubes on the fourth branch can prevent current from flowing from the first end of the fourth branch to the second end of the fourth branch.
  • the second switch tube Q L2 when the inverter of the embodiment is in the fourth sub-operation mode, the second switch tube Q L2 , the second conduction path of the first branch, and the second conduction path of the fourth branch Turning on, the first switching transistor Q L1 , the third switching transistor Q L3 , the fourth switching transistor Q L4 , the second branch and the third branch are turned off. In this case, the second terminal of the first capacitor C 1 (i.e., the first capacitor C 1 and the second common terminal of capacitor C 2) in a discharged state.
  • the first capacitor C 1 i.e., the first capacitor C 1 and the second common terminal of capacitor C 2
  • the current flows in sequence: the reverse parallel diode of the switch tube Q H7 ⁇ the switch tube Q H8 ⁇ second inductance L 2 ⁇ alternating current grid u g ⁇ first inductance L 1 ⁇ switching tube Q H2 ⁇ reverse parallel diode of switching transistor Q H1 ⁇ second switching transistor Q L2 ⁇ second capacitive unit C 2 .
  • the conduction state of the switch tube Q H1 and the switch tube Q H8 is not limited, that is, the switch tube Q H1 can be turned on or off, and the switch tube Q H8 can be turned on or off.
  • two reverse-series switching tubes on the third branch can prevent current from flowing from the second end of the third branch to the first end of the third branch.
  • the inverter When the inverter is in the third sub-operation mode or the fourth sub-operation mode, the common ends of the first capacitor unit C 1 and the second capacitor unit C 2 and the third capacitor unit C 3 and the fourth capacitor unit C 4 Current flows through the connection circuit between the common terminals.
  • the inverter outputs a negative 1 level, but the difference is that, in the third sub-working mode, the second end of the first capacitive unit C 1 is at In the charging state, in the fourth sub-operation mode, the second end of the first capacitor unit C 1 is in a discharging state.
  • the inverter of the embodiment when the inverter of the embodiment is in the sixth operating mode, the inverter outputs a negative zero level.
  • the first conduction path of the third branch and the second conduction path of the fourth branch are turned on, the first switch tube Q L1 , the second switch tube Q L2 , the third switch tube Q L3 , and the fourth The switch tube Q L4 , the first branch and the second branch are turned off.
  • the current flows in sequence: the second inductor L 2 ⁇ the alternating current grid ⁇ the first inductor L 1 ⁇ Switch tube Q H5 ⁇ Reverse parallel diode of switch tube Q H6 ⁇ Switch tube Q H7 ⁇ Reverse parallel diode of switch tube Q H8 .
  • the conduction state of the switch tube Q H6 and the switch tube Q H8 is not limited, that is, the switch tube Q H6 can be turned on or off, and the switch tube Q H8 can be turned on or off.
  • the inverter When the inverter is in the sixth working mode, a small amount of current is also connected in the connection circuit between the common end of the third branch and the fourth branch and the common end of the third capacitor unit C 3 and the fourth capacitor unit C 4 flow past. If the capacitance values of the third capacitor unit C 3 and the fourth capacitor unit C 4 are similar, the capacitance values of the first capacitor unit C 1 and the second capacitor unit C 2 are similar, and the inductances of the first inductor L 1 and the second inductor L 2 are When the values are close, the current is small.
  • the inverter shown in FIG. 2 when the inverter shown in FIG. 2 is in the first or second working mode, the voltage of the first end of the first branch is higher than the voltage of the second end, so only The conduction of the first branch can be controlled by the switch tube Q H1 , and the voltage of the second end of the second branch is higher than the voltage of the first end, so the guide of the second branch can only be controlled by the switch tube Q H4 through.
  • the voltage of the second end of the first branch is higher than the voltage of the first end, so the conduction of the first branch can only be controlled by the switch Q H2 .
  • the voltage of the first end of the second branch is higher than the voltage of the second end, so the conduction of the second branch can only be controlled by the switch Q H3 .
  • the conduction between the third branch and the fourth branch is controlled by the switch tube Q H6 and the switch tube Q H8 , respectively.
  • the switching of the third branch and the fourth branch is controlled by the switching tube Q H5 and the switching tube Q H7 , respectively.
  • the inverter can output periodic signals.
  • the periodic signal output by the inverter is divided into a first time period, a second time period, a third time period, a fourth time period, a fifth time period, and a sixth time period in one cycle.
  • the inverter in the first time period, the second time period and the third time period, the inverter outputs a positive voltage
  • the fourth time period, the fifth time period and the sixth time period the inverter outputs a negative voltage.
  • the inverter In the first time period and the third time period, the inverter is alternately in the second working mode and the third working mode, and the inverter alternately outputs the positive 1 and positive 0 levels.
  • the inverter alternates between the first operating mode and the second operating mode, at which time the inverter alternately outputs positive 1 and positive 2 levels.
  • the inverter is alternately in the fifth working mode and the sixth working mode; at this time, the inverter alternately outputs negative 1 and negative 0 levels.
  • the inverter alternates between the fourth operating mode and the fifth operating mode, at which time the inverter alternately outputs negative 1 and negative 2 levels.
  • the inverter when the inverter is in the second working mode, it may be in the first sub working mode or in the second sub working mode, and the inverter may be in the fifth working mode. It is in the third sub-work mode, or it can be in the fourth sub-work mode.
  • the inverter When the inverter is in the first sub-operation mode and the third sub-operation mode, the second end of the first capacitor unit C 1 is in a charging state, and the inverter is in the second sub-working mode and the fourth sub-operation In the modal state, the second end of the first capacitor unit C 1 is in a discharged state.
  • a preferred method is to make the second end of the first capacitor unit C 1 (ie, the midpoint of the DC bus) in one cycle by assigning the second working mode and the fifth working mode.
  • the time in the state of charge and the state of discharge is equal or differs within a predetermined range, so that the voltage at the midpoint of the DC bus is as balanced as possible.
  • the following describes three ways to ensure that the voltage at the midpoint of the DC bus is as balanced as possible.
  • the first mode of distribution is that, in the first time period, the second time period, and the third time period, the second end of the first capacitor unit has the same charge and discharge state, and may be both in a charged state and in a discharged state.
  • the charging and discharging states of the second end of the first capacitor unit are the same at the fourth period, the fifth period, and the sixth period, and charging of the second end of the first capacitor unit with the first period, the second period, and the third period
  • the discharge state is reversed. Therefore, if the second end of the first capacitor unit is in the charging state during the first period, the second period, and the third period, then in the fourth period, the fifth period, and the sixth period, the first The second end of the capacitor unit is in a discharged state. If the second end of the first capacitor unit is in a discharge state during the first period, the second period, and the third period, the second end of the first capacitor unit is in the fourth period, the fifth period, and the sixth period For the state of charge.
  • the inverter is alternately operated in the first sub-section during the first period (or the third period).
  • the working mode and the third working mode if the second end of the first capacitor unit is in a discharging state in the first period (or the third period), the inverter is alternately operated during the first period (or the third period) In the second sub-operation mode and the third working mode; if the second end of the first capacitor unit is in a charging state in the second period, the second period of time, the inverter alternately operates in the first sub-working mode and In the first working mode, if the second end of the first capacitor unit is in a discharging state in the second period, the inverter is alternately operated in the second sub-working mode and the first working mode in the second period.
  • the inverter alternately operates in the third sub-working mode and the sixth Working mode, if the second end of the first capacitor unit is in a discharging state in the fourth period (or the sixth period), indicating that the fourth period (or the sixth period), the inverter alternately operates in the fourth sub-working mode And the sixth working mode; if the second end of the first capacitor unit in the fifth period is in a charging state, it indicates that the inverter alternately operates in the third sub working mode and the fourth working mode in the fifth time period, If the second end of the first capacitor unit is in a discharging state in the fifth period, it indicates that the inverter alternately operates in the fourth sub-working mode and the fourth working mode in the fifth period.
  • the inverter may be alternately in the B mode and the D mode in the first time period T1 and the third time period T3, in the second
  • the period T2 causes the inverter to alternately be in the A mode and the D mode
  • the fourth period T4 and the sixth period T6 the inverter is alternately in the C mode and the D mode
  • the fifth period T5 the inverter is alternated.
  • FIG. 6 is a modal switching control diagram for the inverter. Therefore, in FIG. 6, the negative level signal output from the inverter is inverted to a positive level signal.
  • the A mode includes a first operating mode that outputs positive 2 or a fourth operating mode that outputs a negative 2 level
  • the B mode includes a third operating mode that outputs a positive zero level or outputs a negative zero level.
  • the C mode includes a first sub-operation mode in which a positive 1-level is output and a voltage at a midpoint of the DC bus is a first sub-operation mode of a state of charge, or a negative 1-level is output and a voltage at a midpoint of the DC bus is a state of charge.
  • the D mode includes a second sub-operation mode in which a positive 1-level output and a voltage at a midpoint of the DC bus is a discharge state, or a fourth sub-operation mode in which a negative 1-level is output and a voltage at a midpoint of the DC bus is a discharge state.
  • the voltage at the midpoint of the DC bus is in a discharged state
  • the fourth period T4 the fifth period T5, and the sixth period T6, that is, in the second half of a period signal, in the DC bus.
  • the voltage at the point is in a state of charge.
  • the voltage of the midpoint of the DC bus in the distribution mode is The charging and discharging times are equal, which ensures the voltage balance of the midpoint of the DC bus.
  • the second distribution mode is that the charging and discharging states of the second end of the first capacitor unit are the same in the first period, the second half of the second period, the first half of the fifth period, and the sixth period, and both may be in a charging state. It can also be in a discharged state.
  • the charge and discharge states of the second end of the first capacitor unit are the same, and the second period of the first period and the second period
  • the charge and discharge states of the second end of the first capacitor unit in the first half of the fifth period and the sixth period are opposite. Therefore, if the second end of the first capacitor unit is in a charging state during the first period, the second half of the second period, the first half of the fifth period, and the sixth period, then in the first half of the second period, During the third period, the fourth period, and the second half of the fifth period, the second end of the first capacitor unit is in a discharged state.
  • the second end of the first capacitor unit is in a discharged state, then in the first half period and the third period of the second period During the fourth period and the second half of the fifth period, the second end of the first capacitor unit is in a charged state.
  • the inverter may be alternately in the B mode and the D mode in the first time period T1 and the sixth time period T6, in the second The second half period of the period T2 and the first half period of the fifth period T5 cause the inverter to alternately be in the A mode and the D mode.
  • the inverter is alternately in the B mode and the C mode
  • the first half period of the second period T2 and the second half period of the fifth period T5 cause the inverter to alternately be in the A mode and the C mode.
  • FIG. 7 is a modal switching control diagram for the inverter, and therefore, the negative level signal output from the inverter is inverted to a positive level signal in FIG.
  • the voltage of the midpoint of the DC bus is in a discharging state
  • the third period T3 and The fourth period T4 the first half period of the second period T2, and the second half period of the fifth period T5
  • the voltage at the midpoint of the DC bus is in a state of charge, and thus the charging and discharging time of the voltage at the midpoint of the DC bus in this distribution mode Equal, to ensure the voltage balance of the midpoint of the DC bus.
  • the third mode of distribution is that in the second period of the first period, the second period of the second period, the fourth period, and the second period of the fifth period, the second end of the first capacitor unit has the same charge and discharge state, and may be in a state of charge. It can also be in a discharged state.
  • the charge and discharge states of the second end of the first capacitor unit are the same, and the first period, the second half of the second period, The charge and discharge states of the second end of the first capacitor unit are opposite in the fourth period and the fifth period. Therefore, if the second end of the first capacitor unit is in a charging state during the first period, the second half of the second period, the fourth period, and the second half of the fifth period, then in the first half of the second period, In the third period, the first half of the fifth period, and the sixth period, the second end of the first capacitor unit is in a discharged state.
  • the second end of the first capacitor unit is in a discharged state, then in the first half of the second period, the third During the period, the first half of the fifth period, and the sixth period, the second end of the first capacitor unit is in a charged state.
  • the inverter may be alternately in the B mode and the D mode in the first time period T1 and the fourth time period T4, in the second Time
  • the latter half period of the segment T2 and the second half period of the fifth period T5 cause the inverter to alternately be in the A mode and the D mode.
  • the third period T3 and the sixth period T6 cause the inverter to alternately be in the B mode and the C mode, and the inverter is alternately in the A mode and in the first half period of the second period T2 and the first half period of the fifth period T5.
  • FIG. 8 is a modal switching control diagram for the inverter, and therefore, the negative level signal output from the inverter is inverted to a positive level signal in FIG.
  • the voltage of the midpoint of the DC bus is in a discharging state
  • the sixth period T6 the first half period of the second period T2, and the first half period of the fifth period T5
  • the voltage of the midpoint of the DC bus is in a state of charge, and thus the charging and discharging time of the voltage at the midpoint of the DC bus in this distribution mode Equal, to ensure the voltage balance of the midpoint of the DC bus.
  • the first distribution mode charges and discharges the DC bus midpoint once in one cycle, and contains a power frequency (generally 50hz) harmonic
  • the second distribution mode is in one cycle.
  • the DC bus is charged 3 times in the midpoint, discharged 3 times, and contains power frequency multiple harmonics.
  • the third distribution method charges and discharges the DC bus midpoint four times in one cycle. Obviously, the third distribution method has the highest charge and discharge frequency, so the busbar electric ripple is the smallest.
  • the first type of distribution has the lowest charge and discharge frequency and the bus voltage ripple is the largest.
  • the inverter in this embodiment has three reactive working modes, which are a seventh working mode, an eighth working mode, and a ninth working mode.
  • the inverter of the embodiment when the inverter of the embodiment is in the seventh operating mode, the inverter outputs a positive level.
  • the first switch tube Q L1 , the fourth switch tube Q L4 , the first conduction path and the second conduction path of the first branch, and the first conduction path and the second conduction path of the second branch The path is turned on, and the second switching transistor Q L2 , the third switching transistor Q L3 , the third branch, and the fourth branch are turned off.
  • the current can flow through: first switch tube Q L1 ⁇ first branch ⁇ first inductor L 1 ⁇ AC grid u g ⁇ second inductor L 2 ⁇ second branch ⁇ fourth switch tube Q L4 ⁇
  • the second capacitor unit C 2 ⁇ the first capacitor unit C 1 .
  • the current can also flow in the opposite direction along the above path.
  • the connection between the common end of the first capacitive unit C 1 and the second capacitive unit C 2 and the common end of the third capacitive unit C 3 and the fourth capacitive unit C 4 There is also a small amount of current flowing through it. If the capacitance values of the third capacitor unit C 3 and the fourth capacitor unit C 4 are similar, the capacitance values of the first capacitor unit C 1 and the second capacitor unit C 2 are similar, and the inductances of the first inductor L 1 and the second inductor L 2 are When the values are close, the current is small.
  • the inverter of the embodiment when the inverter of the embodiment is in the eighth operating mode, the inverter outputs a level of 0.
  • the first conduction path and the second conduction path of the third branch, and the first conduction path and the second conduction path of the fourth branch are turned on, the first switch tube Q L1 , the second switch The tube Q L2 , the third switching tube Q L3 , the fourth switching tube Q L4 , the first branch and the second branch are turned off.
  • the current can flow in sequence: the third branch ⁇ the first inductance L 1 ⁇ the alternating current grid u g ⁇ the second inductance L 2 ⁇ the fourth branch.
  • the current can also flow in the opposite direction along the above path.
  • the connection between the common end of the first capacitive unit C 1 and the second capacitive unit C 2 and the common end of the third capacitive unit C 3 and the fourth capacitive unit C 4 There is also a small amount of current flowing through it. If the capacitance values of the third capacitor unit C 3 and the fourth capacitor unit C 4 are similar, the capacitance values of the first capacitor unit C 1 and the second capacitor unit C 2 are similar, and the inductances of the first inductor L 1 and the second inductor L 2 are When the values are close, the current is small.
  • the inverter of the embodiment when the inverter of the embodiment is in the ninth working mode, the inverter outputs a negative one level.
  • the second switch tube Q L2 , the third switch tube Q L3 , the first conduction path and the second conduction path of the first branch, and the first conduction path and the second path of the second branch The conduction path is turned on, and the first switching transistor Q L1 , the fourth switching transistor Q L4 , the third branch, and the fourth branch are turned off.
  • the current can flow through: third switch tube Q L3 ⁇ second branch ⁇ second inductor L 2 ⁇ AC grid u g ⁇ first inductor L 1 ⁇ first branch ⁇ second switch tube Q L2 ⁇ second capacitor Cell C 2 ⁇ first capacitor cell C 1 .
  • the current can also flow in the opposite direction along the above path.
  • the connection between the common end of the first capacitive unit C 1 and the second capacitive unit C 2 and the common end of the third capacitive unit C 3 and the fourth capacitive unit C 4 There is also a small amount of current flowing through it. If the capacitance values of the third capacitor unit C 3 and the fourth capacitor unit C 4 are similar, the capacitance values of the first capacitor unit C 1 and the second capacitor unit C 2 are similar, and the inductances of the first inductor L 1 and the second inductor L 2 are When the values are close, the current is small.
  • an inductor may be connected in series between the two output ends of the inverter and the AC grid to achieve better grid current quality.
  • the negative electrode of g The inductance values of the third inductor L 3 and the fourth inductor L 4 are generally small relative to the first inductor L 1 and the second inductor L 2 .

Abstract

一种五电平逆变器，包括十二个开关管、两个电感和四个电容单元。第三电容单元（C3）和第四电容单元（C4）的公共端连接第一电容单元（C1）和第二电容单元（C2）的公共端。第三电容单元和第四电容单元为该逆变器的输出滤波电路。第三电容单元和第四电容单元的公共端为直流母线的中点。该逆变器不会出现漏电流问题，输出效率较高，适合光伏发电领域。

Description

一种五电平逆变器
本申请要求于2013年12月30日提交中国专利局、申请号为201310752303.4、发明名称为“一种五电平逆变器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电力电子技术领域，尤其是涉及一种五电平逆变器。
背景技术
逆变器用于将直流电源输出的直流电压转换成交流电压后，输出给负载电路，在光伏、风能发电等领域都有广泛的应用。然而，由于直流电源(例如太阳能电池板)对地寄生电容的存在，导致了逆变器工作时可能会出现漏电流的问题。而漏电流问题不仅会损坏输出电能质量，降低逆变器的工作效率，而且还会对人体产生危害，降低逆变器的可靠性。
目前，为了解决漏电流的问题，已出现H5、H6、HERIC等拓扑的逆变器，但这些逆变器都为三电平逆变器，因此效率较低。而五电平逆变器相比于三电平逆变器，效率更高，但是如何在五电平逆变器中解决漏电流的问题，成为目前人们越来越关注的问题。例如，图1为现有的一种五电平逆变器，该逆变器工作时，直流电源DC正极相对于输出负极，即C点处会存在工频跳变，而该工频跳变电压作用在直流电源DC正极(或负极)与大地之间的寄生电容上，会导致漏电流尖峰的产生。
发明内容
本发明解决的技术问题在于提供一种五电平逆变器，以克服漏电流问题，从而提高逆变器的工作效率和可靠性。
为此，本发明解决技术问题的技术方案是：
本发明提供了一种五电平逆变器，所述逆变器包括：第一开关管、第二开关管、第三开关管、第四开关管、第一支路、第二支路、第三支路、第四支路、 第一电容单元、第二电容单元、第三电容单元、第四电容单元、第一电感和第二电感；
所述第一支路、所述第二支路、所述第三支路和所述第四支路中的各个支路均具有第一导通路径和第二导通路径，所述第一导通路径导通时，电流能够从该支路的第一端流向第二端，所述第二导通路径导通时，电流能够从所述该支路的第二端流向第一端，所述第一导通路径和所述第二导通路径均关断时，该支路关断，电流被禁止从该支路的一端流向另一端；
直流电源的正极连接所述第一开关管的第一端、所述第三开关管的第一端和所述第一电容单元的第一端；所述直流电源的负极连接所述第二开关管的第一端、所述第四开关管的第一端和所述第二电容单元的第二端；
所述第一开关管的第二端连接所述第二开关管的第二端和所述第一支路的第一端；所述第三开关管的第二端连接所述第四开关管的第二端和所述第二支路的第一端；
所述第一支路的第二端连接所述第一电感的第一端和所述第三支路的第一端；所述第二支路的第二端连接所述第二电感的第一端和所述第四支路的第一端；
所述第一电感的第二端连接所述第三电容单元的第一端，所述第二电感的第二端连接所述第四电容单元的第二端；
所述第三电容单元的第二端连接所述第四电容单元的第一端、所述第三支路的第二端、所述第四支路的第二端、所述第一电容单元的第二端和所述第二电容单元的第一端；
所述第一电感的第二端和所述第二电感的第二端为所述逆变器的交流输出端。
可选地，所述第一开关管导通时，电流从所述第一开关管的第一端流向第二端；所述第三开关管导通时，电流从所述第三开关管的第一端流向第二端；
所述第二开关管导通时，电流从所述第二开关管的第二端流向第一端；所述第四开关管导通时，电流从所述第四开关管的第二端流向第一端。
可选地，所述第一支路、所述第二支路、所述第三支路和所述第四支路中 的任一支路包括串联的并且导通方向相反的第五开关管和第六开关管；
所述第五开关管的导通方向使得电流从该支路的第一端流向第二端，所述第六开关管的导通方向使得电流从该支路的第二端流向第一端；其中，所述第五开关管和所述第六开关管的反并联二极管为该支路的所述第一导通路径，所述第六开关管和所述第五开关管的反并联二极管为该支路的所述第二导通路径。
可选地，所述第一支路、所述第二支路、所述第三支路和所述第四支路中的任一支路包括第七开关管、第八开关管、第一二极管和第二二极管；
所述第一二极管和所述第七开关管串联后，与所述第二二极管和所述第八开关管的串联电路并联，所述第一二极管和所述第七开关管的导通方向均使得电流从该支路的第一端流向第二端，所述第二二极管和所述第八开关管的导通方向均使得电流从该支路的第二端流向第一端，所述第一二极管和所述第七开关管为该支路的所述第一导通路径，所述第二二极管和所述第八开关管为该支路的所述第二导通路径。
可选地，所述第一支路、所述第二支路、所述第三支路和所述第四支路中的任一支路包括第三二极管、第四二极管、第五二极管、第六二极管和第九开关管；
所述第三二极管的正极连接所述第四二极管的负极，作为该支路的第一端，所述第五二极管的正极连接所述第六二极管的负极，作为该支路的第二端；所述第三二极管的负极和所述第五二极管的负极连接所述第九开关管的第一端，所述第四二极管的正极和所述第六二极管的正极连接所述第九开关管的第二端，所述第九开关管的导通方向使得电流从所述第九开关管的第一端流向第二端；
所述第三二极管、所述第九开关管和所述第六二极管为该支路的所述第一导通路径；所述第四二极管、所述第九开关管和所述第五二极管为该支路的所述第二导通路径。
可选地，所述逆变器具有六种有功工作模态，分别为第一工作模态、第二工作模态、第三工作模态、第四工作模态、第五工作模态和第六工作模态；
所述逆变器处于所述第一工作模态时，所述第一开关管、第四开关管、所 述第一支路的第一导通路径和所述第二支路的第二导通路径导通，所述第二开关管、第三开关管、所述第三支路和所述第四支路关断；
所述逆变器处于所述第二工作模态时，所述逆变器处于第一子工作模态或者第二子工作模态；所述逆变器处于所述第一子工作模态时，所述第一开关管、所述第一支路的第一导通路径和所述第四支路的第一导通路径导通，所述第二开关管、第三开关管、第四开关管、所述第二支路和所述第三支路关断，所述第一电容单元的第二端处于充电状态；所述逆变器处于所述第二子工作模态时，所述第四开关管、所述第二支路的第二导通路径和所述第三支路的第二导通路径导通，所述第一开关管、第二开关管、第三开关管、所述第一支路和所述第四支路关断，所述第一电容单元的第二端处于放电状态；
所述逆变器处于所述第三工作模态时，所述第三支路的第二导通路径和所述第四支路的第一导通路径导通，所述第一开关管、第二开关管、第三开关管、第四开关管、所述第一支路和所述第二支路关断；
所述逆变器处于所述第四工作模态时，所述第二开关管、第三开关管、所述第一支路的第二导通路径和所述第二支路的第一导通路径导通，所述第一开关管、第四开关管、所述第三支路和所述第四支路关断；
所述逆变器处于所述第五工作模态时，所述逆变器处于第三子工作模态或者第四子工作模态；所述逆变器处于所述第三子工作模态时，所述第三开关管、所述第二支路的第一导通路径和所述第三支路的第一导通路径导通，所述第一开关管、第二开关管、第四开关管、所述第一支路和所述第四支路关断，所述第一电容单元的第二端处于充电状态；所述逆变器处于所述第四子工作模态时，所述第二开关管、所述第一支路的第二导通路径和所述第四支路的第二导通路径导通，所述第一开关管、第三开关管、第四开关管、所述第二支路和所述第三支路关断，所述第一电容单元的第二端处于放电状态；
所述逆变器处于所述第六工作模态时，所述第三支路的第一导通路径和所述第四支路的第二导通路径导通，所述第一开关管、第二开关管、第三开关管、第四开关管、所述第一支路和所述第二支路关断。
可选地，所述逆变器输出的周期信号在一个周期内分为第一时段、第二时段、第三时段、第四时段、第五时段和第六时段；
在所述第一时段和所述第三时段，所述逆变器交替处于第二工作模态和第三工作模态；
在所述第二时段，所述逆变器交替处于第一工作模态和第二工作模态；
在所述第四时段和所述第六时段，所述逆变器交替处于第五工作模态和第六工作模态；
在所述第五时段，所述逆变器交替处于第四工作模态和第五工作模态。
可选地，在所述第一时段、所述第二时段和所述第三时段，所述第一电容单元的第二端的充放电状态相同；在所述第四时段、所述第五时段和所述第六时段时，所述第一电容单元的第二端的充放电状态相同，并且与所述第一时段、所述第二时段和所述第三时段时所述第一电容单元的第二端的充放电状态相反；
或者，
在所述第一时段、所述第二时段的后半段、所述第四时段和所述第五时段的后半段，所述第一电容单元的第二端的充放电状态相同；在所述第二时段的前半段、所述第三时段、所述第五时段的前半段和第六时段，所述第一电容单元的第二端的充放电状态相同，并且与所述第一时段、所述第二时段的后半段、所述第四时段和所述第五时段时所述第一电容单元的第二端的充放电状态相反；
或者，
在所述第一时段、所述第二时段的后半段、所述第五时段的前半段和所述第六时段，所述第一电容单元的第二端的充放电状态相同；在所述第二时段的 前半段、所述第三时段、所述第四时段和所述第五时段的后半段，所述第一电容单元的第二端的充放电状态相同，并且与所述第一时段、所述第二时段的后半段、所述第五时段的前半段和所述第六时段时所述第一电容单元的第二端的充放电状态相反。
可选地，所述逆变器具有三种无功工作模态，分别为第七工作模态、第八工作模态和第九工作模态：
所述逆变器处于所述第七工作模态时，所述第一开关管、第四开关管、所述第一支路的第一和第二导通路径、以及所述第二支路的第一和第二导通路径导通，所述第二开关管、第三开关管、所述第三支路和所述第四支路关断；
所述逆变器处于所述第八工作模态时，所述第三支路的第一和第二导通路径，以及所述第四支路的第一和第二导通路径导通，所述第一开关管、第二开关管、第三开关管、第四开关管、所述第一支路和所述第二支路关断；
所述逆变器处于所述第九工作模态时，所述第二开关管、第三开关管、所述第一支路的第一和第二导通路径、以及所述第二支路的第一和第二导通路径导通，所述第一开关管、第四开关管、所述第三支路和所述第四支路关断。
可选地，所述第一电感的第二端还通过第三电感连接交流电网的正极，所述第二电感的第二端还通过第四电感连接所述交流电网的负极。
通过上述技术方案可知，在本发明的五电平逆变器中，第三电容单元和第四电容单元为该逆变器的输出滤波电路，第一电容单元的第二端为直流母线的中点，并且，第三电容单元和第四电容单元的公共端连接第一电容单元的第二端，从而使得直流母线的中点(或者直流电源正极或者负极)相对于输出滤波电路的中点的电位比较稳定，不会出现跳变电压，因此没有漏电流问题，从而提高了逆变器的工作效率和可靠性。
附图说明
图1为现有的一种五电平逆变器的电路图；
图2为本发明一实施例提供的五电平逆变器的电路图；
图3为本发明一实施例提供的任一支路的电路图；
图4为本发明一实施例提供的任一支路的另一电路图；
图5a为图2所示的逆变器的第一工作模态的电路导通图；
图5b为图2所示的逆变器的第一子工作模态的电路导通图；
图5c为图2所示的逆变器的第二子工作模态的电路导通图；
图5d为图2所示的逆变器的第三工作模态的电路导通图；
图5e为图2所示的逆变器的第四工作模态的电路导通图；
图5f为图2所示的逆变器的第三子工作模态的电路导通图；
图5g为图2所示的逆变器的第四子工作模态的电路导通图；
图5h为图2所示的逆变器的第六工作模态的电路导通图；
图6为对应直流母线中点充放电的第一种分配方式的模态切换控制图；
图7为对应直流母线中点充放电的第二种分配方式的模态切换控制图；
图8为对应直流母线中点充放电的第三种分配方式的模态切换控制图；
图9a为图2所示的逆变器的第七工作模态的电路导通图；
图9b为图2所示的逆变器的第八工作模态的电路导通图；
图9c为图2所示的逆变器的第九工作模态的电路导通图；
图10为图2所示的逆变器的一种优选的电路图。
具体实施方式
逆变器工作时，直流电源相对于输出负极(与大地等电势)可能出现工频或者高频的跳变电压，而由于直流电源(例如太阳能电池板)对地寄生电容的存在，因此导致可能会出现漏电流的问题。而漏电流问题不仅会损坏输出电能质量，降低逆变器的工作效率，而且还会对人体产生危害，降低逆变器的可靠性。例如，图1为现有的一种五电平逆变器，该逆变器工作时，直流电源DC相对于输出负极，即C点处会存在工频跳变，也可以说是母线中点处，即电容C1和电容C2的公共端，或者直流电源DC负极相对于输出负极存在工频跳变。 而输出负极往往与电网N线相连，电网N线与大地电势相近，因此该跳变电压作用在直流电源DC正极(或负极)与大地之间的寄生电容上，会导致漏电流尖峰的产生。
本发明提供了一种五电平逆变器，以解决漏电流问题，从而提高逆变器的工作效率以及提高可靠性。
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明实施例进行详细描述。
请参阅图2，本发明提供了五电平逆变器的具体实施例，在本实施例中，五电平逆变器包括：第一开关管QL1、第二开关管QL2、第三开关管QL3、第四开关管QL4、第一支路201、第二支路202、第三支路203、第四支路204、第一电容单元C1、第二电容单元C2、第三电容单元C3、第四电容单元C4、第一电感L1和第二电感L2。
第一支路201、第二支路202、第三支路203和第四支路204中的各个支路均具有第一导通路径和第二导通路径，其中，当第一导通路径导通时，电流能够从该支路的第一端流向第二端，当第二导通路径导通时，电流能够从该支路的第二端流向第一端，第一导通路径和第二导通路径均关断时，该支路关断，电流被禁止从该支路的任一端流向另一端。
直流电源DC的正极连接第一开关管QL1的第一端、第三开关管QL3的第一端和第一电容单元C1的第一端；直流电源DC的负极连接第二开关管QL2的第一端、第四开关管QL4的第一端和第二电容单元C2的第二端。
第一开关管QL1的第二端连接第二开关管QL2的第二端和第一支路的第一端；第三开关管QL3的第二端连接第四开关管QL4的第二端和第二支路的第一端。
第一支路的第二端连接第一电感L1的第一端和第三支路的第一端；第二支路的第二端连接第二电感L2的第一端和第四支路的第一端。
第一电感L1的第二端连接第三电容单元C3的第一端，第二电感L2的第二端连接第四电容单元C4的第二端。
第三电容单元C3的第二端连接第四电容单元C4的第一端、第三支路的第二端、第四支路的第二端、第一电容单元C1的第二端和第二电容单元C2的第一 端。
第一电感L1的第二端和第二电感L2的第二端为本实施例五电平逆变器的交流输出端。该交流输出端可以连接交流电网。
在本实施例的五电平逆变器中，由第三电容单元C3的第二端连接第四电容单元C4的第一端、第一电容单元C1的第二端和第二电容单元C2的第一端可知，第三电容单元C3和第四电容单元C4的公共端连接直流母线的中点(即第一电容单元C1的第二端)，从而使得直流母线的中点相对于第三电容单元C3和第四电容单元C4的公共端的电位比较稳定，也就是说直流电源DC的正极或者负极相对于第三电容单元C3和第四电容单元C4的公共端的电位比较稳定，不会出现工频或高频跳变。而第三电容单元C3和第四电容单元C4为该逆变器的输出滤波电路，该输出滤波电路一般连接电网N线，而电网N线与大地电势相近，因此本实施例中的直流电源DC正极(或负极)相对于大地之间不会出现工频或高频跳变，因此没有漏电流问题，从而提高了逆变器的工作效率和可靠性。此外，本实施例中的五电平逆变器是一种双buck电路，五电平输出，效率较高，适合光伏发电等应用领域。
在本实施例中，逆变器的两个输出端之间可以连接有交流电网ug。本实施例中的逆变器可以用于光伏发电等领域，因此直流电源DC可以为PV(Photo Voltaics，光伏)电源等。
在本实施例中，第一开关管QL1、第二开关管QL2、第三开关管QL3、和第四开关管QL4均可以为任何形式的开关管，例如IGBT、MOS管等。并且每个开关管的器件本身均并联有反向二极管，即并联有反并联二极管。其中，第一支路201、第二支路202、第三支路203和第四支路204中的各个支路中所包括的开关管，器件本身也均并联有反向二极管。
其中，当第一开关管QL1导通时，电流从所述第一开关管QL1的第一端流向第二端，也就是说，第一开关管QL1并联的反向二极管的正极连接第一开关管QL1的第二端，负极连接第一开关管QL1的第一端。第三开关管QL3导通时，电流从所述第三开关管QL3的第一端流向第二端。第二开关管QL2导通时，电流从第二开关管QL2的第二端流向第一端，也就是说，第二开关管QL2并联的反向二极管的正极连接第二开关管QL2的第一端，负极连接第二开关管QL2的第二端。 第四开关管QL4导通时，电流从第四开关管QL4的第二端流向第一端。
在本实施例中，第一支路201、第二支路202、第三支路203和第四支路204中的每个支路都包括两个导通路径，即第一导通路径和第二导通路径。通过控制一个导通路径导通，则能对应的控制电流从支路的一端流向另一端。其中，任一支路可以如图2所示，包括两个串联并且导通方向相反的第五开关管和第六开关管，第五开关管的导通方向使得电流从该支路的第一端流向第二端，第六开关管的导通方向使得电流从该支路的第二端流向第一端；其中，第五开关管和第六开关管的反并联二极管为该支路的第一导通路径，第六开关管和第五开关管的反并联二极管为该支路的第二导通路径。因此，当第一导通路径导通时，说明该支路的第五开关管导通，当第二导通路径导通时，说明该支路的第六开关管导通，而第一导通路径和第二导通路径均关断，即该支路均关断时，说明该支路的第五开关管和第六开关管均关断。例如在图2中，第一支路包括串联并且导通方向相反的开关管QH1和QH2。第二支路包括串联并且导通方向相反的开关管QH3和QH4。第三支路包括串联并且导通方向相反的开关管QH5和QH6。第四支路包括串联并且导通方向相反的开关管QH7和QH8。
其中，开关管QH1和开关管QH2串联在第一支路上，并且开关管QH1和开关管QH2的导通方向相反，开关管QH1的导通方向使得电流从第一支路的第一端流向第一支路的第二端，开关管QH2的导通方向使得电流从第一支路的第二端流向第一支路的第一端。需要说明的是，开关管QH1和开关管QH2可以如图2所示，开关管QH1连接第一支路的第一端，开关管QH2连接第一支路的第二端，当然，开关管QH1和开关管QH2的位置也可以互换，即开关管QH2连接第一支路的第一端，开关管QH1连接第一支路的第二端，并不影响本发明的实现。类似地，图2中所示的开关管QH3和开关管QH4的位置也可以互换，开关管QH5和开关管QH6的位置也可以互换，开关管QH7和开关管QH8的位置也可以互换。
除了上述电路外，第一支路201、第二支路202、第三支路203和第四支路204中的任一支路还可以用其他电路替换，均不影响本发明的实现。例如，如图3所示，其中任一支路可以包括第七开关管QH9、第八开关管QH10、第一二极管D1和第二二极管D2。
第一二极管D1和第七开关管QH9串联后，与第二二极管D2和第八开关管 QH10的串联电路并联，第一二极管D1和第七开关管QH9的导通方向均使得电流从该支路的第一端流向第二端，第二二极管D2和第八开关管QH10的导通方向均使得电流从该支路的第二端流向第一端，第一二极管D1和第七开关管QH9为该支路的第一导通路径，第二二极管D2和第八开关管QH10为该支路的第二导通路径。因此，当第一导通路径导通时，说明该支路的第七开关管QH9导通，当第二导通路径导通时，说明该支路的第八开关管QH10导通，而第一导通路径和第二导通路径均关断，即该支路关断时，说明该支路的第七开关管QH9和第八开关管QH10均关断。
其中，图3中的第一二极管D1和第七开关管QH9的位置可以互换，第二二极管D2和第八开关管QH10的位置也可以互换。
如图4所示，第一支路201、第二支路202、第三支路203和第四支路204中的任一支路可以包括：第三二极管D3、第四二极管D4、第五二极管D5、第六二极管D6和第九开关管QH11。
其中，第三二极管D3的正极连接第四二极管D4的负极，作为该支路的第一端，第五二极管D5的正极连接第六二极管D6的负极，作为该支路的第二端；第三二极管D3的负极和第五二极管D5的负极连接第九开关管QH11的第一端，第四二极管D4的正极和第六二极管D6的正极连接第九开关管QH11的第二端，第九开关管QH11的导通方向使得电流从第九开关管QH11的第一端流向第二端。
第三二极管D3、第九开关管QH11和第六二极管D6为该支路的第一导通路径；第四二极管D4、第九开关管QH11和第五二极管D5为该支路的第二导通路径。因此，当第一导通路径导通时，说明该支路的第九开关管QH11导通，当第二导通路径导通时，说明该支路的第九开关管QH11导通，而第一导通路径和第二导通路径均关断时，说明该支路的第九开关管QH11关断。
在本实施例中，第一开关管QL1、第二开关管QL2、第三开关管QL3和第四开关管QL4可以为低频开关管，即工频开关管，因此在逆变器工作时，第一开关管QL1、第二开关管QL2、第三开关管QL3和第四开关管QL4低频开关动作。而各个支路上的开关管可以为高频开关管，因此在逆变器工作时，各个支路上的开关管高频开关动作，本发明中所说的高频一般指大于1khz的频率，而低频一般指的是低于1khz的频率(一般为工频，例如50hz)。
在本实施例中，第一电容单元、第二电容单元、第三电容单元、和第四电容单元均可以为电容组成的单元。每个电容单元所包括的电容的数量不受限定。为了使得电路尽量平衡，可以使第一电容单元和第二电容单元的容值相等或者容值的差值在第一预设阈值内，也可以使得第三电容单元和第四电容单元的容值相等或者容值差值在第二预设阈值内。第一预设阈值和第二预设阈值可以根据电路需求进行设定，可以相等也可以不相等。为了使得电路尽量平衡，第一电感和第二电感的电感值也可以相等或者相差在一个阈值范围内。
需要说明的是，本发明实施例提供的逆变器，不但可以应用于需求有功功率的场合，也可以应用于同时需求无功功率和有功功率的场合，下面结合附图对各种工作状态分别进行介绍。
如图5a-5h所示，本实施例中的逆变器具有六种有功工作模态，分别为第一工作模态、第二工作模态、第三工作模态、第四工作模态、第五工作模态和第六工作模态。
如图5a所示，本实施例的逆变器处于第一工作模态时，所述逆变器输出正2电平。此时，第一开关管QL1、第四开关管QL4、第一支路的第一导通路径和第二支路的第二导通路径导通，第二开关管QL2、第三开关管QL3、第三支路和第四支路关断。
以第一支路、第二支路、第三支路和第四支路均为图2所示的结构为例，电流依次流经：第一开关管QL1→开关管QH1→开关管QH2的反向并联二极管→第一电感L1→交流电网ug→第二电感L2→开关管QH4→开关管QH3的反向并联二极管→第四开关管QL4→第二电容单元C2→第一电容单元C1。开关管QH2和开关管QH3的导通状态不受限定，也就是说，开关管QH2可以导通，也可以关断，开关管QH3可以导通，也可以关断。
可见，在第一工作模态时，第三支路上两个反向串联的开关管(即开关管QH5和开关管QH6)能够防止电流从第三支路的第一端流向第三支路的第二端，第四支路上两个反向串联的开关管(即开关管QH7和开关管QH8)能够防止电流从第四支路的第二端流向第四支路的第一端。
当逆变器处于第一工作模态时，第一电容单元C1和第二电容单元C2的公共端与第三电容单元C3和第四电容单元C4的公共端之间的连接电路中也有少量 电流流过。若第三电容单元C3和第四电容单元C4容值相近，第一电容单元C1和第二电容单元C2的容值相近，并且第一电感L1和第二电感L2的电感值相近时，该电流较小。
本实施例的逆变器处于第二工作模态时，所述逆变器输出正1电平，此时逆变器可以处于第一子工作模态，也可以处于第二子工作模态。下面分别说明。
如图5b所示，本实施例的逆变器处于第一子工作模态时，第一开关管QL1、第一支路的第一导通路径和第四支路的第一导通路径导通，第二开关管QL2、第三开关管QL3、第四开关管QL4、第二支路和第三支路关断。此时，第一电容单元C1的第二端(即第一电容单元C1和第二电容单元C2的公共端)处于充电状态。
以第一支路、第二支路、第三支路和第四支路均为图2所示的结构为例，电流依次流经：第一开关管QL1→开关管QH1→开关管QH2的反向并联二极管→第一电感L1→交流电网ug→第二电感L2→开关管QH8→开关管QH7的反向并联二极管→第一电容单元C1。开关管QH2和开关管QH7的导通状态不受限定，也就是说，开关管QH2可以导通，也可以关断，开关管QH7可以导通，也可以关断。
可见，在第一子工作模态时，第三支路上两个反向串联的开关管能够防止电流从第三支路的第一端流向第三支路的第二端。
如图5c所示，逆变器处于第二子工作模态时，第四开关管QL4、第二支路的第二导通路径和第三支路的第二导通路径导通，第一开关管QL1、第二开关管QL2、第三开关管QL3、第一支路和第四支路关断。此时，第一电容单元C1的第二端(即第一电容单元C1和第二电容单元C2的公共端)处于放电状态。
以第一支路、第二支路、第三支路和第四支路均为图2所示的结构为例，电流依次流经：开关管QH6→开关管QH5的反向并联二极管→第一电感L1→交流电网ug→第二电感L2→开关管QH4→开关管QH3的反向并联二极管→第四开关管QL4→第二电容单元C2。开关管QH3和开关管QH5的导通状态不受限定，也就是说，开关管QH3可以导通，也可以关断，开关管QH5可以导通，也可以关断。
可见，在第二子工作模态时，第四支路上两个反向串联的开关管能够防止电流从第四支路的第二端流向第四支路的第一端。
当逆变器处于第一子工作模态或者第二子工作模态时，第一电容单元C1和第二电容单元C2的公共端与第三电容单元C3和第四电容单元C4的公共端之间的连接电路中均有电流流过。
可以看出，在上述两个子工作模态中，逆变器均输出正1电平，但是这两个字工作模态中不同的是，在第一子工作模态时，第一电容单元C1的第二端处于充电状态，在第二子工作模态时，第一电容单元C1的第二端处于放电状态。
如图5d所示，本实施例的逆变器处于第三工作模态时，所述逆变器输出正0电平。此时，第三支路的第二导通路径和第四支路的第一导通路径导通，第一开关管QL1、第二开关管QL2、第三开关管QL3、第四开关管QL4、第一支路和第二支路关断。
以第一支路、第二支路、第三支路和第四支路均为图2所示的结构为例，电流依次流经：第一电感L1→交流电网ug→第二电感L2→开关管QH8→开关管QH7的反向并联二极管→开关管QH6→开关管QH5的反向并联二极管。开关管QH5和开关管QH7的导通状态不受限定，也就是说，开关管QH5可以导通，也可以关断，开关管QH7可以导通，也可以关断。
当逆变器处于第三工作模态时，第三支路和第四支路的公共端与第三电容单元C3和第四电容单元C4的公共端之间的连接电路中也有少量电流流过。若第三电容单元C3和第四电容单元C4容值相近，第一电容单元C1和第二电容单元C2的容值相近，并且第一电感L1和第二电感L2的电感值相近时，该电流较小。
如图5e所示，本实施例的逆变器处于第四工作模态时，所述逆变器输出负2电平。此时，第二开关管QL2、第三开关管QL3、第一支路的第二导通路径和第二支路的第一导通路径导通，第一开关管QL1、第四开关管QL4、第三支路和第四支路关断。
以第一支路、第二支路、第三支路和第四支路均为图2所示的结构为例，此时，电流依次流经：第三开关管QL3→开关管QH3→开关管QH4的反向并联二极管→第二电感L2→交流电网ug→第一电感L1→开关管QH2→开关管QH1的反向并联二极管→第二开关管QL2→第二电容单元C2→第一电容单元C1。开关管QH1和开关管QH4的导通状态不受限定，也就是说，开关管QH1可以导通，也可 以关断，开关管QH4可以导通，也可以关断。
可见，在第四工作模态时，第三支路上两个反向串联的开关管能够防止电流从第三支路的第二端流向第三支路的第一端，第四支路上两个反向串联的开关管能够防止电流从第四支路的第一端流向第四支路的第二端。
当逆变器处于第四工作模态时，第一电容单元C1和第二电容单元C2的公共端与第三电容单元C3和第四电容单元C4的公共端之间的连接电路中也有少量电流流过。若第三电容单元C3和第四电容单元C4容值相近，第一电容单元C1和第二电容单元C2的容值相近，并且第一电感L1和第二电感L2的电感值相近时，该电流较小。
本实施例的逆变器处于第五工作模态时，所述逆变器输出负1电平，此时逆变器可以处于第三子工作模态，也可以处于第四子工作模态。下面分别说明。
如图5f所示，本实施例的逆变器处于第三子工作模态时，第三开关管QL3、第二支路的第一导通路径和第三支路的第一导通路径导通，第一开关管QL1、第二开关管QL2、第四开关管QL4、第一支路和第四支路关断。此时，第一电容单元C1的第二端(即第一电容单元C1和第二电容单元C2的公共端)处于充电状态。
以第一支路、第二支路、第三支路和第四支路均为图2所示的结构为例，电流依次流经：第三开关管QL3→开关管QH3→开关管QH4的反向并联二极管→第二电感L2→交流电网ug→第一电感L1→开关管QH5→开关管QH6的反向并联二极管→第一电容单元C1。开关管QH4和开关管QH6的导通状态不受限定，也就是说，开关管QH4可以导通，也可以关断，开关管QH6可以导通，也可以关断。
可见，在第三子工作模态时，第四支路上两个反向串联的开关管能够防止电流从第四支路的第一端流向第四支路的第二端。
如图5g所示，本实施例的逆变器处于第四子工作模态时，第二开关管QL2、第一支路的第二导通路径和第四支路的第二导通路径导通，第一开关管QL1、第三开关管QL3、第四开关管QL4、第二支路和第三支路关断。此时，第一电容单元C1的第二端(即第一电容单元C1和第二电容单元C2的公共端)处于放电状态。
以第一支路、第二支路、第三支路和第四支路均为图2所示的结构为例，电流依次流经：开关管QH7→开关管QH8的反向并联二极管→第二电感L2→交流电网ug→第一电感L1→开关管QH2→开关管QH1的反向并联二极管→第二开关管QL2→第二电容单元C2。开关管QH1和开关管QH8的导通状态不受限定，也就是说，开关管QH1可以导通，也可以关断，开关管QH8可以导通，也可以关断。
可见，在第四子工作模态时，第三支路上两个反向串联的开关管能够防止电流从第三支路的第二端流向第三支路的第一端。
当逆变器处于第三子工作模态或者第四子工作模态时，第一电容单元C1和第二电容单元C2的公共端与第三电容单元C3和第四电容单元C4的公共端之间的连接电路中均有电流流过。
可以看出，在上述两个子工作模态中，逆变器均输出负1电平，但是有所不同的是，在第三子工作模态时，第一电容单元C1的第二端处于充电状态，在第四子工作模态时，第一电容单元C1的第二端处于放电状态。
如图5h所示，本实施例的逆变器处于第六工作模态时，所述逆变器输出负0电平。此时，第三支路的第一导通路径和第四支路的第二导通路径导通，第一开关管QL1、第二开关管QL2、第三开关管QL3、第四开关管QL4、第一支路和第二支路关断。
以第一支路、第二支路、第三支路和第四支路均为图2所示的结构为例，电流依次流经：第二电感L2→交流电网→第一电感L1→开关管QH5→开关管QH6的反向并联二极管→开关管QH7→开关管QH8的反向并联二极管。开关管QH6和开关管QH8的导通状态不受限定，也就是说，开关管QH6可以导通，也可以关断，开关管QH8可以导通，也可以关断。
当逆变器处于第六工作模态时，第三支路和第四支路的公共端与第三电容单元C3和第四电容单元C4的公共端之间的连接电路中也有少量电流流过。若第三电容单元C3和第四电容单元C4容值相近，第一电容单元C1和第二电容单元C2的容值相近，并且第一电感L1和第二电感L2的电感值相近时，该电流较小。
根据上述六种有功工作模态的工作情况可知，图2所示的逆变器在第一或者第二工作模态时，第一支路第一端的电压高于第二端的电压，因此只能由开 关管QH1控制第一支路的导通，而此时第二支路上的第二端的电压高于第一端的电压，因此只能由开关管QH4控制第二支路的导通。
而所述逆变器在第四或者第五工作模态时，第一支路第二端的电压高于第一端的电压，因此只能由开关管QH2控制第一支路的导通，而此时第二支路上的第一端的电压高于第二端的电压，因此只能由开关管QH3控制第二支路的导通。
所述逆变器在第三工作模态时，由开关管QH6和第开关管QH8分别控制第三支路和第四支路的导通。
所述逆变器在第六工作模态时，由开关管QH5和开关管QH7分别控制第三支路和第四支路的导通。
在上述六种有功工作模态下，逆变器可以输出周期性的信号。逆变器输出的周期信号在一个周期内分为第一时段、第二时段、第三时段、第四时段、第五时段和第六时段。其中，在第一时段、第二时段和第三时段，逆变器输出正电压，在第四时段、第五时段和第六时段，逆变器输出负电压。
第一时段和第三时段，所述逆变器交替处于第二工作模态和第三工作模态，此时逆变器交替输出正1和正0电平。
在第二时段，逆变器交替处于第一工作模态和第二工作模态，此时逆变器交替输出正1和正2电平。
在第四时段和第六时段，逆变器交替处于第五工作模态和第六工作模态；此时逆变器交替输出负1和负0电平。
在第五时段，逆变器交替处于第四工作模态和第五工作模态，此时逆变器交替输出负1和负2电平。
需要说明的是，逆变器处于第二工作模态时，可以是处于第一子工作模态，也可以是处于第二子工作模态，而逆变器处于第五工作模态时，可以是处于第三子工作模态，也可以是处于第四子工作模态。由于逆变器处于第一子工作模态和第三子工作模态时，第一电容单元C1的第二端处于充电状态，而逆变器处 于第二子工作模态和第四子工作模态时，第一电容单元C1的第二端处于放电状态。因此，一种较优的方式是，通过对第二工作模态和第五工作模态的分配方式，使得在一个周期内，第一电容单元C1的第二端(即直流母线中点)处于充电状态和放电状态的时间相等或者相差在一预设范围内，从而使得直流母线中点的电压尽量平衡。下面说明三种保证直流母线中点的电压尽量平衡的分配方式。
第一种分配方式是，在第一时段、第二时段和第三时段，第一电容单元的第二端的充放电状态相同，可以都为充电状态，也可以都为放电状态。
在第四时段、第五时段和第六时段时，第一电容单元的第二端的充放电状态相同，并且与第一时段、第二时段和第三时段时第一电容单元的第二端的充放电状态相反，因此，若在第一时段、第二时段和第三时段时，第一电容单元的第二端为充电状态，则在第四时段、第五时段和第六时段时，第一电容单元的第二端为放电状态。若在第一时段、第二时段和第三时段时，第一电容单元的第二端为放电状态，则在第四时段、第五时段和第六时段时，第一电容单元的第二端为充电状态。
这里需要说明的是，若第一时段(或第三时段)第一电容单元的第二端为充电状态，则说明第一时段(或第三时段)时，逆变器交替工作在第一子工作模态和第三工作模态，若第一时段(或第三时段)第一电容单元的第二端为放电状态，则说明第一时段(或第三时段)时，逆变器交替工作在第二子工作模态和第三工作模态；若第二时段第一电容单元的第二端为充电状态，则说明第二时段时，逆变器交替工作在第一子工作模态和第一工作模态，若第二时段第一电容单元的第二端为放电状态，则说明第二时段时，逆变器交替工作在第二子工作模态和第一工作模态。
若第四时段(或第六时段)第一电容单元的第二端为充电状态，则说明第四时段(或第六时段)时，逆变器交替工作在第三子工作模态和第六工作模态，若第四时段(或第六时段)第一电容单元的第二端为放电状态，则说明第四时段(或第六时段)时，逆变器交替工作在第四子工作模态和第六工作模态；若第五时段第一电容单元的第二端为充电状态，则说明第五时段时，逆变器交替工作在第三子工作模态和第四工作模态，若第五时段第一电容单元的第二端为放电状态，则说明第五时段时，逆变器交替工作在第四子工作模态和第四工作模态。
下面通过图6说明这种分配方式的模态切换控制方式，如图6所示，可以在第一时段T1和第三时段T3使得逆变器交替处于B模态和D模态，在第二时段T2使得逆变器交替处于A模态和D模态，在第四时段T4和第六时段T6使得逆变器交替处于C模态和D模态，在第五时段T5使得逆变器交替处于A模态和C模态。需要说明的是，图6为对逆变器的模态切换控制图，因此，在图6中将逆变器输出的负电平信号翻转为正电平信号。
这里，A模态包括输出正2的第一工作模态或者输出负2电平的第四工作模态，B模态包括输出正0电平的第三工作模态或者输出负0电平的第六工作模态。C模态包括输出正1电平并且直流母线中点的电压为充电状态的第一子工作模态，或者输出负1电平并且直流母线中点的电压为充电状态的第三子工作模态。D模态包括输出正1电平并且直流母线中点的电压为放电状态的第二子工作模态，或者输出负1电平并且直流母线中点的电压为放电状态的第四子工作模态。
可见，在图6中的第一时段T1、第二时段T2和第三时段T3中，也就是 一个周期信号的前半周期中，直流母线中点的电压处于放电状态，而在第四时段T4、第五时段T5和第六时段T6中，也就是一个周期信号的后半周期中，直流母线中点的电压处于充电状态。由于一般情况下，第一时段、第三时段、第四时段和第六时段的时间均相等，而第二时段和第五时段的时间相等，因此这种分配方式中，直流母线中点的电压的充电和放电时间相等，保证了直流母线中点的电压平衡。
第二种分配方式是，在第一时段、第二时段的后半段、第五时段的前半段和第六时段，第一电容单元的第二端的充放电状态相同，可以都为充电状态，也可以都为放电状态。
在第二时段的前半段、第三时段、第四时段和第五时段的后半段，第一电容单元的第二端的充放电状态相同，并且与第一时段、第二时段的后半段、第五时段的前半段和第六时段时第一电容单元的第二端的充放电状态相反。因此，若在第一时段、第二时段的后半段、第五时段的前半段和第六时段时，第一电容单元的第二端为充电状态，则在第二时段的前半段、第三时段、第四时段和第五时段的后半段时，第一电容单元的第二端为放电状态。若在第一时段、第二时段的后半段、第五时段的前半段和第六时段时，第一电容单元的第二端为放电状态，则在第二时段的前半段、第三时段、第四时段和第五时段的后半段时，第一电容单元的第二端为充电状态。
下面通过图7说明这种分配方式的模态切换控制方式，如图7所示，可以在第一时段T1和第六时段T6使得逆变器交替处于B模态和D模态，在第二时段T2的后半时段和第五时段T5的前半时段使得逆变器交替处于A模态和D模态。在第三时段T3和第四时段T4使得逆变器交替处于B模态和C模态，在 第二时段T2的前半时段和第五时段T5的后半时段使得逆变器交替处于A模态和C模态。需要说明的是，图7为对逆变器的模态切换控制图，因此，在图7中将逆变器输出的负电平信号翻转为正电平信号。
可见，在图7中的第一时段T1、第二时段T2的后半时段、第五时段T5的前半时段和第六时段T6，直流母线中点的电压处于放电状态，在第三时段T3和第四时段T4、第二时段T2的前半时段和第五时段T5的后半时段，直流母线中点的电压处于充电状态，因此这种分配方式中，直流母线中点的电压的充电和放电时间相等，保证了直流母线中点的电压平衡。
第三种分配方式是，在第一时段、第二时段的后半段、第四时段和第五时段的后半段，第一电容单元的第二端的充放电状态相同，可以都为充电状态，也可以都为放电状态。
在第二时段的前半段、第三时段、第五时段的前半段和第六时段，第一电容单元的第二端的充放电状态相同，并且与第一时段、第二时段的后半段、第四时段和第五时段时第一电容单元的第二端的充放电状态相反。因此，若在第一时段、第二时段的后半段、第四时段和第五时段的后半段时，第一电容单元的第二端为充电状态，则在第二时段的前半段、第三时段、第五时段的前半段和第六时段时，第一电容单元的第二端为放电状态。若在第一时段、第二时段的后半段、第四时段和第五时段的后半段时，第一电容单元的第二端为放电状态，则在第二时段的前半段、第三时段、第五时段的前半段和第六时段时，第一电容单元的第二端为充电状态。
下面通过图8说明这种分配方式的模态切换控制方式，如图8所示，可以在第一时段T1和第四时段T4使得逆变器交替处于B模态和D模态，在第二时 段T2的后半时段和第五时段T5的后半时段使得逆变器交替处于A模态和D模态。在第三时段T3和第六时段T6使得逆变器交替处于B模态和C模态，在第二时段T2的前半时段和第五时段T5的前半时段使得逆变器交替处于A模态和C模态。需要说明的是，图8为对逆变器的模态切换控制图，因此，在图8中将逆变器输出的负电平信号翻转为正电平信号。
可见，在图8中的第一时段T1、第二时段T2的后半时段、第五时段T5的后半时段和第四时段T4，直流母线中点的电压处于放电状态，在第三时段T3和第六时段T6、第二时段T2的前半时段和第五时段T5的前半时段，直流母线中点的电压处于充电状态，因此这种分配方式中，直流母线中点的电压的充电和放电时间相等，保证了直流母线中点的电压平衡。
在上述三种分配方式中，第一种分配方式在一个周期内对直流母线中点充电、放电各一次，含有工频(一般为50hz)谐波，而第二种分配方式在一个周期内对直流母线中点充电3次，放电3次，含有工频倍数次谐波，第三种分配方式在一个周期内对直流母线中点充电、放电各4次。显然，第三种分配方式的充放电频率最高，因此母线电纹波最小。而第一种分配方式的充放电频率最低，母线电压纹波最大。
如图9a-9c所示，本实施例中的逆变器具有三种无功工作模态，分别为第七工作模态、第八工作模态和第九工作模态。
如图9a所示，本实施例的逆变器处于第七工作模态时，所述逆变器输出正1电平。此时，第一开关管QL1、第四开关管QL4、第一支路的第一导通路径和第二导通路径、以及第二支路的第一导通路径和第二导通路径导通，第二开关管QL2、第三开关管QL3、第三支路和第四支路关断。
此时，电流可以依次流经：第一开关管QL1→第一支路→第一电感L1→交 流电网ug→第二电感L2→第二支路→第四开关管QL4→第二电容单元C2→第一电容单元C1。电流还可以沿着上述路径反向流。
当逆变器处于第七工作模态时，第一电容单元C1和第二电容单元C2的公共端与第三电容单元C3和第四电容单元C4的公共端之间的连接电路中也有少量电流流过。若第三电容单元C3和第四电容单元C4容值相近，第一电容单元C1和第二电容单元C2的容值相近，并且第一电感L1和第二电感L2的电感值相近时，该电流较小。
如图9b所示，本实施例的逆变器处于第八工作模态时，所述逆变器输出0电平。此时，第三支路的第一导通路径和第二导通路径，以及第四支路的第一导通路径和第二导通路径导通，第一开关管QL1、第二开关管QL2、第三开关管QL3、第四开关管QL4、第一支路和第二支路关断。电流可以依次流经：第三支路→第一电感L1→交流电网ug→第二电感L2→第四支路。电流还可以沿着上述路径反向流。
当逆变器处于第八工作模态时，第一电容单元C1和第二电容单元C2的公共端与第三电容单元C3和第四电容单元C4的公共端之间的连接电路中也有少量电流流过。若第三电容单元C3和第四电容单元C4容值相近，第一电容单元C1和第二电容单元C2的容值相近，并且第一电感L1和第二电感L2的电感值相近时，该电流较小。
如图9c所示，本实施例的逆变器处于第九工作模态时，所述逆变器输出负1电平。此时，第二开关管QL2、第三开关管QL3、第一支路的第一导通路径和第二导通路径、以及所述第二支路的第一导通路径和第二导通路径导通，第一开关管QL1、第四开关管QL4、第三支路和第四支路关断。电流可以依次流经：第三开关管QL3→第二支路→第二电感L2→交流电网ug→第一电感L1→第一支路→第二开关管QL2→第二电容单元C2→第一电容单元C1。电流还可以沿着上述路径反向流。
当逆变器处于第九工作模态时，第一电容单元C1和第二电容单元C2的公共端与第三电容单元C3和第四电容单元C4的公共端之间的连接电路中也有少量电流流过。若第三电容单元C3和第四电容单元C4容值相近，第一电容单元C1和第二电容单元C2的容值相近，并且第一电感L1和第二电感L2的电感值相近时， 该电流较小。
本实施例中的逆变器中，还可以在逆变器的两个输出端和交流电网之间各串联一个电感进行滤波，从而实现更好的电网电流质量。如图10所示，第一电感L1的第二端还通过第三电感L3连接交流电网ug的正极，第二电感L2的第二端还通过第四电感L4连接交流电网ug的负极。其中，第三电感L3和第四电感L4的电感值相对于第一电感L1和第二电感L2来说，通常较小。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种五电平逆变器，其特征在于，所述逆变器包括：第一开关管、第二开关管、第三开关管、第四开关管、第一支路、第二支路、第三支路、第四支路、第一电容单元、第二电容单元、第三电容单元、第四电容单元、第一电感和第二电感；
    所述第一支路、所述第二支路、所述第三支路和所述第四支路中的各个支路均具有第一导通路径和第二导通路径，所述第一导通路径导通时，电流能够从该支路的第一端流向第二端，所述第二导通路径导通时，电流能够从所述该支路的第二端流向第一端，所述第一导通路径和所述第二导通路径均关断时，该支路关断，电流被禁止从该支路的任一端流向另一端；
    直流电源的正极连接所述第一开关管的第一端、所述第三开关管的第一端和所述第一电容单元的第一端；所述直流电源的负极连接所述第二开关管的第一端、所述第四开关管的第一端和所述第二电容单元的第二端；
    所述第一开关管的第二端连接所述第二开关管的第二端和所述第一支路的第一端；所述第三开关管的第二端连接所述第四开关管的第二端和所述第二支路的第一端；
    所述第一支路的第二端连接所述第一电感的第一端和所述第三支路的第一端；所述第二支路的第二端连接所述第二电感的第一端和所述第四支路的第一端；
    所述第一电感的第二端连接所述第三电容单元的第一端，所述第二电感的第二端连接所述第四电容单元的第二端；
    所述第三电容单元的第二端连接所述第四电容单元的第一端、所述第三支路的第二端、所述第四支路的第二端、所述第一电容单元的第二端和所述第二电容单元的第一端；
    所述第一电感的第二端和所述第二电感的第二端为所述逆变器的交流输出端。
  2. 根据权利要求1所述的逆变器，其特征在于，所述第一开关管导通时，电流从所述第一开关管的第一端流向第二端；所述第三开关管导通时，电流从 所述第三开关管的第一端流向第二端；
    所述第二开关管导通时，电流从所述第二开关管的第二端流向第一端；所述第四开关管导通时，电流从所述第四开关管的第二端流向第一端。
  3. 根据权利要求1所述的逆变器，其特征在于，所述第一支路、所述第二支路、所述第三支路和所述第四支路中的任一支路包括串联的并且导通方向相反的第五开关管和第六开关管；
    所述第五开关管的导通方向使得电流从该支路的第一端流向第二端，所述第六开关管的导通方向使得电流从该支路的第二端流向第一端；其中，所述第五开关管和所述第六开关管的反并联二极管为该支路的所述第一导通路径，所述第六开关管和所述第五开关管的反并联二极管为该支路的所述第二导通路径。
  4. 根据权利要求1所述的逆变器，其特征在于，所述第一支路、所述第二支路、所述第三支路和所述第四支路中的任一支路包括第七开关管、第八开关管、第一二极管和第二二极管；
    所述第一二极管和所述第七开关管串联后，与所述第二二极管和所述第八开关管的串联电路并联，所述第一二极管和所述第七开关管的导通方向均使得电流从该支路的第一端流向第二端，所述第二二极管和所述第八开关管的导通方向均使得电流从该支路的第二端流向第一端，所述第一二极管和所述第七开关管为该支路的所述第一导通路径，所述第二二极管和所述第八开关管为该支路的所述第二导通路径。
  5. 根据权利要求1所述的逆变器，其特征在于，所述第一支路、所述第二支路、所述第三支路和所述第四支路中的任一支路包括第三二极管、第四二极管、第五二极管、第六二极管和第九开关管；
    所述第三二极管的正极连接所述第四二极管的负极，作为该支路的第一端，所述第五二极管的正极连接所述第六二极管的负极，作为该支路的第二端；所述第三二极管的负极和所述第五二极管的负极连接所述第九开关管的第一端，所述第四二极管的正极和所述第六二极管的正极连接所述第九开关管的第二端，所述第九开关管的导通方向使得电流从所述第九开关管的第一端流向第二端；
    所述第三二极管、所述第九开关管和所述第六二极管为该支路的所述第一导通路径；所述第四二极管、所述第九开关管和所述第五二极管为该支路的所述第二导通路径。
  6. 根据权利要求1所述的逆变器，其特征在于，所述逆变器具有六种有功工作模态，分别为第一工作模态、第二工作模态、第三工作模态、第四工作模态、第五工作模态和第六工作模态；
    所述逆变器处于所述第一工作模态时，所述第一开关管、第四开关管、所述第一支路的第一导通路径和所述第二支路的第二导通路径导通，所述第二开关管、第三开关管、所述第三支路和所述第四支路关断；
    所述逆变器处于所述第二工作模态时，所述逆变器处于第一子工作模态或者第二子工作模态；所述逆变器处于所述第一子工作模态时，所述第一开关管、所述第一支路的第一导通路径和所述第四支路的第一导通路径导通，所述第二开关管、第三开关管、第四开关管、所述第二支路和所述第三支路关断，所述第一电容单元的第二端处于充电状态；所述逆变器处于所述第二子工作模态时，所述第四开关管、所述第二支路的第二导通路径和所述第三支路的第二导通路径导通，所述第一开关管、第二开关管、第三开关管、所述第一支路和所述第四支路关断，所述第一电容单元的第二端处于放电状态；
    所述逆变器处于所述第三工作模态时，所述第三支路的第二导通路径和所述第四支路的第一导通路径导通，所述第一开关管、第二开关管、第三开关管、第四开关管、所述第一支路和所述第二支路关断；
    所述逆变器处于所述第四工作模态时，所述第二开关管、第三开关管、所述第一支路的第二导通路径和所述第二支路的第一导通路径导通，所述第一开关管、第四开关管、所述第三支路和所述第四支路关断；
    所述逆变器处于所述第五工作模态时，所述逆变器处于第三子工作模态或者第四子工作模态；所述逆变器处于所述第三子工作模态时，所述第三开关管、所述第二支路的第一导通路径和所述第三支路的第一导通路径导通，所述第一开关管、第二开关管、第四开关管、所述第一支路和所述第四支路关断，所述第一电容单元的第二端处于充电状态；所述逆变器处于所述第四子工作模态时，所述第二开关管、所述第一支路的第二导通路径和所述第四支路的第二导 通路径导通，所述第一开关管、第三开关管、第四开关管、所述第二支路和所述第三支路关断，所述第一电容单元的第二端处于放电状态；
    所述逆变器处于所述第六工作模态时，所述第三支路的第一导通路径和所述第四支路的第二导通路径导通，所述第一开关管、第二开关管、第三开关管、第四开关管、所述第一支路和所述第二支路关断。
  7. 根据权利要求6所述的逆变器，其特征在于，所述逆变器输出的周期信号在一个周期内分为第一时段、第二时段、第三时段、第四时段、第五时段和第六时段；
    在所述第一时段和所述第三时段，所述逆变器交替处于第二工作模态和第三工作模态；
    在所述第二时段，所述逆变器交替处于第一工作模态和第二工作模态；
    在所述第四时段和所述第六时段，所述逆变器交替处于第五工作模态和第六工作模态；
    在所述第五时段，所述逆变器交替处于第四工作模态和第五工作模态。
  8. 根据权利要求7所述的逆变器，其特征在于，在所述第一时段、所述第二时段和所述第三时段，所述第一电容单元的第二端的充放电状态相同；在所述第四时段、所述第五时段和所述第六时段时，所述第一电容单元的第二端的充放电状态相同，并且与所述第一时段、所述第二时段和所述第三时段时所述第一电容单元的第二端的充放电状态相反；
    或者，
    在所述第一时段、所述第二时段的后半段、所述第四时段和所述第五时段的后半段，所述第一电容单元的第二端的充放电状态相同；在所述第二时段的 前半段、所述第三时段、所述第五时段的前半段和第六时段，所述第一电容单元的第二端的充放电状态相同，并且与所述第一时段、所述第二时段的后半段、所述第四时段和所述第五时段时所述第一电容单元的第二端的充放电状态相反；
    或者，
    在所述第一时段、所述第二时段的后半段、所述第五时段的前半段和所述第六时段，所述第一电容单元的第二端的充放电状态相同；在所述第二时段的前半段、所述第三时段、所述第四时段和所述第五时段的后半段，所述第一电容单元的第二端的充放电状态相同，并且与所述第一时段、所述第二时段的后半段、所述第五时段的前半段和所述第六时段时所述第一电容单元的第二端的充放电状态相反。
  9. 根据权利要求1至8任意一项所述的逆变器，其特征在于，所述逆变器具有三种无功工作模态，分别为第七工作模态、第八工作模态和第九工作模态：
    所述逆变器处于所述第七工作模态时，所述第一开关管、第四开关管、所述第一支路的第一和第二导通路径、以及所述第二支路的第一和第二导通路径导通，所述第二开关管、第三开关管、所述第三支路和所述第四支路关断；
    所述逆变器处于所述第八工作模态时，所述第三支路的第一和第二导通路径，以及所述第四支路的第一和第二导通路径导通，所述第一开关管、第二开关管、第三开关管、第四开关管、所述第一支路和所述第二支路关断；
    所述逆变器处于所述第九工作模态时，所述第二开关管、第三开关管、所述第一支路的第一和第二导通路径、以及所述第二支路的第一和第二导通路径导通，所述第一开关管、第四开关管、所述第三支路和所述第四支路关断。
  10. 根据权利要求1至8任意一项所述的逆变器，其特征在于，所述第一电感的第二端还通过第三电感连接交流电网的正极，所述第二电感的第二端还 通过第四电感连接所述交流电网的负极。
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