WO2015096398A1 - Poe供电防护系统及方法 - Google Patents

Poe供电防护系统及方法 Download PDF

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Publication number
WO2015096398A1
WO2015096398A1 PCT/CN2014/079180 CN2014079180W WO2015096398A1 WO 2015096398 A1 WO2015096398 A1 WO 2015096398A1 CN 2014079180 W CN2014079180 W CN 2014079180W WO 2015096398 A1 WO2015096398 A1 WO 2015096398A1
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Prior art keywords
module
pse
current
chip
protection
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PCT/CN2014/079180
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English (en)
French (fr)
Inventor
张佳洁
王昕�
唐余兵
杜永红
Original Assignee
中兴通讯股份有限公司
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Priority to US15/108,447 priority Critical patent/US20160323115A1/en
Publication of WO2015096398A1 publication Critical patent/WO2015096398A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/10—Current supply arrangements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/001—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection limiting speed of change of electric quantities, e.g. soft switching on or off

Definitions

  • the present invention relates to the field of computer technology, and in particular, to a power over Ethernet (Power Over Ethernet, Referred to as POE) power supply protection system and method.
  • a power over Ethernet Power Over Ethernet, Referred to as POE
  • POE is a standard specification for powering data while transmitting data using existing standard Ethernet transmission cables. It is compatible with existing Ethernet systems and users. Realize the injection of power into the transformer at the beginning of the Ethernet signal The common mode tap extracts the power of the power from the common mode tap at the end of the Ethernet signal. Which involves a series of tests, Identification, there are a number of voltage, current control, the corresponding originating controller is called power supply equipment (Power Supply Equipment (referred to as PSE), the terminating controller is called Powered Device (PD).
  • PSE Power Supply Equipment
  • PD Powered Device
  • the IEEE began to develop POE technology and set out to develop the first POE power supply standard 802.3af. 2003
  • the IEEE officially approved the 802.3af standard, which added a straight line through the network cable based on IEEE802.3.
  • the relevant standards for power supply are an extension of the existing Ethernet standard and the first international standard for power distribution. It specifies a 15.4W PSE output power, which clarifies the power detection and control issues in the remote system. Ethernet, cable, and wireless LAN access points through Ethernet cables from switches, switches, and hubs The way the equipment is powered is regulated.
  • the IEEE approved the 802.3at standard, which specifies a PSE output power of 25.5W.
  • POE electrodes are susceptible to external signal interference, while PSE and PD chips are limited by their own performance indicators. When the external interference reaches a certain level, the POE will not be able to supply power properly, and even the PSE and PD chips will be damaged. Therefore, gas discharge tubes, varistor, TVS tubes and the like are generally used to suppress and discharge common mode interference. Since the positive and negative power supply paths of the POE power supply are not completely symmetrical during the actual application, the common mode interference will be converted into Differential mode interference, while POE power supply has its own special characteristics, such as fixed power positive and negative switch control, and current The interference in the same direction is sensitive, which will cause the POE power supply to be interfered by external signals, thus improving the POE power supply. Reliability, therefore, there is an urgent need for a technical solution that enables POE to be reliably powered.
  • Embodiments of the present invention have been made in order to provide a POE power supply protection system and method that overcomes the above problems.
  • An embodiment of the present invention provides a POE power supply protection system, including at least one of the following modules: PSE near End protection module, PSE remote protection module, PD remote protection module, PD near-end protection module, wherein:
  • PSE near-end protection module set at the near end of the PSE chip, set to the power loop voltage at the near end of the PSE chip During the current mutation process, the pins of the PSE chip are protected;
  • the PSE remote protection module is disposed between the near end of the PSE chip and the PSE network port, and is configured to suppress the network port.
  • the interference of the network cable reduces the mutation of the PSE chip loop to the extent that the near end of the PSE can withstand;
  • the PD remote protection module is disposed between the near end of the PD chip and the PD network port, and is configured to suppress the network from the network port. Line interference, the PD chip loop mutation is reduced to the extent that the PD near the end can withstand;
  • the PD near-end protection module is disposed at the near end of the PD chip and is set to be at the near end of the PD chip. During the process of the mutation, the pins of the PD chip are protected.
  • the PSE near-end protection module specifically includes: an external voltage clamping module, a network port voltage clamping module, A spike current absorbing module, a reverse current suppression module, and a short circuit protection bleeder module, wherein:
  • An external voltage clamping module configured to clamp the external input power supply
  • the network port voltage clamping module is configured to clamp the voltage fluctuation from the direction of the network port
  • a spike current absorbing module configured to absorb surge current spikes
  • a reverse current suppression module configured to suppress current fluctuations in a direction opposite to a POE supply current
  • the short circuit protection bleeder module is set to bleed the port inrush current during the POE short circuit protection process.
  • the PSE remote protection module is disposed between the proximal end of the PSE chip and the transformer of the PSE end network port, specifically
  • the method includes: a first common mode differential mode bleeder module, a symmetrical current abrupt suppression module, a common mode differential mode voltage clamping module, A protective ground-to-line low impedance bleeder module, and an asymmetric current abrupt suppression module, wherein:
  • a first common mode differential mode bleeder module configured to bleed surge energy from the network port
  • the symmetrical current abrupt suppression module is configured to suppress a common mode current abrupt change of the positive and negative poles of the power line;
  • a common mode differential mode voltage clamping module configured to clamp the PSE chip proximal voltage to a specific range
  • the asymmetry current abrupt module is set to suppress a sudden change in the negative current of the PSE chip near-end power supply.
  • the PD remote protection module is disposed between the near end of the PD chip and the transformer of the PD end network port, and the specific package
  • the second common mode differential mode bleeder module, the reverse current suppression module, and the current mutation suppression module wherein:
  • a second common mode differential mode bleeder module configured to bleed a large amount of surge energy from the network port
  • a reverse current suppression module configured to suppress a current opposite to a direction of the POE current
  • the current mutation suppression module is configured to suppress a sudden change in the current side of the PD.
  • the PD near-end protection module specifically includes: a first voltage clamping module, and a second voltage clamping module, among them,
  • a first voltage clamping module configured to clamp a sudden change in voltage from a distal end of the PD chip
  • a second voltage clamping module configured to clamp voltage fluctuations from the load terminal.
  • the system further comprises:
  • the boost module is disposed between the external input power source and the proximal end of the PSE chip and is configured to increase the voltage of the path.
  • the embodiment of the invention further provides a POE power supply protection method, including: the PSE near-end protection module receives the slave PSE chip input power, in the process of the PSE chip near-end power loop voltage and current mutation, on the PSE chip Each pin is protected and the power is input to the PSE remote protection module;
  • the PSE remote protection module receives the input power, suppresses interference from the network cable of the network port, and connects the PSE chip circuit.
  • the mutation is reduced to the extent that the proximal end of the PSE can withstand, and the power is input to the PD remote protection module;
  • the PD remote protection module receives the input power, suppresses the interference from the network cable of the network port, and the PD chip loops. Reduce the range to the near end of the PD and input the power to the PD near-end protection module;
  • the PD near-end protection module receives the input power, during the sudden change of the power loop voltage and current of the PD chip.
  • the pins of the PD chip are protected and the power is supplied to the load.
  • the PSE near-end protection module is in the process of a sudden change of the power loop voltage and current of the PSE chip to the PSE
  • the protection of each pin of the chip includes:
  • the external input power supply is clamped by an external voltage clamping module
  • the short-circuit protection bleeder module bleeds the port surge current during the POE short-circuit protection process.
  • the PSE remote protection module suppresses interference from the network cable of the network port, and reduces the mutation of the PSE chip loop. To the extent that the near end of the PSE can withstand:
  • the common mode current mutation of the positive and negative poles of the power line is suppressed by the symmetrical current mutation suppression module;
  • the PSE chip proximal voltage is clamped to a specific range by a common mode differential mode voltage clamping module;
  • the asymmetry current mutation module will suppress the sudden change of the negative current of the PSE chip near-end power supply.
  • the PD remote protection module suppresses interference from the network cable of the network port, and reduces the mutation of the PD chip loop to The range that the PD can withstand at the near end includes:
  • the PD current side current mutation is suppressed by the current mutation suppression module.
  • the PD near-end protection module is in the process of a sudden change of the power loop voltage and current of the PD chip to the PD
  • the protection of each pin of the chip includes:
  • the voltage fluctuation from the load terminal is clamped by the second voltage clamping module.
  • the above method further comprises:
  • a boost module disposed between the external input power source and the near end of the PSE chip boosts the external input power source, The boosted power is transferred to the PSE chip.
  • the prior art is solved by step-by-step protection of the reliability design mode of the chip distal end and the chip proximal end.
  • the problem of low reliability of POE power transmission transmission can effectively suppress sudden changes in power circuit voltage and current, and ensure chip off.
  • the key pins meet the chip design requirements to ensure that the chip is in normal operation.
  • FIG. 1 is a schematic structural diagram of a POE power supply protection system according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a POE power supply protection system according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of PSE proximal protection according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram showing an example of a PSE near-end protection part module according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of PSE remote protection according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of an example of a PSE remote protection part module according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of PD remote protection according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of PD near-end protection according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of boosting of an external input power supply according to an embodiment of the present invention.
  • FIG. 10 is a flowchart of a POE power supply protection method according to an embodiment of the present invention.
  • the present invention provides a POE.
  • the power supply protection system and method can improve the reliability of the POE power supply while ensuring the normal transmission of the Ethernet service.
  • Sexuality including: PSE chip remote protection, suppression of PSE chip remote power loop voltage and current mutation, will suddenly Reduced to the end of the PSE can withstand; PSE chip near-end protection, inhibit PSE chip near-end power loop The sudden change of the voltage current ensures that the key pins of the PSE chip are in the process of mutation, and all the indicators meet the chip design requirements; Remote protection of the PD chip, suppressing sudden changes in the voltage and current of the power loop of the PD, reducing the mutation to the near end of the PD Withstand range; PD chip near-end protection, inhibiting the sudden change of voltage and current of the power circuit near the PD chip, ensuring the PD core During the mutation process, each key pin meets the chip design requirements.
  • FIG. 1 is an embodiment of the present invention.
  • Schematic diagram of a POE power supply protection system as shown in FIG. 1, a POE power supply protection system according to an embodiment of the present invention
  • the system includes at least one of the following modules: PSE proximal protection module 10, PSE remote protection module 12, PD far End protection module 14, PD near-end protection module 16, the following is a detailed description of each module of the embodiment of the present invention Bright.
  • the PSE near-end protection module 10 is disposed at the proximal end of the PSE chip and is disposed at the proximal power loop of the PSE chip. During the sudden change of voltage and current, the pins of the PSE chip are protected;
  • the PSE near-end protection module 10 specifically includes: an external voltage clamping module, a network port voltage clamping module, and a peak electric A flow absorbing module, a reverse current suppression module, and a short circuit protection bleeder module, wherein:
  • An external voltage clamping module configured to clamp the external input power supply
  • the network port voltage clamping module is configured to clamp the voltage fluctuation from the direction of the network port
  • a spike current absorbing module configured to absorb surge current spikes
  • a reverse current suppression module configured to suppress current fluctuations in a direction opposite to a POE supply current
  • the short circuit protection bleeder module is set to bleed the port inrush current during the POE short circuit protection process.
  • the PSE remote protection module 12 is disposed between the proximal end of the PSE chip and the PSE network port, and is configured to suppress the The interference of the network port network cable reduces the PSE chip loop mutation to the range that the PSE near end can bear;
  • the PSE remote protection module 12 is disposed between the PSE chip proximal end and the PSE end network port transformer, and specifically includes: First common mode differential mode bleeder module, symmetrical current abrupt suppression module, common mode differential mode voltage clamping module, protection ground A line low impedance bleeder module, and an asymmetric current abrupt suppression module, wherein:
  • a first common mode differential mode bleeder module configured to bleed surge energy from the network port
  • the symmetrical current abrupt suppression module is configured to suppress a common mode current abrupt change of the positive and negative poles of the power line;
  • a common mode differential mode voltage clamping module configured to clamp the PSE chip proximal voltage to a specific range
  • the asymmetry current abrupt module is set to suppress a sudden change in the negative current of the PSE chip near-end power supply.
  • the PD remote protection module 14 is disposed between the near end of the PD chip and the PD network port, and is configured to suppress the network port.
  • the interference of the network cable reduces the PD chip loop mutation to the range that the PD near the end can bear;
  • the PD remote protection module 14 is disposed between the PD chip proximal end and the PD end network port transformer, and specifically includes: A common mode differential mode bleeder module, a reverse current suppression module, and a current mutation suppression module, wherein:
  • a second common mode differential mode bleeder module configured to bleed a large amount of surge energy from the network port
  • a reverse current suppression module configured to suppress a current opposite to a direction of the POE current
  • the current mutation suppression module is configured to suppress a sudden change in the current side of the PD.
  • the PD near-end protection module 16 is disposed at the near end of the PD chip and is set to the power loop voltage at the near end of the PD chip. During the current abrupt change, each pin of the PD chip is protected.
  • the PD near-end protection module 16 specifically includes: a first voltage clamping module, and a second voltage clamping module, in,
  • a first voltage clamping module configured to clamp a sudden change in voltage from a distal end of the PD chip
  • a second voltage clamping module configured to clamp voltage fluctuations from the load terminal.
  • the boosting module may be further configured to be externally connected. Between the power supply and the near end of the PSE chip, set to increase the voltage of the path.
  • FIG. 2 is a schematic diagram showing the structure of a POE power supply protection system according to an embodiment of the present invention.
  • external input Enter the power input to the PSE near-end protection and input it to the PSE remote protection through the PSE near-end protection.
  • the power supply reaches the remote protection of the PD and is input to the near end of the PD through the remote end of the PD, and finally provided to the load.
  • PSE near-end protection module 10 PSE near-end protection
  • PSE remote protection module 12 PSE remote protection
  • PD remote protection PD remote protection
  • PD proximal protection PD proximal protection module 16
  • the PSE chip since the PSE chip is responsible for detecting whether the PD is legal, the legal PD is correctly classified, and is classified into Power PD, monitoring PSE supply voltage and current, PSE overcurrent short circuit and other key functions, and key
  • the pin itself has limited reliability and is an object that needs to be protected.
  • Circuit design application of PSE near-end protection module 10 At the near end of the PSE chip, the protection comes from a sudden change in the voltage and current introduced by the input power supply or the PSE end network port, ie Ensure that all indicators meet the chip design requirements during the sudden change of the power loop voltage and current in the PSE chip.
  • the PSE chip is in normal working condition. This part of the circuit ensures the key pins of the PSE chip.
  • the PSE near-end consists of a PSE chip and a PSE near-end protection module 10 (PSE chip key pin protection).
  • the power is input to the PSE chip, and after the PSE chip completes the detection and classification of the legal PD, the PSE chip outputs the power. Go to the PSE remote circuit.
  • PSE near-end protection module 10 PSE chip key pin protection
  • the key pin of the chip is in the process of sudden change of voltage and current of the power loop. All the indicators meet the chip design requirements and ensure the PSE. The chip works stably.
  • a PSE near-end protection module 10 specific details include: voltage clamping module 1, voltage clamping module 2, peak current absorbing module, reverse current Suppression module, short circuit protection bleeder module.
  • the voltage clamping module 1 is set to clamp the external input power supply to ensure The external input power is within the allowable range.
  • the voltage clamping module 2 is arranged to clamp voltage fluctuations from the direction of the network port.
  • the spike current sink module is configured to absorb surge current spikes to prevent PSE chips from malfunctioning during a surge POE power supply.
  • the reverse current suppression module is configured to suppress current fluctuations that are opposite to the direction of the POE supply current.
  • Short circuit The protection bleeder module ensures that the port surge current is effectively vented during the POE short circuit protection.
  • FIG. 4 is a schematic diagram of an example of a PSE near-end protection part module according to an embodiment of the present invention, as shown in FIG.
  • An example of a peak current absorbing module and a short circuit protection bleeder module wherein the TVS in FIG. 6 is transient suppression two Abbreviation for Transient Voltage Suppressor, MOS is the abbreviation of MOSFET mosfetmos, AGND Abbreviation for Analog Ground; OUT is the abbreviation of the output; GATE is the abbreviation of the gate G in the FET; SENSE is the abbreviation of the measuring circuit; VEE is the abbreviation of the negative power supply.
  • MOS is the abbreviation of MOSFET mosfetmos, AGND Abbreviation for Analog Ground
  • OUT is the abbreviation of the output
  • GATE is the abbreviation of the gate G in the FET
  • SENSE is the abbreviation of the measuring circuit
  • VEE
  • the circuit design of the PSE remote protection module 12 is applied to the PSE near-end and Between the transformers, it is set to suppress the interference from the network cable of the network port, and ensure that the loop mutation is reduced to the near end of the PSE. The scope of acceptance.
  • the PSE remote end is composed of PSE remote protection module 12 (PSE output network port protection) and PSE end network port transformer group. to make. Power from the PSE chip input to the PSE remote protection module 12 (PSE output network port protection), after PSE The remote protection module 12 outputs to the network port transformer.
  • PSE remote protection module 12 PSE output network port protection
  • PSE output network port protection can Effectively suppress the sudden change of the power loop voltage and current introduced by the network port cable, and ensure that the abrupt voltage and current are reduced to PSE. The range that the proximal end can withstand.
  • FIG. 5 is a schematic diagram of PSE remote protection according to an embodiment of the present invention, as shown in FIG. 5, a PSE remote protection module 12 specifically includes: common mode, differential mode bleeder module, symmetrical current abrupt suppression module, common mode, differential mode voltage clamp Module, protective ground-to-line low-impedance bleeder module, asymmetric current mutation suppression module.
  • Common mode differential mode The release module is set to bleed most of the surge energy from the network port.
  • Symmetry current mutation suppression module is set to suppress The common mode current of the positive and negative poles of the power line is abrupt.
  • Common mode, differential mode voltage clamps clamp the PSE near-end voltage to specific range.
  • the protective ground-to-line low-impedance bleeder module is set to ensure the line-to-ground surge, and the inrush current passes through the shortest path. Flow back, does not interfere with the PSE chip power main loop. Due to the asymmetry of the POE power supply, the POE is powered The current direction is sensitive to interference, and the asymmetric current abrupt module will suppress the sudden change of the negative current of the PSE near-end power supply.
  • FIG. 6 is a schematic diagram of an example of a PSE remote protection part module according to an embodiment of the present invention, as shown in FIG. Including asymmetric current mutation suppression module, protective ground-to-line low-impedance bleeder module, common mode, differential mode bleeder module Example.
  • the PD remote protection module 14 should be set to the PD near-end and Between the transformers, it is set to suppress the interference from the network cable network, and ensure that the loop mutation is reduced to the near end of the PD. The scope of acceptance.
  • the PD remote end is composed of a PD remote protection module 14 (PD output network port protection) and a PD end network port transformer.
  • the power from the network port network cable is input to the remote end of the PD, and passes through the PD remote protection module 14 (PD output network port protection). Output to the near end of the PD.
  • the PD remote protection module 14 (PD output network port protection) can effectively suppress the network port network cable
  • the sudden change in the voltage loop current of the incoming power circuit ensures that the abrupt voltage and current are reduced to the extent that the near-end of the PD can withstand.
  • FIG. 7 is a schematic diagram of the remote protection of the PD according to the embodiment of the present invention.
  • the PD remote protection module 14 is shown in FIG. Specifically, it includes: common mode, differential mode bleeder module, reverse current suppression module, and current mutation suppression module. Common mode, poor The mode bleeder module is configured to bleed a large amount of surge energy from the network port. Reverse current suppression module, set to suppress and POE Current with opposite current directions. The current mutation suppression module prevents sudden changes in the current on the PD current side, causing the PD to malfunction. Power off the POE.
  • the PD chip since the PD chip assumes that it is legal, it is normally handshake with the PSE, and monitors the PD receiving power. Important functions such as voltage current, PD overcurrent short circuit and timely protection, and the critical pins themselves have limited reliability and need to be focused. Protection.
  • the circuit design of the PD near-end protection module 16 is applied to the near end of the PD chip, and the protection comes from the PD network cable. A sudden change in the voltage and current or a sudden change in the load at the rear stage, that is, the voltage and current of the power loop in the near end of the PD chip are suddenly changed. In the process, all indicators meet the chip design requirements to ensure that the PD chip is in normal working condition.
  • the PD chip and the PD near-end protection module 16 are composed. Remote power supply from PD At the near end of the PD, the PD chip supplies power to the load.
  • PD near-end protection module 16 (PD chip key Pin protection) ensures that the key pins of the PD chip are full during the sudden change of the power loop voltage and current. Foot chip design requirements ensure that the PD chip works stably.
  • FIG. 8 is a schematic diagram of the PD near-end protection according to an embodiment of the present invention. As shown in FIG. 8, a specific voltage clamping module is provided. Voltage clamping module 2. The voltage clamping module 1 is configured to clamp a sudden change in voltage from the far end of the PD. Voltage clamping module 2 Set to clamp voltage fluctuations from the load side.
  • the impedance of the device such as the network cable, the transformer, and the crystal head is constant, in the case where the total power of the POE transmission is determined, Improve the transmission voltage and reduce the transmission current, which can effectively reduce the loss on the transmission path, thus providing efficient POE Transmission scheme.
  • This part of the circuit design is applied between the external input power supply and the PSE near-end, and the external power supply is boosted. After the module, the boosted power is input to the PSE near-end.
  • the boost module boosts the external input supply voltage and outputs the boosted power supply to the PSE near-end. Input power The increase in pressure can reduce the loss on the POE transmission path and effectively improve the transmission efficiency of the POE.
  • the technical solution of the embodiment of the present invention provides a reliable power supply method based on POE, PSE near-end protection, PSE remote protection, PD remote protection, and PD near-end protection ensure that Ethernet services are normal.
  • an efficient and reliable POE power supply scheme is realized.
  • External power input to the PSE chip through positive Often hierarchical detection process, the PSE chip outputs power to the network port protection circuit, while the PSE chip is protected by key pins. It is used to ensure that the key pins of the PSE chip are in normal working condition and are not affected by the sudden change of power loop power.
  • the PD is powered by the network cable.
  • the remote protection of the PSE is used to suppress the sudden change of the power supply introduced by the network cable. Reduce loop mutations to the extent that the PSE can withstand the near end.
  • the power from the network port network cable is input to the remote end of the PD.
  • the PD near-end protection circuit is input to the PD chip, and the PD chip supplies the input power to the load.
  • the POE power supply performance of the embodiment of the present invention satisfies the International Electrotechnical Commission (International Electro Technical Commission (referred to as IEC), International Radio Interference Special Committee (International Special Committee on Radio Interference (CISPR) reliability indicator.
  • IEC Reliability indicators include: electrostatic immunity test contact ⁇ 6kV, air ⁇ 8kV, CLASS B (IEC61000-4-2); Radiated immunity test 80-2700MHz, 80% AM, 10V/m CLASS B (IEC61000-4-3); Conducted anti-interference test Test 150k-80MHz, 80% AM, 3V, CLASS B (IEC61000-4-6); pulse line immunity test ⁇ 2KV, 5kHz, CLASS B (IEC61000-4-4); Surge immunity test 10/700us, line ground ⁇ 6kV/40 ⁇ , CLASS B (IEC61000-4-5), inrush current test 2KA, 8/20us, CLASS B (IEC61312-3).
  • the CISPR Reliability indicators include: Conducted Dist
  • the technical solution of the embodiment of the present invention includes all cables supporting the POE function. Not limited to the cable category.
  • the technical solution of the embodiment of the present invention includes PSE chip key pin protection, PD Chip key pin protection, PSE output network port protection, PD input network port protection, but not limited to protection scheme Crop only select one or more of the protected application scenarios.
  • the technical solution of the embodiment of the present invention passes the IEC, CISPR reliability indicators, but not limited to meeting some of the indicators mentioned in the text or the same level and below Use the scene.
  • the technical solution of the embodiment of the present invention includes the use of the network port transformer, but is not limited to not being used.
  • the application scenario of the POE function is implemented in other ways.
  • FIG. 10 is a flowchart of a POE power supply protection method according to an embodiment of the present invention, as shown in FIG.
  • the POE power supply protection method according to an embodiment of the present invention includes the following processing:
  • Step 1001 the PSE near-end protection module 10 receives the power input from the PSE chip, at the proximal end of the PSE chip. During the sudden change of the power loop voltage and current, the pins of the PSE chip are protected and the power is input to the PSE.
  • the PSE near-end protection module 10 is in the process of sudden change of the power loop voltage and current of the PSE chip.
  • the protection of each pin of the PSE chip includes:
  • the external input power supply is clamped by an external voltage clamping module
  • the short-circuit protection bleeder module bleeds the port surge current during the POE short-circuit protection process.
  • Step 1002 The PSE remote protection module 12 receives the input power and suppresses interference from the network cable of the network port. Reduce the PSE chip loop mutation to the range that the PSE near-end can withstand, and input the power to the PD remote control Protection module 14;
  • the PSE remote protection module 12 suppresses interference from the network cable of the network port, and reduces the mutation of the PSE chip loop to the PSE.
  • the range that can be tolerated by the near end includes:
  • the common mode current mutation of the positive and negative poles of the power line is suppressed by the symmetrical current mutation suppression module;
  • the PSE chip proximal voltage is clamped to a specific range by a common mode differential mode voltage clamping module;
  • the asymmetry current mutation module will suppress the sudden change of the negative current of the PSE chip near-end power supply.
  • Step 1003 the PD remote protection module 14 receives the input power, and suppresses interference from the network cable of the network port.
  • the PD chip loop is reduced to the range that can be withheld at the near end of the PD, and the power is input to the PD near-end protection module. 16;
  • the PD remote protection module 14 suppresses interference from the network port of the network port, and reduces the PD chip loop mutation to PD.
  • the range that the near end can withstand specifically includes:
  • the PD current side current mutation is suppressed by the current mutation suppression module.
  • Step 1004 the PD near-end protection module 16 receives the input power, and the power loop voltage at the near end of the PD chip. During the current abrupt change, each pin of the PD chip is protected and the power is supplied to the load.
  • the PD near-end protection module 16 is in the process of a sudden change of the power loop voltage and current of the PD chip, and the PD chip
  • the protection of each pin includes:
  • the voltage fluctuation from the load terminal is clamped by the second voltage clamping module.
  • the boost mode is set between the external input power source and the proximal end of the PSE chip.
  • the block boosts the external input supply and transfers the boosted supply to the PSE chip.
  • the technical solution of the embodiment of the present invention provides a reliable power supply method based on POE, PSE near-end protection, PSE remote protection, PD remote protection, and PD near-end protection ensure that Ethernet services are normal.
  • an efficient and reliable POE power supply scheme is realized.
  • External power input to the PSE chip through positive Often hierarchical detection process, the PSE chip outputs power to the network port protection circuit, while the PSE chip is protected by key pins. It is used to ensure that the key pins of the PSE chip are in normal working condition and are not affected by the sudden change of power loop power.
  • the PD is powered by the network cable.
  • the remote protection of the PSE is used to suppress the sudden change of the power supply introduced by the network cable. Reduce loop mutations to the extent that the PSE can withstand the near end.
  • the power from the network port network cable is input to the remote end of the PD.
  • the PD near-end protection circuit is input to the PD chip, and the PD chip supplies the input power to the load.
  • the prior art is solved by step-by-step protection of the reliability design mode of the chip distal end and the chip proximal end.
  • the problem of low reliability of POE power transmission transmission can effectively suppress sudden changes in power circuit voltage and current, and ensure chip off.
  • the key pins meet the chip design requirements to ensure that the chip is in normal operation.
  • the above technical solution provided by the present invention can be applied to the POE power supply protection process by using the remote end of the chip,
  • the reliability design mode of the near-end of the chip is step-by-step protection, which solves the problem that the POE power supply transmission reliability in the prior art is not
  • the high problem can effectively suppress the sudden change of the voltage and current of the power loop, ensuring that the key pins of the chip meet the chip design. Seek to ensure that the chip is working properly.

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Abstract

一种以太网供电（POE）的供电防护系统及方法。该系统包括以下模块中的至少之一：供电设备（PSE）近端防护模块（10），设置于PSE芯片近端，用于在PSE芯片近端功率回路电压电流突变过程中，对PSE芯片的各引脚进行防护；PSE远端防护模块（12），设置于PSE芯片近端与PSE网口之间，用于抑制来自网口网线的干扰，将PSE芯片回路突变减低到PSE近端所能承受的范围内；受电（PD）远端防护模块（14），设置于PD芯片近端与PD网口之间，用于抑制来自网口网线的干扰，将PD芯片回路减低到PD近端所能承受的范围；PD近端防护模块（16），设置于PD芯片近端，在PD芯片近端功率回路电压电流突变过程中，对PD芯片的各引脚进行防护。

Description

POE供电防护系统及方法 技术领域
本发明涉及计算机技术领域，特别是涉及一种以太网供电(Power Over Ethernet， 简称为POE)供电防护系统及方法。
背景技术
POE是利用现存标准以太网传输电缆传送数据的同时进行供电的标准规范，它保 持了与现存以太网系统和用户的兼容性。实现在以太网信号发端将电源注入变压器的 共模抽头，在以太网信号收端从共模抽头中提取出电源能量。其中涉及一系列检测、 识别，存在若干电压、电流的控制，相应发端控制器称为供电设备(Power Supply  Equipment，简称为PSE)，收端控制器称为受电设备(Powered Device，简称为PD)。
1999年IEEE开始研制POE技术，并着手制定首个POE供电标准802.3af。2003 年6月，IEEE正式批准了802.3af标准，它在IEEE802.3的基础上增加了通过网线直 接供电的相关标准，是现有以太网标准的扩展，也是第一个关于电源分配的国际标准。 它规定了15.4W的PSE输出功率，明确了远程系统中的电力检测和控制事项，并对路 由器、交换机和集线器通过以太网电缆向IP电话、安全系统以及无线LAN接入点等 设备供电的方式进行了规定。为了满足日益增大的终端功率需求，2005年7月在兼 容802.3af的基础上IEEE批准了802.3at标准，它规定了25.5W的PSE输出功率。
POE供电极易受到外界信号干扰，而PSE、PD芯片受到本身性能指标限制，当 外界干扰达到一定程度时，将造成POE无法正常供电，甚至造成PSE、PD芯片损坏。 因此目前一般采用气体放电管、压敏电阻、TVS管等器件对共模干扰进行抑制和泄放。 由于实际应用过程中POE供电正负电源路径的并不是完全对称，共模干扰将会转化为 差模干扰，同时POE供电具有其自身的特殊性，如固定电源正负极开关控制、与电流 同方向干扰敏感，都会使POE供电受到外界信号干扰，从而提高了POE供电的不可 靠性，因此，目前急需一种能够使POE进行可靠供电的技术方案。
发明内容
针对现有技术中POE供电容易受到外界信号干扰而导致的供电不可靠的问题，提 出了本发明实施例以便提供一种克服上述问题的POE供电防护系统及方法。
本发明实施例提供一种POE供电防护系统，包括以下模块中的至少之一：PSE近 端防护模块、PSE远端防护模块、PD远端防护模块、PD近端防护模块，其中：
PSE近端防护模块，设置于PSE芯片近端，设置为在PSE芯片近端功率回路电压 电流突变过程中，对PSE芯片的各引脚进行防护；
PSE远端防护模块，设置于PSE芯片近端与PSE网口之间，设置为抑制来自网口 网线的干扰，将PSE芯片回路突变减低到PSE近端所能承受的范围内；
PD远端防护模块，设置于PD芯片近端与PD网口之间，设置为抑制来自网口网 线的干扰，将PD芯片回路突变减低到PD近端所能承受的范围；
PD近端防护模块，设置于PD芯片近端，设置为在PD芯片近端功率回路电压电 流突变过程中，对PD芯片的各引脚进行防护。
优选地，PSE近端防护模块具体包括：外部电压钳位模块、网口电压钳位模块、 尖峰电流吸收模块、反向电流抑制模块、以及短路保护泄放模块，其中：
外部电压钳位模块，设置为对外部输入电源进行钳位；
网口电压钳位模块，设置为对来自网口方向的电压波动进行钳位；
尖峰电流吸收模块，设置为吸收浪涌电流尖峰；
反向电流抑制模块，设置为抑制与POE供电电流方向相反的电流波动；
短路保护泄放模块，设置为在POE短路保护过程中对端口冲击电流进行泄放。
优选地，PSE远端防护模块设置于PSE芯片近端与PSE端网口变压器之间，具体 包括：第一共模差模泄放模块、对称性电流突变抑制模块、共模差模电压钳位模块、 保护地对线低阻抗泄放模块、以及非对称性电流突变抑制模块，其中：
第一共模差模泄放模块，设置为泄放来自网口的浪涌能量；
对称性电流突变抑制模块，设置为抑制电源线正极、负极的共模电流突变；
共模差模电压钳位模块，设置为将PSE芯片近端电压钳制在特定范围；
保护地对线低阻抗泄放模块，设置为在线对地浪涌时，使浪涌电流通过最短路径 流回；
非对称性电流突变模块，设置为将抑制PSE芯片近端电源负极电流突变。
优选地，PD远端防护模块设置于PD芯片近端与PD端网口变压器之间，具体包 括：第二共模差模泄放模块、反向电流抑制模块、以及电流突变抑制模块，其中：
第二共模差模泄放模块，设置为泄放来自网口大量浪涌能量；
反向电流抑制模块，设置为抑制与POE电流方向相反的电流；
电流突变抑制模块，设置为抑制PD电流侧电流突变。
优选地，PD近端防护模块具体包括：第一电压钳位模块、以及第二电压钳位模块， 其中，
第一电压钳位模块，设置为钳位来自PD芯片远端的电压突变；
第二电压钳位模块，设置为钳位来自负载端的电压波动。
优选地，系统进一步包括：
升压模块，设置于外部输入电源与PSE芯片近端之间，设置为升高通路的电压。
本发明实施例还提供了一种POE供电防护方法，包括：PSE近端防护模块接收从 PSE芯片输入的电源，在PSE芯片近端功率回路电压电流突变过程中，对PSE芯片的 各引脚进行防护，并将电源输入到PSE远端防护模块；
PSE远端防护模块接收输入的电源，抑制来自网口网线的干扰，将PSE芯片回路 突变减低到PSE近端所能承受的范围内，并将电源输入到PD远端防护模块；
PD远端防护模块接收输入的电源，抑制来自网口网线的干扰，将PD芯片回路突 变减低到PD近端所能承受的范围，并将电源输入到PD近端防护模块；
PD近端防护模块接收输入的电源，在PD芯片近端功率回路电压电流突变过程中， 对PD芯片的各引脚进行防护，并将电源提供给负载。
优选地，PSE近端防护模块在PSE芯片近端功率回路电压电流突变过程中，对PSE 芯片的各引脚进行防护具体包括：
通过外部电压钳位模块对外部输入电源进行钳位；
通过网口电压钳位模块对来自网口方向的电压波动进行钳位；
通过尖峰电流吸收模块吸收浪涌电流尖峰；
通过反向电流抑制模块抑制与POE供电电流方向相反的电流波动；
通过短路保护泄放模块在POE短路保护过程中对端口冲击电流进行泄放。
优选地，PSE远端防护模块抑制来自网口网线的干扰，将PSE芯片回路突变减低 到PSE近端所能承受的范围内具体包括：
通过第一共模差模泄放模块泄放来自网口的浪涌能量；
通过对称性电流突变抑制模块抑制电源线正极、负极的共模电流突变；
通过共模差模电压钳位模块将PSE芯片近端电压钳制在特定范围；
通过保护地对线低阻抗泄放模块在线对地浪涌时，使浪涌电流通过最短路径流回；
通过非对称性电流突变模块将抑制PSE芯片近端电源负极电流突变。
优选地，PD远端防护模块抑制来自网口网线的干扰，将PD芯片回路突变减低到 PD近端所能承受的范围具体包括：
通过第二共模差模泄放模块泄放来自网口大量浪涌能量；
通过反向电流抑制模块抑制与POE电流方向相反的电流；
通过电流突变抑制模块抑制PD电流侧电流突变。
优选地，PD近端防护模块在PD芯片近端功率回路电压电流突变过程中，对PD 芯片的各引脚进行防护具体包括：
通过第一电压钳位模块钳位来自PD芯片远端的电压突变；
通过第二电压钳位模块钳位来自负载端的电压波动。
优选地，上述方法进一步包括：
设置于外部输入电源与PSE芯片近端之间的升压模块对外部输入电源进行升压， 并将升压后的电源传输到PSE芯片。
本发明实施例有益效果如下：
通过对芯片远端、芯片近端的可靠性设计模式进行逐级防护，解决了现有技术中 POE供电传输可靠性不高的问题，能够有效抑制功率回路电压电流突变，确保芯片关 键引脚满足芯片设计要求，保证芯片工作处于正常状态。
上述说明仅是本发明实施例技术方案的概述，为了能够更清楚了解本发明的技术 手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其它目的、特征 和优点能够更明显易懂，以下特举本发明的具体实施方式。
附图说明
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通 技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本 发明的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：
图1是本发明实施例的POE供电防护系统的结构示意图；
图2是本发明实施例的POE供电防护系统优选结构示意图；
图3是本发明实施例的PSE近端防护的示意图；
图4是本发明实施例的PSE近端防护部分模块示例示意图；
图5是本发明实施例的PSE远端防护的示意图；
图6是本发明实施例的PSE远端防护部分模块示例的示意图；
图7是本发明实施例的PD远端防护的示意图；
图8是本发明实施例的PD近端防护的示意图；
图9是本发明实施例的外部输入电源升压的示意图；以及
图10是本发明实施例的POE供电防护方法的流程图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开 的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实 施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本 公开的范围完整的传达给本领域的技术人员。
为了解决现有技术中POE供电传输可靠性不高的问题，本发明提供了一种POE 供电防护系统及方法，能够在保证以太网业务正常传输的同时提高POE供电的可靠 性，具体包括：PSE芯片远端防护，抑制PSE芯片远端功率回路电压电流突变，将突 变降低到PSE近端所能承受范围；PSE芯片近端防护，抑制PSE芯片近端功率回路电 压电流突变，确保PSE芯片各关键引脚在突变过程中，各指标均满足芯片设计需求； PD芯片远端防护，抑制PD远端功率回路电压电流突变，将突变降低到PD近端所能 承受范围；PD芯片近端防护，抑制PD芯片近端功率回路电压电流突变，确保PD芯 片各关键引脚在突变过程中，各指标均满足芯片设计需求。以下结合附图以及实施例， 对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本 发明，并不限定本发明。
系统实施例
根据本发明的实施例，提供了一种POE供电防护系统，图1是本发明实施例的 POE供电防护系统的结构示意图，如图1所示，根据本发明实施例的POE供电防护系 统包括以下模块中的至少之一：PSE近端防护模块10、PSE远端防护模块12、PD远 端防护模块14、PD近端防护模块16，以下对本发明实施例的各个模块进行详细的说 明。
PSE近端防护模块10，设置于PSE芯片近端，设置为在PSE芯片近端功率回路 电压电流突变过程中，对PSE芯片的各引脚进行防护；
PSE近端防护模块10具体包括：外部电压钳位模块、网口电压钳位模块、尖峰电 流吸收模块、反向电流抑制模块、以及短路保护泄放模块，其中：
外部电压钳位模块，设置为对外部输入电源进行钳位；
网口电压钳位模块，设置为对来自网口方向的电压波动进行钳位；
尖峰电流吸收模块，设置为吸收浪涌电流尖峰；
反向电流抑制模块，设置为抑制与POE供电电流方向相反的电流波动；
短路保护泄放模块，设置为在POE短路保护过程中对端口冲击电流进行泄放。
PSE远端防护模块12，设置于PSE芯片近端与PSE网口之间，设置为抑制来自 网口网线的干扰，将PSE芯片回路突变减低到PSE近端所能承受的范围内；
PSE远端防护模块12设置于PSE芯片近端与PSE端网口变压器之间，具体包括： 第一共模差模泄放模块、对称性电流突变抑制模块、共模差模电压钳位模块、保护地 对线低阻抗泄放模块、以及非对称性电流突变抑制模块，其中：
第一共模差模泄放模块，设置为泄放来自网口的浪涌能量；
对称性电流突变抑制模块，设置为抑制电源线正极、负极的共模电流突变；
共模差模电压钳位模块，设置为将PSE芯片近端电压钳制在特定范围；
保护地对线低阻抗泄放模块，设置为在线对地浪涌时，使浪涌电流通过最短路径 流回；
非对称性电流突变模块，设置为将抑制PSE芯片近端电源负极电流突变。
PD远端防护模块14，设置于PD芯片近端与PD网口之间，设置为抑制来自网口 网线的干扰，将PD芯片回路突变减低到PD近端所能承受的范围；
PD远端防护模块14设置于PD芯片近端与PD端网口变压器之间，具体包括：第 二共模差模泄放模块、反向电流抑制模块、以及电流突变抑制模块，其中：
第二共模差模泄放模块，设置为泄放来自网口大量浪涌能量；
反向电流抑制模块，设置为抑制与POE电流方向相反的电流；
电流突变抑制模块，设置为抑制PD电流侧电流突变。
PD近端防护模块16，设置于PD芯片近端，设置为在PD芯片近端功率回路电压 电流突变过程中，对PD芯片的各引脚进行防护。
PD近端防护模块16具体包括：第一电压钳位模块、以及第二电压钳位模块，其 中，
第一电压钳位模块，设置为钳位来自PD芯片远端的电压突变；
第二电压钳位模块，设置为钳位来自负载端的电压波动。
优选地，根据本发明实施例的技术方案，还可以包括：升压模块，设置于外部输 入电源与PSE芯片近端之间，设置为升高通路的电压。
以下结合附图，对本发明实施例的上述技术方案进行详细说明。
图2是本发明实施例的POE供电防护系统优选结构示意图。如图2所示，外部输 入电源输入到PSE近端防护，经过PSE近端防护输入到PSE远端防护。经过POE供 电，电源达到PD远端防护，经过PD远端输入到PD近端，最终提供给负载。下面分 别对PSE近端防护(PSE近端防护模块10)、PSE远端防护(PSE远端防护模块12)、 PD远端防护(PD远端防护模块14)、以及PD近端防护(PD近端防护模块16)进行 详细说明。
1、PSE近端防护
具体地，由于PSE芯片承担检测PD是否合法、为合法PD正确分级、为分级成 功PD供电、监控PSE供电电压电流、PSE过流短路及时保护等关键职能，而各关键 引脚本身可靠性有限，是需要重点防护的对象。PSE近端防护模块10的电路设计应用 于PSE芯片近端，防护来自输入电源突变或PSE端网线网口引入的电压电流突变，即 保证在PSE芯片近端功率回路电压电流突变过程中，各指标均满足芯片设计需求，保 证PSE芯片处于正常的工作状态。该部分电路可以确保PSE芯片关键引脚。
PSE近端由PSE芯片及PSE近端防护模块10(PSE芯片关键引脚防护)组成。 电源输入到PSE芯片，PSE芯片在完成合法PD的检测分级后，PSE芯片将电源输出 到PSE远端电路。PSE近端防护模块10(PSE芯片关键引脚防护)能够确保PSE芯 片关键引脚在功率回路电压电流突变过程中，各指标均满足芯片设计需求，保证PSE 芯片稳定工作。
图3是本发明实施例的PSE近端防护的示意图，如图3所示，PSE近端防护模块 10具体细节包含：电压钳位模块1、电压钳位模块2、尖峰电流吸收模块、反向电流 抑制模块、短路保护泄放模块。其中电压钳位模块1设置为钳位外部输入电源，保证 外部输入电源在允许范围内。电压钳位模块2设置为钳位来自网口方向的电压波动。 尖峰电流吸收模块设置为吸收浪涌电流尖峰，防止浪涌过程中PSE芯片误动作关闭 POE供电。反向电流抑制模块设置为抑制与POE供电电流方向相反的电流波动。短路 保护泄放模块保证在POE短路保护过程中端口冲击电流有效泄放。
图4是本发明实施例的PSE近端防护部分模块示例示意图，如图4所示，包含尖 峰电流吸收模块、以及短路保护泄放模块的示例，其中，图6中的TVS为瞬态抑制二 极管(Transient Voltage Suppressor)的简称，MOS是场效应管mosfetmos的简称，AGND 为Analog Ground的简称；OUT为输出端的简称；GATE为场效应管中栅极G的简称； SENSE为测量电路的简称；VEE为接电源负的简称。
2、PSE远端防护
具体地，由于通过PSE端网线网口等极可能引入大能量干扰，如浪涌、冲击电流 测试中PSE远端电压电流突变，从而危害到PSE芯片的正常工作，因此需要对这部分 干扰能量进行有效抑制和泄放。PSE远端防护模块12的电路设计应用于PSE近端与 变压器之间，设置为抑制来自网口网线干扰，保证将回路突变减低到PSE近端所能承 受的范围。
PSE远端由PSE远端防护模块12(PSE输出网口防护)和PSE端网口变压器组 成。从PSE芯片输入到PSE远端防护模块12(PSE输出网口防护)的电源，经过PSE 远端防护模块12，输出到网口变压器。PSE远端防护模块12(PSE输出网口防护)能 够有效抑制网口网线引入的功率回路电压电流突变，确保将突变电压电流降低到PSE 近端所能承受的范围。
图5是本发明实施例的PSE远端防护的示意图，如图5所示，PSE远端防护模块 12具体包含：共模、差模泄放模块、对称性电流突变抑制模块、共模、差模电压钳位 模块、保护地对线低阻抗泄放模块、非对称性电流突变抑制模块。其中共模、差模泄 放模块设置为泄放来自网口的大部分浪涌能量。对称性电流突变抑制模块设置为抑制 电源线正极、负极的共模电流突变。共模、差模电压钳位将PSE近端电压钳制在特定 范围。保护地对线低阻抗泄放模块设置为保证线对地浪涌时，浪涌电流通过最短路径 流回，不干扰PSE芯片功率主回路。由于POE供电具有的非对称性，即对POE供电 电流方向干扰敏感，非对称性电流突变模块将抑制PSE近端电源负极电流突变。
图6是本发明实施例的PSE远端防护部分模块示例的示意图，如图6所示，其中 包括非对称性电流突变抑制模块、保护地对线低阻抗泄放模块、共模、差模泄放模块 的示例。
3、PD远端防护
具体地，由于通过PD端网线网口等及可能引入大能量干扰，如浪涌、冲击电流 测试中PD远端电压电流突变，从而危害到PSE芯片的正常工作，因此需要对这部分 干扰能量进行有效抑制和泄放。PD远端防护模块14的电路设计应设置为PD近端与 变压器之间，设置为抑制来自网线网口干扰，保证将回路突变减低到PD近端所能承 受的范围。
PD远端由PD远端防护模块14(PD输出网口防护)和PD端网口变压器组成。 来自网口网线电源输入到PD远端，经过PD远端防护模块14(PD输出网口防护)， 输出到PD近端。PD远端防护模块14(PD输出网口防护)能够有效抑制网口网线引 入的功率回路电压电流突变，确保将突变电压电流降低到PD近端所能承受的范围。
图7是本发明实施例的PD远端防护的示意图，如图7所示，PD远端防护模块14 具体包括：共模、差模泄放模块、反向电流抑制模块、电流突变抑制模块。共模、差 模泄放模块设置为泄放来自网口大量浪涌能量。反向电流抑制模块，设置为抑制与POE 电流方向相反的电流。电流突变抑制模块防止PD电流侧电流突变，造成PD误动作关 断POE供电。
4、PD芯片关键引脚防护
具体地，由于PD芯片承担表征自身为合法、与PSE正常握手、监控PD受电电 压电流、PD过流短路及时保护等重要职能，而各关键引脚本身可靠性有限，需要重点 防护。PD近端防护模块16的电路设计应用于PD芯片近端，防护来自PD网线网口引 入的电压电流突变或后级负载突变，即保证在PD芯片近端功率回路电压电流突变过 程中，各指标均满足芯片设计需求，保证PD芯片处于正常的工作状态。PD近端由 PD芯片及PD近端防护模块16(PD芯片关键引脚防护)组成。来自PD远端电源输 入到PD近端，PD芯片将电源提供给负载使用。PD近端防护模块16(PD芯片关键 引脚防护)能够确保PD芯片关键引脚在功率回路电压电流突变过程中，各指标均满 足芯片设计需求，保证PD芯片稳定工作。
图8是本发明实施例的PD近端防护的示意图，如图8所示，具体电压钳位模块1、 电压钳位模块2。电压钳位模块1设置为钳位来自PD远端的电压突变。电压钳位模块 2设置为钳位来自负载端的电压波动。
5、升压模块
由于网线、变压器、水晶头等器件阻抗恒定，在POE传输总功率确定的情况下， 提高传输电压，降低传输电流，能够有效减小传输路径上的损耗，从而提供高效的POE 传输方案。该部分电路设计应用于外部输入电源与PSE近端之间，外部电源通过升压 模块后，将升压后电源输入到PSE近端。
图9是本发明实施例的外部输入电源升压的示意图。外部电源输入到升压模块， 升压模块提升外部输入电源电压，并将升压后的电源输出到PSE近端。对输入电源电 压的提升能够降低POE传输路径上的损耗，有效提高POE的传输效率。
综上所述，本发明实施例的技术方案提供了一种基于POE的可靠供电方法，通过 PSE近端防护、PSE远端防护、PD远端防护、PD近端防护，在保证以太网业务正常 传输的基础上，实现高效可靠的POE供电方案。外部电源输入到PSE芯片，通过正 常分级检测过程，PSE芯片将电源输出到网口防护电路，而PSE芯片关键引脚防护， 用于确保PSE芯片关键引脚处于正常的工作状态，免受功率回路电源突变影响。输入 到PSE远端防护电路电源，经过PSE网口防护电路，输出到网口变压器中心抽头，继 而通过网线为PD供电。而PSE远端防护，用于抑制网口网线引入的电源突变，保证 将回路突变减低到PSE近端能承受的范围内。来自网口网线电源输入到PD远端，通 过PD近端防护电路输入到PD芯片，PD芯片将输入电源提供给负载使用。
通过验证，本发明实施例的POE供电性能满足国际电工委员会(International  Electro technical Commission，简称为IEC)、)国际无线电干扰特别委员会(International  Special Committee on Radio Interference，简称为CISPR)可靠性指标。其中，所述IEC 可靠性指标包含：静电抗扰测试接触±6kV，空气±8kV，CLASS B(IEC61000-4-2)； 辐射抗扰测试80-2700MHz，80％AM，10V/m CLASS B(IEC61000-4-3)；传导抗扰测 试150k-80MHz，80％AM，3V,CLASS B(IEC61000-4-6)；脉冲串抗扰测试±2KV， 5kHz,CLASS B(IEC61000-4-4)；浪涌抗扰测试10/700us，线地±6kV/40Ω，CLASS B (IEC61000-4-5)，冲击电流测试2KA，8/20us,CLASS B(IEC61312-3)。所述CISPR 可靠性指标包含：传导骚扰测试CLASS B(CISPR22)；辐射骚扰测试CLASS B(CISPR 22)。
需要说明的是，第一，本发明实施例的技术方案包含支持POE功能的所有线缆， 不限于线缆类别。第二，本发明实施例的技术方案包含PSE芯片关键引脚防护、PD 芯片关键引脚防护、PSE输出网口防护、PD输入网口防护，但不限于对防护方案进行 裁剪只选择其中1个或多个防护的应用场景。第三，本发明实施例的技术方案通过IEC、 CISPR可靠性指标，但不限于满足文中提到的部分指标或同等级及以下测试指标的应 用场景。第四，本发明实施例的技术方案中包含网口变压器的使用，但不限于不使用 网口变压器而使用其他方式实现POE功能的应用场景。
方法实施例
根据本发明的实施例，基于上述系统实施例中的POE供电防护系统，提供了一种 POE供电防护方法，图10是本发明实施例的POE供电防护方法的流程图，如图10 所示，根据本发明实施例的POE供电防护方法包括如下处理：
步骤1001，PSE近端防护模块10接收从PSE芯片输入的电源，在PSE芯片近端 功率回路电压电流突变过程中，对PSE芯片的各引脚进行防护，并将电源输入到PSE 远端防护模块12；
其中，PSE近端防护模块10在PSE芯片近端功率回路电压电流突变过程中，对 PSE芯片的各引脚进行防护具体包括：
通过外部电压钳位模块对外部输入电源进行钳位；
通过网口电压钳位模块对来自网口方向的电压波动进行钳位；
通过尖峰电流吸收模块吸收浪涌电流尖峰；
通过反向电流抑制模块抑制与POE供电电流方向相反的电流波动；
通过短路保护泄放模块在POE短路保护过程中对端口冲击电流进行泄放。
步骤1002，PSE远端防护模块12接收输入的电源，抑制来自网口网线的干扰， 将PSE芯片回路突变减低到PSE近端所能承受的范围内，并将电源输入到PD远端防 护模块14；
PSE远端防护模块12抑制来自网口网线的干扰，将PSE芯片回路突变减低到PSE 近端所能承受的范围内具体包括：
通过第一共模差模泄放模块泄放来自网口的浪涌能量；
通过对称性电流突变抑制模块抑制电源线正极、负极的共模电流突变；
通过共模差模电压钳位模块将PSE芯片近端电压钳制在特定范围；
通过保护地对线低阻抗泄放模块在线对地浪涌时，使浪涌电流通过最短路径流回；
通过非对称性电流突变模块将抑制PSE芯片近端电源负极电流突变。
步骤1003，PD远端防护模块14接收输入的电源，抑制来自网口网线的干扰，将 PD芯片回路突变减低到PD近端所能承受的范围，并将电源输入到PD近端防护模块 16；
PD远端防护模块14抑制来自网口网线的干扰，将PD芯片回路突变减低到PD 近端所能承受的范围具体包括：
通过第二共模差模泄放模块泄放来自网口大量浪涌能量；
通过反向电流抑制模块抑制与POE电流方向相反的电流；
通过电流突变抑制模块抑制PD电流侧电流突变。
步骤1004，PD近端防护模块16接收输入的电源，在PD芯片近端功率回路电压 电流突变过程中，对PD芯片的各引脚进行防护，并将电源提供给负载。
PD近端防护模块16在PD芯片近端功率回路电压电流突变过程中，对PD芯片的 各引脚进行防护具体包括：
通过第一电压钳位模块钳位来自PD芯片远端的电压突变；
通过第二电压钳位模块钳位来自负载端的电压波动。
优选地，在本发明实施例中，设置于外部输入电源与PSE芯片近端之间的升压模 块对外部输入电源进行升压，并将升压后的电源传输到PSE芯片。
综上所述，本发明实施例的技术方案提供了一种基于POE的可靠供电方法，通过 PSE近端防护、PSE远端防护、PD远端防护、PD近端防护，在保证以太网业务正常 传输的基础上，实现高效可靠的POE供电方案。外部电源输入到PSE芯片，通过正 常分级检测过程，PSE芯片将电源输出到网口防护电路，而PSE芯片关键引脚防护， 用于确保PSE芯片关键引脚处于正常的工作状态，免受功率回路电源突变影响。输入 到PSE远端防护电路电源，经过PSE网口防护电路，输出到网口变压器中心抽头，继 而通过网线为PD供电。而PSE远端防护，用于抑制网口网线引入的电源突变，保证 将回路突变减低到PSE近端能承受的范围内。来自网口网线电源输入到PD远端，通 过PD近端防护电路输入到PD芯片，PD芯片将输入电源提供给负载使用。
通过对芯片远端、芯片近端的可靠性设计模式进行逐级防护，解决了现有技术中 POE供电传输可靠性不高的问题，能够有效抑制功率回路电压电流突变，确保芯片关 键引脚满足芯片设计要求，保证芯片工作处于正常状态。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精 神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的 范围之内，则本发明也意图包含这些改动和变型在内。
工业实用性
本发明提供的上述技术方案，可以应用于POE供电防护过程中，通过对芯片远端、 芯片近端的可靠性设计模式进行逐级防护，解决了现有技术中POE供电传输可靠性不 高的问题，能够有效抑制功率回路电压电流突变，确保芯片关键引脚满足芯片设计要 求，保证芯片工作处于正常状态。

Claims (12)

  1. 一种POE供电防护系统，包括以下模块中的至少之一：PSE近端防护模块、PSE 远端防护模块、PD远端防护模块、PD近端防护模块，其中：
    PSE近端防护模块，设置于PSE芯片近端，设置为在PSE芯片近端功率回 路电压电流突变过程中，对PSE芯片的各引脚进行防护；
    PSE远端防护模块，设置于PSE芯片近端与PSE网口之间，设置为抑制来 自网口网线的干扰，将PSE芯片回路突变减低到PSE近端所能承受的范围内；
    PD远端防护模块，设置于PD芯片近端与PD网口之间，设置为抑制来自 网口网线的干扰，将PD芯片回路突变减低到PD近端所能承受的范围；
    PD近端防护模块，设置于PD芯片近端，设置为在PD芯片近端功率回路 电压电流突变过程中，对PD芯片的各引脚进行防护。
  2. 如权利要求1所述的系统，其中，所述PSE近端防护模块具体包括：外部电压 钳位模块、网口电压钳位模块、尖峰电流吸收模块、反向电流抑制模块、以及 短路保护泄放模块，其中：
    外部电压钳位模块，设置为对外部输入电源进行钳位；
    网口电压钳位模块，设置为对来自网口方向的电压波动进行钳位；
    尖峰电流吸收模块，设置为吸收浪涌电流尖峰；
    反向电流抑制模块，设置为抑制与POE供电电流方向相反的电流波动；
    短路保护泄放模块，设置为在POE短路保护过程中对端口冲击电流进行泄 放。
  3. 如权利要求1所述的系统，其中，所述PSE远端防护模块设置于PSE芯片近端 与PSE端网口变压器之间，具体包括：第一共模差模泄放模块、对称性电流突 变抑制模块、共模差模电压钳位模块、保护地对线低阻抗泄放模块、以及非对 称性电流突变抑制模块，其中：
    第一共模差模泄放模块，设置为泄放来自网口的浪涌能量；
    对称性电流突变抑制模块，设置为抑制电源线正极、负极的共模电流突变；
    共模差模电压钳位模块，设置为将PSE芯片近端电压钳制在特定范围；
    保护地对线低阻抗泄放模块，设置为在线对地浪涌时，使浪涌电流通过最 短路径流回；
    非对称性电流突变模块，设置为将抑制PSE芯片近端电源负极电流突变。
  4. 如权利要求1所述的系统，其中，所述PD远端防护模块设置于PD芯片近端 与PD端网口变压器之间，具体包括：第二共模差模泄放模块、反向电流抑制 模块、以及电流突变抑制模块，其中：
    第二共模差模泄放模块，设置为泄放来自网口大量浪涌能量；
    反向电流抑制模块，设置为抑制与POE电流方向相反的电流；
    电流突变抑制模块，设置为抑制PD电流侧电流突变。
  5. 如权利要求1所述的系统，其中，所述PD近端防护模块包括：第一电压钳位 模块、以及第二电压钳位模块，其中，
    第一电压钳位模块，设置为钳位来自PD芯片远端的电压突变；
    第二电压钳位模块，设置为钳位来自负载端的电压波动。
  6. 如权利要求1所述的系统，其中，所述系统进一步包括：
    升压模块，设置于外部输入电源与PSE芯片近端之间，设置为升高通路的 电压。
  7. 一种POE供电防护方法，包括以下至少之一步骤：
    PSE近端防护模块接收从PSE芯片输入的电源，在PSE芯片近端功率回路 电压电流突变过程中，对PSE芯片的各引脚进行防护，并将电源输入到PSE远 端防护模块；
    所述PSE远端防护模块接收输入的电源，抑制来自网口网线的干扰，将 PSE芯片回路突变减低到PSE近端所能承受的范围内，并将电源输入到PD远 端防护模块；
    所述PD远端防护模块接收输入的电源，抑制来自网口网线的干扰，将PD 芯片回路突变减低到PD近端所能承受的范围，并将电源输入到PD近端防护 模块；
    所述PD近端防护模块接收输入的电源，在PD芯片近端功率回路电压电 流突变过程中，对PD芯片的各引脚进行防护，并将电源提供给负载。
  8. 如权利要求7所述的方法，其中，PSE近端防护模块在PSE芯片近端功率回路 电压电流突变过程中，对PSE芯片的各引脚进行防护包括：
    通过外部电压钳位模块对外部输入电源进行钳位；
    通过网口电压钳位模块对来自网口方向的电压波动进行钳位；
    通过尖峰电流吸收模块吸收浪涌电流尖峰；
    通过反向电流抑制模块抑制与POE供电电流方向相反的电流波动；
    通过短路保护泄放模块在POE短路保护过程中对端口冲击电流进行泄放。
  9. 如权利要求7所述的方法，其中，所述PSE远端防护模块抑制来自网口网线的 干扰，将PSE芯片回路突变减低到PSE近端所能承受的范围内包括：
    通过第一共模差模泄放模块泄放来自网口的浪涌能量；
    通过对称性电流突变抑制模块抑制电源线正极、负极的共模电流突变；
    通过共模差模电压钳位模块将PSE芯片近端电压钳制在特定范围；
    通过保护地对线低阻抗泄放模块在线对地浪涌时，使浪涌电流通过最短路 径流回；
    通过非对称性电流突变模块将抑制PSE芯片近端电源负极电流突变。
  10. 如权利要求7所述的方法，其中，所述PD远端防护模块抑制来自网口网线的 干扰，将PD芯片回路突变减低到PD近端所能承受的范围包括：
    通过第二共模差模泄放模块泄放来自网口大量浪涌能量；
    通过反向电流抑制模块抑制与POE电流方向相反的电流；
    通过电流突变抑制模块抑制PD电流侧电流突变。
  11. 如权利要求7所述的方法，其中，所述PD近端防护模块在PD芯片近端功率 回路电压电流突变过程中，对PD芯片的各引脚进行防护包括：
    通过第一电压钳位模块钳位来自PD芯片远端的电压突变；
    通过第二电压钳位模块钳位来自负载端的电压波动。
  12. 如权利要求7所述的方法，其中，所述方法进一步包括：
    设置于外部输入电源与PSE芯片近端之间的升压模块对外部输入电源进行 升压，并将升压后的电源传输到PSE芯片。
PCT/CN2014/079180 2013-12-27 2014-06-04 Poe供电防护系统及方法 WO2015096398A1 (zh)

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