WO2015081894A1 - 视频信号调节模块及调节方法 - Google Patents

视频信号调节模块及调节方法 Download PDF

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Publication number
WO2015081894A1
WO2015081894A1 PCT/CN2014/093189 CN2014093189W WO2015081894A1 WO 2015081894 A1 WO2015081894 A1 WO 2015081894A1 CN 2014093189 W CN2014093189 W CN 2014093189W WO 2015081894 A1 WO2015081894 A1 WO 2015081894A1
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Prior art keywords
video signal
impedance matching
resistor
matching circuit
video
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English (en)
French (fr)
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王林
刘松
王绍惇
阚伟生
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Leshi Zhixin Electronic Technology Tianjin Co Ltd
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Leshi Zhixin Electronic Technology Tianjin Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/52—Automatic gain control

Definitions

  • the present application relates to the field of video signal processing, and in particular, to a video signal adjustment module and an adjustment method.
  • the present application provides a video signal adjustment module and an adjustment method for the technical problem to be solved.
  • the method by switching between the first impedance matching circuit and the second impedance matching circuit, adapts to the characteristics of the video signals output by different tuners, so that the output amplitudes of the video signals can reach the standard value, thereby solving the deviation of the output amplitude of the video signal.
  • a standard value that causes image distortion (such as a picture that is too dark or too bright).
  • the present application discloses a video signal adjustment module suitable for use in a video processing system including a tuner and a video decoder.
  • the video signal adjustment module includes a first impedance matching circuit, a second impedance matching circuit, a switch, and a processing unit.
  • the first impedance matching circuit is electrically connected between the tuner and the video decoder to implement impedance matching between the tuner and the video decoder.
  • the second impedance matching circuit is electrically connected between the tuner and the video decoder to implement impedance matching between the tuner and the video decoder.
  • the processing unit is electrically connected to the switch and the video decoder, respectively.
  • the video signal sent by the tuner is transmitted to the video decoder through the switch and the first impedance matching circuit, and the processing unit receives and determines whether the output amplitude of the video signal processed by the video decoder is lower than a standard value, and if so, the processing unit An open circuit is formed between the control switch and the first impedance matching circuit, and a closed circuit is formed between the switch and the second impedance matching circuit. If not, the switch does not operate.
  • the present application also discloses a video signal adjustment method suitable for a video processing system, the video processing system including a tuner and a video decoder.
  • the video signal adjustment method includes: outputting a video signal through a tuner; transmitting a video signal to a video decoder through a switching switch of the video signal adjustment module and the first impedance matching circuit; receiving and processing the video signal through the video decoder, and outputting the processed video signal a video signal; receiving, by the processing unit of the video signal adjustment module, determining whether the output amplitude of the processed video signal is lower than a standard value; if so, the processing unit controls an open circuit between the switch and the first impedance matching circuit, and controls switching A closed circuit is formed between the switch and the second impedance matching circuit of the video signal adjustment module, so that the video signal is increased by the second impedance matching circuit to increase the output amplitude to a standard value; if not, the switch does not operate.
  • the video signal adjustment module and the adjustment method of the present application the switching between the first impedance matching circuit and the second impedance matching circuit by the switching switch, and the receiving and determining by the processing unit whether the output amplitude of the video signal reaches a standard value, If the output amplitude meets the standard value, the switch does not operate; if the output amplitude is lower than the standard value, it indicates that the first impedance matching circuit causes the tuner and video decoding The impedance mismatch between the devices, at this time, the processing unit controls the switching switch to switch from the first impedance matching circuit to the second impedance matching circuit, so that the impedance matching characteristic is achieved between the tuner and the video decoder, thereby allowing the output of the video signal The amplitude is increased to the standard value. Therefore, the video signal adjustment module and the adjustment method of the present application can adapt to the characteristics of the video signals output by different tuners, so that the output amplitudes of the video signals can reach the standard value, thereby preventing the image picture from being too dark or
  • FIG. 1 is a block diagram of an embodiment of the present application.
  • FIG. 2 is a schematic circuit diagram of a video signal adjustment module applied to a video signal processing system according to a preferred embodiment of the present application.
  • FIG. 3 is a flowchart of a video signal adjustment method according to an embodiment of the present application.
  • the first device may be directly electrically coupled to the second device, or may be electrically coupled to the second device indirectly through other devices or coupling means.
  • the description of the specification is intended to be illustrative of the preferred embodiments of the invention. The scope of protection of the application is subject to the definition of the appended claims.
  • the video signal adjustment module of the present application is suitable for use in a video processing system, which includes a tuner and a video decoder electrically disposed on a circuit board, in which the tuner and the video decoder are In the purchase and installation, the tuner and video decoder of different manufacturers are selected to be mounted on the circuit board according to different usage requirements and output characteristics of the video signal.
  • the video processing module of the present application is electrically disposed on the circuit board and electrically connected between the tuner and the video decoder respectively to implement impedance matching between the tuner and the video decoder, thereby allowing different output characteristics.
  • the output amplitude (or amplitude) of the video signal can reach the standard value, and the image picture is prevented from being too dark due to the decrease of the output amplitude.
  • the video signal adjustment module 10 disclosed in the embodiment of the present application is electrically connected between the tuner 20 of the video processing system and the video decoder 30 .
  • the video signal adjustment module 10 includes a first impedance matching circuit 110 .
  • One end of the switch 130 is electrically connected to the tuner 20, and the other end is connected to the first impedance matching circuit 110 or the second impedance matching circuit 120, and is selectively connected to the first impedance matching circuit 110 and the second impedance matching circuit 120. Switching between, so that the video signal sent by the tuner 20 can be selectively transmitted through the first impedance matching circuit 110 or the second impedance matching circuit 120 It is sent to the video decoder 30.
  • the processing unit 140 may be, but not limited to, a central processing unit (CPU) or a micro-controller unit (MCU) or the like.
  • the processing unit 140 is electrically connected to the switch 130 and the video decoder 30, respectively, for receiving the processed video signal from the video decoder 30, and determining whether the output amplitude of the video signal is lower than a standard value, for example, if the output The amplitude is in accordance with the standard value, and the processing unit 140 determines that the current impedance matching circuit (for example, the first impedance matching circuit 110) is adapted to achieve impedance matching between the tuner 20 and the video decoder 30, and thus does not need to transmit the switching signal to the switching.
  • the current impedance matching circuit for example, the first impedance matching circuit 110
  • the switch 130 therefore, the switch 130 does not operate; conversely, if the output amplitude is lower than the standard value, the processing unit 140 determines that the current impedance matching circuit is not suitable for connecting the tuner 20 and the video decoder 30, and then sends the switching signal to the switch. 130, causing the switch 130 to switch to another impedance matching circuit (eg, the second impedance matching circuit 120) according to the switching signal, thereby allowing the video signal to be transmitted between the tuner 20 and the video decoder 30 through the second impedance matching circuit 120. While maintaining a stable output that meets the standard value, the video signal can be displayed after passing through the processing at the back end. Presented with a screen image that conforms to the standard video device (eg TV screen).
  • the standard video device eg TV screen
  • the first impedance matching circuit 110 is electrically connected between the tuner 20 and the video decoder 30 for implementing the tuner 20 and the video decoding. Impedance matching between the devices 30.
  • the first impedance matching circuit 110 is an impedance matching circuit that meets a 75 ohm (ohm, ⁇ ) group anti-matching standard, and includes a first resistor R1, a second resistor R2, and a first capacitor C1.
  • the first capacitor C1 is electrically connected to the first capacitor C1.
  • a resistor R1 is connected between the video decoder 30; the first resistor R1 is connected in series with the first capacitor C1; the second resistor R2 is connected in parallel with the first resistor R1, and is grounded (GND), wherein the resistance of the first resistor R1 is the second
  • the sum of the resistance values of the resistor R2 is equal to 75 ohms, so the resistance value of the first resistor R1 may be smaller than the resistance value of the second resistor R2; or is greater than or equal to the resistance value of the second resistor R2, in this embodiment, For example, the resistance value of the first resistor R1 is smaller than the resistance value of the second resistor R2.
  • the first resistor R1 is a 24 ohm resistor
  • the second resistor R2 is a 51 ohm resistor, but is not limited thereto.
  • the capacitance of the first capacitor C1 is between 0.1 ⁇ F (micro method) and 10 ⁇ F.
  • the larger capacitance value has a better effect on filtering out low frequency interference, and the smaller capacitance value helps to shorten the rising edge of the signal. With falling edge time.
  • the first capacitor C1 is a 0.1 ⁇ F capacitor as an example. Therefore, the first impedance matching circuit 110 is caused
  • a 75 ohm group anti-matching circuit is formed by the arrangement of the first resistor R1, the second resistor R2, and the first capacitor C1.
  • the second impedance matching circuit 120 is electrically connected between the tuner 20 and the video decoder 30 to implement impedance matching between the tuner 20 and the video decoder 30.
  • the second impedance matching circuit 120 includes a third resistor R3 and a second capacitor C2 connected in series, and the second capacitor C2 is electrically connected between the third resistor R3 and the video decoder 30, wherein the capacitance value of the second capacitor C2 is the same.
  • the second capacitor C2 and the first capacitor C1 are capacitors having the same capacitance value, so that the signal has the same when passing through the first impedance circuit 110 or the second impedance circuit 120.
  • the first capacitor C1 and the second capacitor C2 may also be capacitors having different capacitance values, and are not limited to the above embodiments.
  • the resistance value of the third resistor R3 of the second impedance matching circuit 120 corresponds to the characteristics of the video processing chip (for example, a tuner chip) disposed on the circuit. Since traditional video processing chips are generally suitable for 75 ohm impedance matching standard circuits, with the continuous advancement of electronic technology, many high-performance video processing chips have been developed, although the overall performance of these video processing chips Beyond the traditional video processing chip, but the internal architecture is adjusted to meet the current trend of miniaturization or other requirements, resulting in the video signal output of these video processing chips exactly match the standard value of 700 ⁇ 30mV, or It is not higher than the standard value.
  • the output amplitude of the video signal is easily interfered by the grounding resistance in the 75 ohm impedance matching circuit, causing the output amplitude to be pulled down, for example, from 700 mV to 400 mV.
  • the back-end display causes the back-end display to be too dark and does not meet the standards specified by the video metrics. In this case, it is applicable to the solution of the present application.
  • the workflow will only assemble the video processing chip on the circuit board, and will not deliberately check whether the video processing chip is suitable for the circuit with 75 ohm impedance matching standard, resulting in good product.
  • the problem of low rate occurs.
  • the video signal adjustment system 10 of the present application simultaneously provides the first impedance matching circuit 110 and the second impedance matching circuit 120, and the first impedance matching circuit 110 and the second impedance according to the amplitude of the video signal output by the video processing chip.
  • the matching circuit 120 automatically switches between the conventional video processing chip and the subsequently developed high-performance video processing chip to solve the above problems and improve the production efficiency of the product.
  • the resistance value of the third resistor R3 of the second impedance matching circuit 120 may be the same as or different from the resistance value of the first resistor R1 or the second resistor R2.
  • the resistance value of the third resistor R3 may be but not In the embodiment, the configuration is limited to the resistance value of the second resistor R2. In the embodiment, the configuration of the resistance of the third resistor R3 is equal to the resistance of the first resistor R1.
  • the impedance matching between the tuner 20 and the video decoder 30 avoids the attenuation of the output amplitude of the video signal during transmission, and also reduces the procurement cost of components (such as resistors) on the circuit and improves the convenience of circuit configuration. .
  • one end of the switch 130 is electrically connected to the tuner 20, and the other end is selectively switchable between the first impedance matching circuit 110 and the second impedance matching circuit 120, that is, selective electrical properties.
  • the switch 130 is coupled to the first impedance matching circuit 110 to the video decoder 30; or is selectively electrically connected to the third resistor R3 of the second impedance matching circuit 120, thereby forming a closed circuit with the second impedance matching circuit 120, And forming an open circuit with the first impedance matching circuit 110, so that the video signal sent by the tuner 20 is transmitted to the video decoder 30 through the switch 130 and the second impedance matching circuit 120.
  • the processing unit 140 is electrically connected to the switch 130 and the video decoder 30 for receiving and determining whether the output amplitude of the video signal processed by the video decoder 30 is lower than a standard value. If yes, the processing unit 140 controls the switch 130. Forming an open circuit with the first resistor R1 of the first impedance matching circuit 110 and forming a closed circuit with the third resistor R3 of the second impedance matching circuit 120, after the video signal is transmitted through the second impedance matching circuit 120, The output amplitude can reach the standard value; conversely, if the output amplitude of the video signal has already matched the standard value, the switch 130 does not operate, maintaining the initial mode (or default mode) in which the video signal is transmitted through the first impedance matching circuit 110. .
  • a flowchart of a video signal adjustment method according to an embodiment of the present application includes:
  • step S10 the video signal is output through the tuner.
  • step S20 the video signal is transmitted to the video decoder through the switch of the video signal adjustment module and the first impedance matching circuit.
  • Step S30 receiving and processing a video signal through a video decoder, and outputting the processed view Frequency signal.
  • step S40 the processing unit of the video signal adjustment module receives and determines whether the output amplitude of the processed video signal is lower than a standard value.
  • Step S41 if yes, the processing unit controls the switching switch to form an open circuit with the first impedance matching circuit, and forms a closed circuit between the control switching switch and the second impedance matching circuit of the video signal adjusting module, so that the video signal passes through the second impedance matching circuit. Increase the output amplitude to the standard value.
  • step S42 if not, the switch does not operate.
  • the video signal output by the tuner 20 may be, but not limited to, composite video, super-video, RGBHV video, VGA video.
  • Video signals such as graphics array), workstation video (IBM PowerPC/Sun Color), or signal-digital interface (informed by the inventor to confirm whether these signal formats are applicable), in the embodiment of the present application,
  • the video signal is used as a standard composite video signal (CVBS) as an example, but is not limited thereto.
  • the changeover switch 130 is set to be normally closed to form a closed circuit with the first impedance matching circuit 110, and to form an open circuit with the second impedance matching circuit 120. Therefore, when the tuner 20 outputs the video signal (step S10), the video signal is transmitted to the video decoder 30 through the changeover switch 130 of the video signal adjustment module 10 and the first impedance matching circuit 110 (step S20). Next, the video signal is received and processed by the video decoder 30, and the processed video signal is output to the processing unit 140 (step S30). At this time, the processing unit 140 receives the processed video signal, and determines whether the output amplitude of the video signal is lower than the standard value (step S40), for example, outputs a standard value having an amplitude of 700 ⁇ 30 mV.
  • the processing unit 140 determines that the output amplitude of the video signal is lower than the standard value, it indicates that the output amplitude of the video signal is affected by the output characteristic of the tuner 20, and cannot be pulled high at the output, thereby receiving the first impedance during transmission.
  • the second resistor R2 grounded in the matching circuit 110 is pulled low, resulting in a decrease in the output amplitude.
  • the processing unit 140 transmits a switching signal to the switch 130, and the control switch 130 is switched from the first impedance matching circuit 110 to the second impedance matching circuit 120, and through the third resistor R3 and the second of the second impedance matching circuit 120.
  • the series connection of the capacitor C2 realizes the impedance matching between the tuner 20 and the video processor 30, so that the load resistance is equal to the internal resistance of the signal source, so that the output amplitude of the video signal is maintained at the standard value during the transmission of the video signal (step S40). ).
  • the output amplitude of the standard composite video signal (CVBS) output by the tuner can reach 700 mV.
  • each video index such as sync pulse amplitude, luminance nonlinearity, K coefficient (2T pulse), differential gain, differential phase, chrominance-brightness gain difference, chromaticity-luminance delay difference, amplitude-frequency characteristic And the random signal to noise ratio, etc., can also meet the test standard values of various performance indicators.
  • the processing unit 140 determines that the output amplitude of the video signal meets the standard value, it indicates that the first impedance matching circuit 110 is adapted to implement impedance matching between the current tuner 20 and the video processor 30, at which time the processing unit 140 does not transmit.
  • the switching signal is switched to the changeover switch 130, so the changeover switch 130 does not operate (step S42).

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Circuits Of Receivers In General (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)

Abstract

一种视频信号调节模块及调节方法，视频信号调节模块包括第一阻抗匹配电路、第二阻抗匹配电路、切换开关以及处理单元。视频信号调节模块电性连接于视频处理系统的调谐器与视频解码器之间，通过处理单元接收与判断视频信号的输出幅值是否低于标准值，对应控制切换开关于第一阻抗匹配电路与第二阻抗匹配电路之间进行切换，让输出视频信号的调谐器与接收视频信号的视频解码器之间实现阻抗匹配，从而使视频信号的输出幅值能达到标准值，而避免图像失真（例如画面太暗或太亮）的情况发生。

Description

视频信号调节模块及调节方法
交叉引用
本申请引用于2013年12月6日递交的名称为“视频信号调节模块及调节方法”的第2013106626279号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请涉及视频信号处理领域，具体涉及一种视频信号调节模块及调节方法。
背景技术
随着数字电视技术的发展和普及，以及消费者对电视的功能要求愈来愈高，现有的数字电视已不仅仅是收看电视节目,其功能也愈来愈多，除了可以播放传统的广播电视节目外，还能够为用户提供电子节目指南、购物和旅游等方面的信息，从而使数字电视成为家庭的娱乐中心。它所播放的节目与多媒体信息已逐渐的融入用户的生活当中，其中，如何使电视能更容易的被使用、有更佳的可靠度以及有更好的画质是现今研究课题之一。
因此，在目前的消费性电子产品中，尤其是电视机产品的视频信号质量受到广泛的关注。然而，随着电视技术的发展，目前业界所开发出来的视频处理芯片(例如调谐器与视频解码器等)的厂牌型号也愈来愈多，其视频信号的输出特性也不尽相同。因此，在这些视频处理芯片的使用上，不尽然都适用于现有的电路设计，而存在有视频信号输出幅值(或幅度)偏低或偏高的问题，从而导致图像失真(例如画面太暗或太亮)、信噪比降低、甚至出现图像不同步等不良现象的发生。
发明内容
本申请针对所要解决的技术问题提供一种视频信号调节模块及调节方 法，通过第一阻抗匹配电路与第二阻抗匹配电路的切换，适应不同调谐器输出的视频信号特性，让这些视频信号的输出幅值均能达到标准值，从而解决视频信号的输出幅值偏离标准值，导致图像失真(例如画面太暗或太亮)的问题。
为了解决上述问题，本申请揭示了一种视频信号调节模块，适用于视频处理系统内，此视频处理系统包括调谐器与视频解码器。视频信号调节模块包括第一阻抗匹配电路、第二阻抗匹配电路、切换开关以及处理单元。第一阻抗匹配电路电性连接于调谐器与视频解码器之间，用以实现调谐器与视频解码器之间的阻抗匹配。第二阻抗匹配电路电性连接于调谐器与视频解码器之间，用以实现调谐器与视频解码器之间的阻抗匹配。处理单元分别电性连接于切换开关与视频解码器。其中，调谐器发送的视频信号通过切换开关与第一阻抗匹配电路传送至视频解码器，处理单元接收及判断视频解码器处理后的视频信号的输出幅值是否低于标准值，若是，处理单元控制切换开关与第一阻抗匹配电路之间形成开路，以及与第二阻抗匹配电路之间形成闭路，若否，切换开关不动作。
进一步地，本申请还揭示一种视频信号调节方法，适用于视频处理系统，此视频处理系统包括调谐器与视频解码器。视频信号调节方法包括：通过调谐器输出视频信号；通过视频信号调节模块的切换开关与第一阻抗匹配电路传送视频信号至视频解码器；通过视频解码器接收和处理视频信号，并且输出处理后的视频信号；通过视频信号调节模块的处理单元接收和判断处理后的视频信号的输出幅值是否低于标准值；若是，处理单元控制切换开关与第一阻抗匹配电路之间形成开路，以及控制切换开关与视频信号调节模块的第二阻抗匹配电路之间形成闭路，使视频信号通过第二阻抗匹配电路提高输出幅值至标准值；若否，切换开关不动作。
工业实用性
本申请的视频信号调节模块及调节方法，通过切换开关在第一阻抗匹配电路与第二阻抗匹配电路之间进行的切换，以及通过处理单元接收与判断视频信号的输出幅值是否达到标准值，若输出幅值符合标准值，切换开关不动作；若输出幅值低于标准值，表示第一阻抗匹配电路造成调谐器与视频解码 器之间的阻抗失配，此时处理单元即控制切换开关从第一阻抗匹配电路切换至第二阻抗匹配电路，使调谐器与视频解码器之间达到阻抗匹配特性，从而让视频信号的输出幅值提升至标准值。因此，本申请的视频信号调节模块及调节方法可以适应不同的调谐器输出的视频信号特性，让这些视频信号的输出幅值均能达到标准值，从而避免图像画面太暗或太亮的情形发生。
附图概述
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1为本申请实施例的方块示意图。
图2为本申请优选实施例的视频信号调节模块应用于视频信号处理系统的电路示意图。
图3为本申请实施例的视频信号调节方法流程图。
本申请的较佳实施方式
以下将配合附图及实施例来详细说明本申请的实施方式，藉此对本申请如何应用技术手段来解决技术问题并达成技术功效的实现过程能充分理解并据以实施。
如在说明书及权利要求当中使用了某些词汇来指称特定组件。本领域技术人员应可理解，硬件制造商可能会用不同名词来称呼同一个组件。本说明书及权利要求并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。如在通篇说明书及权利要求当中所提及的“包含”为一开放式用语，故应解释成“包含但不限定于”。“大致”是指在可接收的误差范围内，本领域技术人员能够在一定误差范围内解决所述技术问题，基本达到所述技术效果。此外，“耦接”或“电性连接”一词在此包含任何直接及间接的电性耦接手段。因此，若文中描述一第一装置耦接于一第二装置，则 代表所述第一装置可直接电性耦接于所述第二装置，或通过其他装置或耦接手段间接地电性耦接至所述第二装置。说明书后续描述为实施本申请的较佳实施方式，然所述描述乃以说明本申请的一般原则为目的，并非用以限定本申请的范围。本申请的保护范围当视所附权利要求所界定者为准。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者系统不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者系统所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者系统中还存在另外的相同要素。
本申请的应用场景
本申请的视频信号调节模块适用于视频处理系统内，此视频处理系统包括电性设置于电路板上的调谐器(Tuner)与视频解码器(Video decoder)，在这些调谐器与视频解码器的选购与安装上，一般会依据不同的使用需求以及视频信号的输出特性，而选择不同厂家型号的调谐器与视频解码器安装于电路板上。本申请的视频处理模块电性设置于电路板上，并且分别电性连接于调谐器与视频解码器之间，用以实现调谐器与视频解码器之间的阻抗匹配，从而让不同输出特性的视频信号的输出幅值(或幅度)均能达到标准值，而避免图像画面因为输出幅值降低而过暗的情形发生。
实施例描述
请参照图1，本申请实施例所揭示的视频信号调节模块10电性连接于视频处理系统的调谐器20与视频解码器30之间，视频信号调节模块10包括第一阻抗匹配电路110、第二阻抗匹配电路120、切换开关130以及处理单元140，其中第一阻抗匹配电路110与第二阻抗匹配电路120分别电性连接于调谐器20与视频解码器30之间，用以实现调谐器20与视频解码器30之间的阻抗匹配。切换开关130的一端电性连接于调谐器20，另一端连接于第一阻抗匹配电路110或第二阻抗匹配电路120，并且可选择性的在第一阻抗匹配电路110与第二阻抗匹配电路120之间切换，从而使调谐器20发送的视频信号可选择性的通过第一阻抗匹配电路110或第二阻抗匹配电路120传 送到视频解码器30。
处理单元140可以是但并不局限于中央处理器(central processing unit,CPU)或微控制器(micro-controller unit,MCU)等。处理单元140分别电性连接于切换开关130与视频解码器30，用以从视频解码器30接收处理后的视频信号，并且判断此视频信号的输出幅值是否低于标准值，例如，若输出幅值符合标准值，处理单元140即判断当前的阻抗匹配电路(例如第一阻抗匹配电路110)适于实现调谐器20与视频解码器30之间的阻抗匹配，也就不用发送切换信号至切换开关130，因此，切换开关130不动作；反之，若输出幅值低于标准值，处理单元140判断当前的阻抗匹配电路不适合连接调谐器20与视频解码器30，于是发送切换信号至切换开关130，使切换开关130依据切换信号切换至另一阻抗匹配电路(例如第二阻抗匹配电路120)，从而让视频信号在调谐器20与视频解码器30之间通过第二阻抗匹配电路120的传送而维持稳定的，并且符合标准值的输出幅度，让视频信号在通过后端的处理程序后，可以在显示器(例如电视屏幕)上呈现符合视频标准的画面图像。
以下通过优选实施例对本申请的视频信号调节模块10做进一步说明。如图2所示，在本实施例所揭示的视频信号调节模块10中，第一阻抗匹配电路110电性连接于调谐器20与视频解码器30之间，用以实现调谐器20与视频解码器30之间的阻抗匹配。第一阻抗匹配电路110为符合75欧姆(ohm,Ω)组抗匹配标准的阻抗匹配电路，其包括第一电阻R1、第二电阻R2与第一电容C1，第一电容C1电性连接于第一电阻R1与视频解码器30之间；第一电阻R1与第一电容C1串联；第二电阻R2与第一电阻R1并联，并且接地(GND)，其中第一电阻R1的电阻值与第二电阻R2的电阻值的和等于75欧姆，因此第一电阻R1的电阻值可以是小于第二电阻R2的电阻值；或者是大于或等于第二电阻R2的电阻值，在本实施例中，是以第一电阻R1的电阻值小于第二电阻R2的电阻值作为举例说明，例如第一电阻R1为24欧姆电阻，第二电阻R2为51欧姆电阻，但并不以此为限。而第一电容C1的电容值介于0.1μF(微法)～10μF，其中较大的电容值对于滤除低频干扰有较好的作用，较小的电容值则有助于缩短信号的上升沿与下降沿时间。在本实施例中，是以第一电容C1为0.1μF电容作为举例说明。因此，使第一阻抗匹配电路110 通过第一电阻R1、第二电阻R2和第一电容C1的配置方式构成75欧姆组抗匹配电路。
同样地，第二阻抗匹配电路120电性连接于调谐器20与视频解码器30之间，用以实现调谐器20与视频解码器30之间的阻抗匹配。第二阻抗匹配电路120包括相互串联的第三电阻R3与第二电容C2，并且第二电容C2电性连接于第三电阻R3与视频解码器30之间，其中第二电容C2的电容值同样介于0.1μF～10μF，在本实施例中，第二电容C2与第一电容C1是采用同样电容值的电容，以便于让信号通过第一阻抗电路110或第二阻抗电路120时具有相同的沿时间。可以理解的是，在本申请的其他实施例中，第一电容C1与第二电容C2也可以是具有不同电容值的电容，并不以上述实施例为限。
此外，在本实施例中，第二阻抗匹配电路120的第三电阻R3的电阻值与电路上所配置的视频处理芯片(例如调谐器芯片)的特性相对应。由于传统的视频处理芯片一般都适用于75欧姆阻抗匹配标准的电路上，惟，随着电子科技的不断进步，目前有许多高效能的视频处理芯片被开发出来，虽然这些视频处理芯片的整体效能超越了传统的视频处理芯片，但是为了符合现今微小化的趋势或其他需求而对其内部架构进行调整，导致这些视频处理芯片所输出的视频信号幅值恰好匹配于700±30mV的标准值，或者是超过标准值的幅度不高。因此，当这些视频处理芯片搭配75欧姆阻抗匹配电路使用时，其视频信号的输出幅值容易受到75欧姆阻抗匹配电路中接地的电阻干扰，使输出幅值被拉低，例如从700mV下降至400mV，导致后端显示器的画面太暗，而不符合视频指标所规范的标准。在此情形下，适用于本申请的方案。
此外，对于生产端而言，其作业流程只会将视频处理芯片组装在电路板上，并不会特意的去检视视频处理芯片是否适于搭配75欧姆阻抗匹配标淮的电路，从而导致产品良率不高的问题发生。而本申请的视频信号调节系统10同时提供了第一阻抗匹配电路110与第二阻抗匹配电路120，可依据视频处理芯片所输出的视频信号幅值，在第一阻抗匹配电路110与第二阻抗匹配电路120之间自动切换，而同时适用于传统的视频处理芯片以及后续开发出的高效能视频处理芯片，从而解决上述问题，而提升产品的生产效率。
基于上述，第二阻抗匹配电路120的第三电阻R3的电阻值可以是与第一电阻R1或第二电阻R2的电阻值相同或相异，例如第三电阻R3的电阻值可以是但并不局限于小于第二电阻R2的电阻值的配置方式，在本实施例中，是以第三电阻R3的电阻值与第一电阻R1的电阻值相等的配置方式作为举例说明，如此，除了可以实现调谐器20与视频解码器30之间的阻抗匹配，避免视频信号的输出幅值在传送过程中衰减外，也可以降低电路上元器件(如电阻)的采购成本以及提升电路配置上的便利性。
请参照图2，切换开关130的一端电性连接于调谐器20，另一端可选择性的在第一阻抗匹配电路110与第二阻抗匹配电路120之间切换，也就是可选择性的电性连接于第一阻抗匹配电路110的第一电阻R1，从而与第一阻抗匹配电路110之间形成闭路，以及与第二阻抗匹配电路120之间形成开路，使调谐器20发送的视频信号通过切换开关130与第一阻抗匹配电路110传送到视频解码器30；或者是选择性的电性连接于第二阻抗匹配电路120的第三电阻R3，从而与第二阻抗匹配电路120之间形成闭路，以及与第一阻抗匹配电路110之间形成开路，使调谐器20发送的视频信号通过切换开关130与第二阻抗匹配电路120传送到视频解码器30。
处理单元140分别电性连接于切换开关130与视频解码器30，用以接收和判断视频解码器30处理后的视频信号的输出幅值是否低于标准值，若是，处理单元140控制切换开关130与第一阻抗匹配电路110的第一电阻R1之间形成开路，以及与第二阻抗匹配电路120的第三电阻R3之间形成闭路，让视频信号在通过第二阻抗匹配电路120的传送后，其输出幅值能达到标准值；反之，若视频信号的输出幅值已经匹配于标准值，则切换开关130不动作，维持视频信号通过第一阻抗匹配电路110传送的初始模式(或默认模式)。
下面以一实施例对本申请方法的实现作进一步说明。如图3所示，为本申请实施例的视频信号调节方法流程图，包括：
步骤S10，通过调谐器输出视频信号。
步骤S20，通过视频信号调节模块的切换开关与第一阻抗匹配电路传送视频信号至视频解码器。
步骤S30，通过视频解码器接收和处理视频信号，并且输出处理后的视 频信号。
步骤S40，通过视频信号调节模块的处理单元接收和判断处理后的视频信号的输出幅值是否低于一标准值。
步骤S41，若是，处理单元控制切换开关与第一阻抗匹配电路之间形成开路，以及控制切换开关与视频信号调节模块的第二阻抗匹配电路之间形成闭路，使视频信号通过第二阻抗匹配电路提高输出幅值至标准值。
步骤S42，若否，切换开关不动作。
请参照图2和图3，调谐器20输出的视频信号可以是但并不局限于复合视频(composite-video)、超级视频(super-video)、模拟分量视频(RGBHV video)、VGA视频(video graphics array)、工作站视频(IBM PowerPC/Sun Color)或数字符串行视频(signal-digital interface)等视频信号(请发明人协助确认这些信号格式是否都适用)，在本申请实施例中，是以视频信号为标准复合视频信号(composite video broadcast signal,CVBS)作为举例说明，但并不以此为限。
此外，在本实施例中，切换开关130被设置为常态的与第一阻抗匹配电路110之间形成闭路，以及与第二阻抗匹配电路120之间形成开路。因此，当调谐器20输出视频信号后(步骤S10)，此视频信号通过视频信号调节模块10的切换开关130与第一阻抗匹配电路110传送至视频解码器30(步骤S20)。接着，通过视频解码器30接收与处理视频信号，并将处理后的视频信号输出至处理单元140(步骤S30)。此时，处理单元140接收处理后的视频信号，并且判断视频信号的输出幅值是否低于标准值(步骤S40)，例如输出幅度为700±30mV的标准值。
若处理单元140判断视频信号的输出幅值低于标准值，表示视频信号的输出幅值受到调谐器20的输出特性影响，而在输出时便无法拉高，从而在传送过程中受到第一阻抗匹配电路110中接地的第二电阻R2拉低，而导致输出幅度的降低。此时，处理单元140即传送切换信号至切换开关130，控制切换开关130从第一阻抗匹配电路110切换至第二阻抗匹配电路120，通过第二阻抗匹配电路120的第三电阻R3与第二电容C2的串联，实现调谐器20与视频处理器30之间的阻抗匹配，使负载电阻跟信号源内阻相等，从而使视频信号的输出幅度在视频信号的传送过程中维持于标准值(步骤S40)。 例如当图像调制度为87.5％时，调谐器输出的标准复合视频信号(CVBS)的输出幅度能达到700mV。并且，在各视频指标的测试上，例如同步脉冲幅度、亮度非线性、K系数(2T脉冲)、微分增益、微分相位、色度-亮度增益差、色度-亮度延时差、幅频特性以及随机信噪比等，也能满足各项性能指针的测试标准值。
反之，若处理单元140判断视频信号的输出幅值符合标准值，表示第一阻抗匹配电路110适于在当前的调谐器20与视频处理器30之间实现阻抗匹配，此时处理单元140不发送切换信号至切换开关130，因此切换开关130不动作(步骤S42)。
上述说明示出并描述了本申请的若干优选实施例，但如前所述，应当理解本申请并非局限于本文所披露的形式，不应看作是对其他实施例的排除，而可用于各种其他组合、修改和环境，并能够在本文所述发明构想范围内，通过上述教导或相关领域的技术或知识进行改动。而本领域人员所进行的改动和变化不脱离本申请的精神和范围，则都应在本申请所附权利要求的保护范围内。

Claims (12)

  1. 一种视频信号调节模块，适用于视频处理系统内，所述视频处理系统包括调谐器与视频解码器，其特征在于，所述视频信号调节模块包括：
    第一阻抗匹配电路，电性连接于所述调谐器与所述视频解码器之间，配置为实现所述调谐器与所述视频解码器之间的阻抗匹配；
    第二阻抗匹配电路，电性连接于所述调谐器与所述视频解码器之间，配置为实现所述调谐器与所述视频解码器之间的阻抗匹配；
    切换开关，其一端电性连接于所述调谐器，另一端可选择性的电性连接于所述第一阻抗匹配电路或所述第二阻抗匹配电路；以及
    处理单元，分别电性连接于所述切换开关与所述视频解码器；
    其中，所述调谐器发送的视频信号通过所述切换开关与所述第一阻抗匹配电路传送至所述视频解码器，所述处理单元接收及判断所述视频解码器处理后的所述视频信号的输出幅值是否低于标准值，若是，所述处理单元控制所述切换开关与所述第一阻抗匹配电路之间形成开路，以及与所述第二阻抗匹配电路之间形成闭路，若否，所述切换开关不动作。
  2. 如权利要求1所述的视频信号调节模块，其特征在于，
    所述第一阻抗匹配电路包括第一电容、第一电阻与第二电阻，所述第一电容电性连接于所述第一电阻与所述视频解码器之间，所述第一电阻与所述第一电容串联，所述第二电阻与所述第一电阻并联，并且接地，其中所述第一电阻的电阻值与所述第二电阻的电阻值的和为75欧姆。
  3. 如权利要求2所述的视频信号调节模块，其特征在于，
    所述第一电阻为24欧姆电阻，所述第二电阻为51欧姆电阻。
  4. 如权利要求2所述的视频信号调节模块，其特征在于，
    所述第一电容的电容值介于0.1μF～10μF。
  5. 如权利要求1所述的视频信号调节模块，其特征在于，
    所述第二阻抗匹配电路包括相互串联的第二电容与第三电阻，所述第二电容电性连接于所述第三电阻与所述视频解码器之间，其中所述第三电阻的 电阻值小于所述第二电阻的电阻值。
  6. 如权利要求5所述的视频信号调节模块，其特征在于，
    所述第二电容的电容值介于0.1μF～10μF，所述第三电阻为24欧姆电阻。
  7. 如权利要求1所述的视频信号调节模块，其特征在于，
    所述视频信号为标准复合视频信号。
  8. 一种视频信号调节方法，适用于视频处理系统，所述视频处理系统包括调谐器与视频解码器，其特征在于，所述视频信号调节方法包括：
    通过所述调谐器输出视频信号；
    通过视频信号调节模块的切换开关与第一阻抗匹配电路传送所述视频信号至所述视频解码器；
    通过所述视频解码器接收和处理所述视频信号，并且输出处理后的所述视频信号；以及
    通过视频信号调节模块的处理单元接收和判断处理后的所述视频信号的输出幅值是否低于标准值；若是，所述处理单元控制所述切换开关与所述第一阻抗匹配电路之间形成开路，以及控制所述切换开关与所述视频信号调节模块的第二阻抗匹配电路之间形成闭路，使所述视频信号通过所述第二阻抗匹配电路提高所述输出幅值至所述标准值；若否，所述切换开关不动作。
  9. 如权利要求8所述的视频信号调节方法，其特征在于，
    通过视频信号调节模块的所述切换开关与所述第一阻抗匹配电路传送所述视频信号至所述视频解码器的操作中，所述调谐器与所述视频解码器之间通过所述第一阻抗匹配电路实现75欧姆阻抗匹配。
  10. 如权利要求9所述的视频信号调节方法，其特征在于，
    所述调谐器与所述视频解码器之间通过所述第一阻抗匹配电路的第一电阻、第二电阻与第一电容实现75欧姆阻抗匹配，其中所述第一电阻与所述第一电容串联，所述第二电阻与所述第一电阻并联，并且接地。
  11. 如权利要求10所述的视频信号调节方法，其特征在于，
    所述第一阻抗匹配电路的所述第一电阻的电阻值小于所述第二电阻的 电阻值。
  12. 如权利要求8所述的视频信号调节方法，其特征在于，
    通过所述第二阻抗匹配电路提高所述输出幅值至所述标准值的操作中，所述调谐器与所述视频解码器之间通过所述第二阻抗匹配电路的第三电阻与第二电容实现阻抗匹配，其中所述第三电阻与所述第二电容串联。
PCT/CN2014/093189 2013-12-06 2014-12-05 视频信号调节模块及调节方法 Ceased WO2015081894A1 (zh)

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