WO2015076025A1 - Distortion correction device, amplifier device, and wireless communication device - Google Patents

Abstract

This distortion correction device (14) comprises a distortion correction unit (3) which carries out a distortion correction of an amplifier (2) which amplifies a signal (x), and an A/D converter (11) which A/D converts an output signal (y) outputted by the amplifier (2) and provides the same to the distortion correction unit (3). The A/D converter (11) A/D converts the output signal (y) at a low sampling rate which is lower than a sampling rate of a D/A converter (4) which D/A converts a signal which is provided to the amplifier (2). The distortion correction unit (3) carries out the distortion correction on the basis of the signal (x) and the output signal (y) which is A/D converted at the low sampling rate.

Description

Distortion compensation device, amplification device, and wireless communication device

The present invention relates to a distortion compensation device, an amplification device, and a wireless communication device.

In recent years, in a wireless communication system used for a mobile phone or the like, a high-speed and wide-band communication method such as LTE (Long Term Evolution) is spreading (for example, see Patent Document 1).

JP2010-211981

In LTE, the maximum system bandwidth is about 20 MHz, but in LTE-A (Advanced), which is an LTE successor system, the system bandwidth is scheduled to be expanded to about 100 MHz. .
For this reason, the amplification device of the base station apparatus used in the wireless communication system needs to cope with a wide band, and there is a concern about an increase in component costs accompanying the wide band.

On the other hand, in the LTE-A, a small cell is actively introduced for the purpose of increasing the communication capacity. Therefore, a low-cost amplifying device is required as an amplifying device used for a small base station device corresponding to the small cell. It has been.

In the amplifying apparatus for small base station apparatus corresponding to the above small cell, there is a problem that further cost reduction is required even though there is a concern that the cost of parts is increased due to the wide band due to the adoption of LTE-A. have.

The present invention has been made in view of such circumstances, and an object thereof is to provide an amplifying apparatus and a wireless communication apparatus that can be further reduced in cost.

A distortion compensation apparatus according to an embodiment includes: a distortion compensation unit that performs distortion compensation of an amplifier that amplifies an input signal; and an AD converter that AD-converts an output signal output from the amplifier and supplies the signal to the distortion compensation unit. The AD converter performs AD conversion on the output signal at a low sampling rate lower than a sampling rate when DA conversion is performed on a signal supplied to the amplifier, and the distortion compensator includes the input signal, Distortion compensation is performed based on the output signal AD-converted at a low sampling rate.

In addition, an amplification device according to an embodiment includes an amplifier and the distortion compensation device.

Also, a wireless communication apparatus according to an embodiment includes the amplifying apparatus for amplifying communication signals.

According to the distortion compensating device, the amplifying device, and the wireless communication device of the present invention, the cost can be further reduced.

It is a block diagram which shows the principal part of the radio | wireless communication apparatus provided with the amplifier which concerns on embodiment. It is a flowchart which shows the procedure of the delay adjustment process which the delay process part which concerns on 1st Embodiment performs. It is the graph which showed an example of the result obtained by performing a simulation about the case where the delay error estimation value is repeatedly calculated immediately after the delay processing unit of the first embodiment starts the operation. It is a flowchart which shows the procedure of the process which performs the delay adjustment which the delay process part which concerns on 2nd Embodiment performs. FIG. 5 is a flowchart illustrating a procedure of delay adjustment processing in FIG. 4. It is the graph which showed an example of the result obtained by performing simulation about the case where the delay processing part of a 2nd embodiment performed delay adjustment processing. It is a block diagram which shows the principal part of the radio | wireless communication apparatus which concerns on the modification of 2nd Embodiment. It is a figure which shows an example of the frequency spectrum of the OFDM signal amplified by the amplifier which concerns on other embodiment. It is a figure which shows an example of the frequency spectrum of the OFDM signal amplified by the amplifier which concerns on 1st Embodiment. It is a figure which shows an example of the frequency spectrum of the OFDM signal amplified by the amplifier which concerns on 2nd Embodiment.

[Description of Embodiment]
2. Description of the Related Art In general, an amplification device used in a wireless communication device of a wireless communication system includes a distortion compensation device that performs distortion compensation of an amplifier by digital signal processing. This distortion compensation device includes an AD converter that converts an analog output signal into a digital signal in order to acquire an analog output signal output from the amplifier as a feedback signal. If the bandwidth of the output signal to be converted becomes large, this AD converter must use a higher sampling rate accordingly, and the bandwidth of the radio signal may increase the cost of the AD converter. There is.

First, the contents of the embodiment will be listed and described.
(1) A distortion compensation apparatus according to an embodiment includes a distortion compensation unit that performs distortion compensation of an amplifier that amplifies an input signal, and an AD converter that AD-converts an output signal output from the amplifier and supplies the output signal to the distortion compensation unit The AD converter performs AD conversion on the output signal at a sampling rate lower than a sampling rate when DA conversion is performed on a signal supplied to the amplifier, and the distortion compensator includes the input signal. And distortion compensation based on the output signal AD-converted at the low sampling rate.

According to the distortion compensation apparatus configured as described above, the AD converter AD-converts the output signal at a low sampling rate lower than the sampling rate when the signal supplied to the amplifier is DA-converted, and the distortion compensation unit Performs distortion compensation based on an input signal and an output signal that has been AD-converted at a low sampling rate. Therefore, even when processing a wideband signal, AD conversion with a higher sampling rate is performed according to the wideband signal. Since it is not necessary to use a vessel, the cost can be reduced.

(2) The number of samples of the output signal may be relatively smaller than that when AD conversion is performed at the same sampling rate as that at the time of DA conversion by AD conversion at a low sampling rate. For this reason, it is preferable that the distortion compensation unit estimates a model of the amplifier based on the input signal and the output signal AD-converted at the low sampling rate, and performs distortion compensation based on the model. .
In this case, even if the output signal has a low sampling rate, distortion compensation can be performed without reducing accuracy by extending the observation period accordingly.

(3) When the distortion compensation apparatus further includes a filter connected between the amplifier and the AD converter, a pass bandwidth of the filter is equal to or greater than a frequency bandwidth of the input signal. It is preferable that it is set to.
In this case, since the pass band width of the filter becomes larger than the low sampling rate that is the sampling rate of the AD converter, not only the signal component of the band acquired by the low sampling rate but also the signal component of the output signal. The signal in the peripheral band is also given to the AD converter as a folding component. As a result, the AD converter can acquire not only the signal component in the band acquired at the low sampling rate but also the signal in the peripheral band of the signal component as the folded component.
As a result, it is possible to obtain signal components that are generated due to distortion generated in the output signal without losing information on the signal components that appear in the adjacent band of the output signal, so that distortion compensation is performed without reducing accuracy. Can do.

(4) In the distortion compensator, a delay error generated between the timing of the output signal AD-converted at the low sampling rate and the timing of the input signal is determined from the length of the period corresponding to the low sampling rate. It is preferable to further include a delay processing unit that estimates and corrects in units of a small period.
In this case, although the output signal is AD-converted at a low sampling rate, the delay error can be estimated in a unit of a period smaller than the length of the cycle corresponding to the low sampling rate. The delay error can be corrected with higher accuracy than the period length.

(5) In the distortion compensation device, the delay processing unit obtains an estimated value of the delay error for each of a plurality of different predetermined periods, and obtains the estimated value of each delay error for each of the plurality of predetermined periods. The obtained representative value may be obtained as the estimated value of the delay error.
In this case, since the true value of the delay error does not vary greatly with time, even if there is a variation in the estimated value of each delay error for a plurality of predetermined periods, the representative value can be obtained from the estimated value of each delay error. The delay error estimation value can be obtained in units of periods smaller than the length of the period corresponding to the sampling rate of the AD converter, and as a result, the delay error can be obtained more accurately.

(6) (7) In the distortion compensation device, the delay processing unit changes the delay error by a predetermined unit time, and changes the delay error every time the delay error is changed by the predetermined unit time. A residual between the output signal after being changed and the input signal is obtained, and the delay based on the magnitude of the residual is selected from the delay errors changed by the predetermined unit time. An error estimate may be determined.
In this case, an estimated value of delay error can be obtained in units of unit time.
For this reason, it is preferable that the predetermined unit time is shorter than a period corresponding to the low sampling rate.
Thereby, the estimated value of the delay error can be obtained in a unit of a period smaller than the length of the cycle corresponding to the low sampling rate, and the estimated value of the delay error can be obtained more accurately.

(8) The delay processing unit can change a delay error between the timing of the output signal and the timing of the input signal by digital processing, but adjusts the phase of the operation clock supplied to the AD converter. Thus, the delay error can be changed by adjusting the timing of the output signal.
In this case, the delay processing unit can change the delay error between the timing of the output signal and the timing of the input signal by analog processing, and can reduce the load on the delay processing unit.

(9) Further, in the above distortion compensation device, if there is a delay that occurs when the distortion compensation unit performs distortion compensation, a delay error that occurs between the timing of the output signal and the timing of the input signal, which is obtained by the delay processing unit. The accuracy of the estimated value may be reduced.
For this reason, the distortion compensator is configured to provide a compensation signal obtained by performing distortion compensation on the input signal to the amplifier, and the delay processing unit includes the timing of the input signal and the timing of the compensation signal. It is preferable to correct a delay error occurring between the two.
In this case, the delay processing unit can correct a delay error that occurs between the timing of the input signal and the timing of the compensation signal. Thereby, it is possible to suppress the influence of the delay that occurs during distortion compensation on the accuracy of the estimated value of the delay error that occurs between the timing of the output signal and the timing of the input signal.

(10) In the distortion compensation apparatus, the low sampling rate may be set lower than the frequency bandwidth of the input signal. In this case, the low sampling rate can be set to a lower value, and the cost is low. Is more advantageous.

(11) In the distortion compensation apparatus, the pass band width of the filter may be set to be equal to or greater than a frequency bandwidth of a distortion component generated in the output signal when the amplifier amplifies the input signal. Thus, it is possible to more effectively acquire signal component information that is generated due to distortion generated in the output signal and that appears in the adjacent band of the output signal.

(12) Further, an amplifying apparatus according to an embodiment includes an amplifier and the distortion compensating apparatus according to (1) above.

(13) In addition, a wireless communication apparatus according to an embodiment includes the amplifying apparatus described in (12) above for amplifying a communication signal.

According to the amplification device and the wireless communication device configured as described above, even when processing a wideband signal in the distortion compensation device, it is not necessary to use an AD converter having a higher sampling rate in accordance with the wideband signal. Cost reduction is possible.

[Details of the embodiment]
Hereinafter, preferred embodiments will be described with reference to the drawings.
[1. Configuration of main part of wireless communication device]
FIG. 1 is a block diagram illustrating a main part of a wireless communication device including an amplification device according to an embodiment. In the figure, the wireless communication device includes an amplifying device 1 for amplifying a transmission signal transmitted as a wireless signal. Note that the amplifying apparatus 1 may be used for amplification of a received signal.

The amplifying apparatus 1 includes a high-power amplifier (HPA, hereinafter simply referred to as an amplifier) 2 and a distortion compensator 3.
The distortion compensation unit 3 has a function of performing distortion compensation processing by digital signal processing on a signal x that is a transmission signal given as a digital signal. The distortion compensator 3 outputs a compensation signal u by distortion compensation processing.

A DA converter (DAC) 4 for converting a digital signal into an analog signal and an up converter 5 are connected between the distortion compensation unit 3 and the signal input terminal of the amplifier 2.
The compensation signal u output from the distortion compensator 3 is converted to an analog signal by being applied to the DAC 4, and further up-converted to a radio frequency by being multiplied by the radio frequency local signal generated by the oscillator 6 by the up-converter 5. After being converted, it is supplied to the amplifier 2.
The amplifier 2 amplifies the input compensation signal u. An antenna 7 is connected to the signal output terminal of the amplifier 2, and the output signal y output from the amplifier 2 is radiated from the antenna 7 as a radio transmission signal.

Between the signal output terminal of the amplifier 2 and the distortion compensator 3, a coupler 8, a down converter 9, a filter unit 10, and an AD converter 11 for obtaining an output signal y output from the amplifier 2 are provided. It is connected.
The output signal y of the amplifier 2 obtained from the coupler 8 is given to the down converter 9.
The output signal y is down-converted to a baseband frequency by multiplying the local signal of the baseband frequency generated by the oscillator 6 by the downconverter 9, and then the AD converter (ADC) 11 through the filter unit 10. Given to.

The ADC 11 converts the output signal y into a digital signal at a low sampling rate that is lower than the sampling rate when the DAC 4 converts the compensation signal u into an analog signal.
In the present embodiment, if the frequency bandwidth of the signal x amplified by the amplifier 2 is 100 MHz, for example, the sampling rate of the DAC 4 is set to 614.4 MHz. Therefore, the low sampling rate that is the sampling rate of the ADC 11 is set to a frequency lower than 614.4 MHz.
The frequency bandwidth of the main signal component of the signal x is 20 MHz.

Furthermore, the low sampling rate is preferably set lower than the frequency bandwidth of the signal x.
When the frequency bandwidth of the signal x is 100 MHz, the low sampling rate that is the sampling rate of the ADC 11 can be set to 15.36 MHz that is a value lower than 100 MHz, for example.

Here, the signal x as the digital signal and the output signal y are signals composed of sample data discretized at a predetermined sampling rate.
Therefore, the output signal y converted into a digital signal is constituted by a sample sequence discretized by a low sampling rate that is a frequency lower than 614.4 MHz.

The filter unit 10 provided in the front stage of the ADC 11 is a low-pass filter, and the pass bandwidth is set to be equal to or larger than the frequency bandwidth of the signal x. Note that the pass bandwidth of the filter unit 10 of the present embodiment is set to about 6 times the frequency bandwidth of the signal x, and is set so as to pass up to the fifth-order distortion of the signal x.

The DAC 4, up-converter 5, oscillator 6, amplifier 2, antenna 7, coupler 8, down-converter 9, filter unit 10, and ADC 11 receive the compensation signal u that is a digital signal and convert it into an analog signal, then necessary It is included in an analog processing unit 12 that performs analog signal processing.

The distortion compensation unit 3 is included in a digital processing unit 13 that provides a compensation signal u, which is a digital signal, to the analog processing unit 12.
The distortion compensator 3 is supplied with a signal x as an input signal amplified by the amplifier 2 and an output signal y converted into a digital signal by the ADC 11. The distortion compensation unit 3 performs distortion compensation based on these signals.

[2. About distortion compensation device)
The distortion compensation unit 3 accepts the output signal y obtained from the coupler 8 as a feedback signal via the filter unit 10, ADC 11, etc., and estimates the model of the amplifier 2 based on the output signal y and the signal x, Based on the model estimated by the digital signal processing, distortion compensation of the amplifier 2 is performed.

That is, in this embodiment, the distortion compensation unit 3, the filter unit 10, and the ADC 11 constitute a distortion compensation device 14 that receives the output signal y as a feedback signal and compensates for distortion of the signal x.

The distortion compensation unit 3 includes a compensation processing unit 20 that performs predistortion processing on the signal x, a coefficient calculation unit 21 that calculates a coefficient (distortion compensation coefficient) in the model of the amplifier 2, and an input / output signal. Are provided with a delay processing unit 22 that performs a process for correcting a delay error and a delay adjustment unit 23 that adjusts the signal timing of the signal x supplied to the coefficient calculation unit 21 to adjust the delay.

The compensation processing unit 20 performs predistortion processing using a model representing the compensation signal u that has been subjected to distortion compensation for the given signal x.
Specifically, the compensation processing unit 20 performs the predistortion compensation process by obtaining the compensation signal u [n] from the signal x [n] using, for example, a model represented by the following formula (1). Note that n is a number indicating the order of the sample sequence constituting the signal x which is a digital signal discretized at a predetermined sampling rate.

The above equation (1) is a generalization of an amplifier model called a Hammerstein model, and is also called a memory polynomial model.
In the above equation (1), h _{k, l} is a coefficient (DPD coefficient) necessary for determining the characteristics of the compensation signal u [n], and is expressed as the following equation (2).

The compensation processing unit 20 of the present embodiment applies the signal x [n] and the DPD coefficient to the model shown in Expression (1) to obtain the compensation signal u [n].
The DPD coefficient is given from the coefficient calculation unit 21.
When the DPD coefficient is given from the coefficient calculation unit 21, the compensation processing unit 20 updates the DPD coefficient in the model to a new DPD coefficient given from the coefficient calculation unit 21, and obtains a compensation signal u [n].

In the present embodiment, an example in which the Hammerstein model is used as the amplifier model is shown, but another model, for example, a Wiener model or a Wiener-Hammerstein model can also be used.

The coefficient calculation unit 21 has a function of calculating a DPD coefficient and a function of updating the DPD coefficient by supplying the calculated DPD coefficient to the compensation processing unit 20.
The coefficient calculation unit 21 is supplied with an output signal y converted into a digital signal by the ADC 11 and a signal x given through the delay adjustment unit 23.
The coefficient calculation unit 21 obtains a residual Res between the signal x and the output signal y as shown in the following formula (3).
Residual Res = y−x (3)

Since the signal y is AD-converted at a low sampling rate lower than the sampling rate of the DAC 4, for example, when the sampling rate (low sampling rate) of the ADC 11 is lower than the sampling rate of the signal x, the signal x is There is a possibility that there is a sample in which the sample of the corresponding output signal y does not exist on the time axis in the sample sequence. The coefficient calculation unit 21 of the present embodiment does not obtain a residual for a sample in which there is no sample of the corresponding output signal y on the time axis in the sample sequence of the signal x, and when there are samples corresponding to each other. It is configured to obtain the residual Res.

The coefficient calculation unit 21 refers to the previously calculated DPD coefficient, and can compensate for the new DPD coefficient that can minimize the mean square of the residual Res, that is, the distortion between the signal x and the output signal y as much as possible. The coefficient is obtained recursively.

As described above, in this embodiment, the above-described distortion compensation model is estimated by obtaining the DPD coefficient from the signal x as the input signal amplified by the amplifier 2 and the output signal y output from the amplifier 2. The so-called direct learning method is adopted.

In the distortion compensation device 14 configured as described above, the ADC 11 AD-converts the output signal y at a low sampling rate, and the distortion compensation unit 3 generally includes a signal x sampled at a sampling rate higher than the low sampling rate, Since distortion compensation is performed based on the output signal y AD-converted at a low sampling rate, it is not necessary to use the ADC 11 having a higher sampling rate in accordance with the wideband signal when processing a wideband signal. Cost reduction is possible.

As described above, the low sampling rate may be set lower than the frequency bandwidth of the signal x. In this case, the low sampling rate can be set to a lower value, which is advantageous for cost reduction. It is.

The number of samples of the output signal y may be relatively smaller than that when AD conversion is performed at the same sampling rate as that at the time of DA conversion due to AD conversion at a low sampling rate. In this regard, since the direct learning method is employed in this embodiment, even if the output signal has a low sampling rate, distortion compensation can be performed without reducing accuracy by extending the observation period accordingly. it can.

Further, in the present embodiment, the pass bandwidth of the filter unit 10 connected between the amplifier 2 and the ADC 11 is set to be equal to or less than the frequency bandwidth of the signal x.
In this case, since the pass bandwidth of the filter unit 10 is larger than the sampling rate of the ADC 11, not only the signal component of the band acquired by the low sampling rate but also the signal of the peripheral band of the signal component in the output signal y. Is also given to the ADC 11 as a folding component. As a result, the ADC 11 can acquire not only the signal component in the band acquired at the low sampling rate but also the signal in the peripheral band of the signal component as the folded component.
As a result, it is possible to obtain signal components that are generated due to distortion generated in the output signal without losing information on the signal components that appear in the adjacent band of the output signal, so that distortion compensation is performed without reducing accuracy. Can do.

Note that, as described above, the pass bandwidth of the filter unit 10 of the present embodiment is set to about 6 times the frequency bandwidth of the signal x, and is set to pass up to the fifth-order distortion of the signal x. .
As described above, the pass bandwidth of the filter unit 10 may be set to be equal to or greater than the frequency bandwidth of the distortion component (fifth-order distortion) generated in the output signal y when the amplifier 2 amplifies the signal x. Thus, it is possible to more effectively acquire information on signal components that are generated by distortion generated in the output signal y and appear in the adjacent band of the output signal y.

The delay adjusting unit 23 has a function of adjusting the timing of the signal x given to the coefficient calculating unit 21. The delay adjusting unit 23 adjusts the timing of the signal x based on the information regarding the estimated value of the delay error given from the delay processing unit 22.

The signal x and the output signal y supplied to the coefficient calculation unit 21 need to be supplied to the coefficient calculation unit 21 with the timings of both signals matched as much as possible so that the samples corresponding to each other are processed. This is because an accurate DPD coefficient cannot be obtained unless calculation is performed between samples corresponding to each other.

The output signal y passes through the filter unit 10 and the ADC 11 of the analog processing unit 12 and reaches the coefficient calculation unit 21. Therefore, the output signal y reaches the coefficient calculator 21 with a delay from the signal x.
For this reason, the delay adjustment unit 23 acquires the signal x from the previous stage of the compensation processing unit 20, and adjusts the timing of the acquired signal x, thereby giving the timing of the output signal y when given to the coefficient calculation unit 21. And a delay error occurring between the timing of the signal x and the timing of the signal x are corrected.

Here, in general, the delay error between the input signal to be amplified and the feedback signal when performing distortion compensation falls within a range of about 1.6 ns (614.4 MHz) if the signal has a frequency bandwidth of 100 MHz. It is necessary to perform correction so as to achieve accuracy, and by correcting the delay in this way, it is possible to maintain the accuracy required in the distortion compensation processing. Note that the delay error between the input signal and the feedback signal is obtained based on the correlation value of both signals.

When the feedback signal (amplifier output signal) is AD-converted at the same sampling rate as the DA conversion of the input signal amplified by the amplifier, a delay error between the input signal timing and the feedback signal timing Can be estimated and corrected with high accuracy. The sampling rate for DA conversion of the input signal is set to a frequency that can accurately correct the delay error (for example, about 5 to 6 times the frequency bandwidth of the signal), and the delay error has the same accuracy. This is because it can be estimated.

However, in the distortion compensation device 14 (distortion compensation unit 3) of the present embodiment, the output signal y AD-converted at a low sampling rate and the signal x that is generally sampled at a sampling rate higher than the low sampling rate. Therefore, if a delay error between the timing of the signal x and the timing of the output signal y is estimated and corrected, the accuracy is finer than the length of the period corresponding to the low sampling rate. There is a possibility that the delay error cannot be estimated and corrected.

For example, if the frequency bandwidth of the signal x is 100 MHz, the sampling rate of the DAC 4 is set to about 600 MHz. Then, since the ADC 11 is set to a low sampling rate lower than 600 MHz, the delay error generated between the timing of the signal x and the timing of the output signal y is estimated in the unit of the length of the cycle of the sampling rate of 600 MHz. Can not do it.

In this regard, the delay processing unit 22 according to the present embodiment corresponds to an estimated value of the delay error generated between the timing of the output signal y AD-converted at the low sampling rate and the timing of the signal x to the low sampling rate. It can be determined and corrected in units of periods smaller than the length of the period.
That is, although the output signal y is AD converted at a low sampling rate, an estimated value of the delay error can be obtained in a unit of a period smaller than the length of the cycle corresponding to the low sampling rate. The delay error can be corrected more accurately with a finer accuracy than the corresponding period length.
As a result, it is possible to maintain the necessary accuracy in the distortion compensation process.
Hereinafter, the delay processing unit 22 will be described.

[3. Regarding Delay Processing Unit According to First Embodiment]
The delay processing unit 22 has a function of obtaining an estimated value of a delay error between the output signal y given to the distortion compensation unit 3 and the signal x. Further, the delay processing unit 22 gives the obtained delay error to the delay adjustment unit 23 as information on the delay error, and causes the delay adjustment unit 23 to adjust the timing of the signal x. In this way, the delay processing unit 22 obtains an estimated value of the delay error, and performs a delay adjustment process that corrects the delay error between the timing of the output signal y and the timing of the signal x.

The delay processing unit 22 has a function of controlling the coefficient calculation unit 21 and controlling the update of the DPD coefficient in the compensation processing unit 20. The delay processing unit 22 causes the coefficient calculation unit 21 to stop outputting the DPD coefficient as necessary in performing the delay adjustment process, or to stop updating the DPD coefficient in the compensation processing unit 20, or the coefficient calculation unit 21. It is possible to cause the compensation processing unit 20 to update the DPD coefficient by executing the output of the DPD coefficient.

The delay processing unit 22 is provided with the signal x acquired from the previous stage of the compensation processing unit 20 and the output signal y from the ADC 11. In addition, the delay processing unit 22 is also given a compensation signal u acquired from the subsequent stage of the compensation processing unit 20.
The delay processing unit 22 estimates the delay error between the timing of the output signal y and the timing of the input signal x (output signal) based on the output signal y and the signal x given to the delay processing unit 22. a first delay error estimator 22a for calculating a delay error estimate value of y).
In addition, the delay processing unit 22 is based on the signal x and the compensation signal u, between the timing of the input signal x resulting from the predistortion processing performed by the compensation processing unit 20 and the timing of the compensation signal u. A second delay error estimator 22b for calculating an estimated value of delay error (estimated value of delay error of DPD) is provided.

FIG. 2 is a flowchart showing a procedure of delay adjustment processing performed by the delay processing unit 22 according to the first embodiment. The flowchart shown in FIG. 2 shows a procedure immediately after the wireless communication device (distortion compensation device 14) is activated and the delay processing unit 22 starts its operation.

First, when starting the operation, the delay processing unit 22 sets the number of iterations I indicating the number of iterations of processing to “1” (step S101). As will be described later, the number of iterations I is incremented by “1” every time the processing loop is completed, and thus indicates the elapsed time since the start of the wireless communication apparatus (distortion compensation unit 3).
Next, the delay processing unit 22 acquires the signal x and the output signal y (step S102). At this time, the delay processing unit 22 acquires the sample sequences of the signal x and the output signal y included in the acquisition period as a predetermined period set to acquire the signal x and the output signal y.

Next, the delay processing unit 22 performs upsampling processing on the signal x and the output signal y (step S103). As will be described later, the signal x and the output signal y are used to obtain a correlation value with each other and to obtain an estimated value of delay error. Therefore, the upsampling process is performed on the signal x and the output signal y so that the sampling rate is equal to or higher than the sampling rate of the DAC 4 so that the correlation value can be obtained with higher accuracy.
Note that the magnification of the upsampling process can be set to about 100 times, for example. When the sampling rate (low sampling rate) of the ADC 11 is 15.36 MHz, the output signal y is up-sampled to a sampling rate of about 1.6 GHz.

After performing the upsampling process on the signal x and the output signal y, the delay processing unit 22 performs an operation for obtaining a delay error estimated value Δτ between the timing of the output signal y and the timing of the input signal x. The first delay error estimator 22a is executed.

The first delay error estimation unit 22a obtains a correlation value between the output signal y acquired in step S102 and the signal x, and based on the correlation value, the timing of the output signal y and the timing of the input signal x An estimated value of the delay error between the two is obtained by calculation (step S104).
The correlation value between the output signal y and the signal x is expressed by, for example, the following formula (4).
Correlation value R (τ) = x ^* (t−τ) × y (t) (4)

In the above equation (4), t is time, τ is a delay error (delay amount), and x ^* (t−τ) is a complex conjugate of x (t−τ).
The first delay error estimator 22a obtains the correlation value R (τ) based on the above equation (4), and calculates τ that maximizes the correlation value R (τ) as shown in the following equation (5). The delay error estimated value Δτ (I) of the output signal y is obtained.
Delay error estimate value Δτ (I) = argmax | R (τ) |
... (5)

In the above equation (5), Δτ (I) represents an estimated value of the delay error of the output signal y acquired in the acquisition period when the number of iterations is I.

Next, the delay processing unit 22 determines whether or not the number of iterations I is equal to or greater than a preset number of times W (step S105).
When determining that the number of iterations I is not equal to or greater than the set number of times W, the delay processing unit 22 adds “1” to the number of iterations I (step S106), returns to step S102, and an acquisition period different from the acquisition period in which the previous signal was acquired. The signal x and the output signal y are obtained, and the delay error estimated value Δτ (I) of the output signal y is obtained again (steps S102 to S104).
The delay processing unit 22 repeats steps S102 to S104 until the number of iterations I reaches the set number W, thereby obtaining the delay error estimated value Δτ (I) of the output signal y for each of a plurality of different acquisition periods.

On the other hand, if it is determined in step S105 that the number of iterations I is greater than or equal to the set number W, the delay processing unit 22 further determines whether or not the number of iterations I is the set number of times W (step S107).
If it is determined that the number of iterations I is the set number of times W, the delay processing unit 22 obtains the current delay error estimated value Δτ _I of the output signal y based on the following equation (6). As shown in the equation (6), the delay processing unit 22 calculates the delay error estimate Δτ (I of the output signal y for each iteration number I obtained from the iteration number I ranging from “1” to the set number W. ) (I = 1, 2, 3,... W) to obtain an average value of delay error estimated value Δτ _I of the current output signal y (step S108).
The estimated delay error value Δτ _{I of the} current output signal y
= (Δτ (1) + Δτ (2) + Δτ (3) +
+ Δτ (W)) / W
... (6)

Next, the delay processing unit 22 causes the second delay error estimating unit 22b to obtain an estimated value of the delay error caused by the processing by the compensation processing unit 20 (step S109).

The second delay error estimation unit 22b obtains a correlation value between the signal x and the compensation signal u, and based on this correlation value, a delay error between the timing of the input signal x and the timing of the compensation signal u. An estimated value Δi is obtained. The second delay error estimator 22b obtains a correlation value and obtains a DPD delay error estimate Δi. The calculation of the correlation value and the DPD delay error estimated value based on the correlation value is the same as the calculation shown in the above equations (4) and (5).

Furthermore, as shown in the following equation (7), the delay processing unit 22 converts the DPD delay error estimated value Δi obtained by the second delay error estimating unit 22b into the current delay error estimated value Δτ _I of the output signal y. Addition (subtraction) is performed to obtain a delay error estimated value Δτ to be adjusted by the delay adjustment unit 23 (step S110).
Delay error estimate Δτ = Δτ _I − (K _p × Δi)
... (7)

At this time, the delay processing unit 22 multiplies the DPD delay error estimated value Δi by the correction coefficient K _P and adds it. This correction coefficient K _P is a coefficient that determines the degree of correction for the delay of the DPD, and is set to a value that can reduce the influence of the delay of the DPD on the delay of the output signal y as much as possible. Specifically, the correction coefficient K _P is set to a value between “0” and “1”.

Next, the delay processing unit 22 gives information indicating the obtained delay error estimated value Δτ to the delay adjusting unit 23, and causes the delay adjusting unit 23 to adjust the timing of the signal x (step S111).
The delay adjusting unit 23 adjusts the timing of the signal x based on the given information indicating the estimated delay error value Δτ, and the delay generated between the timing of the output signal y and the timing of the signal x in the coefficient calculating unit 21. Correct so that the error is eliminated.

As a result, the delay error generated between the timing of the output signal y and the timing of the signal x in the coefficient calculation unit 21 is corrected to such an extent that the necessary accuracy in the predistortion processing by the compensation processing unit 20 can be maintained. be able to.

The delay processing unit 22 having adjusted the timing of the signal x by the delay adjustment unit 23 causes the coefficient calculation unit 21 to start calculating the DPD coefficient and to start updating the DPD coefficient of the compensation processing unit 20 (step S112). Thereby, the predistortion compensation processing by the compensation processing unit 20 is started.

Thereafter, the delay processing unit 22 proceeds to step S106, adds “1” to the number of iterations I (step S106), returns to step S102, and again obtains the current number of iterations I through steps S102 to S105. The delay error estimated value Δτ (I) of the output signal y is obtained, and the process proceeds to step S107.

After it is determined that the number of iterations I is the set number of times W, the number of times of iteration I is greater than the set number of times W, so the delay processing unit 22 determines in step S107 that the number of iterations I is not the set number of times W. (Step S107).

In this case, the delay processing unit 22 obtains the current delay error estimated value Δτ _I of the output signal y based on the following equation (8) (step S113).
The estimated delay error value Δτ _{I of the} current output signal y
= Β · Δτ _I-1 + (1-β) · argmax | R (τ) |
= Β · Δτ _I-1 + (1-β) · Δτ (I)
... (8)

In the above formula (8), β is a time constant. After the number of iterations I becomes equal to or greater than the set number of times W, the delay processing unit 22 uses a value obtained by multiplying the delay error estimated value Δτ (I) obtained for each iteration by the time constant β to a past delay error estimated value Δτ. _The moving average value is calculated by adding to _I-1 . The delay processing unit 22 obtains this moving average value as a delay error estimated value Δτ _I of the current output signal y. The time constant β is set to a numerical value greater than or equal to 0 and less than 1.

If this time constant β is set as large as possible, the delay error estimated value Δτ (I) of the newly added number of iterations I in equation (8) becomes the current delay error estimated value Δτ _I of the output signal y. The fluctuation that occurs can be suppressed, and a stable delay error estimated value Δτ _I can be obtained.
For example, if the set number of times W is set to “100”, the time constant β is set to “0.999”.

Thereafter, the delay processing unit 22 proceeds to step S109, and performs the same processing as described above, thereby obtaining a delay error estimated value Δτ to be adjusted by the delay adjustment unit 23, which is expressed by Expression (7), and delay adjustment. The unit 23 adjusts the timing of the signal x.

As described above, the delay processing unit 22 performs the delay adjustment process, so that the timing required for the output signal y in the coefficient calculation unit 21 can be maintained to such an extent that the accuracy necessary for the predistortion processing by the compensation processing unit 20 can be maintained. And the estimated value of the delay error that occurs between the timing of the signal x and the delay error can be corrected with high accuracy.

In the present embodiment, the delay processing unit 22 obtains the delay error estimated value Δτ (I) between the timing of the output signal y AD-converted at the low sampling rate and the timing of the signal x from a plurality of different acquisition periods. A delay between the timing of the output signal y obtained by AD conversion at a low sampling rate and the average value obtained from each delay error estimated value Δτ (I) for each of a plurality of acquisition periods and the timing of the signal x It is obtained as an error estimated value Δτ _I.

Here, since the true value of the delay error between the timing of the output signal y and the timing of the signal x does not vary greatly with time, the value of each delay error estimated value Δτ (I) for each of a plurality of acquisition periods. Even if a variation occurs, the average value or the moving average value is obtained from each delay error estimated value Δτ (I), so that the delay is performed in a unit of a period smaller than the length of the period corresponding to the sampling rate of the ADC 11. An estimated value of error can be obtained, and as a result, an estimated value of delay error can be obtained more accurately.

As described above, the delay error can be obtained in a unit of a period smaller than the length of the period corresponding to the low sampling rate in spite of the AD conversion of the output signal y at the low sampling rate. The delay error can be corrected more accurately with a precision finer than the length of the period to be performed.
As a result, it is possible to maintain the necessary accuracy in the distortion compensation process.

Further, if there is a delay in the predistortion processing performed by the compensation processing unit 20, the accuracy of the delay error estimated value Δτ may be reduced.
In this regard, in the present embodiment, the delay error estimated value Δτ to be adjusted by the delay adjusting unit 23 is added to the delay error estimated value Δτ _I of the DPD in addition to the delay error estimated value Δτ _I of the current output signal y. Therefore, the delay processing unit 22 can correct the delay error estimated value Δi of the DPD. Thereby, it is possible to suppress the influence of the delay that occurs during the predistortion processing on the accuracy of the delay error that occurs between the timing of the output signal y and the timing of the signal x.

In the present embodiment, when the number of iterations I is less than the set number W after the delay processing unit 22 starts to operate, the predistortion compensation process is not executed, and the number of iterations I is equal to or greater than the set number W. The predistortion compensation process is started.
This is because the delay error estimated value Δτ _I obtained based on the equation (6) obtained when the number of iterations I reaches the set number of times W is the moving average obtained thereafter in step S113 and equation (8). This is because it is used as an initial value.

In the present embodiment, after obtaining the initial value of the moving average value, updating of the DPD coefficient is started and the predistortion compensation process is started.
If the update of the DPD coefficient is started without obtaining the initial value of the moving average value, the delay error estimated value Δτ includes an error due to a large fluctuation, and the delay error estimated value including such an error is included. If the DPD coefficient is calculated based on Δτ, an incorrect DPD coefficient may be calculated and the predistortion compensation process may not be performed normally.

In this respect, in the present embodiment, for the period from the start of the operation of the delay processing unit 22 to the number of iterations I until the set number of times W, the initial value of the moving average value is obtained without executing the predistortion processing. Thereafter, execution of the predistortion compensation process is started. That is, since the delay processing unit 22 obtains the initial value of the moving average value based on Step S108 and Expression (6) before the start of the predistortion compensation process, it suppresses obtaining an incorrect DPD coefficient and appropriately In addition, predistortion compensation processing can be performed.

The set number of times W is a weight for stably obtaining the initial value of the moving average value, and is set to a value at which a stable initial value (delay error Δτ _I obtained based on Expression (6)) can be obtained. The

FIG. 3 is a graph showing an example of a result obtained by performing simulation for a case where the delay error estimated value is repeatedly calculated immediately after the delay processing unit 22 of the present embodiment starts operation. In the figure, the horizontal axis represents the number of iterations I, and the vertical axis represents the delay error.
In the figure, the broken line indicates the true value of the delay error of the output signal y. The “delay error estimated value obtained by conventional sampling” indicated by a one-dot chain line indicates an estimated value of the delay error of the output signal y obtained by using the output signal y sampled at the same sampling rate as the DAC 4. Yes.

Further, the example of FIG. 3 shows the result of setting the set number of times W to “100”, and in the range up to the number of iterations I of “100”, the output for each acquisition period obtained by the above equation (5). The delay error estimated value Δτ (I) of the signal y is shown. In the range where the number of iterations I is “100” or more, the delay error estimated value Δτ _{I of the} output signal y obtained as a moving average by the above equation (8). Is shown.

As shown in FIG. 3, the delay error estimated value obtained by the present embodiment varies in the delay error estimated value Δτ (I) for each acquisition period in the range where the number of iterations I is up to “100”. However, these average values and the moving average values obtained thereafter in the range where the number of iterations I is “100” or more are compared with the estimated delay error values obtained by the conventional sampling. It can be confirmed that the delay error can be estimated accurately.

In the first embodiment, when an average value or a moving average value of each delay error estimated value Δτ (I) is obtained as a representative value obtained from each delay error estimated value Δτ (I) for each of a plurality of acquisition periods. However, for example, the median of each delay error estimated value Δτ (I) may be used as a representative value.
In the first embodiment, after the average value of each delay error estimated value Δτ (I) as an initial value of the moving average value is obtained, the moving average value is continuously obtained. Instead, the average value of all the delay error estimated values Δτ (I) may be obtained continuously.

[4. Regarding Delay Processing Unit According to Second Embodiment]
FIG. 4 is a flowchart illustrating a procedure of processing for performing delay adjustment performed by the delay processing unit 22 according to the second embodiment.
Differences between the delay processing unit 22 of the present embodiment and the delay processing unit 22 according to the first embodiment are as follows. That is, in the delay processing unit 22 according to the first embodiment, a delay error estimated value between the timing of the signal x and the timing of the output signal y is calculated for each of a plurality of acquisition periods, and the delay error estimated value is calculated. The case where the delay adjustment process is performed using the averaged value is illustrated.

In contrast, in the delay processing unit 22 according to the second embodiment, the timing of the signal x given to the coefficient calculation unit 21 is adjusted little by little, and the residual Res between the signal x and the output signal y is adjusted for each adjustment. Is different from the first embodiment in that the coefficient calculation unit 21 calculates the delay error and obtains the estimated value of the delay error based on the residual Res. Hereinafter, although the difference between the present embodiment and the first embodiment will be described, the other points are the same as those of the first embodiment.

In the present embodiment, the delay processing unit 22 first determines whether or not the wireless communication device (distortion compensation device 14) has just been started (step S301).
When determining that it is immediately after startup, the delay processing unit 22 executes delay adjustment processing before starting to update the DPD coefficient (step S302).

FIG. 5 is a flowchart showing the procedure of the delay adjustment process in FIG.
First, the delay processing unit 22 acquires the signal x and the output signal y in step S401 (step S400). The delay processing unit 22 acquires data strings of the signal x and the output signal y included in the acquisition period as a predetermined period set for acquiring the signal x and the output signal y.

Next, the delay processing unit 22 performs upsampling processing on the signal x and the output signal y (step S401). As will be described later, the signal x and the output signal y are used to obtain a correlation value with each other and to obtain an estimated value of delay error. Therefore, an upsampling process is performed on the signal x and the output signal y so that the correlation value can be obtained. Note that the estimation of the delay error based on the correlation value performed here is performed with accuracy determined in units of the period length corresponding to the sampling rate of the frequency similar to the frequency bandwidth of the signal x, and an approximate delay error estimation value is obtained. Therefore, the upsampling process in step S401 is performed at a magnification such that the signal x and the output signal y have a sampling rate with a frequency comparable to the frequency bandwidth of the signal x.
For example, when the sampling rate (low sampling rate) of the ADC 11 is 15.36 MHz, the upsampling processing magnification is set to several times to about 100 times.

Next, the delay processing unit 22 performs an operation for obtaining an estimated value of the delay error between the timing of the output signal y and the timing of the input signal x (estimated value of the delay error of the output signal y) as a first delay. The error estimation part 22a is made to perform.

The first delay error estimator 22a obtains a correlation value between the output signal y acquired in step S401 and the signal x, and obtains a delay error estimate value of the output signal y by calculation based on the correlation value. (Step S402).
The calculation of the correlation value and the delay error estimated value based on the correlation value is the same as the calculation shown in the above formulas (4) and (5).

Here, the first delay error estimator 22a obtains an estimated value of the delay error using the output signal y and the signal x having a sampling rate with a frequency comparable to the frequency bandwidth of the signal x. For this reason, the delay error of the output signal y obtained in step S402 is obtained with an accuracy determined by the unit of the length of the period corresponding to the sampling rate having the same frequency as the frequency bandwidth of the signal x, so that the delay error is corrected. However, by obtaining the estimated value of the delay error, the numerical range including the true value of the delay error can be clarified within the low accuracy.

Next, the delay processing unit 22 sets an initial value of the delay error value T of the signal x based on the output signal y based on the estimated delay error value of the output signal y. Delay adjustment based on the delay error value T is performed (step S403).
At this time, the delay processing unit 22 delays the delay so as to minimize the delay error with respect to the output signal y in the numerical range including the true value of the delay error that is apparent in the estimated value of the delay error. An error value T is set.
This is because, as will be described later, the delay error value T is gradually increased by increments ΔT so that the delay error value T is adjusted to approach the true value.

After correcting the delay error with relatively low accuracy, the delay processing unit 22 causes the coefficient calculation unit 21 to acquire the signal x and the output signal y (step S404). The coefficient calculation unit 21 acquires a signal reflecting the delay error correction performed in step S403.

Next, the coefficient calculation unit 21 performs a downsampling process on the signal x acquired in step S404 (step S405). The downsampling process for the signal x is performed to obtain a residual Res from the output signal y having a low sampling rate.
For this reason, the coefficient calculation unit 21 performs the downsampling process so that the sampling rate of the signal x becomes a value close to a lower sampling rate. The magnification of the downsampling process can be set to, for example, about 1 / several to several tens of times.

After performing the downsampling process on the signal x, the coefficient calculation unit 21 obtains a residual Res between the output signal y and the signal x shown in the above equation (3) (step S406).
When the coefficient calculation unit 21 calculates the residual Res, the coefficient calculation unit 21 gives the calculated residual Res to the delay processing unit 22.

When the residual Res is given, the delay processing unit 22 determines whether or not there is a residual Res that becomes a minimum value (minimum value) in the residual Res or the residual Res given in the past ( Step S407).
If it is determined that there is no residual Res that becomes a local minimum value, the delay processing unit 22 adds the addition value ΔT as a predetermined unit time to the delay error value T (step S409), and the delay adjustment unit 23 again receives the delay. Delay adjustment based on the error value T is performed (step S410), and the process returns to step S404.

The delay processing unit 22 repeatedly executes steps S404 to S409 until it is determined in step S407 that there is a residual Res that becomes a minimum value.

In order for the delay processing unit 22 to determine that there is a residual Res having a minimum value, the following method can be employed. That is, the range in which the delay error value T is changed is set to the entire numerical range specified as including the true value of the delay error, the residual Res is calculated over the numerical range, and then the residual is calculated. The minimum value of Res is obtained as a minimum value.
As another method, when the residual Res is obtained while changing the delay error value T sequentially from a certain initial value, and the local minimum is estimated from the displacement between the residuals Res, the local minimum is estimated to be the local minimum. It can also be determined that there is a residual Res that becomes a value.

The signal x that is delay-adjusted based on the delay error value T is delayed by the addition value ΔT by adding the addition value ΔT to the delay error value T. Therefore, the delay error of the output signal y changes (increases) by the addition value ΔT.

Therefore, the delay processing unit 22 repeatedly executes steps S404 to S409 to change (increase) the delay error of the output signal y by the addition value ΔT (step S409), and also to change the delay error of the output signal y. Each time the added value ΔT is changed, the output signal y after changing the delay error of the output signal y and the signal x are acquired (step S404), and the residual Res between the output signal y and the signal x is obtained. Is obtained (step S406).

In step S407, the delay processing unit 22 repeatedly executes steps S404 to S409, and if it is determined that there is a residual Res that is a minimum value, the delay processing unit 22 specifies a delay error value T that causes the residual Res to be a minimum value (step S407). S411). When the residual Res is a minimum value, it can be said that the output signal y and the signal x are the best match among the delay error values T calculated repeatedly. Therefore, the delay error value T at that time (residual Res is the minimum value) is specified as the delay error estimation value of the current output signal y.

Next, the delay processing unit 22 causes the second delay error estimation unit 22b to obtain the DPD delay error estimation value Δi generated by the processing by the compensation processing unit 20 (step S412). The DPD delay error estimated value Δi is calculated by the same method as in the first embodiment.

Next, as shown in the following equation (9), the delay processing unit 22 converts the DPD delay error estimated value Δi obtained by the second delay error estimating unit 22b into a delay error value T with the residual Res as a minimum value. Addition (subtraction) is performed to obtain a delay error estimated value Δτ to be adjusted by the delay adjustment unit 23 (step S413).
Delay error Δτ = T− (K _p × Δi) (9)

In the equation (9), the correction coefficient K _P is a coefficient that determines the degree of correction for the delay of the DPD, and is as described in the first embodiment.

The delay processing unit 22 gives information indicating the obtained delay error estimated value Δτ to the delay adjusting unit 23, and causes the delay adjusting unit 23 to adjust the timing of the signal x (step S414).
The delay adjusting unit 23 adjusts the timing of the signal x based on the given information indicating the estimated delay error value Δτ, and the delay generated between the timing of the output signal y and the timing of the signal x in the coefficient calculating unit 21. Correct so that the error is eliminated.
As described above, the delay processing unit 22 finishes the delay adjustment process.

As described above, in this embodiment, the delay error of the output signal y is changed by the addition value ΔT, and the delay error of the output signal y is changed every time the delay error of the output signal y is changed by the addition value ΔT. A residual Res between the subsequent output signal y and the signal x is obtained, and the present state is determined based on the magnitude of the residual Res from the delay errors (delay error value T) changed by the addition value ΔT. The delay error estimated value of the output signal y is determined.
In the above-described embodiment, the delay error value T when the residual Res becomes the minimum value is obtained as the delay error estimated value of the output signal y from among the delay error values T changed by the addition value ΔT.
In this case, the delay error estimated value can be obtained in units of the added value ΔT.

For this reason, the added value ΔT is set to a time shorter than the length of the cycle corresponding to the low sampling rate.
As a result, the delay error estimated value of the output signal y can be obtained in a unit of a period smaller than the length of the cycle corresponding to the low sampling rate, and the delay error can be obtained with higher accuracy.
More preferably, the addition value ΔT is set to a time shorter than the length of the period corresponding to the sampling rate of the DAC 4. In this case, the delay error estimated value of the output signal y can be obtained in units of a smaller period, and the delay error can be obtained with higher accuracy.

FIG. 6 is a graph illustrating an example of a result obtained by performing a simulation when the delay processing unit 22 of the present embodiment performs the delay adjustment process. In the figure, the horizontal axis represents the number of iterations, and the vertical axis represents the value indicating the residual Res as power.
In the drawing, the light color diagram shows the residual power obtained when the signals x are delayed from each other with a predetermined delay error and the delay adjustment processing according to the present embodiment is performed, and the dark color diagram. Indicates the residual power obtained by the present embodiment for the output signal y and the signal x with the predetermined delay error.
Each diagram shows the residual power obtained within a period of 2 samples (± 1 sample) in a signal having a sampling rate having the same frequency as the frequency bandwidth of the signal x.

In each diagram, many sharp peaks directed to the low value side of the residual power are seen corresponding to the calculation of the residual power (residual Res). The value on the low value side of each peak indicates the residual power (residual Res) calculated by the delay processing unit 22.
Since the calculation of the residual power changes the delay error by an additional value ΔT each time it is repeated, if a true value exists when the delay error is changed in a more delayed direction, as shown in FIG. The residual power gradually decreases as the number of iterations increases, and becomes a local minimum near the delay error (delay error value T) becomes a true value. When the minimum value is passed, the residual power increases again.

Since the light color diagram is the residual power obtained between the signals x, the timing at which the residual power becomes a minimum value is the true value of the delay error.
Although the minimum value of the residual power according to the present embodiment is slightly deviated from the true value, it can be confirmed that the delay error can be estimated with high accuracy without being greatly deviated.

When the delay adjustment process is completed, the delay processing unit 22 proceeds to step S303 in FIG. 4 and causes the coefficient calculation unit 21 to start calculating the DPD coefficient and also starts updating the DPD coefficient of the compensation processing unit 20 (step S303). S303). Thereby, the predistortion compensation process by the compensation processor 20 is started and the process is finished.

If it is determined in step S301 that it is not immediately after startup, the delay processing unit 22 determines whether or not a predetermined period has elapsed since the previous delay adjustment processing was executed (step S304).

If it is determined that the predetermined period has elapsed since the previous delay adjustment process was executed, the delay processing unit 22 stops updating the DPD coefficient of the compensation processing unit 20 (step S305), and proceeds to step S302. Delay adjustment processing is executed (step S302). Thereafter, the delay processing unit 22 starts updating the DPD coefficient (step S303) and ends the process.
On the other hand, when it is determined that the predetermined period has not elapsed since the previous delay adjustment process was executed, the delay processing unit 22 ends the process.

As described above, the delay processing unit 22 is configured to perform a delay adjustment process every time a predetermined period elapses.
The delay error between the timing of the output signal y and the timing of the signal x has a small change with time, but does not change, and therefore needs to be adjusted with a certain frequency.
For this reason, the delay processing unit 22 of the present embodiment performs a delay adjustment process every time a predetermined period elapses. As a result, the delay error can be accurately corrected over a long period of time. The predetermined period is set to about 1 to 2 days, for example.

In addition, the delay processing unit 22 performs the delay adjustment process after stopping the update of the DPD coefficient.
That is, the delay processing unit 22 does not execute the delay adjustment process while executing the update of the DPD coefficient, and executes the delay adjustment process while the update of the DPD coefficient is stopped.
If the delay adjustment process is executed without stopping the updating of the DPD coefficient, the delay processing unit 22 changes the delay error by the addition value ΔT, so that the error is included in the delay error. There is a possibility that the predistortion compensation processing cannot be performed normally.

In this regard, in the present embodiment, the delay processing unit 22 does not execute the delay adjustment process while executing the update of the DPD coefficient, and performs the delay adjustment process while the update of the DPD coefficient is stopped. Since this is executed, it is possible to suppress the determination of an incorrect DPD coefficient and to appropriately perform the predistortion processing.

In the above embodiment, the delay processing unit 22 shows the case where the delay error between the timing of the output signal y and the timing of the signal x is changed and adjusted by digital processing. For example, the analog processing unit 12 side Thus, by adjusting the timing of the output signal y, it is possible to obtain the residual Res by adding the addition value ΔT to the delay error value T and changing the delay error, thereby obtaining an estimated value of the delay error.

FIG. 7 is a block diagram illustrating a main part of a wireless communication device according to a modification of the second embodiment.
The distortion compensation device 14 included in the wireless communication device illustrated in FIG. 7 is different from the wireless communication device of the second embodiment in that it includes an adjustment unit 30 for adjusting the phase of the operation clock supplied to the ADC 11.
The adjustment unit 30 has a function of arbitrarily adjusting the phase of the operation clock supplied to the ADC 11 under the control of the delay processing unit 22.

The delay processing unit 22 controls the adjustment unit 30 to adjust the phase of the operation clock of the ADC 11 and adjust the timing of the output signal y that is AD-converted and output from the ADC 11.
Thereby, the delay processing unit 22 can change the delay error between the timing of the output signal y and the timing of the signal x.
Therefore, also in the distortion compensation apparatus 14 shown in FIG. 7, the delay adjustment process shown in FIGS. 4 and 5 can be executed.
In this case, since the delay processing unit 22 can change the delay error by analog processing, the load on the delay processing unit 22 can be reduced.

[5. (Evaluation of distortion compensation)
In order to confirm that the distortion compensation accuracy of the distortion compensator 14 according to the present embodiment is not inferior to that of the conventional distortion compensator, the inventor of the present invention has the amplification provided with the distortion compensator 14 according to the present embodiment. The input / output characteristics of the signal by the device were verified and evaluated. Hereinafter, the evaluation result will be described.

As an evaluation test, a computer is used for the aspect of input / output signals when an OFDM signal having a frequency bandwidth of 100 MHz is amplified using the amplification device according to the first embodiment and the amplification device according to the second embodiment. The distortion compensation accuracy was evaluated by simulation.
In addition to the first and second embodiments, as another embodiment, the delay processing unit 22 included in the amplifying apparatus according to the first embodiment shown in FIG. 1 estimates and corrects delay errors by a general method. An apparatus configured as described above was also evaluated. As a general method, a correlation value is obtained between the output signal y having a low sampling rate and the signal x, and the delay error estimated value obtained based on the correlation value is used as it is. Was corrected.

In each amplifying apparatus, an OFDM signal having a frequency bandwidth of 100 MHz was used as the signal x, the DAC 4 sampling rate was 614.4 MHz, and the ADC 11 sampling rate (low sampling rate) was 15.36 MHz. The pass bandwidth of the filter unit 10 is about 600 MHz.

FIG. 8 is a diagram illustrating an example of a frequency spectrum of an OFDM signal amplified by an amplifying apparatus according to another embodiment.
In the figure, an “original signal” is an input signal (signal x) and indicates the frequency spectrum of the input signal.
Also, in the figure, “output signal by conventional distortion compensation processing” means that a delay error estimated value of the output signal y is obtained using the output signal y sampled at the same sampling rate as the DAC 4, and this delay error estimated value is This is an output signal when delay compensation is performed based on the distortion compensation processing, and the frequency spectrum of this output signal is shown.

The “output signal without distortion compensation processing” is an output signal when the input signal is amplified without distortion compensation processing, and indicates the frequency spectrum of this output signal.
The “output signal according to another embodiment” is an output signal that has been subjected to distortion compensation processing by the amplifying apparatus according to the other embodiment, and indicates a frequency spectrum of the output signal.

As shown in the figure, it can be seen that the output power according to the other embodiment has improved leakage power in the adjacent channel of the signal band as compared with the output signal without distortion compensation processing.
However, the output signal according to the other embodiment tends to deteriorate in signal quality as it goes away from the center frequency as compared with the original signal or the output signal obtained by the conventional distortion compensation processing.

FIG. 9 is a diagram illustrating an example of a frequency spectrum of an OFDM signal amplified by the amplification device according to the first embodiment, and FIG. 10 is an example of a frequency spectrum of the OFDM signal amplified by the amplification device according to the second embodiment. FIG.
Also in the output signals according to the first and second embodiments, it can be seen that the leakage power in the adjacent channel of the signal band is improved as compared with the output signal without distortion compensation processing.
In addition, it can be seen that the output signals according to the first and second embodiments have substantially the same signal quality as the original signals and the output signals obtained by the conventional distortion compensation processing.

As described above, according to the evaluation test, it was confirmed that the amplifying apparatus of this embodiment has sufficient distortion compensation accuracy.

[6. Others]
The present invention is not limited to the above embodiments.
For example, in each of the above embodiments, the case where the distortion compensation unit 3 of the distortion compensation device 14 includes the delay processing unit 22 is illustrated, but the delay processing unit 22 is not necessarily provided, and a general method is used. For example, a correlation value may be obtained between the output signal y having a low sampling rate and the signal x, and the delay error may be corrected using the estimated value of the delay error obtained based on the correlation value as it is. .

In addition, the distortion compensation device 14 of each of the above embodiments estimates the above-described distortion compensation model by obtaining the DPD coefficient from the signal x amplified by the amplifier 2 and the output signal y output from the amplifier 2. The so-called direct learning method is employed, but an indirect learning method in which an inverse model is estimated from the compensation signal u from the compensation processing unit 20 and the output signal y and reflected in the signal x may be employed.

The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the meanings described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

DESCRIPTION OF SYMBOLS 1 Amplifying device 2 Amplifier 3 Distortion compensation part 4 DA converter 5 Up converter 6 Oscillator 7 Antenna 8 Coupler 9 Down converter 10 Filter part 11 AD converter 12 Analog processing part 13 Digital processing part 14 Distortion compensation apparatus 20 Compensation processing part 21 Coefficient Calculation unit 22 Delay processing unit 22a First delay error estimation unit 22b Second delay error estimation unit 23 Delay adjustment unit 30 Adjustment unit

Claims (13)

1. A distortion compensation unit that performs distortion compensation of an amplifier that amplifies an input signal;
   An AD converter that AD-converts an output signal output from the amplifier and supplies the signal to the distortion compensator, and
   The AD converter AD-converts the output signal at a low sampling rate lower than a sampling rate when the signal supplied to the amplifier is DA-converted,
   The distortion compensation unit is a distortion compensation device that performs distortion compensation based on the input signal and the output signal that has been AD-converted at the low sampling rate.
2. 2. The distortion compensation unit according to claim 1, wherein the distortion compensation unit estimates a model of the amplifier based on the input signal and the output signal that is AD-converted at the low sampling rate, and performs distortion compensation based on the model. Distortion compensation device.
3. A filter connected between the amplifier and the AD converter;
   The distortion compensation apparatus according to claim 1 or 2, wherein a pass bandwidth of the filter is set to be equal to or greater than a frequency bandwidth of the input signal.
4. A delay error occurring between the timing of the output signal AD-converted at the low sampling rate and the timing of the input signal is estimated and corrected in units of periods smaller than the length of the period corresponding to the low sampling rate. The distortion compensation apparatus according to any one of claims 1 to 3, further comprising a delay processing unit that performs the processing.
5. The delay processing unit obtains an estimated value of the delay error for each of a plurality of different predetermined periods, and obtains a representative value obtained from the estimated value of each delay error for each of the plurality of predetermined periods as an estimated value of the delay error. The distortion compensation apparatus according to claim 4, which is obtained as follows.
6. The delay processing unit changes the delay error by a predetermined unit time, and each time the delay error is changed by the predetermined unit time, the output signal after changing the delay error, and the input 5. The residual error is obtained from a signal, and an estimated value of the delay error is determined based on a magnitude of the residual from each delay error changed by the predetermined unit time. Distortion compensation device.
7. The distortion compensation apparatus according to claim 6, wherein the predetermined unit time is a time shorter than a length of a cycle corresponding to the low sampling rate.
8. The distortion compensation apparatus according to claim 6, wherein the delay processing unit adjusts a timing of the output signal by changing a phase of an operation clock given to the AD converter to change the delay error.
9. The distortion compensator is configured to provide a compensation signal that has been subjected to distortion compensation for the input signal to the amplifier,
   The distortion compensation apparatus according to claim 4, wherein the delay processing unit corrects a delay error generated between the timing of the input signal and the timing of the compensation signal.
10. The distortion compensation device according to claim 1, wherein the low sampling rate is set lower than a frequency bandwidth of the signal x.
11. The distortion compensation device according to claim 3, wherein a pass bandwidth of the filter is set to be equal to or greater than a frequency bandwidth of a distortion component generated in the output signal when the amplifier amplifies the input signal.
12. An amplifying apparatus comprising: an amplifier; and the distortion compensating apparatus according to claim 1.
13. A wireless communication device comprising the amplification device according to claim 12 for amplification of a communication signal.

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