WO2015072516A1 - Semiconductor device and manufacturing method for same - Google Patents

Semiconductor device and manufacturing method for same Download PDF

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Publication number
WO2015072516A1
WO2015072516A1 PCT/JP2014/080076 JP2014080076W WO2015072516A1 WO 2015072516 A1 WO2015072516 A1 WO 2015072516A1 JP 2014080076 W JP2014080076 W JP 2014080076W WO 2015072516 A1 WO2015072516 A1 WO 2015072516A1
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Prior art keywords
main surface
film
semiconductor
semiconductor film
substrate
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PCT/JP2014/080076
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French (fr)
Japanese (ja)
Inventor
隆道 住友
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住友電気工業株式会社
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Publication of WO2015072516A1 publication Critical patent/WO2015072516A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66469—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Definitions

  • the present invention relates to a semiconductor device including a semiconductor composite film having a carrier channel layer, a source electrode, and a drain electrode, and a manufacturing method thereof.
  • FETs field effect transistors
  • HEMTs high electron mobility transistors
  • Patent Document 1 discloses a high-performance HEMT in which buffer leakage current and gate leakage current are suppressed.
  • Patent Document 2 discloses a semiconductor device having an inclined channel structure in which excellent vertical breakdown voltage and drain leakage current during transistor operation are suppressed.
  • Patent Document 3 discloses a semiconductor device having a super junction structure with low on-resistance and high breakdown voltage, and a method for manufacturing the same.
  • the HEMT disclosed in Japanese Patent Application Laid-Open No. 2012-243792 is a type of lateral FET in which a source electrode, a gate electrode, and a drain electrode are arranged on one main surface side.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2012-243792
  • a source electrode, a gate electrode, and a drain electrode are arranged on one main surface side.
  • Patent Document 2 has a problem that mobility is limited because of the presence of a drift layer.
  • the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2013-038101 has a problem in that the on-resistance of the semiconductor device does not fall below a certain value because the resistance of the drift layer exists.
  • An object of the present invention is to solve the above-described problems and to provide a semiconductor device having a low on-resistance and a high breakdown voltage without increasing the area of the main surface of the device and a method for manufacturing the same.
  • the present invention has a first main surface and a second main surface that is a main surface opposite to the first main surface, the first main surface and the second main surface.
  • a semiconductor composite film including a carrier channel layer having a main surface perpendicular to the semiconductor composite film; a drain electrode disposed on the first main surface of the semiconductor composite film; and a second main surface of the semiconductor composite film. And a source electrode.
  • a step of preparing a composite substrate including a base substrate and a semiconductor film disposed on one main surface side of the base substrate, and removing a part of the semiconductor film of the composite substrate thus, the step of forming the first semiconductor film having the main surface in which the first trench portion perpendicular to the main surface of the semiconductor film is formed, and the first trench portion of the first semiconductor film are formed.
  • the first semiconductor film is formed at the interface between the first semiconductor film and the second semiconductor film and is the main surface on the first semiconductor film side.
  • a semiconductor composite film including a carrier channel layer having a main surface perpendicular to the main surface; and a second surface perpendicular to the carrier channel layer, the main surface of the semiconductor composite film on the second semiconductor film side.
  • the present invention it is possible to provide a semiconductor device that has a low on-resistance and can increase the breakdown voltage without increasing the area of the main surface of the device, and a method for manufacturing the semiconductor device.
  • FIG. 1 It is a schematic sectional drawing which shows an example with the process from formation of the source electrode of the manufacturing method of the semiconductor device concerning this invention to formation of a drain electrode. It is a schematic sectional drawing which shows an example with the process of arrangement
  • semiconductor devices 2A, 2B, 2C have a first main surface and a second main surface that is a main surface opposite to the first main surface.
  • a semiconductor composite film 20C including a carrier channel layer 20c having a main surface perpendicular to the first main surface and the second main surface, and a drain disposed on the first main surface of the semiconductor composite film 20C 30d including electrode 30d and source electrode 30s disposed on the second main surface of semiconductor composite film 20C.
  • the semiconductor device of the present embodiment includes the carrier channel layer 20c having a main surface perpendicular to the first main surface and the second main surface, the on-resistance can be lowered and the main part of the semiconductor device can be reduced.
  • the breakdown voltage can be increased without increasing the surface area.
  • the semiconductor composite film 20C is formed with the first main surface and the first trench portion 21t perpendicular to the first main surface.
  • a first semiconductor film 21 having a main surface and a first semiconductor film 21 disposed on the main surface of the first semiconductor film 21 where the first trench portion 21t is formed and corresponding to the first trench portion 21t.
  • a second semiconductor film 22 having a second main surface in which two trench portions 22t are formed, and the carrier channel layer 20c is an interface between the first semiconductor film 21 and the second semiconductor film 22 Can be formed.
  • the carrier channel layer 20c having a main surface perpendicular to the first main surface and the second main surface is formed, and the semiconductor device has a low on-resistance and a high breakdown voltage without increasing the area of the main surface. Is obtained.
  • the semiconductor device 2B according to the embodiment of the present invention can further include a conductive support substrate 70 disposed on the first main surface side of the semiconductor composite film 20C. Thereby, a semiconductor device with high mechanical strength is obtained.
  • the semiconductor device 2C according to the embodiment of the present invention can further include a support substrate 80 disposed on the second main surface side of the semiconductor composite film 20C. Thereby, a semiconductor device with high mechanical strength is obtained.
  • a method for manufacturing semiconductor devices 2A, 2B, and 2C includes a step of preparing a composite substrate 1 including a base substrate 10 and a semiconductor film 20 disposed on one main surface side of the base substrate 10. Then, by removing a part of the semiconductor film 20 of the composite substrate 1, the first semiconductor film 21 having a main surface in which the first trench portion 21t perpendicular to the main surface of the semiconductor film 20 is formed is formed. The first semiconductor film 21 and the second semiconductor film are formed by forming the second semiconductor film 22 on the main surface of the first semiconductor film 21 where the first trench portion 21t is formed.
  • a semiconductor composite film 20C including a carrier channel layer 20c that is formed at the interface with the first semiconductor film 21 and has a main surface perpendicular to the first main surface that is the main surface on the first semiconductor film 21 side.
  • the second semiconductor of the semiconductor composite film 20C A step of forming a source electrode 30s on a second main surface which is a main surface on the film 22 side and perpendicular to the carrier channel layer 20c, and a first main surface on the first semiconductor film 21 side of the semiconductor composite film 20C. Forming a drain electrode 30d on the surface.
  • the manufacturing method of the semiconductor devices 2A, 2B, and 2C according to the present embodiment includes the above-described steps, thereby efficiently manufacturing a semiconductor device having a low on-resistance and a high breakdown voltage without increasing the area of the main surface of the semiconductor device. be able to.
  • the semiconductor film of the composite substrate 1 after the step of preparing the composite substrate 1 and before the step of forming the first semiconductor film 21 The method further includes the step of forming a further semiconductor film 20b on 20a, and the step of forming the first semiconductor film 21 includes a part of the further semiconductor film 20b and any one of the semiconductor film 20a and a part of the further semiconductor film 20b. This can be done by removing. As a result, a part of the thick semiconductor film 20 in which the semiconductor film 20a and the semiconductor film 20b are integrated (one of the semiconductor film 20b and one of the semiconductor film 20a and the further semiconductor film 20b) is desired.
  • the first semiconductor film 21 can be obtained.
  • the conductive support substrate 70 is disposed on the first main surface side where the drain electrode 30d is formed after the step of forming the drain electrode 30d.
  • a process can be further included. Thereby, a semiconductor device with high mechanical strength can be manufactured efficiently.
  • semiconductor devices 2A, 2B and 2C which are embodiments of the present invention are first main surfaces opposite to the first main surface and the first main surface.
  • a semiconductor composite film 20C including a carrier channel layer 20c having a main surface perpendicular to the first main surface and the second main surface, and a first main surface of the semiconductor composite film 20C.
  • a drain electrode 30d disposed on the surface and a source electrode 30s disposed on the second main surface of the semiconductor composite film 20C are included.
  • the range indicated by the symbol U in FIG. 1 indicates one unit of the semiconductor device 2A of the present embodiment.
  • a semiconductor device 2R which is a typical lateral FET as shown in FIG. 2, has an Al 1-x Ga x N film (0 ⁇ x ⁇ 1) on the first semiconductor film 21 such as a GaN film as the semiconductor composite film 20C. ), The carrier channel layer 20c is formed at the interface between the first semiconductor film 21 and the second semiconductor film 22, and the second main film of the semiconductor composite film 20C is formed.
  • a source electrode 30s, a gate electrode 30g, and a drain electrode 30d are arranged in this order on the main surface of the second semiconductor film 22 on the surface side with an insulating film 40 interposed therebetween.
  • the range indicated by the symbol U in FIG. 2 indicates one unit of a typical horizontal semiconductor device 2R.
  • the semiconductor devices 2A, 2B, and 2C of the present embodiment include a carrier channel layer having a first main surface on which the drain electrode 30d is disposed and a main surface that is perpendicular to the second main surface on which the source electrode 30s is disposed. Since it has 20c, the on-resistance can be lowered and the breakdown voltage can be increased without increasing the area of the main surface of the device.
  • semiconductor devices 2 ⁇ / b> A, 2 ⁇ / b> B, and 2 ⁇ / b> C have a main surface that is perpendicular to the first main surface and the second main surface, although there is no particular limitation.
  • the semiconductor composite film 20C is a first semiconductor having a first main surface and a main surface on which a first trench portion perpendicular to the first main surface is formed.
  • the film 21 and the second trench part disposed on the main surface where the first trench part of the first semiconductor film 21 is formed and the second trench part corresponding to the first trench part is formed. It is preferable that the carrier channel layer 20 c is formed at the interface between the first semiconductor film 21 and the second semiconductor film 22.
  • the semiconductor composite film 20 ⁇ / b> C of the semiconductor devices 2 ⁇ / b> A, 2 ⁇ / b> B, and 2 ⁇ / b> C of the present embodiment has, for example, a main surface opposite to the first main surface and the first main surface
  • a first semiconductor film 21 having a first main surface and a main surface on which a first trench portion perpendicular to the first main surface is formed
  • the second main surface of the first semiconductor film 21 is disposed on the main surface where the first trench portion is formed and the second trench portion corresponding to the first trench portion is formed.
  • a second semiconductor film 22 having.
  • the band gap energy of the first semiconductor film 21 and the band gap energy of the second semiconductor film 22 are It is preferable that the chemical composition of the first semiconductor film 21 is different from the chemical composition of the second semiconductor film 22.
  • the first semiconductor film 21 is preferably a GaN film
  • the second semiconductor film 22 is preferably an Al 1-x Ga x N film (0 ⁇ x ⁇ 1).
  • the thickness of the thick portion of the first semiconductor film 21 is 1 ⁇ m from the viewpoint of increasing the off-state breakdown voltage and reducing the on-state resistance. It is preferably 10 ⁇ m or less and more preferably 4 ⁇ m or more and 6 ⁇ m or less.
  • the thickness of the thin portion of the first semiconductor film 21 is preferably 0.001 ⁇ m or more and 1 ⁇ m or less from the viewpoint of reducing resistance during energization. More preferably, it is not less than 01 ⁇ m and not more than 0.1 ⁇ m.
  • the thickness of the second semiconductor film 22 is preferably 1 nm or more and 30 nm or less, and more preferably 10 nm or more and 20 nm or less from the viewpoint of increasing the amount of induced carriers and reducing the contact resistance between the source electrodes 30s.
  • the first semiconductor film 21 has a main surface in which a first trench portion perpendicular to the first main surface is formed, the first trench portion of the first semiconductor film 21 is By forming a second semiconductor film 22 having a second main surface disposed on the formed main surface and having a second trench corresponding to the first trench portion, the first semiconductor film 22 is formed.
  • a carrier channel layer 20c having a first principal surface and a principal surface perpendicular to the second principal surface is formed at the interface between the semiconductor film 21 and the second semiconductor film 22.
  • the length L of the carrier channel layer 20c is such that the first trench portion 21t of the first semiconductor film 21 (see FIG. 5B) and the second trench portion 22t of the second semiconductor film 22 (see FIG. 5B). C)) (refer to the length of the wall portion from the bottom of the first and second trench portions to the ceiling portion, hereinafter the same).
  • the carrier channel layer 20c having a main surface perpendicular to the first main surface and the second main surface is formed.
  • the on-resistance can be lowered and the breakdown voltage can be increased without increasing the area of the main surface of the semiconductor device.
  • the term “perpendicular to the first main surface and the second main surface” is substantially sufficient to increase the breakdown voltage without increasing the first main surface and the second main surface of the semiconductor device. For example, it is sufficient if it is not less than 80 ° and not more than 100 ° with respect to the first main surface and the second main surface.
  • the length L of the carrier channel layer 20c is preferably 1 ⁇ m or more from the viewpoint of increasing the breakdown voltage of the semiconductor device, more preferably 4 ⁇ m or more, and preferably 10 ⁇ m or less and more preferably 6 ⁇ m or less from the viewpoint of decreasing the on-resistance.
  • the width of the second trench portion 22t (see FIG. 5C) of the second semiconductor film 22 of the semiconductor composite film 20C is preferably 1 ⁇ m or more and more preferably 5 ⁇ m or more from the viewpoint of ensuring the processing accuracy of the gate electrode 30g.
  • it is preferably 10 ⁇ m or less, and more preferably 6 ⁇ m or less.
  • a third semiconductor film may be further formed on the second semiconductor film 22 from the viewpoint of increasing the amount of induced carriers and protecting the surface.
  • the band gap energy of the second semiconductor film 22 and the band gap energy of the third semiconductor film are different, that is, the chemical composition of the second semiconductor film 22 and the second
  • the chemical composition of the semiconductor film 3 is preferably different.
  • the third semiconductor film is preferably a GaN film.
  • the thickness of the third semiconductor film is preferably 1 nm or more and 20 nm or less, and more preferably 5 nm or more and 10 nm or less from the viewpoint of reducing contact resistance with the source electrode.
  • the drain electrode 30d of the semiconductor devices 2A, 2B, 2C of the present embodiment is, for example, the first surface of the semiconductor composite film 20C on the first semiconductor film 21 side. 1 is disposed on the main surface.
  • the drain electrode 30d is not particularly limited, but is preferably in ohmic contact with the first semiconductor film 21 from the viewpoint of improving the characteristics of the semiconductor device by reducing the resistance of the drain electrode 30d.
  • the drain electrode 30d is preferably a Ti / Al / Ni / Au electrode from the viewpoint of making ohmic contact with the first semiconductor film 21.
  • the source electrode 30s of the semiconductor devices 2A, 2B, and 2C of the present embodiment is, for example, the first main surface of the semiconductor composite film 20C on the second semiconductor film 22 side. 2 is arranged on the main surface.
  • the second semiconductor film 22 is disposed on the main surface on which the first trench portion substantially perpendicular to the first main surface of the first semiconductor film 21 is formed, Since the second trench portion corresponding to the first trench portion is formed, the main surface of the second semiconductor film 22 is substantially the same as the first main surface of the first semiconductor film 21.
  • the source electrode 30s is not particularly limited, but is preferably in ohmic contact with the second semiconductor film 22 from the viewpoint of improving the characteristics of the semiconductor device by reducing the resistance of the source electrode 30s.
  • the source electrode 30 s is preferably a Ti / Al / Ni / Au electrode from the viewpoint of making ohmic contact with the second semiconductor film 22.
  • the semiconductor devices 2 ⁇ / b> A, 2 ⁇ / b> B, and 2 ⁇ / b> C of the present embodiment have a semiconductor composite film in addition to the drain electrode 30 d and the source electrode 30 s from the viewpoint of developing a transistor function.
  • Electrically connected to a main surface on the second semiconductor film 22 side of 20C and substantially perpendicular to the first main surface of the first semiconductor film 21, and A gate electrode 30g drawn to the second main surface side of the second semiconductor film 22 can be further included.
  • the gate electrode 30g is preferably in Schottky contact with the second semiconductor film 22 from the viewpoint of developing an FET (field effect transistor) function.
  • the gate electrode 30g is preferably a Ni electrode, a Ta electrode, a Ni / Au electrode, a Ta / Au electrode, or the like from the viewpoint of making a Schottky contact with the second semiconductor film 22.
  • the contact distance (gate width) between the gate electrode 30g and the second semiconductor film 22 is preferably 100 nm or more, more preferably 500 nm or more, from the viewpoint of improving workability at the time of manufacturing a semiconductor device and increasing the breakdown voltage at the time of switching. From the viewpoint of increasing the speed, it is preferably 2 ⁇ m or less, more preferably 1 ⁇ m or less.
  • the semiconductor devices 2A, 2B and 2C of the present embodiment have a second semiconductor of the semiconductor composite film 20C as the insulating film 40 from the viewpoint of increasing the insulation and breakdown voltage.
  • the first insulating film 40a disposed between the second trench portion formed on the second main surface on the film 22 side and the gate electrode 30g, and the second semiconductor film 22 side of the semiconductor composite film 20C It is preferable to include a second insulating film 40b disposed between the source electrode 30s on the second main surface side and the gate electrode 30g.
  • the first insulating film 40a and the second insulating film 40b are not particularly limited, but a SiO 2 film, a Si 3 N 4 film, an Al 2 O 3 film, or the like is preferable from the viewpoint of high insulation.
  • the semiconductor composite film 20C when the semiconductor composite film 20C is thin, for example, when the thickness of the thinnest part of the semiconductor composite film 20C is 10 ⁇ m or less, the mechanical strength of the semiconductor device is improved. From the viewpoint of enhancing, it is preferable to further include a conductive support substrate 70 disposed on the first main surface side of the semiconductor composite film 20C.
  • the conductive support substrate 70 is not particularly limited, but from the viewpoint of high conductivity and high mechanical strength, the specific resistance is preferably 1 ⁇ 10 ⁇ 4 ⁇ ⁇ cm or less, more preferably 1 ⁇ 10 ⁇ 5 ⁇ ⁇ cm or less.
  • the Young's modulus is preferably 0.1 GPa or more, more preferably 1 GPa or more, for example, a metal sintered substrate or the like.
  • the conductive support substrate 70 is disposed on the drain electrode 30d disposed on the first main surface of the semiconductor composite film 20C on the first semiconductor film 21 side.
  • the semiconductor composite film 20C when the semiconductor composite film 20C is thin, for example, when the thickness of the thinnest part of the semiconductor composite film 20C is 10 ⁇ m or less, the mechanical strength of the semiconductor device is increased. From the viewpoint of increasing, it is preferable to further include a support substrate 80 disposed on the second main surface side of the semiconductor composite film 20C.
  • the support substrate 80 is disposed on the third insulating film 40c covering the source electrode 30s and the gate electrode 30g disposed on the second main surface of the semiconductor composite film 20C on the second semiconductor film 22 side. . Since the source electrode 30s and the gate electrode 30g cannot be drawn out to the second main surface side of the semiconductor composite film 20C due to the presence of the support substrate 80, the source electrode 30s and the gate electrode 30g are removed from the side surfaces of the second insulating film 40b and the third insulating film 40c. Has been drawn to.
  • FIGS. 5 to 7 in a method for manufacturing semiconductor devices 2A, 2B, and 2C according to another embodiment of the present invention, semiconductor substrate 20 disposed on base substrate 10 and one main surface side of base substrate 10 is described. And a first trench perpendicular to the main surface of the semiconductor film 20 by removing a part of the semiconductor film 20 of the composite substrate 1 (see FIG. 5A). A step of forming the first semiconductor film 21 having the main surface on which the portion 21t is formed (FIG. 5B), and on the main surface on which the first trench portion 21t of the first semiconductor film 21 is formed.
  • the first main film is formed at the interface between the first semiconductor film 21 and the second semiconductor film 22 and is the main surface on the first semiconductor film 21 side.
  • the source electrode 30s (FIG. 5C) is formed on the second main surface that is perpendicular to the carrier channel layer 20c and is the main surface on the second semiconductor film 22 side of the semiconductor composite film 20C. 6 (D)) and a step of forming the drain electrode 30d on the first main surface of the semiconductor composite film 20C on the first semiconductor film 21 side (FIG. 7B).
  • the manufacturing method of the semiconductor devices 2A, 2B, and 2C of the present embodiment can efficiently manufacture the semiconductor device of the first embodiment having a low on-resistance and a high breakdown voltage without increasing the area of the main surface of the semiconductor device.
  • the method for manufacturing semiconductor devices 2A, 2B, 2C of this embodiment includes a composite substrate including a base substrate 10 and a semiconductor film 20 disposed on one main surface side of the base substrate 10. 1 is provided.
  • the thickness of the semiconductor film 20 of the composite substrate 1 is not particularly limited, and can be adjusted from a thin film thickness of about 50 nm to a thick film thickness of about 250 ⁇ m, that is, over a wide range of 50 nm to 250 ⁇ m. From the viewpoint of increasing the breakdown voltage of the semiconductor device to be formed, the thickness of the semiconductor film 20 of the composite substrate 1 is preferably 1 ⁇ m or more, and more preferably 5 ⁇ m or more.
  • a first to be described later is provided after the step of preparing the composite substrate 1.
  • a step of forming a further semiconductor film 20b on the semiconductor film 20a of the composite substrate 1 is included before the step of forming the semiconductor film 21 (FIG. 5B).
  • a further semiconductor film 20b on the semiconductor film 20a a thick semiconductor film 20 in which the semiconductor film 20a and the further semiconductor film 20b are integrated can be obtained.
  • the semiconductor film 20a and the further semiconductor film 20b preferably have the same chemical composition from the viewpoint of obtaining a uniform thick semiconductor film 20.
  • the method of forming the semiconductor film 20a and the further semiconductor film 20b is the same as the method of forming the semiconductor film 20 described later.
  • the method of disposing the semiconductor film 20 on the one main surface side of the base substrate 10 is not particularly limited, and the following first to third methods can be mentioned.
  • the first method is a method of removing the base substrate 100 after bonding the semiconductor film 20 formed on the main surface of the base substrate 100 to one main surface of the base substrate 10. It is.
  • the semiconductor film donor substrate 20D is bonded to one main surface of the base substrate 10
  • the semiconductor film donor substrate 20D is bonded to the bonding surface by a predetermined depth.
  • the semiconductor film 20 is formed on one main surface of the base substrate 10.
  • the semiconductor film donor substrate 20D is ground from the main surface opposite to the bonded surface.
  • the group III nitride film 13 is formed on one main surface of the base substrate 10 by adjusting the thickness by reducing the thickness by at least one of polishing and etching.
  • the semiconductor film 20 is bonded to the base substrate 10 by bonding the main surface of the semiconductor film 20 with the bonding film 12 interposed on one main surface of the base substrate 10 (FIG. 11).
  • the semiconductor film donor substrate 20D is bonded to the base substrate 10 with the bonding film 12 interposed on one main surface of the base substrate 10 and the semiconductor film donor substrate 20D. Examples include a method of bonding main surfaces (see FIGS. 12 to 14).
  • the bonding film 12 may be formed only on the base substrate 10 and bonded to the semiconductor film 20 or the semiconductor film donor substrate 20D, or the bonding film 12 may be formed only on the semiconductor film 20 or the semiconductor film donor substrate 20D.
  • the base substrate 10 may be pasted together.
  • the step of preparing composite substrate 1 by the first method is not particularly limited, but from the viewpoint of efficiently forming composite substrate 1, a bonding film is formed on one main surface of base substrate 10.
  • a sub-process for forming 12a (FIG. 11A) and a sub-process for forming the semiconductor film 20 on the main surface of the base substrate 100 and forming the bonding film 12b on the main surface of the semiconductor film 20 (FIG. 11B).
  • the main surface of the bonding film 12a formed on the base substrate 10 and the main surface of the bonding film 12b formed on the semiconductor film 20 formed on the base substrate 100 are bonded together to form the bonding substrate 1L.
  • FIG. 11C and a sub-process of removing the base substrate 100 from the bonding substrate 1L (FIG. 11D) are preferably included.
  • base substrate 10 used in the sub-process for forming bonding film 12a on one main surface of base substrate 10 is not particularly limited, and may be, for example, an oxide containing metal element M.
  • the bonding film 12a is not particularly limited as long as the bonding with the base substrate 10 is good, and a SiO 2 film, a Si 3 N 4 film, an Al 2 O 3 film, or the like is preferable.
  • the method for forming the bonding film 12a is not particularly limited as long as it is a method suitable for the material, but from the viewpoint of suppressing the film formation cost, a sputtering method, a vapor deposition method, a CVD (chemical vapor deposition) method, or the like is preferable. It is.
  • the base substrate 100 used is a semiconductor film.
  • the semiconductor film 20 is a group III nitride film such as a GaN film or an Al 1-x Ga x N film (0 ⁇ x ⁇ 1)
  • the base substrate 100 may be used.
  • a group III nitride substrate such as a GaN substrate, a sapphire substrate, a SiC substrate, a Si substrate, or the like is suitable.
  • the method for forming the semiconductor film 20 is not particularly limited as long as it is suitable for the material.
  • an OMVPE organometallic vapor phase epitaxy
  • a sputtering method an MBE ( A molecular beam epitaxy method, a PLD (pulse laser deposition) method, an HVPE (hydride vapor phase epitaxy) method, a sublimation method, a flux method, a high nitrogen pressure solution method, and the like are suitable.
  • the bonding film 12b is not particularly limited as long as bonding with the bonding film 12a and the semiconductor film 20 is satisfactory, and a SiO 2 film, a Si 3 N 4 film, an Al 2 O 3 film, or the like is preferable.
  • the method for forming the bonding film 12b is the same as the method for forming the bonding film 12a.
  • a method of bonding the bonding film 12a and the bonding film 12b in a sub-process of forming the bonding substrate 1L by bonding the main surface of the bonding film 12a and the main surface of the bonding film 12b There are no particular restrictions on the bonding surface, the bonding surface is washed and bonded as it is, then the direct bonding method in which the temperature is raised to about 600 ° C. to 1200 ° C. and the bonding surface is cleaned and activated by plasma or ions.
  • the bonded surface is cleaned with a chemical solution and pure water, and then a high pressure of about 0.1 MPa to 10 MPa is applied.
  • a high-pressure bonding method in which the bonding surfaces are cleaned with a chemical solution and pure water and then bonded in a high vacuum atmosphere of about 10 ⁇ 6 Pa to 10 ⁇ 3 Pa is preferable.
  • the bonding strength can be further increased by raising the temperature to about 600 ° C. to 1200 ° C. after the bonding.
  • the effect of increasing the bonding strength by raising the temperature to about 600 ° C. to 1200 ° C. after the bonding is large.
  • a method for removing base substrate 100 in the sub-step of removing base substrate 100 from bonding substrate 1L is not particularly limited, but from the viewpoint of efficiently removing base substrate 100.
  • a method of removing the base substrate 100 by dissolving it with an etchant such as hydrofluoric acid, a method of removing the base substrate 100 from the exposed main surface side by grinding or polishing, and the like are suitable.
  • a protective member (not shown) for protecting the base substrate 10 may be formed around the base substrate 10. preferable.
  • the composite substrate 1 including the base substrate 10, the bonding film 12 disposed on one main surface of the base substrate 10, and the semiconductor film 20 disposed on the main surface of the bonding film 12 is obtained. It is done.
  • the step of preparing composite substrate 1 by the second method is not particularly limited, but from the viewpoint of efficiently manufacturing composite substrate 1, the cutting method shown in FIG.
  • the cutting method is particularly suitable for preparing the composite substrate 1 having the relatively thick semiconductor film 20 having a thickness of 10 ⁇ m or more and 250 ⁇ m or less
  • the ion implantation method is a relatively thin semiconductor film having a thickness of 50 nm or more and less than 10 ⁇ m.
  • the cutting method and the ion implantation method will be described.
  • the step of preparing composite substrate 1 by a cutting method is not particularly limited, but from the viewpoint of efficiently forming composite substrate 1, bonding film 12 a is formed on one main surface of base substrate 10.
  • the main surface of the semiconductor substrate and the main surface of the bonding film 12b formed on the semiconductor film donor substrate 20D are bonded together to form a bonding substrate 1L (FIG. 12C), and the semiconductor film donor substrate 20D of the bonding substrate 1L.
  • the semiconductor film donor substrate 20D is a donor substrate that provides the semiconductor film 20 by separation in a later step.
  • the method of forming the semiconductor film donor substrate 20D is the same as the method of forming the semiconductor film 20 in the method of preparing the composite substrate by the first method.
  • the method for forming the bonding films 12a and 12b is the same as the method for forming the bonding films 12a and 12b in the method for preparing the composite substrate by the first method.
  • the method of bonding the base substrate 10 and the semiconductor film donor substrate 20D is the same as the method of bonding the base substrate 10 and the semiconductor film 20 in the method of preparing the composite substrate by the first method.
  • the cutting method used in the sub-process for cutting the semiconductor film donor substrate 20D is not particularly limited, and a wire saw, blade, laser, electric discharge machining, water jet, or the like is preferably used.
  • the bonding substrate 1L is separated from the main surface, which is the bonding surface of the semiconductor film donor substrate 20D, at a surface positioned at a predetermined depth, and the base substrate 10 and one main surface of the base substrate 10 are separated.
  • the composite substrate 1 including the bonding film 12 disposed on the semiconductor film 20 disposed on the main surface of the bonding film 12 is obtained.
  • the step of preparing composite substrate 1 by an ion implantation method is not particularly limited, but from the viewpoint of efficiently forming composite substrate 1, bonding film 12 a is formed on one main surface of basic substrate 10.
  • a sub-process (FIG. 13 (A)) for forming an ion implantation region from a main surface side of the semiconductor film donor substrate 20D to a surface at a predetermined depth from the main surface. 20i and a sub-process for forming the bonding film 12b on the main surface (FIG. 13B), and the main surface of the bonding film 12a formed on the base substrate 10 and the semiconductor film donor substrate 20D.
  • a sub-process (FIG. 13 (A)) for forming an ion implantation region from a main surface side of the semiconductor film donor substrate 20D to a surface at a predetermined depth from the main surface. 20i and a sub-process for forming the bonding film 12b on the main surface (FIG. 13B), and the main surface of the bonding film 12a formed on the base
  • the method of forming the semiconductor film donor substrate 20D is the same as the method of forming the semiconductor film 20 in the method of preparing the composite substrate by the first method.
  • the method for forming the bonding films 12a and 12b is the same as the method for forming the bonding films 12a and 12b in the method for preparing the composite substrate by the first method.
  • the method of bonding the base substrate 10 and the semiconductor film donor substrate 20D is the same as the method of bonding the base substrate 10 and the semiconductor film 20 in the method of preparing the composite substrate by the first method.
  • the ions I implanted into the semiconductor film donor substrate 20D are not particularly limited, but the gasification temperature of the ions I implanted into the ion implantation region 20i can be determined from the viewpoint of suppressing the deterioration of the quality of the semiconductor film 20. From the viewpoint of making the temperature lower than the decomposition temperature, ions of atoms having a small mass such as hydrogen ions and helium ions are preferable.
  • the method for separating the semiconductor film donor substrate 20D by the ion implantation region 20i is not particularly limited as long as it is a method for gasifying the ions I implanted into the ion implantation region 20i.
  • the bonding substrate 1L is separated from the main surface, which is the bonding surface of the semiconductor film donor substrate 20D, at a surface positioned at a predetermined depth, and the base substrate 10 and one main surface of the base substrate 10 are separated.
  • the composite substrate 1 including the bonding film 12 disposed on the semiconductor film 20 disposed on the main surface of the bonding film 12 is obtained.
  • the step of preparing composite substrate 1 by the third method is not particularly limited, but a bonding film is formed on one main surface of base substrate 10 from the viewpoint of efficiently manufacturing composite substrate 1.
  • a sub-process for forming 12a (FIG. 14A), a sub-process for forming the bonding film 12b on one main surface of the semiconductor donor substrate 20D (FIG. 14B), and the base substrate 10
  • the third method is particularly suitable for preparing the composite substrate 1 having the relatively thick semiconductor film 20 having a thickness of 10 ⁇ m or more and 250 ⁇ m or less.
  • the semiconductor film donor substrate 20D is a donor substrate that provides the semiconductor film 20 by at least one of grinding, polishing, and etching in addition to the separation in the second method in a later step.
  • the method of forming the semiconductor film donor substrate 20D is the same as the method of forming the semiconductor film 20 in the method of preparing the composite substrate by the first method.
  • the method for forming the bonding films 12a and 12b is the same as the method for forming the bonding films 12a and 12b in the method for preparing the composite substrate by the first method.
  • the method of bonding the base substrate 10 and the semiconductor film donor substrate 20D is the same as the method of bonding the base substrate 10 and the semiconductor film 20 in the method of preparing the composite substrate by the first method.
  • the method for grinding the semiconductor film donor substrate 20D is not particularly limited, and examples thereof include grinding with a grindstone (surface grinding) and shot blasting.
  • the method for polishing the semiconductor film donor substrate 20D is not particularly limited, and examples thereof include mechanical polishing and CMP (chemical mechanical polishing).
  • the method for etching the semiconductor film donor substrate 20D is not particularly limited, and examples include wet etching with a chemical solution and dry etching such as RIE (reactive ion etching).
  • the composite substrate 1 including the base substrate 10, the bonding film 12 disposed on one main surface of the base substrate 10, and the semiconductor film 20 disposed on the main surface of the bonding film 12 is obtained. It is done.
  • Step of forming first semiconductor film Next, referring to FIG. 5B, the method of manufacturing the semiconductor devices 2A, 2B, 2C of the present embodiment removes a part of the semiconductor film 20 of the composite substrate 1 so that the main part of the semiconductor film 20 is removed. A step of forming a first semiconductor film 21 having a main surface on which a first trench portion 21t perpendicular to the surface is formed.
  • a method for removing a part of the semiconductor film 20 is not particularly limited.
  • patterning is performed on the main surface of the semiconductor film 20 by an electron beam lithography method and a photolithography method.
  • the etching is preferably dry etching such as RIE (reactive ion etching) from the viewpoint of forming the first trench portion 21 t perpendicular to the main surface of the semiconductor film 20.
  • RIE reactive ion etching
  • the term “perpendicular to the main surface of the semiconductor film 20” is sufficient if it is substantially vertical enough to increase the breakdown voltage without increasing the main surface of the semiconductor device to be formed. It is sufficient if it is 80 ° or more and 100 ° or less with respect to the main surface of the device.
  • the depth of the first trench portion 21t corresponds to the length L of the carrier channel layer 20c described later. From the viewpoint of increasing the thickness, it is preferably 1 ⁇ m or more, more preferably 4 ⁇ m or more. From the viewpoint of reducing the on-resistance of the semiconductor device, it is preferably 20 ⁇ m or less, and more preferably 10 ⁇ m or less.
  • the composite substrate in the case where the step of forming the additional semiconductor film 20b on the first semiconductor film 20a is included, the step of forming the first semiconductor film 21 includes a part of the additional semiconductor film 20b and one of the semiconductor film 20a and the additional semiconductor film 20b. This can be done by removing any of the parts. Thus, a part of the thick semiconductor film 20 in which the semiconductor film 20a and the semiconductor film 20b are integrated (a part of the semiconductor film 20b and any one of the semiconductor film 20a and the further semiconductor film 20b) is removed. Thus, the desired first semiconductor film 21 can be obtained.
  • the main surface of the first semiconductor film 21 on which the first trench portion 21t is formed is formed.
  • the first main surface is formed at the interface between the first semiconductor film 21 and the second semiconductor film 22 and is the main surface on the first semiconductor film 21 side.
  • the method for forming the second semiconductor film 22 is not particularly limited as long as it is suitable for the material.
  • an OMVPE (organometallic vapor phase epitaxy) method is used.
  • the sputtering method, MBE (molecular beam epitaxy) method, PLD (pulse laser deposition) method, HVPE (hydride vapor phase epitaxy) method, sublimation method, flux method, high nitrogen pressure solution method and the like are suitable.
  • the OMVPE method and the MBE method are particularly preferable from the viewpoint of forming a thin semiconductor film with high crystallinity.
  • the first semiconductor film 21 having the first main surface and the main surface on which the first trench portion 21t perpendicular to the first main surface is formed, and the first semiconductor film The second main surface is disposed on the main surface on which the 21st first trench portion 21t is formed and has a second main surface on which the second trench portion 22t corresponding to the first trench portion 21t is formed.
  • a semiconductor composite film 20C including two semiconductor films 22 is obtained.
  • Step of forming the first insulating film Next, referring to FIG. 5D, the method for manufacturing the semiconductor devices 2A, 2B, 2C of the present embodiment is performed on the second main surface of the semiconductor composite film 20C on the second semiconductor film 22 side and on the second main surface.
  • the process of forming the 1st insulating film 40a on the 2nd trench part 22t formed in 2 main surfaces can be included.
  • the method for forming the first insulating film 40a is not particularly limited as long as it is suitable for the material, and a sputtering method, an ALD (atomic layer deposition) method, or the like is preferable.
  • the manufacturing method of the semiconductor devices 2A, 2B, and 2C according to the present embodiment may include a step of removing a part of the first insulating film 40a.
  • a step of removing a part of the first insulating film 40a Through this step, at least a part of the second main surface of the semiconductor composite film 20C on the second semiconductor film 22 side and the surface of the third trench portion 23t formed on the second main surface can be exposed.
  • the method for removing a part of the first insulating film 40a is not particularly limited, and at least one of dry etching and wet etching can be used.
  • the position of the gate electrode formed in the process described later is determined by the thickness of the first insulating film 40a remaining after the third trench portion 23t is formed.
  • the third trench portion 23t is formed by disposing the first insulating film 40a in a part of the second trench portion 22t.
  • the method of manufacturing the semiconductor devices 2A, 2B, and 2C according to the present embodiment is the second main side of the semiconductor composite film 20C on the second semiconductor film 22 side.
  • the first insulation so as to be in contact with a part of the main surface which is the exposed surface of the third trench portion 23 t formed on the surface and is perpendicular to the first main surface of the first semiconductor film 21.
  • a step of forming a gate electrode 30g on the film 40a can be included.
  • the method for forming the gate electrode 30g is not particularly limited as long as it is suitable for the material, and vacuum evaporation (particularly, resistance heating vacuum evaporation, electron beam evaporation) is preferable.
  • the gate electrode 30g is disposed in a part of the third trench portion 23t, and the fourth trench portion 24t is formed.
  • Step of forming the second insulating film Next, with reference to FIGS. 6B and 6C, in the method of manufacturing the semiconductor devices 2A, 2B, and 2C of the present embodiment, the second main side of the semiconductor composite film 20C on the second semiconductor film 22 side is described. Forming a second insulating film 40b on the surface, the surface of the fourth trench portion 24t, and the gate electrode 30g.
  • the method for forming the second insulating film 40b is the same as the method for forming the first insulating film 40a described above.
  • the method for manufacturing the semiconductor devices 2A, 2B, and 2C according to the present embodiment may include a step of removing a part of the second insulating film 40b. Through this step, a part of the second main surface of the semiconductor composite film 20C on the second semiconductor film 22 side and a part of the gate electrode 30g can be exposed.
  • a step of forming a lead portion of the gate electrode 30g on the exposed portion of the gate electrode 30g may be included.
  • the gate electrode 30g is drawn to the second main surface side of the second semiconductor film 22 of the semiconductor composite film 20C.
  • the method for forming the lead portion of the gate electrode 30g is the same as the method for forming the gate electrode described above.
  • the second main surface of the semiconductor composite film 20C on the second semiconductor film 22 side is exposed.
  • a step of forming a source electrode 30s on the portion is included.
  • the method for forming the source electrode 30s is not particularly limited as long as it is suitable for the material, and vacuum deposition (particularly, resistance heating vacuum deposition, electron beam heating vacuum deposition) and the like are suitable.
  • the gate electrode 30g and the source electrode 30s of the second semiconductor film 22 of the semiconductor composite film 20C are formed.
  • the step of forming the protective insulating film 50 on the second main surface side can be included.
  • Protective insulating film 50 is not particularly limited, from the viewpoint of protecting the gate electrode 30g and the source electrode 30s, SiO 2 film, Si 3 N 4 film, such as an Al 2 O 3 film is preferable.
  • a method for forming the protective insulating film 50 is not particularly limited as long as it is suitable for the material, and a sputtering method, an ALD (atomic layer deposition) method, or the like is preferable.
  • the gate electrode 30g and the source electrode 30s of the second semiconductor film 22 of the semiconductor composite film 20C are formed.
  • the step of disposing the temporary support substrate 60 on the protective insulating film 50 formed on the second main surface side can be included. Since the semiconductor composite film 20C is supported by the temporary support substrate 60 disposed by such a process, the semiconductor composite film 20C exposed by removing the base substrate 10 is exposed on the first main surface on the first semiconductor film 21 side. It becomes easy to form the drain electrode 30d.
  • the temporary support substrate 60 is not particularly limited as long as it can support the semiconductor composite film 20C, but a silicon substrate, a sapphire substrate, a metal substrate, and the like are preferable from the viewpoint of low cost.
  • the method for arranging the temporary support substrate 60 is not particularly limited, but from the viewpoint of facilitating the removal of the temporary support substrate 60 after the arrangement, a method of temporarily bonding with wax or the like is preferable.
  • the method of manufacturing the semiconductor devices 2A, 2B, 2C of the present embodiment is arranged on the first main surface side of the first semiconductor film 21 of the semiconductor composite film 20C.
  • a step of removing the underlying base substrate 10 may be included.
  • the bonding film 12 is formed between the first semiconductor film 21 of the semiconductor composite film 20C and the base substrate 10, the base substrate 10 and the bonding film 12 can be removed (FIG. 7 ( A) arrows indicate removal).
  • the method for removing the base substrate 10 and the bonding film 12 is not particularly limited as long as it is suitable for these materials, and there are methods such as etching such as dry etching and wet etching, grinding, and polishing.
  • the first semiconductor film 21 side of the semiconductor composite film 20C exposed by removing the base substrate 10 is used. Forming a drain electrode 30d on the first main surface.
  • the method for forming the drain electrode 30d is not particularly limited as long as it is suitable for the material, and a vacuum evaporation method (particularly, resistance heating vacuum evaporation method, electron beam heating vacuum evaporation method) or the like is preferable.
  • the method for manufacturing the semiconductor devices 2 ⁇ / b> A, 2 ⁇ / b> B, and 2 ⁇ / b> C of this embodiment may include a step of removing the temporary support substrate 60.
  • the method for removing the temporary support substrate 60 is not particularly limited, and when the temporary support substrate 60 is temporarily bonded with wax or the like, a method of melting, dissolving or removing the wax or the like is preferable.
  • the method for manufacturing the semiconductor devices 2A, 2B, and 2C of the present embodiment may include a step of removing the protective insulating film 50.
  • the method for removing the protective insulating film 50 is not particularly limited as long as it is suitable for the material, and at least one of dry etching and wet etching can be used.
  • the semiconductor device 2A of the first embodiment having a low on-resistance and a high breakdown voltage without increasing the area of the main surface of the device (that is, the first main surface and the first main surface perpendicular to the first main surface).
  • a semiconductor composite film 20C including a carrier channel layer 20c having a vertical main surface, a drain electrode 30d disposed on the first main surface of the semiconductor composite film 20C, and a second main surface of the semiconductor composite film 20C
  • a semiconductor device) that includes can be produced efficiently.
  • semiconductor device 2A (FIGS. 7D and 8A) after the step of forming drain electrode 30d (FIG. 7B) is performed. )) May further include a step (FIG. 8B) of disposing the conductive support substrate 70 on the first main surface side where the drain electrode 30d is formed.
  • the semiconductor composite film 20C can be supported and the mechanical strength of the semiconductor device can be increased.
  • the conductive support substrate 70 is not particularly limited, but has a specific resistivity of 1 ⁇ 10 ⁇ 4 ⁇ ⁇ cm or less in order to increase the mechanical strength and characteristics of the semiconductor device, and the drain. From the viewpoint of ohmic contact with the electrode 30d, a silicon substrate, a metal substrate, a metal sintered substrate, or the like is preferable.
  • the method for disposing the conductive support substrate 70 is not particularly limited, and there is a method in which the conductive support substrate 70 is bonded onto the drain electrode 30d.
  • Examples of the method for attaching the conductive support substrate 70 include a pressure fusion method, a current heating method, and the like.
  • a bonding film (not shown) may be interposed between the conductive support substrate 70 and the drain electrode 30d.
  • the bonding film between the conductive support substrate 70 and the drain electrode 30d is not particularly limited as long as the bonding between the conductive support substrate 70 and the drain electrode 30d is good, and a metal solder film, a conductive paste film, or the like Is preferred.
  • the support substrate 80 is not particularly limited, but a silicon substrate, a sapphire substrate, a glass substrate, a GaN substrate, a metal substrate, or the like is preferable in order to increase the mechanical strength of the semiconductor device.
  • the support substrate 80 In order to dispose the support substrate 80 on the second main surface side from which the gate electrode 30g of the second semiconductor film 22 of the semiconductor composite film 20C is drawn and the source electrode 30s is formed, as shown in FIG.
  • the method for forming the source electrode 30s and the lead-out portion of the gate electrode is the same as the method for forming the source electrode 30s and the gate electrode 30g, respectively.
  • the semiconductor device manufacturing method of the present embodiment is performed after the step of forming the gate electrode 30g and the step of forming the source electrode 30s (FIG. 6D). See), the gate electrode 30g drawn to the second main surface side of the second semiconductor film 22 of the semiconductor composite film 20C, the formed source electrode 30s, and the formed second insulating film 40b on the source electrode A step of forming the third insulating film 40c so as to cover the lead portion of 30s and the lead portion of the gate electrode 30g may be included.
  • the method for forming the third insulating film 40c is not particularly limited as long as it is suitable for the material, and a sputtering method, an ALD (atomic layer deposition) method, an electron beam heating vapor deposition method and the like are preferable.
  • the method for manufacturing a semiconductor device of this embodiment may include a step of disposing a support substrate 80 on the third insulating film 40c.
  • the method for arranging the support substrate 80 is not particularly limited, and there is a method in which the support substrate 80 is bonded onto the third insulating film 40c.
  • a method for attaching the support substrate 80 there are a heat fusion method, an electric heating method, and the like.
  • a bonding film (not shown) may be interposed between the support substrate 80 and the third insulating film 40c.
  • the bonding film between the support substrate 80 and the third insulating film 40c is not particularly limited as long as the bonding between the support substrate 80 and the third insulating film 40c is good, and is a metal solder film or a resin cured film. Etc. are suitable.
  • the step of removing base substrate 10 that can be included after the step of disposing support substrate 80 is the same as the step of removing base substrate 10 shown in FIG. .
  • the step of forming the drain electrode 30d shown in FIG. 9C is the same as the step of forming the drain electrode shown in FIG.
  • Example 1 According to the following procedure, a semiconductor device 2A which is a vertical FET (field effect transistor) shown in FIG. 1 was produced and its characteristics were evaluated.
  • a semiconductor device 2A which is a vertical FET (field effect transistor) shown in FIG. 1 was produced and its characteristics were evaluated.
  • a Mo sintered substrate having a thickness of 400 ⁇ m that is the base substrate 10 and a SiO 2 film having a thickness of 200 nm that is the bonding film 12 are interposed on one main surface thereof.
  • a patterned resist film (not shown) is formed on the main surface of the semiconductor film 20 by electron beam lithography and photolithography. After that, by removing a part of the semiconductor film 20 by RIE (reactive ion etching), the first trench portion 21t having a depth of 6 ⁇ m and a width of 2 ⁇ m perpendicular to the main surface of the semiconductor film 20 is formed. A first semiconductor film 21 formed at a pitch of 4 ⁇ m was formed.
  • ALD on the main surface of the semiconductor composite film 20C on which the second trench portion 22t on the second semiconductor film 22 side is formed.
  • the thickness from the bottom of the second trench portion 22t formed on the main surface of the semiconductor composite film 20C on the second semiconductor film 22 side by the atomic layer deposition method is 6.5 ⁇ m.
  • a SiO 2 film was formed.
  • a part of the first insulating film 40a is removed by RIE (reactive ion etching), whereby the second semiconductor film 22 side of the semiconductor composite film 20C is removed.
  • the surface of the 3rd trench part 23t formed in 2 main surface and 2nd main surface was exposed.
  • the depth of the exposed third trench portion 23t was 2 ⁇ m. That is, the thickness of the first insulating film 40a was 4.5 ⁇ m.
  • a gate width as a gate electrode 30g is formed on the first insulating film 40a so as to be in contact with a part of the main surface which is an exposed surface and is perpendicular to the first main surface of the first semiconductor film 21.
  • a 0.5 ⁇ m Ni / Au electrode was formed by vacuum deposition.
  • the gate electrode 30g is disposed in a part of the third trench portion 23t, and the fourth trench portion 24t is formed.
  • Second Insulating Film Formation of Second Insulating Film
  • ALD atomic layer deposition
  • a part of the second main surface on the second semiconductor film 22 side of the semiconductor composite film 20C and the gate electrode are removed by removing a part of the second insulating film 40b by RIE (reactive ion etching). A portion of 30 g was exposed.
  • an Au electrode lead portion was formed as a lead portion of the gate electrode 30g on the exposed portion of the gate electrode 30g by vacuum deposition.
  • a thickness of 20 nm is formed as a source electrode 30s on the exposed portion of the second main surface of the semiconductor composite film 20C on the second semiconductor film 22 side.
  • the Ti electrode was formed by vacuum deposition.
  • a protective film is formed on the second main surface side of the second semiconductor film 22 of the semiconductor composite film 20C on which the gate electrode 30g and the source electrode 30s are formed.
  • a SiO 2 film having a thickness of 3 ⁇ m from the second main surface was formed.
  • an Si (silicon) substrate having a thickness of 400 ⁇ m is disposed as a temporary support substrate 60 on the protective insulating film 50 by bonding with wax.
  • a part of the first semiconductor film 21 of the composite film 20C was removed by polishing and dry etching.
  • the thickness of the thin portion of the first semiconductor film 21 (which is equal to the shortest distance between the carrier channel layer in the plane perpendicular to the first main surface and the first main surface) is determined by the X-ray diffraction method. It was 10 nm when measured.
  • drain electrode 30d is formed on the first main surface of the semiconductor composite film 20C exposed by removing the base substrate 10 on the first semiconductor film 21 side.
  • a Ti electrode having a thickness of 20 nm was formed by vacuum evaporation.
  • the protective insulating film 50 is removed by RIE (reactive ion etching), and the second semiconductor film 22 side second semiconductor film 20C side is removed.
  • RIE reactive ion etching
  • the semiconductor device 2R which is a lateral FET (electric field transistor) shown in FIG. 2, was manufactured by the following procedure, and the characteristics thereof were evaluated.
  • a first semiconductor film which is an n-GaN film having a thickness of 7 ⁇ m, was formed on the prepared composite substrate.
  • an Al 0.3 Ga 0.7 N film having a thickness of 10 nm was formed as a second semiconductor film on the main surface of the first semiconductor film by OMVPE (metal organic vapor phase epitaxy).
  • OMVPE metal organic vapor phase epitaxy
  • the main surface parallel to the first main surface on the first semiconductor film side and the second main surface on the second semiconductor film side is formed at the interface between the first semiconductor film and the second semiconductor film.
  • a semiconductor composite film including the carrier channel layer was obtained.
  • the main film on the second semiconductor film side of the semiconductor composite film as an insulating film is formed by ALD (atomic layer deposition) method.
  • a SiO 2 film having a thickness of 1 ⁇ m was formed on the surface.
  • a Ti electrode having a thickness of 20 nm as a source electrode and a Ni having a gate width of 0.5 ⁇ m and a thickness of 30 nm as a gate electrode A Ti electrode having a thickness of 20 nm was formed by vacuum deposition as an electrode and a drain electrode.
  • the distance between the source electrode end and the gate electrode end is 1 ⁇ m
  • the distance between the gate electrode end and the drain electrode end is 4.5 ⁇ m
  • the distance between the source electrode end and the drain electrode end is 6 ⁇ m
  • the length L of the carrier channel layer was 6 ⁇ m. In this way, a lateral FET was obtained as the semiconductor device 2R.
  • the obtained semiconductor device 2R had a withstand voltage of 300 V and an on-resistance of 1 m ⁇ ⁇ cm 2 .
  • the vertical FET which is a semiconductor device according to the present invention, has the same breakdown voltage and on-resistance as a typical lateral FET, and has a main surface per unit.
  • the size of the area was 1/3 of a typical lateral FET.
  • the lateral FET as in Comparative Example 1 needs to increase the area of the main surface per unit.
  • the semiconductor composite film It is sufficient to increase the channel length of the carrier channel layer having a main surface perpendicular to the main surfaces (the first main surface and the second main surface), and it is not necessary to increase the area of the main surface per unit. That is, the semiconductor device according to the present invention can increase the breakdown voltage without increasing the area of the main surface per unit.

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Abstract

A semiconductor device (2A) comprises: a semiconductor composite film (20C) having a first main surface and a second main surface which is a main surface on the opposite side of the first main surface, and comprising a carrier channel layer (20c), which has a main surface that is perpendicular to the first main surface and the second main surface; a drain electrode (30d) which is disposed upon the first main surface of the semiconductor composite film (20C); and source electrodes (30s) which are disposed upon the second main surface of the semiconductor composite film (20C). Accordingly, a semiconductor device is provided which has low ON resistance and which can increase breakdown voltage without increasing the size of the area of the main surfaces of the device.

Description

半導体デバイスおよびその製造方法Semiconductor device and manufacturing method thereof
　本発明は、キャリアチャネル層を有する半導体複合膜とソース電極とドレイン電極とを含む半導体デバイスおよびその製造方法に関する。 The present invention relates to a semiconductor device including a semiconductor composite film having a carrier channel layer, a source electrode, and a drain electrode, and a manufacturing method thereof.
　ＨＥＭＴ（高電子移動度トランジスタ）などのＦＥＴ（電界効果トランジスタ）は、電子集積回路などに好適に用いられる高いトランジスタ機能を有する半導体デバイスとして注目されている。 FETs (field effect transistors) such as HEMTs (high electron mobility transistors) are attracting attention as semiconductor devices having high transistor functions that are suitably used in electronic integrated circuits and the like.
　特開２０１２－２４３７９２号公報（特許文献１）は、バッファリーク電流およびゲートリーク電流が抑制された高性能のＨＥＭＴを開示する。また、特開２０１２－０９４６８８号公報（特許文献２）は、優れた縦方向耐圧とトランジスタ動作時のドレインリーク電流が抑制され斜面チャネル構造を有する半導体装置を開示する。また、特開２０１３－０３８１０１号公報（特許文献３）は、オン抵抗が低く耐圧が高いスーパージャンクション構造を有する半導体装置およびその製造方法を開示する。 Japanese Patent Application Laid-Open No. 2012-243792 (Patent Document 1) discloses a high-performance HEMT in which buffer leakage current and gate leakage current are suppressed. Japanese Patent Laying-Open No. 2012-094688 (Patent Document 2) discloses a semiconductor device having an inclined channel structure in which excellent vertical breakdown voltage and drain leakage current during transistor operation are suppressed. Japanese Patent Laying-Open No. 2013-038101 (Patent Document 3) discloses a semiconductor device having a super junction structure with low on-resistance and high breakdown voltage, and a method for manufacturing the same.
特開２０１２－２４３７９２号公報JP 2012-243792 A 特開２０１２－０９４６８８号公報JP 2012-094688 A 特開２０１３－０３８１０１号公報JP2013-0338101A
　特開２０１２－２４３７９２号公報（特許文献１）に開示されたＨＥＭＴは、ソース電極、ゲート電極およびドレイン電極が一方の主面側に配置された横型のＦＥＴの一種であることから、耐圧を高くするためにはソース電極とドレイン電極との間の距離を長くする必要があるため、デバイスの主面の面積を大きくなりコストが高くなるという問題点があった。また、ＨＥＭＴに大電流を流すために、抵抗を低くする観点から、デバイスの主面の面積を大きくする必要があり、コストが高くなるという問題点があった。特開２０１２－０９４６８８号公報（特許文献２）に開示された半導体装置は、ドリフト層が存在するため、移動度が制限されるという問題点があった。特開２０１３－０３８１０１号公報（特許文献３）に開示された半導体装置は、ドリフト層の抵抗が存在するため、半導体装置のオン抵抗が一定値以下にはならないという問題点があった。 The HEMT disclosed in Japanese Patent Application Laid-Open No. 2012-243792 (Patent Document 1) is a type of lateral FET in which a source electrode, a gate electrode, and a drain electrode are arranged on one main surface side. In order to achieve this, since it is necessary to increase the distance between the source electrode and the drain electrode, there is a problem that the area of the main surface of the device is increased and the cost is increased. In addition, since a large current is allowed to flow through the HEMT, it is necessary to increase the area of the main surface of the device from the viewpoint of reducing the resistance, resulting in an increase in cost. The semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2012-094688 (Patent Document 2) has a problem that mobility is limited because of the presence of a drift layer. The semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2013-038101 (Patent Document 3) has a problem in that the on-resistance of the semiconductor device does not fall below a certain value because the resistance of the drift layer exists.
　本発明は、上記の問題点を解決して、オン抵抗が低くデバイスの主面の面積を大きくすることなく耐圧を高くすることができる半導体デバイスおよびその製造方法を提供することを目的とする。 An object of the present invention is to solve the above-described problems and to provide a semiconductor device having a low on-resistance and a high breakdown voltage without increasing the area of the main surface of the device and a method for manufacturing the same.
　本発明は、ある局面に従えば、第１の主面と第１の主面の反対側の主面である第２の主面とを有し、第１の主面および第２の主面に対して垂直な主面を有するキャリアチャネル層を含む半導体複合膜と、半導体複合膜の第１の主面上に配置されたドレイン電極と、半導体複合膜の第２の主面上に配置されたソース電極と、を含む半導体デバイスである。 According to a certain aspect, the present invention has a first main surface and a second main surface that is a main surface opposite to the first main surface, the first main surface and the second main surface. A semiconductor composite film including a carrier channel layer having a main surface perpendicular to the semiconductor composite film; a drain electrode disposed on the first main surface of the semiconductor composite film; and a second main surface of the semiconductor composite film. And a source electrode.
　本発明は、別の局面に従えば、基礎基板と基礎基板の一主面側に配置された半導体膜とを含む複合基板を準備する工程と、複合基板の半導体膜の一部を除去することにより、半導体膜の主面に対して垂直な第１のトレンチ部が形成された主面を有する第１の半導体膜を形成する工程と、第１の半導体膜の第１のトレンチ部が形成された主面上に第２の半導体膜を形成することにより、第１の半導体膜と第２の半導体膜との界面に形成されておりかつ第１の半導体膜側の主面である第１の主面に対して垂直な主面を有するキャリアチャネル層を含む半導体複合膜を形成する工程と、半導体複合膜の第２の半導体膜側の主面でありキャリアチャネル層に対して垂直な第２の主面上にソース電極を形成する工程と、半導体複合膜の第１の半導体側の第１の主面上にドレイン電極を形成する工程と、を含む半導体デバイスの製造方法である。 According to another aspect of the present invention, a step of preparing a composite substrate including a base substrate and a semiconductor film disposed on one main surface side of the base substrate, and removing a part of the semiconductor film of the composite substrate Thus, the step of forming the first semiconductor film having the main surface in which the first trench portion perpendicular to the main surface of the semiconductor film is formed, and the first trench portion of the first semiconductor film are formed. By forming the second semiconductor film on the main surface, the first semiconductor film is formed at the interface between the first semiconductor film and the second semiconductor film and is the main surface on the first semiconductor film side. Forming a semiconductor composite film including a carrier channel layer having a main surface perpendicular to the main surface; and a second surface perpendicular to the carrier channel layer, the main surface of the semiconductor composite film on the second semiconductor film side. Forming a source electrode on the main surface of the semiconductor, and a first semiconductor side of the semiconductor composite film And forming a drain electrode on the first major surface, a method of manufacturing a semiconductor device comprising.
　本発明によれば、オン抵抗が低くデバイスの主面の面積を大きくすることなく耐圧を高くすることができる半導体デバイスおよびその製造方法を提供することができる。 According to the present invention, it is possible to provide a semiconductor device that has a low on-resistance and can increase the breakdown voltage without increasing the area of the main surface of the device, and a method for manufacturing the semiconductor device.
本発明にかかる半導体デバイスのある例を示す概略断面図である。It is a schematic sectional drawing which shows a certain example of the semiconductor device concerning this invention. 典型的な半導体デバイスのある例を示す概略断面図である。It is a schematic sectional drawing which shows a certain example of a typical semiconductor device. 本発明にかかる半導体デバイスの別の例を示す概略断面図である。It is a schematic sectional drawing which shows another example of the semiconductor device concerning this invention. 本発明にかかる半導体デバイスのさらに別の例を示す概略断面図である。It is a schematic sectional drawing which shows another example of the semiconductor device concerning this invention. 本発明にかかる半導体デバイスの製造方法の複合基板の準備からキャリアチャネル層を含む半導体複合膜の形成までの工程のある例を示す概略断面図である。It is a schematic sectional drawing which shows an example with the process from preparation of the composite substrate of the manufacturing method of the semiconductor device concerning this invention to formation of the semiconductor composite film containing a carrier channel layer. 本発明にかかる半導体デバイスの製造方法のキャリアチャネル層を含む半導体複合膜の形成からソース電極の形成までの工程のある例を示す概略断面図である。It is a schematic sectional drawing which shows an example with the process from formation of the semiconductor composite film containing the carrier channel layer of the manufacturing method of the semiconductor device concerning this invention to formation of a source electrode. 本発明にかかる半導体デバイスの製造方法のソース電極の形成からドレイン電極の形成までの工程のある例を示す概略断面図である。It is a schematic sectional drawing which shows an example with the process from formation of the source electrode of the manufacturing method of the semiconductor device concerning this invention to formation of a drain electrode. 本発明にかかる半導体デバイスの製造方法のドレイン電極が形成された第１の主面側への導電性支持基板の配置の工程のある例を示す概略断面図である。It is a schematic sectional drawing which shows an example with the process of arrangement | positioning of the electroconductive support substrate to the 1st main surface side in which the drain electrode of the manufacturing method of the semiconductor device concerning this invention was formed. 本発明にかかる半導体デバイスの製造方法のソース電極が形成された第２の主面側への支持基板の配置から第１の主面側へのドレイン電極の配置までの工程のある例を示す概略断面図である。Schematic showing an example of a process from the arrangement of the support substrate on the second main surface side where the source electrode is formed to the arrangement of the drain electrode on the first main surface side in the method for manufacturing a semiconductor device according to the present invention. It is sectional drawing. 本発明にかかる半導体デバイスの製造方法の複合基板の準備から複合基板の半導体膜上へのさらなる半導体膜の形成までの工程のある例を示す概略断面図である。It is a schematic sectional drawing which shows an example with the process from preparation of the composite substrate of the manufacturing method of the semiconductor device concerning this invention to formation of the further semiconductor film on the semiconductor film of a composite substrate. 本発明にかかる半導体デバイスの製造方法における複合基板を準備する工程のある例を示す概略断面図である。It is a schematic sectional drawing which shows an example with the process of preparing the composite substrate in the manufacturing method of the semiconductor device concerning this invention. 本発明にかかる半導体デバイスの製造方法における複合基板を準備する工程の別の例を示す概略断面図である。It is a schematic sectional drawing which shows another example of the process of preparing the composite substrate in the manufacturing method of the semiconductor device concerning this invention. 本発明にかかる半導体デバイスの製造方法における複合基板を準備する工程のさらに別の例を示す概略断面図である。It is a schematic sectional drawing which shows another example of the process of preparing the composite substrate in the manufacturing method of the semiconductor device concerning this invention. 本発明にかかる半導体デバイスの製造方法における複合基板を準備する工程のさらに別の例を示す概略断面図である。It is a schematic sectional drawing which shows another example of the process of preparing the composite substrate in the manufacturing method of the semiconductor device concerning this invention.
　＜本発明の実施形態の説明＞
　図面を参照して、本発明のある実施形態である半導体デバイス２Ａ，２Ｂ，２Ｃは、第１の主面と第１の主面の反対側の主面である第２の主面とを有し、第１の主面および第２の主面に対して垂直な主面を有するキャリアチャネル層２０ｃを含む半導体複合膜２０Ｃと、半導体複合膜２０Ｃの第１の主面上に配置されたドレイン電極３０ｄと、半導体複合膜２０Ｃの第２の主面上に配置されたソース電極３０ｓと、を含む。本実施形態の半導体デバイスは、第１の主面および第２の主面に対して垂直な主面を有するキャリアチャネル層２０ｃを有しているため、オン抵抗を低くできるとともに、半導体デバイスの主面の面積を大きくすることなく耐圧を高くすることができる。 <Description of Embodiment of the Present Invention>
Referring to the drawings, semiconductor devices 2A, 2B, 2C according to an embodiment of the present invention have a first main surface and a second main surface that is a main surface opposite to the first main surface. A semiconductor composite film 20C including a carrier channel layer 20c having a main surface perpendicular to the first main surface and the second main surface, and a drain disposed on the first main surface of the semiconductor composite film 20C 30d including electrode 30d and source electrode 30s disposed on the second main surface of semiconductor composite film 20C. Since the semiconductor device of the present embodiment includes the carrier channel layer 20c having a main surface perpendicular to the first main surface and the second main surface, the on-resistance can be lowered and the main part of the semiconductor device can be reduced. The breakdown voltage can be increased without increasing the surface area.
　本発明のかかる実施形態である半導体デバイス２Ａ，２Ｂ，２Ｃにおいて、半導体複合膜２０Ｃは、第１の主面と第１の主面に対して垂直な第１のトレンチ部２１ｔが形成されている主面とを有する第１の半導体膜２１と、第１の半導体膜２１の第１のトレンチ部２１ｔが形成されている主面上に配置されておりかつ第１のトレンチ部２１ｔに対応する第２のトレンチ部２２ｔが形成されている第２の主面を有する第２の半導体膜２２と、を含み、キャリアチャネル層２０ｃは、第１の半導体膜２１と第２の半導体膜２２との界面に形成され得る。これにより、第１の主面および第２の主面に垂直な主面を有するキャリアチャネル層２０ｃが形成され、オン抵抗が低く、かつ、主面の面積を大きくすることなく耐圧が高い半導体デバイスが得られる。 In the semiconductor devices 2A, 2B, and 2C according to the embodiments of the present invention, the semiconductor composite film 20C is formed with the first main surface and the first trench portion 21t perpendicular to the first main surface. A first semiconductor film 21 having a main surface and a first semiconductor film 21 disposed on the main surface of the first semiconductor film 21 where the first trench portion 21t is formed and corresponding to the first trench portion 21t. A second semiconductor film 22 having a second main surface in which two trench portions 22t are formed, and the carrier channel layer 20c is an interface between the first semiconductor film 21 and the second semiconductor film 22 Can be formed. As a result, the carrier channel layer 20c having a main surface perpendicular to the first main surface and the second main surface is formed, and the semiconductor device has a low on-resistance and a high breakdown voltage without increasing the area of the main surface. Is obtained.
　また、本発明のかかる実施形態である半導体デバイス２Ｂは、半導体複合膜２０Ｃの第１の主面側に配置された導電性支持基板７０をさらに含むことができる。これにより、機械的強度の高い半導体デバイスが得られる。 In addition, the semiconductor device 2B according to the embodiment of the present invention can further include a conductive support substrate 70 disposed on the first main surface side of the semiconductor composite film 20C. Thereby, a semiconductor device with high mechanical strength is obtained.
　また、本発明のかかる実施形態である半導体デバイス２Ｃは、半導体複合膜２０Ｃの第２の主面側に配置された支持基板８０をさらに含むことができる。これにより、機械的強度の高い半導体デバイスが得られる。 Further, the semiconductor device 2C according to the embodiment of the present invention can further include a support substrate 80 disposed on the second main surface side of the semiconductor composite film 20C. Thereby, a semiconductor device with high mechanical strength is obtained.
　本発明の別の実施形態である半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、基礎基板１０と基礎基板１０の一主面側に配置された半導体膜２０とを含む複合基板１を準備する工程と、複合基板１の半導体膜２０の一部を除去することにより、半導体膜２０の主面に対して垂直な第１のトレンチ部２１ｔが形成された主面を有する第１の半導体膜２１を形成する工程と、第１の半導体膜２１の第１のトレンチ部２１ｔが形成された主面上に第２の半導体膜２２を形成することにより、第１の半導体膜２１と第２の半導体膜２２との界面に形成されておりかつ第１の半導体膜２１側の主面である第１の主面に対して垂直な主面を有するキャリアチャネル層２０ｃを含む半導体複合膜２０Ｃを形成する工程と、半導体複合膜２０Ｃの第２の半導体膜２２側の主面でありキャリアチャネル層２０ｃに対して垂直な第２の主面上にソース電極３０ｓを形成する工程と、半導体複合膜２０Ｃの第１の半導体膜２１側の第１の主面上にドレイン電極３０ｄを形成する工程と、を含む。本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、上記の工程を含むことにより、オン抵抗が低く半導体デバイスの主面の面積を大きくすることなく耐圧の高い半導体デバイスを効率よく製造することができる。 A method for manufacturing semiconductor devices 2A, 2B, and 2C according to another embodiment of the present invention includes a step of preparing a composite substrate 1 including a base substrate 10 and a semiconductor film 20 disposed on one main surface side of the base substrate 10. Then, by removing a part of the semiconductor film 20 of the composite substrate 1, the first semiconductor film 21 having a main surface in which the first trench portion 21t perpendicular to the main surface of the semiconductor film 20 is formed is formed. The first semiconductor film 21 and the second semiconductor film are formed by forming the second semiconductor film 22 on the main surface of the first semiconductor film 21 where the first trench portion 21t is formed. Forming a semiconductor composite film 20C including a carrier channel layer 20c that is formed at the interface with the first semiconductor film 21 and has a main surface perpendicular to the first main surface that is the main surface on the first semiconductor film 21 side. And the second semiconductor of the semiconductor composite film 20C A step of forming a source electrode 30s on a second main surface which is a main surface on the film 22 side and perpendicular to the carrier channel layer 20c, and a first main surface on the first semiconductor film 21 side of the semiconductor composite film 20C. Forming a drain electrode 30d on the surface. The manufacturing method of the semiconductor devices 2A, 2B, and 2C according to the present embodiment includes the above-described steps, thereby efficiently manufacturing a semiconductor device having a low on-resistance and a high breakdown voltage without increasing the area of the main surface of the semiconductor device. be able to.
　本発明のかかる実施形態である半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法において、複合基板１を準備する工程の後、第１の半導体膜２１を形成する工程の前に、複合基板１の半導体膜２０ａ上にさらなる半導体膜２０ｂを形成する工程をさらに含み、第１の半導体膜２１を形成する工程は、さらなる半導体膜２０ｂの一部ならびに半導体膜２０ａおよびさらなる半導体膜２０ｂの一部のいずれかを除去することにより行なうことができる。これにより、半導体膜２０ａおよびと半導体膜２０ｂとが一体化された厚い半導体膜２０の一部（半導体膜２０ｂの一部ならびに半導体膜２０ａおよびさらなる半導体膜２０ｂの一部のいずれか）として、所望の第１の半導体膜２１を得ることができる。 In the manufacturing method of the semiconductor devices 2A, 2B, and 2C according to the embodiment of the present invention, the semiconductor film of the composite substrate 1 after the step of preparing the composite substrate 1 and before the step of forming the first semiconductor film 21 The method further includes the step of forming a further semiconductor film 20b on 20a, and the step of forming the first semiconductor film 21 includes a part of the further semiconductor film 20b and any one of the semiconductor film 20a and a part of the further semiconductor film 20b. This can be done by removing. As a result, a part of the thick semiconductor film 20 in which the semiconductor film 20a and the semiconductor film 20b are integrated (one of the semiconductor film 20b and one of the semiconductor film 20a and the further semiconductor film 20b) is desired. The first semiconductor film 21 can be obtained.
　また、本発明のかかる実施形態である半導体デバイス２Ｂの製造方法において、ドレイン電極３０ｄを形成する工程の後に、ドレイン電極３０ｄが形成された第１の主面側に導電性支持基板７０を配置する工程をさらに含むことができる。これにより、機械的強度の高い半導体デバイスを効率よく製造することができる。 In the method for manufacturing the semiconductor device 2B according to the embodiment of the present invention, the conductive support substrate 70 is disposed on the first main surface side where the drain electrode 30d is formed after the step of forming the drain electrode 30d. A process can be further included. Thereby, a semiconductor device with high mechanical strength can be manufactured efficiently.
　また、本発明のかかる実施形態である半導体デバイス２Ｃの製造方法において、ソース電極３０ｓを形成する工程の後に、ソース電極３０ｓが形成された第２の主面側に支持基板８０を配置する工程をさらに含むことができる。これにより、機械的強度の高い半導体デバイスを効率よく製造することができる。 Further, in the method of manufacturing the semiconductor device 2C according to the embodiment of the present invention, after the step of forming the source electrode 30s, a step of disposing the support substrate 80 on the second main surface side where the source electrode 30s is formed. Further can be included. Thereby, a semiconductor device with high mechanical strength can be manufactured efficiently.
　＜本発明の実施形態の詳細＞
　［実施形態１：半導体デバイス］
　図１、図３および図４を参照して、本発明のある実施形態である半導体デバイス２Ａ，２Ｂ，２Ｃは、第１の主面と第１の主面の反対側の主面である第２の主面とを有し、第１の主面および第２の主面に対して垂直な主面を有するキャリアチャネル層２０ｃを含む半導体複合膜２０Ｃと、半導体複合膜２０Ｃの第１の主面上に配置されたドレイン電極３０ｄと、半導体複合膜２０Ｃの第２の主面上に配置されたソース電極３０ｓと、を含む。ここで、図１において符号Ｕで示す範囲は、本実施形態の半導体デバイス２Ａの１ユニットを示している。 <Details of Embodiment of the Present Invention>
[Embodiment 1: Semiconductor Device]
Referring to FIG. 1, FIG. 3 and FIG. 4, semiconductor devices 2A, 2B and 2C which are embodiments of the present invention are first main surfaces opposite to the first main surface and the first main surface. A semiconductor composite film 20C including a carrier channel layer 20c having a main surface perpendicular to the first main surface and the second main surface, and a first main surface of the semiconductor composite film 20C. A drain electrode 30d disposed on the surface and a source electrode 30s disposed on the second main surface of the semiconductor composite film 20C are included. Here, the range indicated by the symbol U in FIG. 1 indicates one unit of the semiconductor device 2A of the present embodiment.
　図２に示すような典型的な横型ＦＥＴである半導体デバイス２Ｒは、半導体複合膜２０Ｃとして、ＧａＮ膜などの第１の半導体膜２１上にＡｌ1-xＧａxＮ膜（０＜ｘ＜１）などの第２の半導体膜２２が配置されていることにより第１の半導体膜２１と第２の半導体膜２２との界面にキャリアチャネル層２０ｃが形成され、半導体複合膜２０Ｃの第２の主面側である第２の半導体膜２２の主面上にソース電極３０ｓ、ゲート電極３０ｇおよびドレイン電極３０ｄが、互いの間に絶縁膜４０を介在させて、この順に配置されている。ここで、図２において符号Ｕで示す範囲は、典型的な横型の半導体デバイス２Ｒの１ユニットを示している。 A semiconductor device 2R, which is a typical lateral FET as shown in FIG. 2, has an Al 1-x Ga x N film (0 <x <1) on the first semiconductor film 21 such as a GaN film as the semiconductor composite film 20C. ), The carrier channel layer 20c is formed at the interface between the first semiconductor film 21 and the second semiconductor film 22, and the second main film of the semiconductor composite film 20C is formed. A source electrode 30s, a gate electrode 30g, and a drain electrode 30d are arranged in this order on the main surface of the second semiconductor film 22 on the surface side with an insulating film 40 interposed therebetween. Here, the range indicated by the symbol U in FIG. 2 indicates one unit of a typical horizontal semiconductor device 2R.
　かかる横型ＦＥＴのような半導体デバイス２Ｒにおいては、耐圧を高めるためにソース電極３０ｓ端とドレイン電極３０ｄ端との間の距離（これはキャリアチャネル層の長さＬに等しくなる）を大きくする必要があるため、また、大電流を流すために、半導体デバイスの主面の面積を大きくする必要がありコストが増大するとともに、回路の集積化に不利である。 In such a semiconductor device 2R such as a lateral FET, it is necessary to increase the distance between the end of the source electrode 30s and the end of the drain electrode 30d (this is equal to the length L of the carrier channel layer) in order to increase the breakdown voltage. For this reason, in order to flow a large current, it is necessary to increase the area of the main surface of the semiconductor device, which increases costs and is disadvantageous for circuit integration.
　本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃは、ドレイン電極３０ｄが配置された第１の主面およびソース電極３０ｓが配置された第２の主面に対して垂直な主面を有するキャリアチャネル層２０ｃを有しているため、オン抵抗を低くできるとともに、デバイスの主面の面積を大きくすることなく耐圧を高くすることができる。 The semiconductor devices 2A, 2B, and 2C of the present embodiment include a carrier channel layer having a first main surface on which the drain electrode 30d is disposed and a main surface that is perpendicular to the second main surface on which the source electrode 30s is disposed. Since it has 20c, the on-resistance can be lowered and the breakdown voltage can be increased without increasing the area of the main surface of the device.
　図１、図３および図４を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃにおいて、特に制限はないが、第１の主面および第２の主面に垂直な主面を有するキャリアチャネル層２０ｃ形成する観点から、半導体複合膜２０Ｃは、第１の主面と第１の主面に対して垂直な第１のトレンチ部が形成されている主面とを有する第１の半導体膜２１と、第１の半導体膜２１の第１のトレンチ部が形成されている主面上に配置されておりかつ第１のトレンチ部に対応する第２のトレンチ部が形成されている第２の主面を有する第２の半導体膜２２膜とを含み、キャリアチャネル層２０ｃが第１の半導体膜２１と第２の半導体膜２２との界面に形成されていることが好ましい。 With reference to FIGS. 1, 3, and 4, semiconductor devices 2 </ b> A, 2 </ b> B, and 2 </ b> C according to the present embodiment have a main surface that is perpendicular to the first main surface and the second main surface, although there is no particular limitation. From the viewpoint of forming the carrier channel layer 20c, the semiconductor composite film 20C is a first semiconductor having a first main surface and a main surface on which a first trench portion perpendicular to the first main surface is formed. The film 21 and the second trench part disposed on the main surface where the first trench part of the first semiconductor film 21 is formed and the second trench part corresponding to the first trench part is formed. It is preferable that the carrier channel layer 20 c is formed at the interface between the first semiconductor film 21 and the second semiconductor film 22.
　（半導体複合膜）
　図１、図３および図４を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの半導体複合膜２０Ｃは、たとえば、第１の主面と第１の主面の反対側の主面である第２の主面とを有し、第１の主面と第１の主面に対して垂直な第１のトレンチ部が形成されている主面とを有する第１の半導体膜２１と、第１の半導体膜２１の第１のトレンチ部が形成されている主面上に配置されておりかつ第１のトレンチ部に対応する第２のトレンチ部が形成されている第２の主面を有する第２の半導体膜２２とを含む。第１の半導体膜２１と第２の半導体膜２２との界面にキャリアチャネル層２０ｃを形成させる観点から、第１の半導体膜２１のバンドギャップエネルギと第２の半導体膜２２のバンドギャップエネルギとが異なること、すなわち、第１の半導体膜２１の化学組成と第２の半導体膜２２の化学組成とが異なることが好ましい。たとえば、第１の半導体膜２１をＧａＮ膜とし、第２の半導体膜２２をＡｌ1-xＧａxＮ膜（０＜ｘ＜１）とすることが好ましい。 (Semiconductor composite film)
1, 3, and 4, the semiconductor composite film 20 </ b> C of the semiconductor devices 2 </ b> A, 2 </ b> B, and 2 </ b> C of the present embodiment has, for example, a main surface opposite to the first main surface and the first main surface A first semiconductor film 21 having a first main surface and a main surface on which a first trench portion perpendicular to the first main surface is formed, The second main surface of the first semiconductor film 21 is disposed on the main surface where the first trench portion is formed and the second trench portion corresponding to the first trench portion is formed. And a second semiconductor film 22 having. From the viewpoint of forming the carrier channel layer 20 c at the interface between the first semiconductor film 21 and the second semiconductor film 22, the band gap energy of the first semiconductor film 21 and the band gap energy of the second semiconductor film 22 are It is preferable that the chemical composition of the first semiconductor film 21 is different from the chemical composition of the second semiconductor film 22. For example, the first semiconductor film 21 is preferably a GaN film, and the second semiconductor film 22 is preferably an Al 1-x Ga x N film (0 <x <1).
　また、第１の半導体膜２１の厚い部分（第１のトレンチが形成されていない部分、以下同じ）の厚さは、オフ時の耐圧を高めるとともにとオン時の抵抗を低減する観点から、１μｍ以上１０μｍ以下が好ましく、４μｍ以上６μｍ以下がより好ましい。第１の半導体膜２１の薄い部分（第１のトレンチが形成されている部分、以下同じ）の厚さは、通電時の抵抗を低減する観点から、０．００１μｍ以上１μｍ以下が好ましく、０．０１μｍ以上０．１μｍ以下がより好ましい。 Further, the thickness of the thick portion of the first semiconductor film 21 (the portion where the first trench is not formed, the same applies hereinafter) is 1 μm from the viewpoint of increasing the off-state breakdown voltage and reducing the on-state resistance. It is preferably 10 μm or less and more preferably 4 μm or more and 6 μm or less. The thickness of the thin portion of the first semiconductor film 21 (the portion where the first trench is formed, hereinafter the same) is preferably 0.001 μm or more and 1 μm or less from the viewpoint of reducing resistance during energization. More preferably, it is not less than 01 μm and not more than 0.1 μm.
　また、第２の半導体膜２２の厚さは、誘起キャリア量を増大させるとともにソース電極３０ｓ間の接触抵抗を低減する観点から、１ｎｍ以上３０ｎｍ以下が好ましく、１０ｎｍ以上２０ｎｍ以下がより好ましい。 Further, the thickness of the second semiconductor film 22 is preferably 1 nm or more and 30 nm or less, and more preferably 10 nm or more and 20 nm or less from the viewpoint of increasing the amount of induced carriers and reducing the contact resistance between the source electrodes 30s.
　第１の半導体膜２１は、第１の主面に対して垂直な第１のトレンチ部が形成されている主面を有しているため、第１の半導体膜２１の第１のトレンチ部が形成されている主面上に配置されかつ第１のトレンチ部に対応する第２のトレンチが形成されている第２の主面を有する第２の半導体膜２２を形成することにより、第１の半導体膜２１と第２の半導体膜２２との界面に、第１の主面および第２の主面に対して垂直な主面を有するキャリアチャネル層２０ｃが形成される。かかるキャリアチャネル層２０ｃの長さＬは、第１の半導体膜２１の第１のトレンチ部２１ｔ（図５（Ｂ）参照）および第２の半導体膜２２の第２のトレンチ部２２ｔ（図５（Ｃ）参照）の深さ（第１および第２のトレンチ部の底部から天井部までの壁部の長さをいう、以下同じ）に等しい。 Since the first semiconductor film 21 has a main surface in which a first trench portion perpendicular to the first main surface is formed, the first trench portion of the first semiconductor film 21 is By forming a second semiconductor film 22 having a second main surface disposed on the formed main surface and having a second trench corresponding to the first trench portion, the first semiconductor film 22 is formed. A carrier channel layer 20c having a first principal surface and a principal surface perpendicular to the second principal surface is formed at the interface between the semiconductor film 21 and the second semiconductor film 22. The length L of the carrier channel layer 20c is such that the first trench portion 21t of the first semiconductor film 21 (see FIG. 5B) and the second trench portion 22t of the second semiconductor film 22 (see FIG. 5B). C)) (refer to the length of the wall portion from the bottom of the first and second trench portions to the ceiling portion, hereinafter the same).
　本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの半導体複合膜２０Ｃには、第１の主面および第２の主面に対して垂直な主面を有するキャリアチャネル層２０ｃが形成されているため、オン抵抗を低くできるとともに、半導体デバイスの主面の面積を大きくすることなく耐圧を高くすることができる。ここで、第１の主面および第２の主面に対して垂直とは、半導体デバイスの第１の主面および第２の主面を大きくすることなく耐圧を高くするのに十分な実質的に垂直であれば足り、たとえば、第１の主面および第２の主面に対して８０°以上１００°以下であれば足りる。キャリアチャネル層２０ｃの長さＬは、半導体デバイスの耐圧を高くする観点から１μｍ以上が好ましく４μｍ以上がより好ましく、オン抵抗を低くする観点から１０μｍ以下が好ましく６μｍ以下がより好ましい。半導体複合膜２０Ｃの第２の半導体膜２２の第２のトレンチ部２２ｔ（図５（Ｃ）参照）の幅は、ゲート電極３０ｇの加工精度を確保する観点から、１μｍ以上が好ましく５μｍ以上がより好ましく、半導体デバイスの主面を大きくしない観点から１０μｍ以下が好ましく６μｍ以下がより好ましい。 In the semiconductor composite film 20C of the semiconductor devices 2A, 2B, and 2C of the present embodiment, the carrier channel layer 20c having a main surface perpendicular to the first main surface and the second main surface is formed. The on-resistance can be lowered and the breakdown voltage can be increased without increasing the area of the main surface of the semiconductor device. Here, the term “perpendicular to the first main surface and the second main surface” is substantially sufficient to increase the breakdown voltage without increasing the first main surface and the second main surface of the semiconductor device. For example, it is sufficient if it is not less than 80 ° and not more than 100 ° with respect to the first main surface and the second main surface. The length L of the carrier channel layer 20c is preferably 1 μm or more from the viewpoint of increasing the breakdown voltage of the semiconductor device, more preferably 4 μm or more, and preferably 10 μm or less and more preferably 6 μm or less from the viewpoint of decreasing the on-resistance. The width of the second trench portion 22t (see FIG. 5C) of the second semiconductor film 22 of the semiconductor composite film 20C is preferably 1 μm or more and more preferably 5 μm or more from the viewpoint of ensuring the processing accuracy of the gate electrode 30g. Preferably, from the viewpoint of not increasing the main surface of the semiconductor device, it is preferably 10 μm or less, and more preferably 6 μm or less.
　なお、誘起キャリア量を増大させるとともに表面を保護する観点から、第２の半導体膜２２上に、さらに第３の半導体膜（図示せず）を形成してもよい。ここで、誘起キャリア量を増大させる観点から、第２の半導体膜２２のバンドギャップエネルギと第３の半導体膜のバンドギャップエネルギとが異なること、すなわち、第２の半導体膜２２の化学組成と第３の半導体膜の化学組成とが異なることが好ましい。たとえば、第２の半導体膜２２をＡｌ1-xＧａxＮ膜（０＜ｘ＜１）とすると、第３の半導体膜をＧａＮ膜とすることが好ましい。また、第３の半導体膜の厚さは、ソース電極との接触抵抗を低減する観点から、１ｎｍ以上２０ｎｍ以下が好ましく、５ｎｍ以上１０ｎｍ以下がより好ましい。 Note that a third semiconductor film (not shown) may be further formed on the second semiconductor film 22 from the viewpoint of increasing the amount of induced carriers and protecting the surface. Here, from the viewpoint of increasing the amount of induced carriers, the band gap energy of the second semiconductor film 22 and the band gap energy of the third semiconductor film are different, that is, the chemical composition of the second semiconductor film 22 and the second The chemical composition of the semiconductor film 3 is preferably different. For example, when the second semiconductor film 22 is an Al 1-x Ga x N film (0 <x <1), the third semiconductor film is preferably a GaN film. The thickness of the third semiconductor film is preferably 1 nm or more and 20 nm or less, and more preferably 5 nm or more and 10 nm or less from the viewpoint of reducing contact resistance with the source electrode.
　（ドレイン電極）
　図１、図３および図４を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃのドレイン電極３０ｄは、たとえば、半導体複合膜２０Ｃの第１の半導体膜２１側の主面である第１の主面上に配置されている。 (Drain electrode)
With reference to FIGS. 1, 3, and 4, the drain electrode 30d of the semiconductor devices 2A, 2B, 2C of the present embodiment is, for example, the first surface of the semiconductor composite film 20C on the first semiconductor film 21 side. 1 is disposed on the main surface.
　ドレイン電極３０ｄは、特に制限はないが、ドレイン電極３０ｄの抵抗を低減することにより半導体デバイスの特性を高くする観点から、第１の半導体膜２１とオーミック接触をすることが好ましい。ドレイン電極３０ｄは、第１の半導体膜２１とオーミック接触をする観点から、Ｔｉ／Ａｌ／Ｎｉ／Ａｕ電極などが好ましい。 The drain electrode 30d is not particularly limited, but is preferably in ohmic contact with the first semiconductor film 21 from the viewpoint of improving the characteristics of the semiconductor device by reducing the resistance of the drain electrode 30d. The drain electrode 30d is preferably a Ti / Al / Ni / Au electrode from the viewpoint of making ohmic contact with the first semiconductor film 21.
　（ソース電極）
　図１、図３および図４を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃのソース電極３０ｓは、たとえば、半導体複合膜２０Ｃの第２の半導体膜２２側の主面である第２の主面上に配置されている。ここで、第２の半導体膜２２は、第１の半導体膜２１の第１の主面に対して実質的に垂直な第１のトレンチ部が形成されている主面上に配置されており、上記第１のトレンチ部に対応する第２のトレンチ部が形成されているため、第２の半導体膜２２の主面は、第１の半導体膜２１の第１の主面に対して、実質的に平行な第２の主面と、実質的に垂直な主面と、を有する。 (Source electrode)
With reference to FIGS. 1, 3, and 4, the source electrode 30s of the semiconductor devices 2A, 2B, and 2C of the present embodiment is, for example, the first main surface of the semiconductor composite film 20C on the second semiconductor film 22 side. 2 is arranged on the main surface. Here, the second semiconductor film 22 is disposed on the main surface on which the first trench portion substantially perpendicular to the first main surface of the first semiconductor film 21 is formed, Since the second trench portion corresponding to the first trench portion is formed, the main surface of the second semiconductor film 22 is substantially the same as the first main surface of the first semiconductor film 21. A second main surface parallel to the main surface and a substantially vertical main surface.
　ソース電極３０ｓは、特に制限はないが、ソース電極３０ｓの抵抗を低減することにより半導体デバイスの特性を高くする観点から、第２の半導体膜２２とオーミック接触をすることが好ましい。ソース電極３０ｓは、第２の半導体膜２２とオーミック接触をする観点から、Ｔｉ／Ａｌ／Ｎｉ／Ａｕ電極などが好ましい。 The source electrode 30s is not particularly limited, but is preferably in ohmic contact with the second semiconductor film 22 from the viewpoint of improving the characteristics of the semiconductor device by reducing the resistance of the source electrode 30s. The source electrode 30 s is preferably a Ti / Al / Ni / Au electrode from the viewpoint of making ohmic contact with the second semiconductor film 22.
　（ゲート電極）
　図１、図３および図４を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃは、トランジスタ機能を発現させる観点から、上記のドレイン電極３０ｄおよびソース電極３０ｓに加えて、半導体複合膜２０Ｃの第２の半導体膜２２側の主面であってかつ第１の半導体膜２１の第１の主面に対して実質的に垂直な主面上に電気的に接続されており、かつ、第２の半導体膜２２の第２の主面側に引き出されているゲート電極３０ｇをさらに有することができる。ゲート電極３０ｇは、ＦＥＴ（電界効果トランジスタ）機能を発現させる観点から、第２の半導体膜２２とショットキー接触をすることが好ましい。ゲート電極３０ｇは、第２の半導体膜２２とショットキー接触をする観点から、Ｎｉ電極、Ｔａ電極、Ｎｉ／Ａｕ電極、Ｔａ／Ａｕ電極などが好ましい。ゲート電極３０ｇと第２の半導体膜２２との接触距離（ゲート幅）は、半導体デバイス作製時の作業性を高めオフ時の耐圧を高める観点から、１００ｎｍ以上が好ましく５００ｎｍ以上がより好ましく、スイッチング動作速度を高める観点から２μｍ以下が好ましく１μｍ以下がより好ましい。 (Gate electrode)
1, 3, and 4, the semiconductor devices 2 </ b> A, 2 </ b> B, and 2 </ b> C of the present embodiment have a semiconductor composite film in addition to the drain electrode 30 d and the source electrode 30 s from the viewpoint of developing a transistor function. Electrically connected to a main surface on the second semiconductor film 22 side of 20C and substantially perpendicular to the first main surface of the first semiconductor film 21, and A gate electrode 30g drawn to the second main surface side of the second semiconductor film 22 can be further included. The gate electrode 30g is preferably in Schottky contact with the second semiconductor film 22 from the viewpoint of developing an FET (field effect transistor) function. The gate electrode 30g is preferably a Ni electrode, a Ta electrode, a Ni / Au electrode, a Ta / Au electrode, or the like from the viewpoint of making a Schottky contact with the second semiconductor film 22. The contact distance (gate width) between the gate electrode 30g and the second semiconductor film 22 is preferably 100 nm or more, more preferably 500 nm or more, from the viewpoint of improving workability at the time of manufacturing a semiconductor device and increasing the breakdown voltage at the time of switching. From the viewpoint of increasing the speed, it is preferably 2 μm or less, more preferably 1 μm or less.
　（絶縁膜）
　図１、図３および図４を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃは、その絶縁性および耐圧を高める観点から、絶縁膜４０として、半導体複合膜２０Ｃの第２の半導体膜２２側の第２の主面に形成されている第２のトレンチ部とゲート電極３０ｇとの間に配置されている第１の絶縁膜４０ａ、半導体複合膜２０Ｃの第２の半導体膜２２側の第２の主面側のソース電極３０ｓとゲート電極３０ｇとの間に配置されている第２の絶縁膜４０ｂなどを含むことが好ましい。第１の絶縁膜４０ａおよび第２の絶縁膜４０ｂは、特に制限はないが、その絶縁性が高い観点から、ＳｉＯ2膜、Ｓｉ3Ｎ4膜、Ａｌ2Ｏ3膜などが好ましい。 (Insulating film)
With reference to FIGS. 1, 3 and 4, the semiconductor devices 2A, 2B and 2C of the present embodiment have a second semiconductor of the semiconductor composite film 20C as the insulating film 40 from the viewpoint of increasing the insulation and breakdown voltage. The first insulating film 40a disposed between the second trench portion formed on the second main surface on the film 22 side and the gate electrode 30g, and the second semiconductor film 22 side of the semiconductor composite film 20C It is preferable to include a second insulating film 40b disposed between the source electrode 30s on the second main surface side and the gate electrode 30g. The first insulating film 40a and the second insulating film 40b are not particularly limited, but a SiO 2 film, a Si 3 N 4 film, an Al 2 O 3 film, or the like is preferable from the viewpoint of high insulation.
　（導電性支持基板）
　図３を参照して、本実施形態の半導体デバイス２Ｂは、半導体複合膜２０Ｃが薄い場合、たとえば半導体複合膜２０Ｃの最薄部分の厚さが１０μｍ以下の場合に、半導体デバイスの機械的強度を高める観点から、半導体複合膜２０Ｃの第１の主面側に配置された導電性支持基板７０をさらに含むことが好ましい。導電性支持基板７０は、特に制限はないが、導電性が高く機械的強度が高い観点から、比抵抗が１×１０-4Ω・ｃｍ以下が好ましく１×１０-5Ω・ｃｍ以下がより好ましく、ヤング率が０．１ＧＰａ以上が好ましく１ＧＰａ以上がより好ましく、たとえば金属焼結基板などが好ましい。導電性支持基板７０は、たとえば、半導体複合膜２０Ｃの第１の半導体膜２１側の第１の主面上に配置されたドレイン電極３０ｄ上に配置される。 (Conductive support substrate)
Referring to FIG. 3, in the semiconductor device 2B of the present embodiment, when the semiconductor composite film 20C is thin, for example, when the thickness of the thinnest part of the semiconductor composite film 20C is 10 μm or less, the mechanical strength of the semiconductor device is improved. From the viewpoint of enhancing, it is preferable to further include a conductive support substrate 70 disposed on the first main surface side of the semiconductor composite film 20C. The conductive support substrate 70 is not particularly limited, but from the viewpoint of high conductivity and high mechanical strength, the specific resistance is preferably 1 × 10 −4 Ω · cm or less, more preferably 1 × 10 −5 Ω · cm or less. Preferably, the Young's modulus is preferably 0.1 GPa or more, more preferably 1 GPa or more, for example, a metal sintered substrate or the like. For example, the conductive support substrate 70 is disposed on the drain electrode 30d disposed on the first main surface of the semiconductor composite film 20C on the first semiconductor film 21 side.
　（支持基板）
　図４を参照して、本実施形態の半導体デバイス２Ｃは、半導体複合膜２０Ｃが薄い場合、たとえば半導体複合膜２０Ｃの最薄部分の厚さが１０μｍ以下の場合に、半導体デバイスの機械的強度を高める観点から、半導体複合膜２０Ｃの第２の主面側に配置された支持基板８０をさらに含むことが好ましい。 (Support substrate)
Referring to FIG. 4, in the semiconductor device 2C of the present embodiment, when the semiconductor composite film 20C is thin, for example, when the thickness of the thinnest part of the semiconductor composite film 20C is 10 μm or less, the mechanical strength of the semiconductor device is increased. From the viewpoint of increasing, it is preferable to further include a support substrate 80 disposed on the second main surface side of the semiconductor composite film 20C.
　支持基板８０は、たとえば、半導体複合膜２０Ｃの第２の半導体膜２２側の第２の主面上に配置されたソース電極３０ｓおよびゲート電極３０ｇを覆う第３の絶縁膜４０ｃ上に配置される。ソース電極３０ｓおよびゲート電極３０ｇは、支持基板８０の存在により半導体複合膜２０Ｃの第２の主面側に引き出すことができないため、第２の絶縁膜４０ｂおよび第３の絶縁膜４０ｃの側面から外に引き出されている。 For example, the support substrate 80 is disposed on the third insulating film 40c covering the source electrode 30s and the gate electrode 30g disposed on the second main surface of the semiconductor composite film 20C on the second semiconductor film 22 side. . Since the source electrode 30s and the gate electrode 30g cannot be drawn out to the second main surface side of the semiconductor composite film 20C due to the presence of the support substrate 80, the source electrode 30s and the gate electrode 30g are removed from the side surfaces of the second insulating film 40b and the third insulating film 40c. Has been drawn to.
　［実施形態２：半導体デバイスの製造方法］
　図５～図７を参照して、本発明の別の実施形態である半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、基礎基板１０と基礎基板１０の一主面側に配置された半導体膜２０とを含む複合基板１を準備する工程（図５（Ａ））と、複合基板１の半導体膜２０の一部を除去することにより、半導体膜２０の主面に対して垂直な第１のトレンチ部２１ｔが形成された主面を有する第１の半導体膜２１を形成する工程（図５（Ｂ））と、第１の半導体膜２１の第１のトレンチ部２１ｔが形成された主面上に第２の半導体膜２２を形成することにより、第１の半導体膜２１と第２の半導体膜２２との界面に形成されておりかつ第１の半導体膜２１側の主面である第１の主面に対して垂直な主面を有するキャリアチャネル層２０ｃを含む半導体複合膜２０Ｃを形成する工程（図５（Ｃ））と、半導体複合膜２０Ｃの第２の半導体膜２２側の主面でありキャリアチャネル層２０ｃに対して垂直な第２の主面上にソース電極３０ｓ（図６（Ｄ））を形成する工程と、半導体複合膜２０Ｃの第１の半導体膜２１側の第１の主面上にドレイン電極３０ｄを形成する工程（図７（Ｂ））と、を含む。 [Embodiment 2: Manufacturing Method of Semiconductor Device]
Referring to FIGS. 5 to 7, in a method for manufacturing semiconductor devices 2A, 2B, and 2C according to another embodiment of the present invention, semiconductor substrate 20 disposed on base substrate 10 and one main surface side of base substrate 10 is described. And a first trench perpendicular to the main surface of the semiconductor film 20 by removing a part of the semiconductor film 20 of the composite substrate 1 (see FIG. 5A). A step of forming the first semiconductor film 21 having the main surface on which the portion 21t is formed (FIG. 5B), and on the main surface on which the first trench portion 21t of the first semiconductor film 21 is formed. By forming the second semiconductor film 22, the first main film is formed at the interface between the first semiconductor film 21 and the second semiconductor film 22 and is the main surface on the first semiconductor film 21 side. Semiconductor composite film 20C including carrier channel layer 20c having a main surface perpendicular to the surface The source electrode 30s (FIG. 5C) is formed on the second main surface that is perpendicular to the carrier channel layer 20c and is the main surface on the second semiconductor film 22 side of the semiconductor composite film 20C. 6 (D)) and a step of forming the drain electrode 30d on the first main surface of the semiconductor composite film 20C on the first semiconductor film 21 side (FIG. 7B).
　本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、オン抵抗が低く半導体デバイスの主面の面積を大きくすることなく耐圧の高い実施形態１の半導体デバイスを効率よく製造することができる。 The manufacturing method of the semiconductor devices 2A, 2B, and 2C of the present embodiment can efficiently manufacture the semiconductor device of the first embodiment having a low on-resistance and a high breakdown voltage without increasing the area of the main surface of the semiconductor device.
　（複合基板を準備する工程）
　図５（Ａ）を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、基礎基板１０と基礎基板１０の一主面側に配置された半導体膜２０とを含む複合基板１を準備する工程を含む。 (Process to prepare composite substrate)
Referring to FIG. 5A, the method for manufacturing semiconductor devices 2A, 2B, 2C of this embodiment includes a composite substrate including a base substrate 10 and a semiconductor film 20 disposed on one main surface side of the base substrate 10. 1 is provided.
　複合基板１の半導体膜２０の厚さは、特に制限はなく、５０ｎｍ程度の薄い膜厚から２５０μｍ程度の厚い膜厚まで、すなわち、５０ｎｍ以上２５０μｍ以下の広い範囲に亘って調製できる。形成する半導体デバイスの耐圧を高くする観点から、複合基板１の半導体膜２０の厚さは、１μｍ以上が好ましく、５μｍ以上がより好ましい。 The thickness of the semiconductor film 20 of the composite substrate 1 is not particularly limited, and can be adjusted from a thin film thickness of about 50 nm to a thick film thickness of about 250 μm, that is, over a wide range of 50 nm to 250 μm. From the viewpoint of increasing the breakdown voltage of the semiconductor device to be formed, the thickness of the semiconductor film 20 of the composite substrate 1 is preferably 1 μm or more, and more preferably 5 μm or more.
　ここで、図１０を参照して、複合基板１の半導体膜２０ａが薄い場合（たとえば半導体膜２０ａの厚さが１μｍ未満の場合）は、複合基板１を準備する工程の後、後述する第１の半導体膜２１を形成する工程（図５（Ｂ））の前に、複合基板１の半導体膜２０ａ上にさらなる半導体膜２０ｂを形成する工程を含むことが好ましい。半導体膜２０ａ上にさらなる半導体膜２０ｂを形成することにより半導体膜２０ａとさらなる半導体膜２０ｂとが一体化した厚い半導体膜２０を得ることができる。半導体膜２０ａとさらなる半導体膜２０ｂとは、均一な厚い半導体膜２０を得る観点から、同一の化学組成を有することが好ましい。半導体膜２０ａおよびさらなる半導体膜２０ｂを形成する方法は、後述する半導体膜２０を形成する方法と同様である。 Here, with reference to FIG. 10, when the semiconductor film 20a of the composite substrate 1 is thin (for example, when the thickness of the semiconductor film 20a is less than 1 μm), a first to be described later is provided after the step of preparing the composite substrate 1. Preferably, a step of forming a further semiconductor film 20b on the semiconductor film 20a of the composite substrate 1 is included before the step of forming the semiconductor film 21 (FIG. 5B). By forming a further semiconductor film 20b on the semiconductor film 20a, a thick semiconductor film 20 in which the semiconductor film 20a and the further semiconductor film 20b are integrated can be obtained. The semiconductor film 20a and the further semiconductor film 20b preferably have the same chemical composition from the viewpoint of obtaining a uniform thick semiconductor film 20. The method of forming the semiconductor film 20a and the further semiconductor film 20b is the same as the method of forming the semiconductor film 20 described later.
　複合基板１を準備する工程において、基礎基板１０の一主面側に半導体膜２０を配置する方法は、特に制限はなく、以下の第１～第３の方法が挙げられる。 In the step of preparing the composite substrate 1, the method of disposing the semiconductor film 20 on the one main surface side of the base substrate 10 is not particularly limited, and the following first to third methods can be mentioned.
　第１の方法は、図１１に示すように、基礎基板１０の一主面に、下地基板１００の主面上に成膜させた半導体膜２０を貼り合わせた後、下地基板１００を除去する方法である。第２の方法は、図１２～図１３に示すように、基礎基板１０の一主面に半導体膜ドナー基板２０Ｄを貼り合わせた後、その半導体膜ドナー基板２０Ｄを貼り合わせ面から所定の深さの面で分離することにより基礎基板１０の一主面上に半導体膜２０を形成する方法である。第３の方法は、図１４に示すように、基礎基板１０の一主面に半導体膜ドナー基板２０Ｄを貼り合わせた後、その半導体膜ドナー基板２０Ｄを貼り合わせ面の反対側の主面から研削、研磨およびエッチングの少なくともいずれかにより厚さを減少させて調整することにより基礎基板１０の一主面上にＩＩＩ族窒化物膜１３を形成する方法である。 As shown in FIG. 11, the first method is a method of removing the base substrate 100 after bonding the semiconductor film 20 formed on the main surface of the base substrate 100 to one main surface of the base substrate 10. It is. In the second method, as shown in FIGS. 12 to 13, after the semiconductor film donor substrate 20D is bonded to one main surface of the base substrate 10, the semiconductor film donor substrate 20D is bonded to the bonding surface by a predetermined depth. In this method, the semiconductor film 20 is formed on one main surface of the base substrate 10. In the third method, as shown in FIG. 14, after the semiconductor film donor substrate 20D is bonded to one main surface of the base substrate 10, the semiconductor film donor substrate 20D is ground from the main surface opposite to the bonded surface. In this method, the group III nitride film 13 is formed on one main surface of the base substrate 10 by adjusting the thickness by reducing the thickness by at least one of polishing and etching.
　上記の第１の方法において、基礎基板１０に半導体膜２０を貼り合わせる方法には、基礎基板１０の一主面に接合膜１２を介在させて半導体膜２０の主面を貼り合わせる方法（図１１を参照）などが挙げられる。また、上記の第２および第３の方法において、基礎基板１０に半導体膜ドナー基板２０Ｄを貼り合わせる方法には、基礎基板１０の一主面に接合膜１２を介在させて半導体膜ドナー基板２０Ｄの主面を貼り合わせる方法（図１２～図１４を参照）などが挙げられる。 In the first method, the semiconductor film 20 is bonded to the base substrate 10 by bonding the main surface of the semiconductor film 20 with the bonding film 12 interposed on one main surface of the base substrate 10 (FIG. 11). For example). In the second and third methods, the semiconductor film donor substrate 20D is bonded to the base substrate 10 with the bonding film 12 interposed on one main surface of the base substrate 10 and the semiconductor film donor substrate 20D. Examples include a method of bonding main surfaces (see FIGS. 12 to 14).
　なお、図１１～図１４には、基礎基板１０に接合膜１２ａを形成するとともに、半導体膜２０または半導体膜ドナー基板２０Ｄに接合膜１２ｂを形成し、それらを貼り合わせる方法が図示されているが、たとえば、基礎基板１０にのみ接合膜１２を形成しておき半導体膜２０または半導体膜ドナー基板２０Ｄと貼り合わせてもよいし、半導体膜２０または半導体膜ドナー基板２０Ｄにのみ接合膜１２を形成しておき基礎基板１０と貼り合わせてもよい。 11 to 14 illustrate a method of forming the bonding film 12a on the base substrate 10, and forming the bonding film 12b on the semiconductor film 20 or the semiconductor film donor substrate 20D, and bonding them together. For example, the bonding film 12 may be formed only on the base substrate 10 and bonded to the semiconductor film 20 or the semiconductor film donor substrate 20D, or the bonding film 12 may be formed only on the semiconductor film 20 or the semiconductor film donor substrate 20D. The base substrate 10 may be pasted together.
　（第１の方法）
　図１１を参照して、第１の方法により複合基板１を準備する工程は、特に制限はないが、効率的に複合基板１を形成する観点から、基礎基板１０の一主面上に接合膜１２ａを形成するサブ工程（図１１（Ａ））と、下地基板１００の主面上に半導体膜２０を形成し半導体膜２０主面上に接合膜１２ｂを形成するサブ工程（図１１（Ｂ））と、基礎基板１０に形成された接合膜１２ａの主面と下地基板１００に形成された半導体膜２０に形成された接合膜１２ｂの主面とを貼り合わせて接合基板１Ｌを形成するサブ工程（図１１（Ｃ））と、接合基板１Ｌから下地基板１００を除去するサブ工程（図１１（Ｄ））と、を含むことが好ましい。 (First method)
Referring to FIG. 11, the step of preparing composite substrate 1 by the first method is not particularly limited, but from the viewpoint of efficiently forming composite substrate 1, a bonding film is formed on one main surface of base substrate 10. A sub-process for forming 12a (FIG. 11A) and a sub-process for forming the semiconductor film 20 on the main surface of the base substrate 100 and forming the bonding film 12b on the main surface of the semiconductor film 20 (FIG. 11B). And the main surface of the bonding film 12a formed on the base substrate 10 and the main surface of the bonding film 12b formed on the semiconductor film 20 formed on the base substrate 100 are bonded together to form the bonding substrate 1L. (FIG. 11C) and a sub-process of removing the base substrate 100 from the bonding substrate 1L (FIG. 11D) are preferably included.
　図１１（Ａ）を参照して、基礎基板１０の一主面上に接合膜１２ａを形成するサブ工程において用いられる基礎基板１０は、特に制限はなく、たとえば、金属元素Ｍを含む酸化物であるＭＯx（ｘは任意の正の実数）、Ａｌを含む酸化物であるＡｌ2Ｏ3、およびＳｉを含む酸化物であるＳｉＯ2を所定のモル比で混合し焼結して得られる焼結体を所定の大きさに切り出して得られる基板の主面を研磨することにより行なうことができる。また、接合膜１２ａは、基礎基板１０との接合が良好なものであれば特に制限はなく、ＳｉＯ2膜、Ｓｉ3Ｎ4膜、Ａｌ2Ｏ3膜などが好適である。接合膜１２ａを形成する方法は、その材料に適した方法であれば特に制限はないが、膜形成コストを抑制する観点から、スパッタ法、蒸着法、ＣＶＤ（化学気相堆積）法などが好適である。 Referring to FIG. 11A, base substrate 10 used in the sub-process for forming bonding film 12a on one main surface of base substrate 10 is not particularly limited, and may be, for example, an oxide containing metal element M. A firing obtained by mixing and sintering a certain MO x (x is an arbitrary positive real number), Al 2 O 3 that is an oxide containing Al, and SiO 2 that is an oxide containing Si at a predetermined molar ratio. This can be done by polishing the main surface of the substrate obtained by cutting the bonded body into a predetermined size. The bonding film 12a is not particularly limited as long as the bonding with the base substrate 10 is good, and a SiO 2 film, a Si 3 N 4 film, an Al 2 O 3 film, or the like is preferable. The method for forming the bonding film 12a is not particularly limited as long as it is a method suitable for the material, but from the viewpoint of suppressing the film formation cost, a sputtering method, a vapor deposition method, a CVD (chemical vapor deposition) method, or the like is preferable. It is.
　図１１（Ｂ）を参照して、下地基板１００の主面上に半導体膜２０を形成し半導体膜２０主面上に接合膜１２ｂを形成するサブ工程において、用いられる下地基板１００は、半導体膜２０の形成に適したものであれば特に制限はなく、半導体膜２０がＧａＮ膜、Ａｌ1-xＧａxＮ膜（０＜ｘ＜１）などのＩＩＩ族窒化物膜の場合、下地基板１００はＧａＮ基板などのＩＩＩ族窒化物基板、サファイア基板、ＳｉＣ基板、Ｓｉ基板などが好適である。半導体膜２０を形成する方法は、その材料に適したものであれば特に制限はなく、半導体膜２０がＩＩＩ族窒化物膜の場合、ＯＭＶＰＥ（有機金属気相エピタキシ）法、スパッタ法、ＭＢＥ（分子線エピタキシ）法、ＰＬＤ（パルス・レーザ堆積）法、ＨＶＰＥ（ハイドライド気相エピタキシ）法、昇華法、フラックス法、高窒素圧溶液法などが好適である。また、接合膜１２ｂは、接合膜１２ａおよび半導体膜２０との接合が良好なものであれば特に制限なく、ＳｉＯ2膜、Ｓｉ3Ｎ4膜、Ａｌ2Ｏ3膜などが好適である。接合膜１２ｂを形成する方法は、接合膜１２ａを形成する方法と同様である。 Referring to FIG. 11B, in the sub-process in which the semiconductor film 20 is formed on the main surface of the base substrate 100 and the bonding film 12b is formed on the main surface of the semiconductor film 20, the base substrate 100 used is a semiconductor film. If the semiconductor film 20 is a group III nitride film such as a GaN film or an Al 1-x Ga x N film (0 <x <1), the base substrate 100 may be used. A group III nitride substrate such as a GaN substrate, a sapphire substrate, a SiC substrate, a Si substrate, or the like is suitable. The method for forming the semiconductor film 20 is not particularly limited as long as it is suitable for the material. When the semiconductor film 20 is a group III nitride film, an OMVPE (organometallic vapor phase epitaxy) method, a sputtering method, an MBE ( A molecular beam epitaxy method, a PLD (pulse laser deposition) method, an HVPE (hydride vapor phase epitaxy) method, a sublimation method, a flux method, a high nitrogen pressure solution method, and the like are suitable. The bonding film 12b is not particularly limited as long as bonding with the bonding film 12a and the semiconductor film 20 is satisfactory, and a SiO 2 film, a Si 3 N 4 film, an Al 2 O 3 film, or the like is preferable. The method for forming the bonding film 12b is the same as the method for forming the bonding film 12a.
　図１１（Ｃ）を参照して、接合膜１２ａの主面と接合膜１２ｂの主面とを貼り合わせて接合基板１Ｌを形成するサブ工程において、接合膜１２ａと接合膜１２ｂとを貼り合わせる方法には、特に制限はなく、貼り合わせ面を洗浄しそのまま貼り合わせた後６００℃～１２００℃程度に昇温して接合する直接接合法、貼り合わせ面を洗浄しプラズマやイオンなどで活性化処理した後に室温（たとえば２５℃）～４００℃程度の低温雰囲気下で接合する表面活性化接合法、貼り合わせ面を薬液と純水で洗浄処理した後、０．１ＭＰａ～１０ＭＰａ程度の高い圧力を掛けて接合する高圧接合法、貼り合わせ面を薬液と純水で洗浄処理した後、１０-6Ｐａ～１０-3Ｐａ程度の高真空雰囲気下で接合する高真空接合法、などが好適である。上記のいずれの接合法においてもそれらの接合後に６００℃～１２００℃程度に昇温することによりさらに接合強度を高めることができる。特に、表面活性化接合法、高圧接合法、および高真空接合法においては、それらの接合後に６００℃～１２００℃程度に昇温することによる接合強度を高める効果が大きい。 With reference to FIG. 11C, a method of bonding the bonding film 12a and the bonding film 12b in a sub-process of forming the bonding substrate 1L by bonding the main surface of the bonding film 12a and the main surface of the bonding film 12b. There are no particular restrictions on the bonding surface, the bonding surface is washed and bonded as it is, then the direct bonding method in which the temperature is raised to about 600 ° C. to 1200 ° C. and the bonding surface is cleaned and activated by plasma or ions. After the surface activation bonding method in which bonding is performed in a low temperature atmosphere of room temperature (for example, 25 ° C.) to 400 ° C., the bonded surface is cleaned with a chemical solution and pure water, and then a high pressure of about 0.1 MPa to 10 MPa is applied. A high-pressure bonding method in which the bonding surfaces are cleaned with a chemical solution and pure water and then bonded in a high vacuum atmosphere of about 10 −6 Pa to 10 −3 Pa is preferable. In any of the above bonding methods, the bonding strength can be further increased by raising the temperature to about 600 ° C. to 1200 ° C. after the bonding. In particular, in the surface activated bonding method, the high pressure bonding method, and the high vacuum bonding method, the effect of increasing the bonding strength by raising the temperature to about 600 ° C. to 1200 ° C. after the bonding is large.
　図１１（Ｄ）を参照して、接合基板１Ｌから下地基板１００を除去するサブ工程において、下地基板１００を除去する方法は、特に制限はないが、下地基板１００を効率的に除去する観点から、下地基板１００をフッ化水素酸などのエッチャントにより溶解させて除去する方法、下地基板１００の露出している主面側から研削または研磨により除去する方法などが好適である。ここで、下地基板１００をフッ化水素酸などのエッチャントにより溶解させて除去する場合には、基礎基板１０を保護するための保護部材（図示せず）を基礎基板１０の回りに形成することが好ましい。 Referring to FIG. 11D, a method for removing base substrate 100 in the sub-step of removing base substrate 100 from bonding substrate 1L is not particularly limited, but from the viewpoint of efficiently removing base substrate 100. A method of removing the base substrate 100 by dissolving it with an etchant such as hydrofluoric acid, a method of removing the base substrate 100 from the exposed main surface side by grinding or polishing, and the like are suitable. Here, when the base substrate 100 is removed by being dissolved with an etchant such as hydrofluoric acid, a protective member (not shown) for protecting the base substrate 10 may be formed around the base substrate 10. preferable.
　このようにして、基礎基板１０と、基礎基板１０の一主面上に配置された接合膜１２と、接合膜１２の主面上に配置された半導体膜２０と、を含む複合基板１が得られる。 In this way, the composite substrate 1 including the base substrate 10, the bonding film 12 disposed on one main surface of the base substrate 10, and the semiconductor film 20 disposed on the main surface of the bonding film 12 is obtained. It is done.
　（第２の方法）
　図１２～１３を参照して、第２の方法により複合基板１を準備する工程は、特に制限はないが、効率的に複合基板１を製造する観点から、図１２に示す切断法あるいは図１３に示すイオン注入法が好適に用いられる。ここで、切断法は厚さが１０μｍ以上２５０μｍ以下の比較的厚い半導体膜２０を有する複合基板１の準備に特に好適であり、イオン注入法は厚さが５０ｎｍ以上１０μｍ未満の比較的薄い半導体膜２０を有する複合基板１の準備に特に好適である。以下、切断法、イオン注入法について説明する。 (Second method)
Referring to FIGS. 12 to 13, the step of preparing composite substrate 1 by the second method is not particularly limited, but from the viewpoint of efficiently manufacturing composite substrate 1, the cutting method shown in FIG. The ion implantation method shown in FIG. Here, the cutting method is particularly suitable for preparing the composite substrate 1 having the relatively thick semiconductor film 20 having a thickness of 10 μm or more and 250 μm or less, and the ion implantation method is a relatively thin semiconductor film having a thickness of 50 nm or more and less than 10 μm. Particularly suitable for the preparation of the composite substrate 1 having 20. Hereinafter, the cutting method and the ion implantation method will be described.
　（切断法）
　図１２を参照して、切断法により複合基板１を準備する工程は、特に制限はないが、効率的に複合基板１を形成する観点から、基礎基板１０の一主面に接合膜１２ａを形成するサブ工程（図１２（Ａ））と、半導体膜ドナー基板２０Ｄの一主面上に接合膜１２ｂを形成するサブ工程（図１２（Ｂ））と、基礎基板１０に形成された接合膜１２ａの主面と半導体膜ドナー基板２０Ｄに形成された接合膜１２ｂの主面とを貼り合わせて接合基板１Ｌを形成するサブ工程（図１２（Ｃ））と、接合基板１Ｌの半導体膜ドナー基板２０Ｄの貼り合わせ面である主面から内部に所定の深さに位置する面で半導体膜ドナー基板２０Ｄを切断するサブ工程（図１２（Ｄ））と、を含むことが好ましい。 (Cutting method)
Referring to FIG. 12, the step of preparing composite substrate 1 by a cutting method is not particularly limited, but from the viewpoint of efficiently forming composite substrate 1, bonding film 12 a is formed on one main surface of base substrate 10. The sub-process (FIG. 12A), the sub-process (FIG. 12B) for forming the bonding film 12b on one main surface of the semiconductor film donor substrate 20D, and the bonding film 12a formed on the base substrate 10. The main surface of the semiconductor substrate and the main surface of the bonding film 12b formed on the semiconductor film donor substrate 20D are bonded together to form a bonding substrate 1L (FIG. 12C), and the semiconductor film donor substrate 20D of the bonding substrate 1L. It is preferable to include a sub-process (FIG. 12D) for cutting the semiconductor film donor substrate 20D at a surface located at a predetermined depth from the main surface as a bonding surface.
　ここで、半導体膜ドナー基板２０Ｄとは、後工程において分離により半導体膜２０を提供するドナー基板である。かかる半導体膜ドナー基板２０Ｄを形成する方法は、上記の第１の方法により複合基板を準備する方法における半導体膜２０を形成する方法と同様である。また、接合膜１２ａ，１２ｂの形成方法は、第１の方法により複合基板を準備する方法における接合膜１２ａ，１２ｂの形成方法と同様である。また、基礎基板１０と半導体膜ドナー基板２０Ｄとを貼り合わせる方法は、上記の第１の方法により複合基板を準備する方法における基礎基板１０と半導体膜２０とを貼り合わせる方法と同様である。 Here, the semiconductor film donor substrate 20D is a donor substrate that provides the semiconductor film 20 by separation in a later step. The method of forming the semiconductor film donor substrate 20D is the same as the method of forming the semiconductor film 20 in the method of preparing the composite substrate by the first method. The method for forming the bonding films 12a and 12b is the same as the method for forming the bonding films 12a and 12b in the method for preparing the composite substrate by the first method. The method of bonding the base substrate 10 and the semiconductor film donor substrate 20D is the same as the method of bonding the base substrate 10 and the semiconductor film 20 in the method of preparing the composite substrate by the first method.
　また、半導体膜ドナー基板２０Ｄを切断するサブ工程において用いられる切断方法は、特に制限なく、ワイヤソー、ブレード、レーザ、放電加工、ウォータージェットなどが好適に用いられる。 The cutting method used in the sub-process for cutting the semiconductor film donor substrate 20D is not particularly limited, and a wire saw, blade, laser, electric discharge machining, water jet, or the like is preferably used.
　このようにして、接合基板１Ｌが半導体膜ドナー基板２０Ｄの貼り合わせ面である主面から内部に所定の深さに位置する面で分離して、基礎基板１０と、基礎基板１０の一主面上に配置された接合膜１２と、接合膜１２の主面上に配置された半導体膜２０と、を含む複合基板１が得られる。 In this way, the bonding substrate 1L is separated from the main surface, which is the bonding surface of the semiconductor film donor substrate 20D, at a surface positioned at a predetermined depth, and the base substrate 10 and one main surface of the base substrate 10 are separated. The composite substrate 1 including the bonding film 12 disposed on the semiconductor film 20 disposed on the main surface of the bonding film 12 is obtained.
　（イオン注入法）
　図１３を参照して、イオン注入法により複合基板１を準備する工程は、特に制限はないが、効率的に複合基板１を形成する観点から、基礎基板１０の一主面上に接合膜１２ａを形成するサブ工程（図１３（Ａ））と、半導体膜ドナー基板２０Ｄの一主面側からイオンＩを注入することによりその主面から内部に所定の深さの位置の面にイオン注入領域２０ｉを形成するとともにその主面上に接合膜１２ｂを形成するサブ工程（図１３（Ｂ））と、基礎基板１０に形成された接合膜１２ａの主面と半導体膜ドナー基板２０Ｄに形成された接合膜１２ｂの主面とを貼り合わせて接合基板１Ｌを形成するサブ工程（図１３（Ｃ））と、接合基板１Ｌの半導体膜ドナー基板２０Ｄをそのイオン注入領域２０ｉで分離するサブ工程（図１３（Ｄ））と、を含むことが好ましい。 (Ion implantation method)
Referring to FIG. 13, the step of preparing composite substrate 1 by an ion implantation method is not particularly limited, but from the viewpoint of efficiently forming composite substrate 1, bonding film 12 a is formed on one main surface of basic substrate 10. And a sub-process (FIG. 13 (A)) for forming an ion implantation region from a main surface side of the semiconductor film donor substrate 20D to a surface at a predetermined depth from the main surface. 20i and a sub-process for forming the bonding film 12b on the main surface (FIG. 13B), and the main surface of the bonding film 12a formed on the base substrate 10 and the semiconductor film donor substrate 20D. A sub-process (FIG. 13C) for bonding the main surface of the bonding film 12b to form the bonding substrate 1L and a sub-process for separating the semiconductor film donor substrate 20D of the bonding substrate 1L by the ion implantation region 20i (FIG. 13 (D)), It is preferable to include.
　ここで、半導体膜ドナー基板２０Ｄを形成する方法は、上記の第１の方法により複合基板を準備する方法における半導体膜２０を形成する方法と同様である。また、接合膜１２ａ，１２ｂの形成方法は、第１の方法により複合基板を準備する方法における接合膜１２ａ，１２ｂの形成方法と同様である。また、基礎基板１０と半導体膜ドナー基板２０Ｄとを貼り合わせる方法は、上記の第１の方法により複合基板を準備する方法における基礎基板１０と半導体膜２０とを貼り合わせる方法と同様である。 Here, the method of forming the semiconductor film donor substrate 20D is the same as the method of forming the semiconductor film 20 in the method of preparing the composite substrate by the first method. The method for forming the bonding films 12a and 12b is the same as the method for forming the bonding films 12a and 12b in the method for preparing the composite substrate by the first method. The method of bonding the base substrate 10 and the semiconductor film donor substrate 20D is the same as the method of bonding the base substrate 10 and the semiconductor film 20 in the method of preparing the composite substrate by the first method.
　半導体膜ドナー基板２０Ｄに注入されるイオンＩは、特に制限はないが、半導体膜２０の品質の低下を抑制する観点およびイオン注入領域２０ｉに注入されたイオンＩのガス化温度を半導体膜２０の分解温度より低くする観点から、質量の小さい原子のイオン、たとえば、水素イオン、ヘリウムイオンなどが好ましい。また、半導体膜ドナー基板２０Ｄをそのイオン注入領域２０ｉで分離する方法は、イオン注入領域２０ｉに注入されたイオンＩをガス化させる方法であれば特に制限はない。たとえば、熱を加えたり、超音波を加えたりする方法などで、接合基板１Ｌの半導体膜ドナー基板２０Ｄの貼り合わせ面である主面から所定の深さの位置に形成されているイオン注入領域２０ｉに注入されているイオンＩをガス化させて急激な体積膨張をさせることにより行なう。 The ions I implanted into the semiconductor film donor substrate 20D are not particularly limited, but the gasification temperature of the ions I implanted into the ion implantation region 20i can be determined from the viewpoint of suppressing the deterioration of the quality of the semiconductor film 20. From the viewpoint of making the temperature lower than the decomposition temperature, ions of atoms having a small mass such as hydrogen ions and helium ions are preferable. The method for separating the semiconductor film donor substrate 20D by the ion implantation region 20i is not particularly limited as long as it is a method for gasifying the ions I implanted into the ion implantation region 20i. For example, an ion implantation region 20i formed at a predetermined depth from the main surface, which is a bonding surface of the semiconductor film donor substrate 20D of the bonding substrate 1L, by a method of applying heat or applying ultrasonic waves. This is carried out by gasifying the ions I implanted into the substrate and causing rapid volume expansion.
　このようにして、接合基板１Ｌが半導体膜ドナー基板２０Ｄの貼り合わせ面である主面から内部に所定の深さに位置する面で分離して、基礎基板１０と、基礎基板１０の一主面上に配置された接合膜１２と、接合膜１２の主面上に配置された半導体膜２０と、を含む複合基板１が得られる。 In this way, the bonding substrate 1L is separated from the main surface, which is the bonding surface of the semiconductor film donor substrate 20D, at a surface positioned at a predetermined depth, and the base substrate 10 and one main surface of the base substrate 10 are separated. The composite substrate 1 including the bonding film 12 disposed on the semiconductor film 20 disposed on the main surface of the bonding film 12 is obtained.
　（第３の方法）
　図１４を参照して、第３の方法により複合基板１を準備する工程は、特に制限はないが、効率的に複合基板１を製造する観点から、基礎基板１０の一主面上に接合膜１２ａを形成するサブ工程（図１４（Ａ））と、半導体膜ドナー基板２０Ｄの一主面上に接合膜１２ｂを形成するサブ工程（図１４（Ｂ））と、基礎基板１０に形成された接合膜１２ａの主面と半導体膜ドナー基板２０Ｄに形成された接合膜１２ｂの主面とを貼り合わせて接合基板１Ｌを形成するサブ工程（図１４（Ｃ））と、接合基板１Ｌの半導体膜ドナー基板２０Ｄの貼り合わせ面である主面と反対側の主面から研削、研磨およびエッチングの少なくともいずれかを行なうサブ工程（図１４（Ｄ））と、を含むことが好ましい。かかる第３の方法は、厚さが１０μｍ以上２５０μｍ以下の比較的厚い半導体膜２０を有する複合基板１の準備に特に好適である。 (Third method)
Referring to FIG. 14, the step of preparing composite substrate 1 by the third method is not particularly limited, but a bonding film is formed on one main surface of base substrate 10 from the viewpoint of efficiently manufacturing composite substrate 1. A sub-process for forming 12a (FIG. 14A), a sub-process for forming the bonding film 12b on one main surface of the semiconductor donor substrate 20D (FIG. 14B), and the base substrate 10 A sub-process (FIG. 14C) for bonding the main surface of the bonding film 12a and the main surface of the bonding film 12b formed on the semiconductor film donor substrate 20D to form the bonding substrate 1L, and the semiconductor film of the bonding substrate 1L It is preferable to include a sub-process (FIG. 14D) in which at least one of grinding, polishing and etching is performed from the main surface opposite to the main surface which is the bonding surface of the donor substrate 20D. The third method is particularly suitable for preparing the composite substrate 1 having the relatively thick semiconductor film 20 having a thickness of 10 μm or more and 250 μm or less.
　ここで、半導体膜ドナー基板２０Ｄとは、後工程において、第２の方法における分離による以外にも研削、研磨およびエッチングの少なくともいずれかにより半導体膜２０を提供するドナー基板である。かかる半導体膜ドナー基板２０Ｄを形成する方法は、上記の第１の方法により複合基板を準備する方法における半導体膜２０を形成する方法と同様である。また、接合膜１２ａ，１２ｂの形成方法は、第１の方法により複合基板を準備する方法における接合膜１２ａ，１２ｂの形成方法と同様である。また、基礎基板１０と半導体膜ドナー基板２０Ｄとを貼り合わせる方法は、上記の第１の方法により複合基板を準備する方法における基礎基板１０と半導体膜２０とを貼り合わせる方法と同様である。 Here, the semiconductor film donor substrate 20D is a donor substrate that provides the semiconductor film 20 by at least one of grinding, polishing, and etching in addition to the separation in the second method in a later step. The method of forming the semiconductor film donor substrate 20D is the same as the method of forming the semiconductor film 20 in the method of preparing the composite substrate by the first method. The method for forming the bonding films 12a and 12b is the same as the method for forming the bonding films 12a and 12b in the method for preparing the composite substrate by the first method. The method of bonding the base substrate 10 and the semiconductor film donor substrate 20D is the same as the method of bonding the base substrate 10 and the semiconductor film 20 in the method of preparing the composite substrate by the first method.
　また、半導体膜ドナー基板２０Ｄを研削する方法は、特に制限はなく、砥石による研削（平面研削）、ショット・ブラストなどが挙げられる。半導体膜ドナー基板２０Ｄを研磨する方法は、特に制限はなく、機械的研磨、ＣＭＰ（化学機械的研磨）などが挙げられる。半導体膜ドナー基板２０Ｄをエッチングする方法は、特に制限はなく、薬液によるウェットエッチング、ＲＩＥ（反応性イオンエッチング）などのドライエッチングなどが挙げられる。 The method for grinding the semiconductor film donor substrate 20D is not particularly limited, and examples thereof include grinding with a grindstone (surface grinding) and shot blasting. The method for polishing the semiconductor film donor substrate 20D is not particularly limited, and examples thereof include mechanical polishing and CMP (chemical mechanical polishing). The method for etching the semiconductor film donor substrate 20D is not particularly limited, and examples include wet etching with a chemical solution and dry etching such as RIE (reactive ion etching).
　このようにして、基礎基板１０と、基礎基板１０の一主面上に配置された接合膜１２と、接合膜１２の主面上に配置された半導体膜２０と、を含む複合基板１が得られる。 In this way, the composite substrate 1 including the base substrate 10, the bonding film 12 disposed on one main surface of the base substrate 10, and the semiconductor film 20 disposed on the main surface of the bonding film 12 is obtained. It is done.
　（第１の半導体膜を形成する工程）
　次に、図５（Ｂ）を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、複合基板１の半導体膜２０の一部を除去することにより、半導体膜２０の主面に対して垂直な第１のトレンチ部２１ｔが形成された主面を有する第１の半導体膜２１を形成する工程を含む。 (Step of forming first semiconductor film)
Next, referring to FIG. 5B, the method of manufacturing the semiconductor devices 2A, 2B, 2C of the present embodiment removes a part of the semiconductor film 20 of the composite substrate 1 so that the main part of the semiconductor film 20 is removed. A step of forming a first semiconductor film 21 having a main surface on which a first trench portion 21t perpendicular to the surface is formed.
　第１の半導体膜２１を形成する工程において、半導体膜２０の一部を除去する方法は、特に制限はなく、たとえば、電子線リソグラフィ法およびフォトリソグラフィ法により半導体膜２０の主面上にパターン化されたレジスト膜（図示せず）を形成した後に、エッチングする方法がある。エッチングは、半導体膜２０の主面に対して垂直な第１のトレンチ部２１ｔを形成する観点から、ＲＩＥ（反応性イオンエッチング）などのドライエッチングが好ましい。ここで、半導体膜２０の主面に対して垂直とは、形成する半導体デバイスの主面を大きくすることなく耐圧を高くするのに十分な実質的に垂直であれば足り、たとえば、形成する半導体デバイスの主面に対して８０°以上１００°以下であれば足りる。 In the step of forming the first semiconductor film 21, a method for removing a part of the semiconductor film 20 is not particularly limited. For example, patterning is performed on the main surface of the semiconductor film 20 by an electron beam lithography method and a photolithography method. There is a method of etching after forming a resist film (not shown). The etching is preferably dry etching such as RIE (reactive ion etching) from the viewpoint of forming the first trench portion 21 t perpendicular to the main surface of the semiconductor film 20. Here, the term “perpendicular to the main surface of the semiconductor film 20” is sufficient if it is substantially vertical enough to increase the breakdown voltage without increasing the main surface of the semiconductor device to be formed. It is sufficient if it is 80 ° or more and 100 ° or less with respect to the main surface of the device.
　第１のトレンチ部２１ｔの深さ（第１のトレンチ部の底部から天井部までの壁部の長さ）は、後述するキャリアチャネル層２０ｃの長さＬに対応するため、半導体デバイスの耐圧を高くする観点から１μｍ以上とすることが好ましく、４μｍ以上とすることがより好ましい、半導体デバイスのオン抵抗を低減する観点から２０μｍ以下が好ましく１０μｍ以下がより好ましい。 The depth of the first trench portion 21t (the length of the wall portion from the bottom portion to the ceiling portion of the first trench portion) corresponds to the length L of the carrier channel layer 20c described later. From the viewpoint of increasing the thickness, it is preferably 1 μm or more, more preferably 4 μm or more. From the viewpoint of reducing the on-resistance of the semiconductor device, it is preferably 20 μm or less, and more preferably 10 μm or less.
　ここで、図１０を参照して、複合基板１を準備する工程（図５（Ａ））の後、第１の半導体膜２１を形成する工程（図５（Ｂ））の前に、複合基板１の半導体膜２０ａ上にさらなる半導体膜２０ｂを形成する工程を含む場合は、第１の半導体膜２１を形成する工程は、さらなる半導体膜２０ｂの一部および半導体膜２０ａおよびさらなる半導体膜２０ｂの一部のいずれかを除去することにより行なうことができる。これにより、半導体膜２０ａおよびと半導体膜２０ｂとが一体化された厚い半導体膜２０の一部（半導体膜２０ｂの一部ならびに半導体膜２０ａおよびさらなる半導体膜２０ｂの一部のいずれか）を除去して、所望の第１の半導体膜２１を得ることができる。 Here, referring to FIG. 10, after the step of preparing composite substrate 1 (FIG. 5A) and before the step of forming first semiconductor film 21 (FIG. 5B), the composite substrate In the case where the step of forming the additional semiconductor film 20b on the first semiconductor film 20a is included, the step of forming the first semiconductor film 21 includes a part of the additional semiconductor film 20b and one of the semiconductor film 20a and the additional semiconductor film 20b. This can be done by removing any of the parts. Thus, a part of the thick semiconductor film 20 in which the semiconductor film 20a and the semiconductor film 20b are integrated (a part of the semiconductor film 20b and any one of the semiconductor film 20a and the further semiconductor film 20b) is removed. Thus, the desired first semiconductor film 21 can be obtained.
　（半導体複合膜を形成する工程）
　次に、図５（Ｃ）を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、第１の半導体膜２１の第１のトレンチ部２１ｔが形成された主面上に第２の半導体膜２２を形成することにより、第１の半導体膜２１と第２の半導体膜２２との界面に形成されており第１の半導体膜２１側の主面である第１の主面に対して垂直な主面を有するキャリアチャネル層２０ｃを含む半導体複合膜２０Ｃを形成する工程を含む。 (Process for forming semiconductor composite film)
Next, referring to FIG. 5C, in the manufacturing method of the semiconductor devices 2A, 2B, and 2C according to the present embodiment, the main surface of the first semiconductor film 21 on which the first trench portion 21t is formed is formed. By forming the second semiconductor film 22, the first main surface is formed at the interface between the first semiconductor film 21 and the second semiconductor film 22 and is the main surface on the first semiconductor film 21 side. Forming a semiconductor composite film 20C including a carrier channel layer 20c having a main surface perpendicular to the surface.
　第２の半導体膜２２を形成する方法は、その材料に適したものであれば特に制限はなく、第２の半導体膜２２がＩＩＩ族窒化物膜の場合、ＯＭＶＰＥ（有機金属気相エピタキシ）法、スパッタ法、ＭＢＥ（分子線エピタキシ）法、ＰＬＤ（パルス・レーザ堆積）法、ＨＶＰＥ（ハイドライド気相エピタキシ）法、昇華法、フラックス法、高窒素圧溶液法などが好適である。ここで、第２の半導体膜２２を形成する方法は、結晶性が高く薄い半導体膜を形成する観点から、ＯＭＶＰＥ法、ＭＢＥ法が特に好ましい。 The method for forming the second semiconductor film 22 is not particularly limited as long as it is suitable for the material. When the second semiconductor film 22 is a group III nitride film, an OMVPE (organometallic vapor phase epitaxy) method is used. The sputtering method, MBE (molecular beam epitaxy) method, PLD (pulse laser deposition) method, HVPE (hydride vapor phase epitaxy) method, sublimation method, flux method, high nitrogen pressure solution method and the like are suitable. Here, as a method of forming the second semiconductor film 22, the OMVPE method and the MBE method are particularly preferable from the viewpoint of forming a thin semiconductor film with high crystallinity.
　このようにして、第１の主面と第１の主面に対して垂直な第１のトレンチ部２１ｔが形成されている主面とを有する第１の半導体膜２１と、第１の半導体膜２１の第１のトレンチ部２１ｔが形成されている主面上に配置されておりかつ第１のトレンチ部２１ｔに対応する第２のトレンチ部２２ｔが形成されている第２の主面を有する第２の半導体膜２２と、を含む半導体複合膜２０Ｃが得られる。 In this way, the first semiconductor film 21 having the first main surface and the main surface on which the first trench portion 21t perpendicular to the first main surface is formed, and the first semiconductor film The second main surface is disposed on the main surface on which the 21st first trench portion 21t is formed and has a second main surface on which the second trench portion 22t corresponding to the first trench portion 21t is formed. A semiconductor composite film 20C including two semiconductor films 22 is obtained.
　（第１の絶縁膜を形成する工程）
　次に、図５（Ｄ）を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、半導体複合膜２０Ｃの第２の半導体膜２２側の第２の主面上および第２の主面に形成された第２のトレンチ部２２ｔ上に第１の絶縁膜４０ａを形成する工程を含むことができる。第１の絶縁膜４０ａを形成する方法は、その材料に適したものであれば特に制限はなく、スパッタ法、ＡＬＤ（原子層堆積）法などが好適である。 (Step of forming the first insulating film)
Next, referring to FIG. 5D, the method for manufacturing the semiconductor devices 2A, 2B, 2C of the present embodiment is performed on the second main surface of the semiconductor composite film 20C on the second semiconductor film 22 side and on the second main surface. The process of forming the 1st insulating film 40a on the 2nd trench part 22t formed in 2 main surfaces can be included. The method for forming the first insulating film 40a is not particularly limited as long as it is suitable for the material, and a sputtering method, an ALD (atomic layer deposition) method, or the like is preferable.
　次に、図６（Ａ）を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、第１の絶縁膜４０ａの一部を除去する工程を含むことができる。かかる工程により、半導体複合膜２０Ｃの第２の半導体膜２２側の第２の主面および第２の主面に形成された第３のトレンチ部２３ｔの表面の少なくとも一部を露出させることができる。第１の絶縁膜４０ａの一部を除去する方法は、特に制限はなく、ドライエッチングおよびウエットエッチングの少なくともひとつの方法を用いることができる。第３のトレンチ部２３ｔが形成されて残存する第１の絶縁膜４０ａの厚さにより後述する工程で形成されるゲート電極の位置が決まる。ここで、第３のトレンチ部２３ｔは、第２のトレンチ部２２ｔの一部に第１の絶縁膜４０ａが配置されて形成されたものである。 Next, referring to FIG. 6A, the manufacturing method of the semiconductor devices 2A, 2B, and 2C according to the present embodiment may include a step of removing a part of the first insulating film 40a. Through this step, at least a part of the second main surface of the semiconductor composite film 20C on the second semiconductor film 22 side and the surface of the third trench portion 23t formed on the second main surface can be exposed. . The method for removing a part of the first insulating film 40a is not particularly limited, and at least one of dry etching and wet etching can be used. The position of the gate electrode formed in the process described later is determined by the thickness of the first insulating film 40a remaining after the third trench portion 23t is formed. Here, the third trench portion 23t is formed by disposing the first insulating film 40a in a part of the second trench portion 22t.
　（ゲート電極を形成する工程）
　次に、図６（Ａ）および（Ｂ）を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、半導体複合膜２０Ｃの第２の半導体膜２２側の第２の主面に形成された第３のトレンチ部２３ｔの露出した表面であってかつ第１の半導体膜２１の第１の主面に対して垂直な主面の一部に接触するように第１の絶縁膜４０ａ上にゲート電極３０ｇを形成する工程を含むことができる。ゲート電極３０ｇを形成する方法は、その材料に適したものであれば特に制限はなく、真空蒸着法（特に、抵抗加熱真空蒸着法、電子線加熱蒸着法）などが好適である。第３のトレンチ部２３ｔの一部にゲート電極３０ｇが配置されて、第４のトレンチ部２４ｔが形成される。 (Process for forming gate electrode)
Next, with reference to FIGS. 6A and 6B, the method of manufacturing the semiconductor devices 2A, 2B, and 2C according to the present embodiment is the second main side of the semiconductor composite film 20C on the second semiconductor film 22 side. The first insulation so as to be in contact with a part of the main surface which is the exposed surface of the third trench portion 23 t formed on the surface and is perpendicular to the first main surface of the first semiconductor film 21. A step of forming a gate electrode 30g on the film 40a can be included. The method for forming the gate electrode 30g is not particularly limited as long as it is suitable for the material, and vacuum evaporation (particularly, resistance heating vacuum evaporation, electron beam evaporation) is preferable. The gate electrode 30g is disposed in a part of the third trench portion 23t, and the fourth trench portion 24t is formed.
　（第２の絶縁膜を形成する工程）
　次に、図６（Ｂ）および（Ｃ）を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、半導体複合膜２０Ｃの第２の半導体膜２２側の第２の主面、第４のトレンチ部２４ｔの表面およびゲート電極３０ｇ上に第２の絶縁膜４０ｂを形成する工程を含むことができる。第２の絶縁膜４０ｂを形成する方法は、上述の第１の絶縁膜４０ａを形成する方法と同様である。 (Step of forming the second insulating film)
Next, with reference to FIGS. 6B and 6C, in the method of manufacturing the semiconductor devices 2A, 2B, and 2C of the present embodiment, the second main side of the semiconductor composite film 20C on the second semiconductor film 22 side is described. Forming a second insulating film 40b on the surface, the surface of the fourth trench portion 24t, and the gate electrode 30g. The method for forming the second insulating film 40b is the same as the method for forming the first insulating film 40a described above.
　次いで、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、第２の絶縁膜４０ｂの一部を除去する工程を含むことができる。かかる工程により、半導体複合膜２０Ｃの第２の半導体膜２２側の第２の主面の一部およびゲート電極３０ｇの一部を露出させることができる。 Next, the method for manufacturing the semiconductor devices 2A, 2B, and 2C according to the present embodiment may include a step of removing a part of the second insulating film 40b. Through this step, a part of the second main surface of the semiconductor composite film 20C on the second semiconductor film 22 side and a part of the gate electrode 30g can be exposed.
　次いで、図６（Ｄ）を参照して、ゲート電極３０ｇの露出した部分上にゲート電極３０ｇの引き出し部を形成する工程を含むことができる。かかる工程により、ゲート電極３０ｇは、半導体複合膜２０Ｃの第２の半導体膜２２の第２の主面側に引き出される。ゲート電極３０ｇの引き出し部を形成する方法は、上述のゲート電極を形成する方法と同様である。 Next, referring to FIG. 6D, a step of forming a lead portion of the gate electrode 30g on the exposed portion of the gate electrode 30g may be included. Through this step, the gate electrode 30g is drawn to the second main surface side of the second semiconductor film 22 of the semiconductor composite film 20C. The method for forming the lead portion of the gate electrode 30g is the same as the method for forming the gate electrode described above.
　（ソース電極を形成する工程）
　次に、図６（Ｄ）を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、半導体複合膜２０Ｃの第２の半導体膜２２側の第２の主面の露出した部分上に、ソース電極３０ｓを形成する工程を含む。ソース電極３０ｓを形成する方法は、その材料に適したものであれば特に制限はなく、真空蒸着法（特に、抵抗加熱真空蒸着法、電子線加熱真空蒸着法）などが好適である。 (Process of forming source electrode)
Next, referring to FIG. 6D, in the manufacturing method of the semiconductor devices 2A, 2B, and 2C of the present embodiment, the second main surface of the semiconductor composite film 20C on the second semiconductor film 22 side is exposed. A step of forming a source electrode 30s on the portion is included. The method for forming the source electrode 30s is not particularly limited as long as it is suitable for the material, and vacuum deposition (particularly, resistance heating vacuum deposition, electron beam heating vacuum deposition) and the like are suitable.
　（保護絶縁膜を形成する工程）
　次に、図７（Ａ）を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、半導体複合膜２０Ｃの第２の半導体膜２２のゲート電極３０ｇとソース電極３０ｓが形成された第２の主面側に保護絶縁膜５０を形成する工程を含むことができる。保護絶縁膜５０は、特に制限はないが、ゲート電極３０ｇおよびソース電極３０ｓを保護する観点から、ＳｉＯ2膜、Ｓｉ3Ｎ4膜、Ａｌ2Ｏ3膜などが好ましい。保護絶縁膜５０を形成する方法は、その材料に適したものであれば特に制限はなく、スパッタ法、ＡＬＤ（原子層堆積）法などが好適である。 (Process for forming protective insulating film)
Next, referring to FIG. 7A, in the manufacturing method of the semiconductor devices 2A, 2B, and 2C of this embodiment, the gate electrode 30g and the source electrode 30s of the second semiconductor film 22 of the semiconductor composite film 20C are formed. The step of forming the protective insulating film 50 on the second main surface side can be included. Protective insulating film 50 is not particularly limited, from the viewpoint of protecting the gate electrode 30g and the source electrode 30s, SiO 2 film, Si 3 N 4 film, such as an Al 2 O 3 film is preferable. A method for forming the protective insulating film 50 is not particularly limited as long as it is suitable for the material, and a sputtering method, an ALD (atomic layer deposition) method, or the like is preferable.
　（仮支持基板を配置する工程）
　次に、図７（Ａ）を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、半導体複合膜２０Ｃの第２の半導体膜２２のゲート電極３０ｇとソース電極３０ｓが形成された第２の主面側に形成された保護絶縁膜５０上に仮支持基板６０を配置する工程を含むことができる。かかる工程により配置された仮支持基板６０により半導体複合膜２０Ｃが支持されるため、基礎基板１０を除去して露出した半導体複合膜２０Ｃの第１の半導体膜２１側の第１の主面上にドレイン電極３０ｄを形成することが容易になる。仮支持基板６０は、半導体複合膜２０Ｃを支持できるものであれば特に制限はないが、コストが低い観点から、シリコン基板、サファイア基板、金属基板などが好適である。仮支持基板６０を配置する方法は、特に制限はないが、仮支持基板６０の配置後の除去を容易にする観点から、ワックスなどで仮に貼り合わせをする方法が好ましい。 (Process of placing a temporary support substrate)
Next, referring to FIG. 7A, in the manufacturing method of the semiconductor devices 2A, 2B, and 2C of this embodiment, the gate electrode 30g and the source electrode 30s of the second semiconductor film 22 of the semiconductor composite film 20C are formed. The step of disposing the temporary support substrate 60 on the protective insulating film 50 formed on the second main surface side can be included. Since the semiconductor composite film 20C is supported by the temporary support substrate 60 disposed by such a process, the semiconductor composite film 20C exposed by removing the base substrate 10 is exposed on the first main surface on the first semiconductor film 21 side. It becomes easy to form the drain electrode 30d. The temporary support substrate 60 is not particularly limited as long as it can support the semiconductor composite film 20C, but a silicon substrate, a sapphire substrate, a metal substrate, and the like are preferable from the viewpoint of low cost. The method for arranging the temporary support substrate 60 is not particularly limited, but from the viewpoint of facilitating the removal of the temporary support substrate 60 after the arrangement, a method of temporarily bonding with wax or the like is preferable.
　（基礎基板を除去する工程）
　次に、図７（Ａ）を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、半導体複合膜２０Ｃの第１の半導体膜２１の第１の主面側に配置されている基礎基板１０を除去する工程を含むことができる。また、半導体複合膜２０Ｃの第１の半導体膜２１と基礎基板１０との間に接合膜１２が形成されている場合には、基礎基板１０および接合膜１２を除去することができる（図７（Ａ）の矢印は除去を示す）。基礎基板１０および接合膜１２を除去する方法は、それらの材料に適したものであれば特に制限なく、ドライエッチングおよびウエットエッチングなどのエッチング、研削、研磨などの方法がある。 (Process to remove the base substrate)
Next, referring to FIG. 7A, the method of manufacturing the semiconductor devices 2A, 2B, 2C of the present embodiment is arranged on the first main surface side of the first semiconductor film 21 of the semiconductor composite film 20C. A step of removing the underlying base substrate 10 may be included. When the bonding film 12 is formed between the first semiconductor film 21 of the semiconductor composite film 20C and the base substrate 10, the base substrate 10 and the bonding film 12 can be removed (FIG. 7 ( A) arrows indicate removal). The method for removing the base substrate 10 and the bonding film 12 is not particularly limited as long as it is suitable for these materials, and there are methods such as etching such as dry etching and wet etching, grinding, and polishing.
　（ドレイン電極を形成する工程）
　次に、図７（Ｂ）を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、基礎基板１０の除去により露出された半導体複合膜２０Ｃの第１の半導体膜２１側の第１の主面上に、ドレイン電極３０ｄを形成する工程を含む。ドレイン電極３０ｄを形成する方法は、その材料に適したものであれば特に制限はなく、真空蒸着法（特に、抵抗加熱真空蒸着法、電子線加熱真空蒸着法）などが好適である。 (Process for forming drain electrode)
Next, referring to FIG. 7B, in the manufacturing method of the semiconductor devices 2A, 2B, and 2C according to the present embodiment, the first semiconductor film 21 side of the semiconductor composite film 20C exposed by removing the base substrate 10 is used. Forming a drain electrode 30d on the first main surface. The method for forming the drain electrode 30d is not particularly limited as long as it is suitable for the material, and a vacuum evaporation method (particularly, resistance heating vacuum evaporation method, electron beam heating vacuum evaporation method) or the like is preferable.
　（仮支持基板を除去する工程）
　次に、図７（Ｃ）を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、仮支持基板６０を除去する工程を含むことができる。仮支持基板６０を除去する方法は、特に制限はなく、仮支持基板６０をワックスなどで仮に貼り合わせている場合は、そのワックスなどを溶融、溶解または除去する方法が好適である。 (Step of removing the temporary support substrate)
Next, with reference to FIG. 7C, the method for manufacturing the semiconductor devices 2 </ b> A, 2 </ b> B, and 2 </ b> C of this embodiment may include a step of removing the temporary support substrate 60. The method for removing the temporary support substrate 60 is not particularly limited, and when the temporary support substrate 60 is temporarily bonded with wax or the like, a method of melting, dissolving or removing the wax or the like is preferable.
　次に、図７（Ｃ）および（Ｄ）を参照して、本実施形態の半導体デバイス２Ａ，２Ｂ，２Ｃの製造方法は、保護絶縁膜５０を除去する工程を含むことができる。保護絶縁膜５０を除去する方法は、その材料に適したものであれば特に制限はなく、ドライエッチングおよびウエットエッチングの少なくともひとつの方法を用いることができる。 Next, with reference to FIGS. 7C and 7D, the method for manufacturing the semiconductor devices 2A, 2B, and 2C of the present embodiment may include a step of removing the protective insulating film 50. The method for removing the protective insulating film 50 is not particularly limited as long as it is suitable for the material, and at least one of dry etching and wet etching can be used.
　このようにして、オン抵抗が低くデバイスの主面の面積を大きくすることなく耐圧の高い実施形態１の半導体デバイス２Ａ（すなわち、第１の主面と第１の主面に対して垂直な第１のトレンチ部２１ｔが形成されている主面とを有する第１の半導体膜２１と第１の半導体膜２１の第１のトレンチ部２１ｔが形成されている主面上に配置されておりかつ第１のトレンチ部２１ｔに対応する第２のトレンチ部が２２ｔ形成されている第２の主面を有する第２の半導体膜２２とを含み、第１の主面および第２の主面に対して垂直な主面を有するキャリアチャネル層２０ｃを含む半導体複合膜２０Ｃと、半導体複合膜２０Ｃの第１の主面上に配置されたドレイン電極３０ｄと、半導体複合膜２０Ｃの第２の主面上に配置されたソース電極３０ｓと、を含む半導体デバイス）を効率よく製造することができる。 In this way, the semiconductor device 2A of the first embodiment having a low on-resistance and a high breakdown voltage without increasing the area of the main surface of the device (that is, the first main surface and the first main surface perpendicular to the first main surface). A first semiconductor film 21 having a main surface on which one trench portion 21t is formed, and a first semiconductor film 21 disposed on the main surface on which the first trench portion 21t is formed and A second semiconductor film 22 having a second main surface in which a second trench portion 22t corresponding to one trench portion 21t is formed, and with respect to the first main surface and the second main surface A semiconductor composite film 20C including a carrier channel layer 20c having a vertical main surface, a drain electrode 30d disposed on the first main surface of the semiconductor composite film 20C, and a second main surface of the semiconductor composite film 20C A disposed source electrode 30s; A semiconductor device) that includes can be produced efficiently.
　（導電性支持基板を配置する工程）
　図８を参照して、本実施形態の半導体デバイス２Ｂの製造方法は、ドレイン電極３０ｄを形成する工程（図７（Ｂ））の後の半導体デバイス２Ａ（図７（Ｄ）、図８（Ａ））に、ドレイン電極３０ｄが形成された第１の主面側に導電性支持基板７０を配置する工程（図８（Ｂ））をさらに含むことができる。かかる工程により、半導体複合膜２０Ｃを支持して半導体デバイスの機械的強度を高くすることができる。 (Process of placing a conductive support substrate)
Referring to FIG. 8, in the manufacturing method of semiconductor device 2B of the present embodiment, semiconductor device 2A (FIGS. 7D and 8A) after the step of forming drain electrode 30d (FIG. 7B) is performed. )) May further include a step (FIG. 8B) of disposing the conductive support substrate 70 on the first main surface side where the drain electrode 30d is formed. Through this process, the semiconductor composite film 20C can be supported and the mechanical strength of the semiconductor device can be increased.
　導電性支持基板７０は、特に制限はないが、半導体デバイスの機械的強度および特性を高くするために、比抵抗率が１×１０-4Ω・ｃｍ以下の導電性を有し、かつ、ドレイン電極３０ｄとオーミック接触させる観点から、シリコン基板、金属基板、金属焼結基板などが好ましい。 The conductive support substrate 70 is not particularly limited, but has a specific resistivity of 1 × 10 −4 Ω · cm or less in order to increase the mechanical strength and characteristics of the semiconductor device, and the drain. From the viewpoint of ohmic contact with the electrode 30d, a silicon substrate, a metal substrate, a metal sintered substrate, or the like is preferable.
　導電性支持基板７０を配置させる方法は、特に制限はなく、ドレイン電極３０ｄ上に導電性支持基板７０を貼り合わせる方法がある。導電性支持基板７０を貼り合わせる方法には、加圧融着法、通電加熱法などがある。 The method for disposing the conductive support substrate 70 is not particularly limited, and there is a method in which the conductive support substrate 70 is bonded onto the drain electrode 30d. Examples of the method for attaching the conductive support substrate 70 include a pressure fusion method, a current heating method, and the like.
　また、導電性支持基板７０とドレイン電極３０ｄとの間に接合膜（図示せず）が介在していてもよい。導電性支持基板７０とドレイン電極３０ｄとの間の接合膜は、導電性支持基板７０およびドレイン電極３０ｄとの接合が良好なものであれば特に制限はなく、金属はんだ膜、導電性ペースト膜などが好適である。 Further, a bonding film (not shown) may be interposed between the conductive support substrate 70 and the drain electrode 30d. The bonding film between the conductive support substrate 70 and the drain electrode 30d is not particularly limited as long as the bonding between the conductive support substrate 70 and the drain electrode 30d is good, and a metal solder film, a conductive paste film, or the like Is preferred.
　（支持基板を配置する工程）
　図９を参照して、本実施形態の半導体デバイス２Ｃの製造方法は、ソース電極３０ｓを形成する工程（図９（Ａ））の後に、ソース電極３０ｓが形成された第２の主面側に支持基板８０を配置する工程（図９（Ｂ））をさらに含むことができる。かかる工程により、半導体複合膜２０Ｃを支持して半導体デバイスの機械的強度を高くすることができる。 (Process of placing support substrate)
Referring to FIG. 9, in the method for manufacturing semiconductor device 2C of the present embodiment, after the step of forming source electrode 30s (FIG. 9A), on the second main surface side where source electrode 30s is formed. A step of disposing the support substrate 80 (FIG. 9B) can be further included. Through this process, the semiconductor composite film 20C can be supported and the mechanical strength of the semiconductor device can be increased.
　支持基板８０は、特に制限はないが、半導体デバイスの機械的強度を高くするために、シリコン基板、サファイア基板、ガラス基板、ＧａＮ基板、金属基板などが好ましい。 The support substrate 80 is not particularly limited, but a silicon substrate, a sapphire substrate, a glass substrate, a GaN substrate, a metal substrate, or the like is preferable in order to increase the mechanical strength of the semiconductor device.
　半導体複合膜２０Ｃの第２の半導体膜２２のゲート電極３０ｇが引き出されかつソース電極３０ｓが形成された第２の主面側に支持基板８０を配置するためには、図９（Ａ）に示すように、ソース電極３０ｓおよびゲート電極３０ｇとの電気的接続を確保するために、ソース電極３０ｓおよびゲート電極３０ｇを半導体デバイスの側面から引き出す必要がある。ソース電極３０ｓおよびゲート電極の引き出し部分を形成する方法は、ソース電極３０ｓおよびゲート電極３０ｇを形成する方法とそれぞれ同様である。 In order to dispose the support substrate 80 on the second main surface side from which the gate electrode 30g of the second semiconductor film 22 of the semiconductor composite film 20C is drawn and the source electrode 30s is formed, as shown in FIG. Thus, in order to ensure electrical connection with the source electrode 30s and the gate electrode 30g, it is necessary to draw out the source electrode 30s and the gate electrode 30g from the side surface of the semiconductor device. The method for forming the source electrode 30s and the lead-out portion of the gate electrode is the same as the method for forming the source electrode 30s and the gate electrode 30g, respectively.
　このため、図９（Ａ）を参照して、本実施形態の半導体デバイスの製造方法は、上記のゲート電極３０ｇを形成する工程およびソース電極３０ｓを形成する工程の後（図６（Ｄ）を参照）、半導体複合膜２０Ｃの第２の半導体膜２２の第２の主面側に引き出されたゲート電極３０ｇ、形成されたソース電極３０ｓおよび形成された第２の絶縁膜４０ｂ上に、ソース電極３０ｓの引き出し部分およびゲート電極３０ｇの引き出し部分を覆うように第３の絶縁膜４０ｃを形成する工程を含むことができる。第３の絶縁膜４０ｃを形成する方法は、その材料に適したものであれば特に制限はなく、スパッタ法、ＡＬＤ（原子層堆積）法、電子線加熱蒸着法などが好適である。 For this reason, referring to FIG. 9A, the semiconductor device manufacturing method of the present embodiment is performed after the step of forming the gate electrode 30g and the step of forming the source electrode 30s (FIG. 6D). See), the gate electrode 30g drawn to the second main surface side of the second semiconductor film 22 of the semiconductor composite film 20C, the formed source electrode 30s, and the formed second insulating film 40b on the source electrode A step of forming the third insulating film 40c so as to cover the lead portion of 30s and the lead portion of the gate electrode 30g may be included. The method for forming the third insulating film 40c is not particularly limited as long as it is suitable for the material, and a sputtering method, an ALD (atomic layer deposition) method, an electron beam heating vapor deposition method and the like are preferable.
　次に、図９（Ｂ）を参照して、本実施形態の半導体デバイスの製造方法は、第３の絶縁膜４０ｃ上に支持基板８０を配置する工程を含むことができる。 Next, with reference to FIG. 9B, the method for manufacturing a semiconductor device of this embodiment may include a step of disposing a support substrate 80 on the third insulating film 40c.
　支持基板８０を配置させる方法は、特に制限はなく、第３の絶縁膜４０ｃ上に支持基板８０を貼り合わせる方法がある。支持基板８０を貼り合わせる方法には、加熱融着法、通電加熱法などがある。 The method for arranging the support substrate 80 is not particularly limited, and there is a method in which the support substrate 80 is bonded onto the third insulating film 40c. As a method for attaching the support substrate 80, there are a heat fusion method, an electric heating method, and the like.
　また、支持基板８０と第３の絶縁膜４０ｃとの間に接合膜（図示せず）が介在していてもよい。支持基板８０と第３の絶縁膜４０ｃとの間の接合膜は、支持基板８０および第３の絶縁膜４０ｃとの接合が良好なものであれば特に制限はなく、金属はんだ膜、樹脂硬化膜などが好適である。 Further, a bonding film (not shown) may be interposed between the support substrate 80 and the third insulating film 40c. The bonding film between the support substrate 80 and the third insulating film 40c is not particularly limited as long as the bonding between the support substrate 80 and the third insulating film 40c is good, and is a metal solder film or a resin cured film. Etc. are suitable.
　なお、図９（Ｂ）を参照して、支持基板８０を配置させる工程後に含まれ得る基礎基板１０を除去する工程は、図７（Ａ）に示す基礎基板１０を除去する工程と同様である。また、図９（Ｃ）に示すドレイン電極３０ｄを形成する工程は、図７（Ｂ）に示すドレイン電極を形成する工程と同様である。 Referring to FIG. 9B, the step of removing base substrate 10 that can be included after the step of disposing support substrate 80 is the same as the step of removing base substrate 10 shown in FIG. . Further, the step of forming the drain electrode 30d shown in FIG. 9C is the same as the step of forming the drain electrode shown in FIG.
　（実施例１）
　以下の手順により、図１に示す縦型ＦＥＴ（電界効果トランジスタ）である半導体デバイス２Ａを作製し、その特性を評価した。 Example 1
According to the following procedure, a semiconductor device 2A which is a vertical FET (field effect transistor) shown in FIG. 1 was produced and its characteristics were evaluated.
　１．複合基板の準備
　図５（Ａ）を参照して、基礎基板１０である厚さ４００μｍのＭｏ焼結基板と、その一主面上に接合膜１２である厚さ２００ｎｍのＳｉＯ2膜を介在させて配置された半導体膜２０である厚さ７μｍのｎ－ＧａＮ膜（キャリア濃度が１×１０15ｃｍ-3）と、を含む直径２インチ（５．０８ｃｍ）の複合基板１を準備した。 1. Preparation of Composite Substrate With reference to FIG. 5 (A), a Mo sintered substrate having a thickness of 400 μm that is the base substrate 10 and a SiO 2 film having a thickness of 200 nm that is the bonding film 12 are interposed on one main surface thereof. And a composite substrate 1 having a diameter of 2 inches (5.08 cm) including an n-GaN film (carrier concentration is 1 × 10 15 cm −3 ) having a thickness of 7 μm, which is a semiconductor film 20 arranged in this manner.
　２．第１の半導体膜の形成
　次に、図５（Ｂ）を参照して、電子線リソグラフィー法およびフォトリソグラフィー法により半導体膜２０の主面上にパターン化されたレジスト膜（図示せず）を形成した後、ＲＩＥ（反応性イオンエッチング）により半導体膜２０の一部を除去することにより、半導体膜２０の主面に対して垂直な深さが６μｍで幅が２μｍの第１のトレンチ部２１ｔが４μｍのピッチで形成された第１の半導体膜２１が形成された。 2. Formation of First Semiconductor Film Next, referring to FIG. 5B, a patterned resist film (not shown) is formed on the main surface of the semiconductor film 20 by electron beam lithography and photolithography. After that, by removing a part of the semiconductor film 20 by RIE (reactive ion etching), the first trench portion 21t having a depth of 6 μm and a width of 2 μm perpendicular to the main surface of the semiconductor film 20 is formed. A first semiconductor film 21 formed at a pitch of 4 μm was formed.
　３．半導体複合膜の形成
　次に、図５（Ｃ）を参照して、第１の半導体膜２１の第１のトレンチ部２１ｔが形成された主面上に、ＯＭＶＰＥ（有機金属気相エピタキシ）法により、第２の半導体膜２２として厚さ１０ｎｍのＡｌ0.3Ｇａ0.7Ｎ膜を形成した。こうして、第１の半導体膜２１と第２の半導体膜２２との界面に第１の半導体膜側の第１の主面に対して垂直な主面を有するキャリアチャネル層２０ｃを含む半導体複合膜２０Ｃが得られた。 3. Formation of Semiconductor Composite Film Next, referring to FIG. 5C, an OMVPE (organometallic vapor phase epitaxy) method is used on the main surface of the first semiconductor film 21 where the first trench portion 21t is formed. Then, an Al 0.3 Ga 0.7 N film having a thickness of 10 nm was formed as the second semiconductor film 22. Thus, the semiconductor composite film 20C including the carrier channel layer 20c having the main surface perpendicular to the first main surface on the first semiconductor film side at the interface between the first semiconductor film 21 and the second semiconductor film 22. was gotten.
　４．第１の絶縁膜の形成
　次に、図５（Ｄ)を参照して、半導体複合膜２０Ｃの第２の半導体膜２２側の第２のトレンチ部２２ｔが形成された主面上に、ＡＬＤ（原子層堆積）法により、第１の絶縁膜４０ａとして半導体複合膜２０Ｃの第２の半導体膜２２側の主面に形成された第２のトレンチ部２２ｔの底部からの厚さが６．５μｍのＳｉＯ2膜を形成した。 4). Formation of First Insulating Film Next, referring to FIG. 5D, ALD (on the main surface of the semiconductor composite film 20C on which the second trench portion 22t on the second semiconductor film 22 side is formed. The thickness from the bottom of the second trench portion 22t formed on the main surface of the semiconductor composite film 20C on the second semiconductor film 22 side by the atomic layer deposition method is 6.5 μm. A SiO 2 film was formed.
　次に、図６（Ａ）を参照して、第１の絶縁膜４０ａの一部をＲＩＥ（反応性イオンエッチング）により除去することにより、半導体複合膜２０Ｃの第２の半導体膜２２側の第２の主面および第２の主面に形成された第３のトレンチ部２３ｔの表面を露出させた。露出させた第３のトレンチ部２３ｔの深さは２μｍであった。すなわち、第１の絶縁膜４０ａの厚さは４．５μｍであった。 Next, referring to FIG. 6A, a part of the first insulating film 40a is removed by RIE (reactive ion etching), whereby the second semiconductor film 22 side of the semiconductor composite film 20C is removed. The surface of the 3rd trench part 23t formed in 2 main surface and 2nd main surface was exposed. The depth of the exposed third trench portion 23t was 2 μm. That is, the thickness of the first insulating film 40a was 4.5 μm.
　５．ゲート電極の形成
　次に、図６（Ａ）および（Ｂ）を参照して、半導体複合膜２０Ｃの第２の半導体膜２２側の第２の主面に形成された第３のトレンチ部２３ｔの露出した表面であってかつ第１の半導体膜２１の第１の主面に対して垂直な主面の一部に接触するように、第１の絶縁膜４０ａ上に、ゲート電極３０ｇとしてゲート幅が０．５μｍのＮｉ／Ａｕ電極を真空蒸着法により形成した。第３のトレンチ部２３ｔの一部にゲート電極３０ｇが配置されて、第４のトレンチ部２４ｔが形成された。 5. Formation of Gate Electrode Next, with reference to FIGS. 6A and 6B, the third trench portion 23t formed on the second main surface of the semiconductor composite film 20C on the second semiconductor film 22 side. A gate width as a gate electrode 30g is formed on the first insulating film 40a so as to be in contact with a part of the main surface which is an exposed surface and is perpendicular to the first main surface of the first semiconductor film 21. A 0.5 μm Ni / Au electrode was formed by vacuum deposition. The gate electrode 30g is disposed in a part of the third trench portion 23t, and the fourth trench portion 24t is formed.
　６．第２の絶縁膜の形成
　次に、図６（Ｃ）を参照して、半導体複合膜２０Ｃの第２の半導体膜２２側の第２の主面、第４のトレンチ部２４ｔの表面およびゲート電極３０ｇ上に、ＡＬＤ（原子層堆積）法により、第２の絶縁膜４０ｂとしてゲート電極３０ｇの主面からの厚さが２μｍのＳｉＯ2膜を形成した。 6). Formation of Second Insulating Film Next, referring to FIG. 6C, the second main surface of the semiconductor composite film 20C on the second semiconductor film 22 side, the surface of the fourth trench portion 24t, and the gate electrode An SiO 2 film having a thickness of 2 μm from the main surface of the gate electrode 30g was formed as the second insulating film 40b on 30 g by ALD (atomic layer deposition).
　次いで、第２の絶縁膜４０ｂの一部をＲＩＥ（反応性イオンエッチング）法により除去することにより、半導体複合膜２０Ｃの第２の半導体膜２２側の第２の主面の一部およびゲート電極３０ｇの一部を露出させた。 Next, a part of the second main surface on the second semiconductor film 22 side of the semiconductor composite film 20C and the gate electrode are removed by removing a part of the second insulating film 40b by RIE (reactive ion etching). A portion of 30 g was exposed.
　次いで、図６（Ｄ）を参照して、ゲート電極３０ｇの露出した部分上に、ゲート電極３０ｇの引き出し部としてＡｕ電極の引き出し部を真空蒸着法により形成した。 Next, referring to FIG. 6D, an Au electrode lead portion was formed as a lead portion of the gate electrode 30g on the exposed portion of the gate electrode 30g by vacuum deposition.
　７．ソース電極の形成
　次に、図６（Ｄ）を参照して、半導体複合膜２０Ｃの第２の半導体膜２２側の第２の主面の露出した部分上に、ソース電極３０ｓとして厚さが２０ｎｍのＴｉ電極を真空蒸着法により形成した。 7). Next, referring to FIG. 6D, a thickness of 20 nm is formed as a source electrode 30s on the exposed portion of the second main surface of the semiconductor composite film 20C on the second semiconductor film 22 side. The Ti electrode was formed by vacuum deposition.
　８．保護絶縁膜の形成
　次に、図７（Ａ）を参照して、半導体複合膜２０Ｃの第２の半導体膜２２のゲート電極３０ｇとソース電極３０ｓが形成された第２の主面側に、保護絶縁膜５０として、第２の主面からの厚さが３μｍのＳｉＯ2膜を形成した。 8). Formation of Protective Insulating Film Next, referring to FIG. 7A, a protective film is formed on the second main surface side of the second semiconductor film 22 of the semiconductor composite film 20C on which the gate electrode 30g and the source electrode 30s are formed. As the insulating film 50, a SiO 2 film having a thickness of 3 μm from the second main surface was formed.
　９．仮支持基板の配置
　次に、図７（Ａ）を参照して、保護絶縁膜５０上に、仮支持基板６０として厚さが４００μｍのＳｉ（シリコン）基板をワックスにより貼り合わせることにより配置した。 9. Next, with reference to FIG. 7A, an Si (silicon) substrate having a thickness of 400 μm is disposed as a temporary support substrate 60 on the protective insulating film 50 by bonding with wax.
　１０．基礎基板の除去
　次に、図７（Ａ）を参照して、半導体複合膜２０Ｃの第１の半導体膜２１の第１の主面側に配置されている基礎基板１０、接合膜１２、および半導体複合膜２０Ｃの第１の半導体膜２１の一部を研磨およびドライエッチングにより除去した。第１の半導体膜２１の薄い部分の厚さ（これは第１の主面に対して垂直な面のキャリアチャネル層と第１の主面との最短距離に等しい）は、Ｘ線回折法により測定したところ、１０ｎｍであった。 10. Next, with reference to FIG. 7A, the base substrate 10, the bonding film 12, and the semiconductor disposed on the first main surface side of the first semiconductor film 21 of the semiconductor composite film 20C. A part of the first semiconductor film 21 of the composite film 20C was removed by polishing and dry etching. The thickness of the thin portion of the first semiconductor film 21 (which is equal to the shortest distance between the carrier channel layer in the plane perpendicular to the first main surface and the first main surface) is determined by the X-ray diffraction method. It was 10 nm when measured.
　１１．ドレイン電極の形成
　次に、図７（Ｂ）を参照して、基礎基板１０の除去により露出された半導体複合膜２０Ｃの第１の半導体膜２１側の第１の主面上に、ドレイン電極３０ｄとして厚さが２０ｎｍのＴｉ電極を真空蒸着法により形成した。 11. Formation of Drain Electrode Next, referring to FIG. 7B, the drain electrode 30d is formed on the first main surface of the semiconductor composite film 20C exposed by removing the base substrate 10 on the first semiconductor film 21 side. A Ti electrode having a thickness of 20 nm was formed by vacuum evaporation.
　１２．仮支持基板の除去
　次に、図７（Ｃ）を参照して、保護絶縁膜５０上に仮支持基板６０を貼り合わせているワックスを溶解することにより、仮支持基板６０を除去した。 12 Removal of Temporary Support Substrate Next, referring to FIG. 7C, the temporary support substrate 60 was removed by dissolving the wax bonding the temporary support substrate 60 on the protective insulating film 50.
　次に、図７（Ｃ）および（Ｄ）を参照して、保護絶縁膜５０をＲＩＥ（反応性イオンエッチング）により除去して、半導体複合膜２０Ｃの第２の半導体膜２２側の第２の主面上にゲート電極３０ｇの引き出し部およびソース電極３０ｓを露出させることにより、半導体デバイス２Ａとして縦型ＦＥＴを得た。 Next, referring to FIGS. 7C and 7D, the protective insulating film 50 is removed by RIE (reactive ion etching), and the second semiconductor film 22 side second semiconductor film 20C side is removed. By exposing the lead portion of the gate electrode 30g and the source electrode 30s on the main surface, a vertical FET was obtained as the semiconductor device 2A.
　１３．半導体デバイスの特性評価
　得られた半導体デバイス２Ａについて、その耐圧はＩ－Ｖ測定したところ３００Ｖであり、そのオン抵抗はＩ－Ｖ測定したところ１ｍΩ・ｃｍ2であった。 13. Evaluation of characteristics of semiconductor device With respect to the obtained semiconductor device 2A, its withstand voltage was 300 V as measured by IV, and its on-resistance was 1 mΩ · cm 2 as measured by IV.
　（比較例１）
　以下の手順により、図２に示す横型ＦＥＴ（電界トランジスタ）である半導体デバイス２Ｒを作製し、その特性を評価した。 (Comparative Example 1)
The semiconductor device 2R, which is a lateral FET (electric field transistor) shown in FIG. 2, was manufactured by the following procedure, and the characteristics thereof were evaluated.
　１．複合基板の準備
　実施例１と同様の複合基板（すなわち、基礎基板である厚さ４００μｍのＭｏ焼結基板と、その一主面上に接合膜である厚さ２００ｎｍのＳｉＯ2膜を介在させて配置された半導体膜である厚さ７μｍのｎ－ＧａＮ膜（キャリア濃度が２×１０15ｃｍ-3）と、を含む直径２インチ（５．０８ｃｍ）の複合基板を準備した。 1. Preparation of Composite Substrate The same composite substrate as in Example 1 (that is, a Mo sintered substrate having a thickness of 400 μm as a basic substrate and a SiO 2 film having a thickness of 200 nm as a bonding film on one main surface thereof) A composite substrate having a diameter of 2 inches (5.08 cm) including an n-GaN film (carrier concentration 2 × 10 15 cm −3 ) having a thickness of 7 μm, which is a semiconductor film, was prepared.
　２．第１の半導体膜の形成
　準備された複合基板には、厚さ７μｍのｎ－ＧａＮ膜である第１の半導体膜が形成されていた。 2. Formation of First Semiconductor Film A first semiconductor film, which is an n-GaN film having a thickness of 7 μm, was formed on the prepared composite substrate.
　３．半導体複合膜の形成
　次に、第１の半導体膜の主面上に、ＯＭＶＰＥ（有機金属気相エピタキシ）法により、第２の半導体膜として厚さ１０ｎｍのＡｌ0.3Ｇａ0.7Ｎ膜を形成した。こうして、第１の半導体膜と第２の半導体膜との界面に第１の半導体膜側の第１の主面および第２の半導体膜側の第２の主面に対して平行な主面を有するキャリアチャネル層を含む半導体複合膜が得られた。 3. Formation of Semiconductor Composite Film Next, an Al 0.3 Ga 0.7 N film having a thickness of 10 nm was formed as a second semiconductor film on the main surface of the first semiconductor film by OMVPE (metal organic vapor phase epitaxy). Thus, the main surface parallel to the first main surface on the first semiconductor film side and the second main surface on the second semiconductor film side is formed at the interface between the first semiconductor film and the second semiconductor film. A semiconductor composite film including the carrier channel layer was obtained.
　４．絶縁膜の形成
　次に、半導体複合膜の第２の半導体膜側の第２の主面上に、ＡＬＤ（原子層堆積）法により、絶縁膜として半導体複合膜の第２の半導体膜側の主面に厚さが１μｍのＳｉＯ2膜を形成した。 4). Formation of Insulating Film Next, on the second main surface of the semiconductor composite film on the second semiconductor film side, the main film on the second semiconductor film side of the semiconductor composite film as an insulating film is formed by ALD (atomic layer deposition) method. A SiO 2 film having a thickness of 1 μm was formed on the surface.
　次いで、絶縁膜の一部をＲＩＥ（反応性イオンエッチング）により除去することにより、半導体複合膜の第２の半導体膜側の第２の主面の一部が露出した絶縁膜の開口部のパターンを形成した。 Next, by removing a part of the insulating film by RIE (reactive ion etching), the pattern of the opening part of the insulating film in which a part of the second main surface on the second semiconductor film side of the semiconductor composite film is exposed. Formed.
　５．電極の形成
　パターン化された絶縁膜の開口部における露出した第２の半導体膜上に、ソース電極として厚さが２０ｎｍのＴｉ電極、ゲート電極としてゲート幅が０．５μｍで厚さが３０ｎｍのＮｉ電極、およびドレイン電極として厚さが２０ｎｍのＴｉ電極を真空蒸着法により形成した。ここで、ソース電極端とゲート電極端との距離は１μｍであり、ゲート電極端とドレイン電極端との距離は４．５μｍであり、ソース電極端とドレイン電極端との距離は６μｍであり、キャリアチャネル層の長さＬは６μｍであった。このようにして、半導体デバイス２Ｒとして横型ＦＥＴを得た。 5. Formation of Electrode On the exposed second semiconductor film in the opening of the patterned insulating film, a Ti electrode having a thickness of 20 nm as a source electrode and a Ni having a gate width of 0.5 μm and a thickness of 30 nm as a gate electrode A Ti electrode having a thickness of 20 nm was formed by vacuum deposition as an electrode and a drain electrode. Here, the distance between the source electrode end and the gate electrode end is 1 μm, the distance between the gate electrode end and the drain electrode end is 4.5 μm, and the distance between the source electrode end and the drain electrode end is 6 μm, The length L of the carrier channel layer was 6 μm. In this way, a lateral FET was obtained as the semiconductor device 2R.
　６．半導体デバイスの特性評価
　得られた半導体デバイス２Ｒについて、その耐圧は３００Ｖであり、そのオン抵抗は１ｍΩ・ｃｍ2であった。 6). Evaluation of characteristics of semiconductor device The obtained semiconductor device 2R had a withstand voltage of 300 V and an on-resistance of 1 mΩ · cm 2 .
　実施例１および比較例１を参照して、本発明にかかる半導体デバイスである縦型ＦＥＴは、その耐圧およびオン抵抗が典型的な横型ＦＥＴと同程度であり、その１ユニット当たりの主面の面積の大きさが典型的な横型ＦＥＴの１／３であった。また、さらに耐圧を高めるために、比較例１のような横型ＦＥＴでは１ユニット当たりの主面の面積を大きくする必要があるが、実施例１のような縦型ＦＥＴにおいては、半導体複合膜の主面（第１の主面および第２の主面）に垂直な主面を有するキャリアチャネル層のチャネル長さを大きくすれば足り、１ユニット当たりの主面の面積を大きくする必要がない。すなわち、本発明にかかる半導体デバイスは、１ユニット当たりの主面の面積を大きくすることなく、耐圧を高くすることができる。 With reference to Example 1 and Comparative Example 1, the vertical FET, which is a semiconductor device according to the present invention, has the same breakdown voltage and on-resistance as a typical lateral FET, and has a main surface per unit. The size of the area was 1/3 of a typical lateral FET. In order to further increase the breakdown voltage, the lateral FET as in Comparative Example 1 needs to increase the area of the main surface per unit. In the vertical FET as in Example 1, the semiconductor composite film It is sufficient to increase the channel length of the carrier channel layer having a main surface perpendicular to the main surfaces (the first main surface and the second main surface), and it is not necessary to increase the area of the main surface per unit. That is, the semiconductor device according to the present invention can increase the breakdown voltage without increasing the area of the main surface per unit.
　今回開示された実施の形態および実施例はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 It should be considered that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
１　複合基板、１Ｌ　接合基板、２Ａ，２Ｂ，２Ｃ，２Ｒ　半導体デバイス、１０　基礎基板、１２，１２ａ，１２ｂ　接合膜、２０，２０ａ，２０ｂ　半導体膜、２０Ｃ　半導体複合膜、２０ｃ　キャリアチャネル層、２０Ｄ，２０Ｄｒ　半導体膜ドナー基板、２１　第１の半導体膜、２１ｔ　第１のトレンチ部、２２　第２の半導体膜、２２ｔ　第２のトレンチ部、２３ｔ　第３のトレンチ部、２４ｔ　第４のトレンチ部、３０ｄ　ドレイン電極、３０ｇ　ゲート電極、３０ｓ　ソース電極、４０　絶縁膜、４０ａ　第１の絶縁膜、４０ｂ　第２の絶縁膜、４０ｃ　第３の絶縁膜、５０　保護絶縁膜、６０　仮支持基板、７０　導電性支持基板、８０　支持基板、１００　下地基板。 1 composite substrate, 1L bonding substrate, 2A, 2B, 2C, 2R semiconductor device, 10 base substrate, 12, 12a, 12b bonding film, 20, 20a, 20b semiconductor film, 20C semiconductor composite film, 20c carrier channel layer, 20D, 20 Dr semiconductor film donor substrate, 21 first semiconductor film, 21 t first trench part, 22 second semiconductor film, 22 t second trench part, 23 t third trench part, 24 t fourth trench part, 30 d drain Electrode, 30 g gate electrode, 30 s source electrode, 40 insulating film, 40 a first insulating film, 40 b second insulating film, 40 c third insulating film, 50 protective insulating film, 60 temporary supporting substrate, 70 conductive supporting substrate 80 support substrate, 100 base substrate.

Claims (8)

  1. 　第１の主面と前記第１の主面の反対側の主面である第２の主面とを有し、前記第１の主面および前記第２の主面に対して垂直な主面を有するキャリアチャネル層を含む半導体複合膜と、
    　前記半導体複合膜の前記第１の主面上に配置されたドレイン電極と、
    　前記半導体複合膜の前記第２の主面上に配置されたソース電極と、を含む半導体デバイス。     A main surface that has a first main surface and a second main surface that is a main surface opposite to the first main surface, and is perpendicular to the first main surface and the second main surface A semiconductor composite film including a carrier channel layer having
    A drain electrode disposed on the first main surface of the semiconductor composite film;
    And a source electrode disposed on the second main surface of the semiconductor composite film.
  2. 　前記半導体複合膜は、前記第１の主面と前記第１の主面に対して垂直な第１のトレンチ部が形成されている主面とを有する第１の半導体膜と、前記第１の半導体膜の前記第１のトレンチ部が形成されている前記主面上に配置されておりかつ前記第１のトレンチ部に対応する第２のトレンチ部が形成されている前記第２の主面を有する第２の半導体膜と、を含み、
    　前記キャリアチャネル層は、前記第１の半導体膜と前記第２の半導体膜との界面に形成されている請求項１に記載の半導体デバイス。     The semiconductor composite film includes a first semiconductor film having the first main surface and a main surface in which a first trench portion perpendicular to the first main surface is formed; The second main surface of the semiconductor film that is disposed on the main surface where the first trench portion is formed and has a second trench portion corresponding to the first trench portion. A second semiconductor film having,
    The semiconductor device according to claim 1, wherein the carrier channel layer is formed at an interface between the first semiconductor film and the second semiconductor film.
  3. 　前記半導体複合膜の前記第１の主面側に配置された導電性支持基板をさらに含む請求項１または請求項２に記載の半導体デバイス。 The semiconductor device according to claim 1, further comprising a conductive support substrate disposed on the first main surface side of the semiconductor composite film.
  4. 　前記半導体複合膜の前記第２の主面側に配置された支持基板をさらに含む請求項１または請求項２に記載の半導体デバイス。 The semiconductor device according to claim 1, further comprising a support substrate disposed on the second main surface side of the semiconductor composite film.
  5. 　基礎基板と前記基礎基板の一主面側に配置された半導体膜とを含む複合基板を準備する工程と、
    　前記複合基板の前記半導体膜の一部を除去することにより、前記半導体膜の主面に対して垂直な第１のトレンチ部が形成された主面を有する第１の半導体膜を形成する工程と、
    　前記第１の半導体膜の前記第１のトレンチ部が形成された前記主面上に第２の半導体膜を形成することにより、前記第１の半導体膜と前記第２の半導体膜との界面に形成されておりかつ前記第１の半導体膜側の主面である第１の主面に対して垂直な主面を有するキャリアチャネル層を含む半導体複合膜を形成する工程と、
    　前記半導体複合膜の前記第２の半導体膜側の主面であり前記キャリアチャネル層に対して垂直な第２の主面上にソース電極を形成する工程と、
    　前記半導体複合膜の前記第１の半導体膜側の前記第１の主面上にドレイン電極を形成する工程と、を含む半導体デバイスの製造方法。     Preparing a composite substrate including a base substrate and a semiconductor film disposed on one main surface side of the base substrate;
    Forming a first semiconductor film having a main surface on which a first trench portion perpendicular to the main surface of the semiconductor film is formed by removing a part of the semiconductor film of the composite substrate; ,
    By forming a second semiconductor film on the main surface of the first semiconductor film where the first trench portion is formed, an interface between the first semiconductor film and the second semiconductor film is formed. Forming a semiconductor composite film including a carrier channel layer that is formed and has a principal surface perpendicular to the first principal surface that is the principal surface on the first semiconductor film side;
    Forming a source electrode on a main surface of the semiconductor composite film on the second semiconductor film side and perpendicular to the carrier channel layer;
    Forming a drain electrode on the first main surface of the semiconductor composite film on the first semiconductor film side.
  6. 　前記複合基板を準備する工程の後、前記第１の半導体膜を形成する工程の前に、前記複合基板の前記半導体膜上にさらなる半導体膜を形成する工程をさらに含み、
    　前記第１の半導体膜を形成する工程は、前記さらなる半導体膜の一部ならびに前記半導体膜および前記さらなる半導体膜の一部のいずれかを除去することにより行なう請求項５に記載の半導体デバイスの製造方法。     After the step of preparing the composite substrate and before the step of forming the first semiconductor film, further comprising the step of forming a further semiconductor film on the semiconductor film of the composite substrate;
    6. The method of manufacturing a semiconductor device according to claim 5, wherein the step of forming the first semiconductor film is performed by removing a part of the further semiconductor film and any one of the semiconductor film and the further semiconductor film. Method.
  7. 　前記ドレイン電極を形成する工程の後に、前記ドレイン電極が形成された前記第１の主面側に導電性支持基板を配置する工程をさらに含む請求項５または請求項６に記載の半導体デバイスの製造方法。 The semiconductor device manufacturing method according to claim 5, further comprising a step of disposing a conductive support substrate on the first main surface side where the drain electrode is formed after the step of forming the drain electrode. Method.
  8. 　前記ソース電極を形成する工程の後に、前記ソース電極が形成された前記第２の主面側に支持基板を配置する工程をさらに含む請求項５または請求項６に記載の半導体デバイスの製造方法。 7. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of arranging a support substrate on the second main surface side where the source electrode is formed after the step of forming the source electrode.
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Citations (4)

* Cited by examiner, † Cited by third party
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JP2003051508A (en) * 2001-06-01 2003-02-21 Furukawa Electric Co Ltd:The GaN-BASED SEMICONDUCTOR DEVICE
JP2008512874A (en) * 2004-09-13 2008-04-24 ノースロップ・グラマン・コーポレーション HEMT apparatus and manufacturing method
JP2012169481A (en) * 2011-02-15 2012-09-06 Sumitomo Electric Ind Ltd Semiconductor device and manufacturing method of the same
JP2013115112A (en) * 2011-11-25 2013-06-10 Sumitomo Electric Ind Ltd Method of manufacturing composite substrate and method of manufacturing semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003051508A (en) * 2001-06-01 2003-02-21 Furukawa Electric Co Ltd:The GaN-BASED SEMICONDUCTOR DEVICE
JP2008512874A (en) * 2004-09-13 2008-04-24 ノースロップ・グラマン・コーポレーション HEMT apparatus and manufacturing method
JP2012169481A (en) * 2011-02-15 2012-09-06 Sumitomo Electric Ind Ltd Semiconductor device and manufacturing method of the same
JP2013115112A (en) * 2011-11-25 2013-06-10 Sumitomo Electric Ind Ltd Method of manufacturing composite substrate and method of manufacturing semiconductor device

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