WO2015067933A1

WO2015067933A1 - Tunnel junction

Info

Publication number: WO2015067933A1
Application number: PCT/GB2014/053275
Authority: WO
Inventors: David GUNNARSSON; Evan Parker; Martin PREST; Mika Prunnila; Terence Whall
Original assignee: The University Of Warwick; Vtt Technical Research Centre Of Finland
Priority date: 2013-11-06
Filing date: 2014-11-04
Publication date: 2015-05-14
Also published as: GB201319613D0; GB2520030A

Abstract

A superconductor-insulator-semiconductor tunnel junction and a method of forming a superconductor-insulator-semiconductor tunnel junction are described. The method comprises removing a surface oxide layer from a surface of a layer of silicon, germanium or silicon-germanium alloy, for example, using a buffered hydrogen fluoride dip. The method comprises heating the layer of silicon, germanium or silicon-germanium alloy to at least 550 °C in a vacuum and forming a dielectric layer on the surface of the layer of silicon, germanium or silicon-germanium alloy, for example, by oxidation. The method comprises depositing a superconductor on the dielectric layer.

Description

Tunnel j unction

Field of the Invention

The present invention relates to a tunnel junction and to a method of fabricating a tunnel junction.

Background

Semiconductor-superconductor tunnel junctions can be used for electron cooling at low temperatures, typically around or below lK. Cooling power can be increased by reducing the tunnel resistance. However, semiconductor-superconductor tunnel junction devices tend to suffer from a high sub-gap leakage if the tunnel resistance is reduced. Reference is made to A. M. Savin et al.: "Efficient electronic cooling in heavily doped silicon by quasiparticle tunneling", Applied Physics Letters, volume 79, pages 1471 to 1473 (2011).

The present invention seeks to provide an improved tunnel junction device, e.g.

providing greater cooling.

Summary

According to a first aspect of the present invention there is provided a method of forming a superconductor-insulator-semiconductor tunnel junction. The method comprises removing a surface oxide layer from a surface of a layer of silicon, germanium or silicon-germanium alloy, heating the layer of silicon, germanium or silicon-germanium alloy to at least 550 °C in a vacuum, forming a dielectric layer on the surface of the layer of silicon, germanium or silicon-germanium alloy and depositing a superconductor on the dielectric layer.

Introducing an insulator (i.e. a dielectric layer) between the semiconductor and the superconductor can help to reduce sub-gap leakage and so increase the cooling efficiency of the junction. Heating the layer of silicon, germanium or silicon-germanium can be used to clean the surface of the layer, for example, by driving off terminating chemical species, such as hydrogen, from the surface of the layer.

Heating the layer of silicon, germanium or silicon-germanium, forming the dielectric layer and depositing the superconductor may be steps which are carried out in a deposition system (which may include more than one chamber). The layer of silicon, germanium or silicon-germanium (which maybe supported on a substrate) is not removed from the system between steps. Thus, the surface of the layer is not exposed to ambient conditions once the layer of silicon, germanium or silicon-germanium are driven off by heating until the dielectric layer is formed and the superconductor deposited.

Forming the dielectric layer may comprise exposing the surface of the layer of silicon, germanium or silicon-germanium alloy to one or more chemical species. Forming the dielectric layer may comprise exposing the surface of the layer of silicon, germanium or silicon-germanium alloy to a gas. Forming the dielectric layer may comprise exposing the surface of the layer of silicon, germanium or silicon-germanium alloy to a mixture of gases or to a sequence of gases (such as oxygen and then nitrogen) and/or gas mixtures (such as a mixture of oxygen and nitrogen). Forming the dielectric layer may comprise exposing the surface of the layer of silicon, germanium or silicon-germanium alloy to oxygen, for example, in the form of (dry) pure oxygen gas (0₂). Forming the dielectric layer may comprise exposing the surface of the layer of silicon, germanium or silicon-germanium alloy to nitrogen, for example, in the form of (dry) pure nitrogen gas (N₂). The method may comprise exposing the surface of the layer of silicon, germanium or silicon-germanium alloy (for example, to oxygen gas) for a time of at least 1 minute, at least 2 minutes, at least 5 minutes or at least 10 minutes. The method may comprise exposing the surface of the layer for a time no more than 2 hours, no more than 1 hour or no more than 0.5 hours. For example, the method may comprise exposing the surface of the layer of silicon, germanium or silicon-germanium alloy for about 10 to 20 minutes.

Formation of the dielectric layer may be carried out at a pressure below atmospheric pressure. Formation of the dielectric layer may be carried out at a pressure between 200 mbar (20,000 Pa) and 400 mbar (40,000 Pa). Formation of the dielectric layer may be carried out at a temperature above room temperature. Forming the dielectric layer may be carried out at a temperature at or above 500 °C. For example, formation of the dielectric layer may be carried out at a temperature of about 550 °C.

Formation of the dielectric layer may be carried out at the same temperature at which the layer is heated.

At least a portion of the dielectric layer and a portion of the superconductor may react to form another dielectric material. For example, some or all of a layer of silicon dioxide may react with aluminium to form aluminium oxide. Removing the surface oxide layer (or "native oxide layer") may comprise using a wet etch. Removing the surface oxide layer may comprise using hydrogen fluoride.

Removing the surface oxide layer may comprise using a dry etch.

The method may comprise loading or transferring the layer of silicon, germanium or silicon-germanium alloy (which may be supported on a substrate) into a deposition system after removing the surface oxide layer and before the surface oxide re-grows. The method may comprise loading or transferring the layer of silicon, germanium or silicon-germanium alloy into a deposition system after removing the surface oxide layer within 15 minutes or within 10 minutes. Heating the layer of silicon, germanium or silicon-germanium alloy may comprise heating the layer at a pressure no more than icr⁶ mbar (lcr^ Pa) or no more than icr⁸ mbar (io^~6Pa). Heating the layer of silicon, germanium or silicon-germanium alloy may comprise heating the layer to at least 600 °C or at least 650 °C.

The superconductor may be aluminium. The superconductor may be selected from the group consisting of indium, molybdenum, niobium, tin, tantalum, titanium, vanadium and zinc. The layer of silicon, germanium or silicon-germanium alloy may be degenerately doped. The layer may be doped n-type. The layer may be doped with phosphorus (P), arsenic (As) or antinomy (Sb). The layer may be doped p-type. The layer may be doped to a concentration of at least ixio¹⁹crrr3. The layer maybe doped with a delta- doped layer. The layer of silicon, germanium or silicon-germanium alloy may be strained.

The layer of silicon, germanium or silicon-germanium alloy may be a layer of silicon.

According to a second aspect of the present invention there is provided a

superconductor-insulator-semiconductor tunnel junction formed by the method.

According to a third aspect of the present invention there is provided a method of fabricating a device comprising the method of forming the superconductor-insulator- semiconductor tunnel junction.

According to a fourth aspect of the present invention there is provided a device formed by the method.

According to a fifth aspect of the present invention there is provided a superconductor- insulator-semiconductor junction wherein the semiconductor comprises silicon, germanium or silicon-germanium alloy and the insulator comprises a layer of dielectric material. The tunnel junction exhibits a tunnel resistance which is less than 50 Ι^Ωμπι² at a temperature which is at, or below, the transition temperature of the

superconductor. The tunnel junction may exhibit a tunnel resistance which is nor more than 20 Ι^Ωμπι² or no more than 10 1<Ωμιη² at a temperature which is at, or below, the transition temperature of the superconductor. A ratio of the density of states broadening factor for the junction without the dielectric layer and a broadening factor for the tunnel junction may be more than 10, or more than 100, or more than 1000 at a temperature which is at, or below, half of the transition temperature of the superconductor. A broadening factor for the tunnel junction may be no more than ixio-3 at a

temperature which is at, or below, half of the transition temperature of the

superconductor.

According to a sixth aspect of the present invention there is provided a superconductor- insulator-semiconductor tunnel junction wherein the semiconductor comprises silicon, germanium or silicon-germanium alloy and the insulator comprises a layer of dielectric material. A ratio of a broadening factor for a tunnel junction without the dielectric layer and a broadening factor for the tunnel junction is more than 10, or more than 100, or more than 1000 at a temperature which is at, or below, half of the transition temperature of the superconductor.

A broadening factor for the tunnel junction may be no more than lxio^-3 at a

temperature which is at, or below, half of the transition temperature of the

superconductor.

The dielectric material is or may comprise an oxide of silicon and/or an oxide of germanium. The dielectric material is or may comprise an oxide and/or nitride of the superconductor. The dielectric material is or may comprise a nitride of silicon and/ or a nitride of germanium. The dielectric material is or may comprise a nitride of the superconductor. The dielectric material is or may comprise an oxynitride of silicon or an oxynitride of germanium. The dielectric material is or may comprise an oxynitride of the superconductor.

The superconductor may be aluminium. The superconductor may be selected from the group consisting of indium, molybdenum, niobium, tin, tantalum, titanium, vanadium and zinc. The superconductor may be an elemental superconductor. The

superconductor may be an alloy of elemental superconductors.

The dielectric layer may have a thickness no more than 5 nm, no more than 3 nm or no more than 2 nm.

According to a seventh aspect of the present invention there is provided a device comprising at least one tunnel junction. The device may comprise two tunnel junctions arranged as superconductor-insulator- semiconductor-insulator-superconductor.

The device may be a bolometer or a thermometer. According to an eighth aspect of the present invention there is provided an

astronomical detection system comprising a tunnel junction or a device.

According to a ninth aspect of the present invention there is provided a biomedical imaging or detection system comprising a tunnel junction or a device.

According to an tenth aspect of the present invention there is provided a security screening comprising a tunnel junction or a device.

According to an eleventh aspect of the present invention there is provided a remote sensing system comprising a tunnel junction or a device.

According to a twelfth aspect of the present invention there is provided a quantum information processing comprising a tunnel junction or a device. Brief Description of the Drawings

Certain embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:

Figure 1 is an energy band diagram of a double junction superconductor- semiconductor-superconductor cooler;

Figure 2 is a plot of density of states against energy for a superconductor- semiconductor junction;

Figure 3 is a side view of superconductor-insulator-semiconductor junction;

Figure 4 is a schematic block diagram of apparatus for forming the superconductor- insulator-semiconductor junction shown in Figure 3;

Figure 5 is process flow diagram of a method of forming the superconductor-insulator- semiconductor junction shown in Figure 3;

Figures 6a to 6e illustrate the superconductor-insulator-semiconductor junction at different stages during formation;

Figure 7 shows plots of density of states broadening factor, Γ, against temperature for a semiconductor-superconductor junction and the junction shown in Figure 3;

Figure 8 shows a plot of current against bias for the junction shown in Figure 3; and Figure 9 shows a plot of conductance against bias for the junction shown in Figure 3. Detailed Description of Certain Embodiments

Referring to Figure 1, an energy diagram of a double junction superconductor- semiconductor-superconductor (S-Sm-S) cooler is shown which may be helpful for understanding the present invention. The cooler comprises a first superconductor in direct contact with a semiconductor resulting in a first Schottky barrier formed in the semiconductor at the interface with the first superconductor due to bending of the conduction band (CB) edge. The semiconductor is in direct contact with a second superconductor resulting in a second Schottky barrier at the interface with the second superconductor.

A potential, V, applied between the superconductors is divided equally between the two junctions, which have equal tunnel resistance, RT-

As shown in Figure 1, electric current, I, flows from the first superconductor to the second superconductor, i.e. left to right. Hot electrons tunnel out of the semiconductor through the first (i.e. left-hand) junction and are replaced by cold electrons which enter the semiconductor through the second (i.e. right-hand) junction. The current, /, is given by equation 1 below:

'= F [f(E -eV/2,T ) - f(E + eV/2,T )] g(E, T)dE. (1)

2eR_T ^J-^∞ where e is electron charge (1.6 x lcr¹⁹ C), i?ris the normal state tunnelling resistance, f(E, T) is the Fermi-Dirac distribution function of electrons ( , T) = i/[i+exp(E/k_BT)] and T_E is the electron temperature in the semiconductor. I B is the Boltzmann constant (1.381 x io ²3 JK ¹) Reference is made to J. T. Muhonen et al.: "Micrometre-scale refrigerators", Reports on Progress in Physics, volume 75, page 046501 (2012), which is incorporated herein by reference.

The term g{E, Γ) is the density of states within the superconductor and is given by equation 2 below:

where E is energy of a state, Γ is the density of states broadening factor and Δ is half the superconducting energy gap, 2Δ. Reference is made to R. C. Dynes et ah: "Tunneling study of superconductivity near the metal-insulator transition", Physical Review Letters, volume 53, page 2437 (1984) and J. P. Pekola et ah: "Limitations in Cooling Electrons using Normal-Metal-Superconductor Tunnel Junctions", Physical Review Letters, volume 92, page 056804-1 (2012), which are incorporated herein by reference.

Equation 2 above helps explain the problem of sub-gap leakage.

Referring to Figure 2, a plot of density of states g{E, Γ) against energy for different values of broadening factor (or "smoothing factor") is shown Figure 2 shows that, as the Γ parameter is increased, the sub-gap density of states is increased and this increases the sub-gap proportion of the total junction current, as given by equation ι. Γ can be used as a figure of merit for semiconductor- superconductor tunnel junctions. Γ may not explicitly refer to the density of states of the superconductor, but may also quantify some other process, such as, a parallel leakage current through the junction.

The present invention is based on the insight that introducing an insulator (i.e. a dielectric layer) between a semiconductor and a superconductor reduces the Γ parameter by about two orders of magnitude in a semiconductor-superconductor junction. This helps to reduce the sub-gap leakage significantly thereby increasing, in the case of a cooler, the cooling efficiency of the junctions, and, in the case of a thermometer, sensitivity of the thermometer. Referring to Figure 3, a semiconductor-insulator-superconductor junction 1 is shown which comprises a semiconductor 2, preferably silicon (Si), germanium (Ge) or silicon- germanium (Sii-xGex), a thin dielectric layer 3 in direct contact with the semiconductor 2 and a superconductor 4, such as aluminium (Al), in direct contact with the dielectric layer 3.

Integration of a thin insulating layer into the junction stack reduces the sub-gap leakage of the junction by at least an order of magnitude.

Referring also to Figure 4, the junction 1 is formed using an in-situ low-temperature, low-pressure oxidation process which is used to oxidise the surface of the

semiconductor prior to depositing aluminium (as the superconductor) in an ultra-high vacuum sputter system 5. It is found that oxidation using a conventional silicon processing furnace or oxidation carried out at room temperature and low pressure does not reduce the sub-gap leakage.

Referring in particular to Figure 4, the vacuum sputter system 5 includes an exchange chamber 6 (or "load lock"), a first chamber 7 and a second chamber 8 separated by valves 9, 10, 11. The exchange chamber 6 is evacuated using a turbo molecular pump 12 backed by a rotary pump (not shown). The first chamber 7 houses a heater 13. A source 14 of pure, dry oxygen is connected to the first chamber 7 via a needle valve 15. The first chamber 7 is selectably evacuated using either a turbo molecular pump 16 backed by a rotary pump (not shown) or a rotary pump 17.

In this case, a d.c. sputtering system is used. However, other forms of sputtering, e.g. r.f. sputtering or ion-beam sputtering, can be used. The second chamber 8 houses a sputter target 18 (i.e. a source of superconducting material) which also serves as a cathode, an anode 19 and a power source 20 for applying biases to the cathode 18 and anode 19. An argon gas source 21 connected to the second chamber 8 via a needle valve 22. The second chamber 8 is evacuated using a turbo molecular pump 23 backed by a rotary pump (not shown).

As shown in Figure 4, a wafer (or "workpiece") 25 is processed in the first and second chambers 7, 8.

Referring to Figures 4, 5 and 6a to 6e, a method of forming semiconductor-insulator- superconductor junction(s) will now be described.

The process starts with a degenerately doped silicon wafer 2' having a native oxide 26, as shown in Figure 6a. The native oxide 26 removed by immersion in 1% hydrofluoric acid (HF) for 1 minute, followed by a rinse in deionised water and dry in nitrogen gas (step Si). The corresponding structure is shown in Figure 6b.

The stripped wafer 2' is placed in the load-lock 6 within 10 minutes of performing the oxide strip and is transferred to the first chamber 7 (step S2).

The pressure in the first chamber 7 is reduced to first pressure Pi, about lcr⁸ mbar (lcr⁶ Pa) (step S3), then the temperature is ramped to a first elevated temperature T_1; 550 °C (step S4). The temperature and pressure are held for a period of time ti, 10 minutes (step S5). The temperature may be ramped up or down to a different temperature, T₂, for oxidation (step S6). In this case, the temperature is maintained, i.e. T₂=Ti.

Chamber pumping is reduced via a high impedance line to the rotary vacuum pump 17 (step S7). Pure oxygen gas is admitted into the chamber 7 via a needle valve 15 and the pressure increased to a pressure P₂, about 300 mbar (30,000 Pa) (step S8). A higher or lower oxidation pressure, P₂, may be used. For example, the pressure may be between 200 mbar (20,000 Pa) and 400 mbar (40,000 Pa). The pressure and temperature are maintained for a time t₂, about 15 minutes (step S9), then the oxygen needle valve was closed (step S10), the high impedance pumping stopped, (step S11) and the turbo pump 16 used to reduce the pressure back to Pi, i.e. around io^-8 mbar (io^-6 Pa) (step S12). As shown in Figures 6c and 6d, the process results in a surface region 27 of the silicon wafer 1' being oxidized to form a thin layer 28 of silicon dioxide (Si0₂).

Heating is stopped (step S13) and the chamber is allowed to cool to T₃, about 90 °C (step S14). This can take approximately 2 hours.

The workpiece 25, i.e. the wafer 1 having a thin oxide 28 is moved, without breaking vacuum, to the second chamber 8 (step S15).

Referring to Figure 6e, a layer 4 of aluminium is d.c. sputtered, initially using a low power (step S16 & S17).

The chamber is allowed to cool and the processed wafer is unloaded (step S18 & S19).

The dielectric layer 3 may comprise silicon dioxide. However, dielectric layer 3 may comprise aluminium oxide, i.e. resulting from a reaction between aluminium and silicon dioxide.

Referring to Figure 7, plots 31, 32 of density of states broadening factor, Γ, against temperature are shown. A first plot 31 shows the temperature variation of the broadening factor, Γ, for the tunnel junction 1 is formed using an in-situ low-temperature, low-pressure oxidation process. A second plot 32 shows the temperature variation of the broadening factor, Γ, for a comparative example which is prepared in the same way, but without the in-situ low-temperature, low-pressure oxidation process.

Referring to Figures 8 and 9, the broadening factor, Γ, is found by obtaining a current- voltage (I-V) plot 33 and differentiating to obtain a conductance (dl/dV) plot 34.

The broadening factor, Γ is found by dividing the value of the mid-gap conductance by the value of the normal state conductance.

As shown in Figure 7, the in-situ low-temperature, low-pressure oxidation process has the effect of reducing the broadening factor, Γ.

Table 1 below shows values of tunnel resistance, RT, and (where available) lowest electron temperature from a 300 mK bath for the tunnel junction structure.

Table 1

Comparative example 1 is a semiconductor-superconductor junction which is formed using a layer of unstrained silicon by stripping the native oxide and depositing aluminium directly on the silicon surface, i.e. without a silicon dioxide layer.

Comparative example 2 is a semiconductor-superconductor junction which is the same as comparative example 1, but strained silicon is used instead of unstrained silicon

Comparative example 3 is a semiconductor-insulator-superconductor junction which is formed using a layer of strained silicon by stripping the native oxide, forming a layer of silicon dioxide on the silicon by dry oxidation in a furnace at atmospheric pressure and at 700 °C for 5 minutes and then loading the sample into the deposition system 5 (Figure 4) and depositing aluminium on the furnace-grown silicon dioxide layer. Table 1 shows that junction 1, using the same material as comparative example 2 and an in-situ low-temperature, low-pressure oxidation process either reduces or at least does not increase tunnel resistance, while providing improved cooling power. When compared to comparative example 1, it should be noted that the electron-phonon conductance is much higher in that sample (which uses unstrained silicon) which can explain the high cooling power, but smaller change in temperature.

Table 1 also shows that junction 1 exhibits improved cooling (namely from 300 mK to 90 mK). When comparing tunnel resistances and cooling powers in Table 1, it can be seen that tunnel resistance is reduced from 100 kD. to 42 kD. using an in-situ low-temperature, low-pressure oxidation process. This alone implies an improvement in the cooling power by a factor of about 2.4. However, an improvement by a factor of 3.7 at 300 mK is observed. This is because of the improved gamma factor of the junction. Also, lower gamma gives a slower decrease in cooling power as electron temperature is reduced.

The process maybe explained as follows:

The hydrofluoric acid step removes the native oxide 26 and terminates the surface silicon atoms with hydrogen (not shown). Once loaded into the high vacuum chamber, the temperature is ramped to 550 °C with the aim of driving off the hydrogen terminations. A higher temperature, for example 600 °C, 650 °C or more, can be used. This leaves a highly-reactive surface and so an oxide quickly forms when oxygen is introduced into the chamber 8. It is believed that oxidation quickly self-limits and stops after a given period of time, i.e. a few minutes. The resulting silicon dioxide layer 28 has a thickness of no more than a few nanometres. Although the silicon dioxide layer 28 is expected to be stable, it is possible that the aluminium reacts to form aluminium dioxide. Regardless, a thin dielectric layer 3 is formed which is responsible for the superior performance the junction 1. The resistance of the junction 1 can be quite low, i.e. about 1 1<Ωμιη². Therefore, it is believed that oxidation of silicon pushes back dopants (i.e. away from the surface) forming a local high dopant concentration and this helps to reduce the tunnel barrier width.

Alternatively or additionally, there might be some de-pinning of the Fermi level at the interface which reduces the height of the tunnel barrier.

Alternatively or additionally, oxidation may occur more strongly at or around the sites of the dopants on and/ or close to the semiconductor surface. These sites can be the origin of the sub-gap leakage and so oxidation may result in deactivation of the sites locally. A continuous thin oxide maybe formed and the n-type dopant atoms at the surface are pushed into the silicon and/or deactivated inside the oxide. It is energetically more favourable for n-type dopants, such as arsenic and phosphorous P, to be in silicon than in silicon dioxide. This can result in an extremely highly doped, thin region next to the silicon dioxide-silicon interface.

Alternatively or additionally, the oxide layer formed between the semiconductor and the superconductor is believed to reduce proximity effects associated with a

degenerately-doped semiconductor. A proximity effect is observed when a thin layer of normal metal, in close contact with a superconductor, becomes superconducting. Conversely, a superconductor can be turned normal (this is referred to as the "the inverse proximity effect"). In the case of superconductor-semiconductor junction, there maybe a proximity effect between a degenerately-doped semiconductor and the superconductor, wherein states appear in the superconductor bandgap. Thus, it is believed that the formation of the oxide layer may result in a reduction of the proximity effect, thereby improving the superconductor density of states.

Although a process based on silicon, oxidation and aluminium has been described, the process can be varied as follows:

Aluminium need not be used as a superconductor. Instead, another elemental superconductor such as indium (In), molybdenum (Mo), niobium (Nb), tin (Sn), tanatalum (Ta), titanium (Ti), vanadium (V), zinc (Zn) or other low-temperature superconductor. Thus, the dielectric layer 3 may comprise an oxide of the elemental superconductor. Additionally or alternatively, oxidation need not be used. Nitridation or a mixture of oxidation and nitridation (or other sacrificial-based reaction of the semiconductor) may be used. Thus, the dielectric layer 3 may comprise silicon nitride or silicon oxynitride and/ or a nitride or oxynitride of aluminium or other elemental superconductor.

Silicon need not be used. Instead, the semiconductor may be germanium (Ge). Thus, the dielectric layer 3 may comprise germanium oxide, germanium nitride, germanium oxynitride. The semiconductor may be silicon-germanium (SiGe).

The semiconductor need not be in the form of a wafer, but may be a layer, for example, an epitaxial layer. The layer may form part of homostructure or a heterostructure, for example, a layer of silicon or germanium formed on a layer of silicon-germanium. The semiconductor may be formed in a structure which includes a buried oxide, for example silicon-on-insulator.

The semiconductor need not be n-type. Instead, it can be p-type. The semiconductor need not be unstrained, but can be strained, for example, using process-induced strain or by virtue of a heterostructure which includes a layer of a different semiconductor having a different lattice constant and/or crystal structure.

A device, such as a cooler or thermometer, may include two or more junctions, for example, such as a superconductor-insulator-semiconductor-insulator-superconductor structure.

Claims

1. A method of forming a superconductor-insulator-semiconductor tunnel junction, the method comprising:

removing a surface oxide layer from a surface of a layer of silicon, germanium or silicon-germanium alloy;

heating the layer of silicon, germanium or silicon-germanium alloy to at least 550 °C in a vacuum;

forming a dielectric layer on the surface of the layer of silicon, germanium or silicon-germanium alloy; and

depositing a superconductor on the dielectric layer.

2. A method according to claim 1, wherein forming the dielectric layer comprises exposing the surface of the layer of silicon, germanium or silicon-germanium alloy to one or more chemical species.

3. A method according to claim 1 or 2, wherein forming the dielectric layer comprises exposing the surface of the layer of silicon, germanium or silicon-germanium alloy to a gas.

4. A method according to any preceding claim, wherein forming the dielectric layer comprises exposing the surface of the layer of silicon, germanium or silicon-germanium alloy to a mixture of gases or to a sequence of gases and/or gas mixtures.

5. A method according to any preceding claim, wherein forming the dielectric layer comprises exposing the surface of the layer of silicon, germanium or silicon-germanium alloy to oxygen.

6. A method according to any preceding claim, wherein forming the dielectric layer comprises exposing the surface of the layer of silicon, germanium or silicon-germanium alloy to nitrogen.

7. A method according to any one of claims 2 to 6, comprising exposing the surface for a time of at least 1 minute, at least 2 minutes, at least 5 minutes or at least 10 minutes.

8. A method according to any one of claims 2 to 7, comprising exposing the surface for a time no more than 2 hours, no more than 1 hour or no more than 0.5 hours

9. A method according to any preceding claim, wherein forming the dielectric layer is carried out at a pressure below atmospheric pressure.

10. A method according to any preceding claim, wherein forming the dielectric layer is carried out at a pressure between 200 mbar (20,000 Pa) and 400 mbar (40,000 Pa).

11. A method according to any preceding claim, wherein forming the dielectric layer is carried out at a temperature above room temperature.

12. A method according to any preceding claim, wherein forming the dielectric layer is carried out at a temperature at or above 500 °C.

13. A method according to any preceding claim, wherein at least a portion of the dielectric layer and a portion of the superconductor react to form another dielectric material.

14. A method according to any preceding claim, wherein removing the surface oxide layer comprises using a wet etch.

15. A method according to any preceding claim, wherein removing the surface oxide layer comprises using hydrogen fluoride.

16. A method according to any preceding, comprising loading or transferring the layer of silicon, germanium or silicon-germanium alloy into a deposition system after removing the surface oxide layer and before the surface oxide re-grows.

17. A method according to any preceding claim, wherein heating the layer of silicon, germanium or silicon-germanium alloy comprises heating the layer at a pressure no more than io^~6 mbar (io^~4 Pa).

18. A method according to any preceding claim, wherein heating the layer of silicon, germanium or silicon-germanium alloy comprises heating the layer at a pressure no more than io^-8 mbar (io^-6 Pa).

19. A method according to any preceding claim, wherein heating the layer of silicon, germanium or silicon-germanium alloy comprises heating the layer to at least 600 °C or at least 650 °C.

20. A method according to any one of claims 1 to 19, wherein the superconductor comprises aluminium.

21. A method according to any one of claims 1 to 19, wherein the superconductor is selected from the group consisting of indium, molybdenum, niobium, tin, tantalum, titanium, vanadium and zinc.

22. A method according to any preceding claim, wherein the layer of silicon, germanium or silicon-germanium alloy is degenerately doped.

23. A method according to any preceding claim, wherein the layer of silicon, germanium or silicon-germanium alloy is strained.

24. A method of fabricating a device comprising a method of forming a

superconductor-insulator-semiconductor tunnel junction according to any preceding claim.

25. A method according to any preceding claim, wherein the layer of silicon, germanium or silicon-germanium alloy is a layer of silicon.

26. A tunnel junction formed by a method according to any one of claims 1 to 25.

27. A device formed by a method according to claim 26.

28. A superconductor-insulator-semiconductor tunnel junction wherein the semiconductor comprises silicon, germanium or silicon-germanium alloy and the insulator comprises a layer of dielectric material, wherein the tunnel junction exhibits a tunnel resistance less than 50 1<Ωμιη² at a temperature which is at, or below, the transition temperature of the superconductor.

29. A tunnel junction according to claim 28, which exhibits a tunnel resistance no more than 10 Ι^Ωμπι² at a temperature which is at or below the transition temperature of the superconductor.

30. A tunnel junction according to claim 28 or 29, wherein a ratio of broadening factor for a tunnel junction without the dielectric layer and a broadening factor for the tunnel junction is more than 10, or more than 100, or more than 1000 at a temperature which is at, or below, half of the transition temperature of the superconductor.

31. A tunnel junction according to claim 28, 29 or 30,wherein a broadening factor for the tunnel junction is no more than lxio^-3 at a temperature which is at, or below, half of the transition temperature of the superconductor.

32. A superconductor-insulator-semiconductor tunnel junction wherein the semiconductor comprises silicon, germanium or silicon-germanium alloy and the insulator comprises a layer of dielectric material, wherein a ratio of a broadening factor for a tunnel junction without the dielectric layer and a broadening factor for the tunnel junction is more than 10, or more than 100, or more than 1000 at a temperature which is at, or below, half of the transition temperature of the superconductor.

33. A tunnel junction according to claim 32, a broadening factor for the tunnel junction is no more than lxio^-3 at a temperature which is at, or below, half of the transition temperature of the superconductor.

34. A tunnel junction according to any one of claims 28 to 33, wherein the dielectric material is or comprises an oxide of silicon and/ or an oxide of germanium.

35. A tunnel junction according to any one of claims 28 to 34, wherein the dielectric material is or comprises an oxide the superconductor.

36. A tunnel junction according to any one of claims 28 to 35, wherein the dielectric material is or comprises a nitride of silicon and/ or a nitride of germanium.

37· A tunnel junction according to any one of claims 28 to 36, wherein the dielectric material is or comprises a nitride of the superconductor.

38. A tunnel junction according to any one of claims 28 to 37, wherein the dielectric material is or comprises an oxynitride of silicon and/ or an oxynitride germanium.

39. A tunnel junction according to any one of claims 28 to 38, wherein the dielectric material is or comprises an oxynitride of the superconductor.

40. A tunnel junction according to any one of claims 28 to 39, wherein the superconductor is or comprises aluminium.

41. A tunnel junction according to any one of claims 28 to 39, wherein the superconductor is an elemental superconductor, such as indium, molybdenum, niobium, tin, tantalum, titanium, vanadium or zinc.

42. A tunnel junction according to any one of claims 28 to 41, wherein the dielectric layer has a thickness no more than 5 nm.

43. A tunnel junction according to any one of claims 28 to 42, wherein the dielectric layer has a thickness no more than 3 nm.

44. A tunnel junction according to any one of claims 28 to 43, wherein the dielectric layer has a thickness no more than 2 nm.

45. A device comprising at least one tunnel junction according to any one of claims 28 to 44.

46. A device according to claim 45 comprising two tunnel junctions according to any preceding claim arranged as superconductor-insulator-semiconductor-insulator- superconductor.

47. A device according to claim 45 or 46, which is a bolometer.

48. A device according to claim 45 or 46, which is a thermometer.

49. An astronomical detection and imaging system comprising one or more tunnel junctions according to claim 26 or any one of claims 28 to 44 or a device according to claim 27 or any one of claims 45 to 48.

50. A biomedical imaging or detection system comprising one or more tunnel junctions according to claim 26 or any one of claims 28 to 44 or a device according to claim 27 or any one of claims 45 to 48.

51. A security screening system comprising one or more tunnel junctions according to claim 26 or any one of claims 28 to 44 or a device according to claim 27 or any one of claims 45 to 48.

52. A remote sensing system comprising one or more tunnel junctions according to claim 26 or any one of claims 28 to 44 or a device according to claim 27 or any one of claims 45 to 48.

53. A quantum information processing system comprising one or more tunnel junctions according to claim 26 or any one of claims 28 to 44 or a device according to claim 27 or any one of claims 45 to 48.