WO2015056021A1 - Simulation multiprocesseur sur une machine multicœur - Google Patents

Simulation multiprocesseur sur une machine multicœur Download PDF

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Publication number
WO2015056021A1
WO2015056021A1 PCT/GB2014/053113 GB2014053113W WO2015056021A1 WO 2015056021 A1 WO2015056021 A1 WO 2015056021A1 GB 2014053113 W GB2014053113 W GB 2014053113W WO 2015056021 A1 WO2015056021 A1 WO 2015056021A1
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Prior art keywords
processor
timeslice
processors
simulated
cores
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PCT/GB2014/053113
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English (en)
Inventor
James Kenney
Original Assignee
Imperas Software Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imperas Software Ltd filed Critical Imperas Software Ltd
Priority to US15/030,216 priority Critical patent/US11574087B2/en
Publication of WO2015056021A1 publication Critical patent/WO2015056021A1/fr
Priority to US18/105,554 priority patent/US20230185991A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/522—Barrier synchronisation

Definitions

  • the field of the invention relates to methods of simulation of a plurality of processors running on a plurality of cores, to multi-core microprocessor systems in which such methods may be carried out, and to computer program products operable to perform a simulation of a plurality of processors, runnable on a plurality of cores.
  • a multi-core processor is a single computing component with two or more independent (or mostly independent) actual central processing units (CPUs) (called “cores"), which are the units that read and execute program instructions.
  • CPUs central processing units
  • the instructions may be ordinary CPU instructions such as add, move data, and branch, but the multiple cores can run multiple instructions at the same time, increasing overall speed for programs amenable to parallel computing.
  • CN102591759(A) and CN102591759(B) disclose, in their own terminology, a clock precision parallel simulation system for an on-chip multi-core processor, which comprises a processor subsystem, a storage subsystem and a simulation object subsystem.
  • the system is characterized in that a module interlayer is arranged between the processor subsystem and the simulation object subsystem in the system and used for implementation of mapping from a logic processor to a simulation object machine, the module interlayer comprises a core module, a mapping interconnection network, a share cache memory, a memory and storage modules for other simulation object structures, wherein the core module is in one-to-one correspondence to a processor core and a private primary cache memory.
  • Point-to-point synchronization is realized between the core module and the storage modules, and group synchronization is realized among the storage modules.
  • the system has higher degree of parallelism and higher speed-up ratio, and performance of the system is promoted under the condition that delicate modeling of each component of the multi-core processor is maintained.
  • a method of running a plurality of simulated processors on a plurality of cores in which simulation of the processors is performed in parallel on the plurality of cores.
  • An advantageous technical effect is that parallel processing is provided for a plurality of simulated processors.
  • the technical effect operates at the level of the architecture of the computer component implementing the method; the technical effect is produced irrespective of the data being processed or the applications being run.
  • a computer implementing the first aspect of the invention operates in a new way.
  • the method may be one applying to a timeslice of the plurality of simulated processors runnable on the plurality of cores, the method including the steps of:
  • step (iv) returning to step (ii) unless the plurality of processors have all been simulated in this timeslice.
  • the method may be one wherein the number of the plurality of simulated processors exceeds the number of the plurality of cores.
  • the method may be one wherein the number of the plurality of simulated processors does not exceed the number of the plurality of cores.
  • the method may be one in which the method is repeated for a set of consecutive timeslices.
  • the method may be one further including a method of ensuring correct synchronization of a plurality of simulated processors, the plurality of simulated processors running on a plurality of cores, the method applying to a timeslice of the plurality of simulated processors running on the plurality of cores, including:
  • An advantageous technical effect is that data structure consistency is supported, which strongly reduces the occurrences of crashes, or use of erroneous data, by a computer implementing this aspect of the invention.
  • the technical effect operates at the level of the architecture of the computer component; the technical effect is produced irrespective of the data being processed or the applications being run.
  • the computer implementing this aspect of the invention operates in a new way.
  • the computer is a better computer in the sense of running more efficiently and effectively as a computer.
  • the method may be one including the steps of:
  • step (v) returning to step (ii) unless the plurality of processors have all been simulated in this timeslice.
  • the method may be one further including a method of completing a timeslice of a simulation of a plurality of processors running on a plurality of cores, in which a plurality of processors have been suspended, including:
  • An advantageous technical effect is that data structure consistency is supported, which strongly reduces the occurrences of crashes, or use of erroneous data, by a computer implementing this aspect of the invention.
  • the technical effect operates at the level of the architecture of a computer or of a computer component; the technical effect is produced irrespective of the data being processed or the applications being run.
  • the computer implementing this aspect of the invention operates in a new way.
  • the computer is a better computer in the sense of running more efficiently and effectively as a computer.
  • the method may be one including the steps of:
  • step (iv) if a synch event is found, suspending the process, saving the simulation state and time, adding the processor back to the list of remaining suspended processors and returning to step (i);
  • step (iii) is performed on the same core, to ensure data structure consistency.
  • the method may be one further including a method of timeslicing instruction sets for a plurality of processors to be simulated using a plurality of cores, including the steps of:
  • step (iii) for each simulated processor, estimating how many instructions will be run in the time period, using the results of step (ii);
  • An advantageous technical effect is that different processors can be simulated using a plurality of cores, because for each processor model, a record is consulted of its timing information. This means that a greater set of simulations are possible, because the simulation is not limited to a single model of processor.
  • the technical effect operates at the level of the architecture of the computer; the technical effect is produced irrespective of the data being processed or the applications being run. Furthermore, the computer implementing this aspect of the invention operates in a new way.
  • the method may be one further including the step of:
  • the method may be one wherein a time period is user-defined.
  • the method may be one wherein a time period is pre-defined.
  • the method may be one wherein a single core runs a single processor's instruction list at any one time.
  • a multi-core microprocessor system including a plurality of execution units which can run concurrently, the system configured to run a plurality of simulated processors on a plurality of cores, in which simulation of the processors is performable in parallel on the plurality of cores.
  • the multi-core microprocessor system may be configured to complete a timeslice of a simulation of a plurality of processors running on a plurality of cores, configured to:
  • the multi-core microprocessor system may be one wherein the number of the plurality of simulated processors exceeds the number of the plurality of cores.
  • the multi-core microprocessor system may be one wherein the number of the plurality of simulated processors does not exceed the number of the plurality of cores.
  • the multi-core microprocessor system may be one configured to repeat for a set of consecutive timeslices.
  • the multi-core microprocessor system may be one configured to ensure correct synchronization of a plurality of simulated processors, the plurality of simulated processors running on a plurality of cores, the system configured to run a timeslice of the plurality of simulated processors running on the plurality of cores, the system configured to:
  • the multi-core microprocessor system may be one configured to:
  • the multi-core microprocessor system may be one configured to complete a timeslice of a simulation of a plurality of processors running on a plurality of cores, in which a plurality of processors have been suspended, the system configured to:
  • the multi-core microprocessor system may be one configured to:
  • item (iii) is performed on the same core, to ensure data structure consistency.
  • the multi-core microprocessor system may be one further configured to timeslice instruction sets for a plurality of processors to be simulated using a plurality of cores, the system configured to:
  • the multi-core microprocessor system may be further configured to:
  • the multi-core microprocessor system may be one wherein a time period is user-defined.
  • the multi-core microprocessor system may be one wherein a time period is pre-defined.
  • the multi-core microprocessor system may be one wherein a single core runs a single processor's instruction list at any one time.
  • a computer program product operable to run a plurality of simulated processors on a plurality of cores, in which simulation of the processors is performed in parallel on the plurality of cores.
  • the computer program product may be operable to complete a timeslice of a simulation of the plurality of simulated processors runnable on the plurality of cores, the computer program product operable to:
  • the computer program product may be one wherein the number of the plurality of simulated processors exceeds the number of the plurality of cores.
  • the computer program product may be one wherein the number of the plurality of simulated processors does not exceed the number of the plurality of cores.
  • the computer program product may be one in which the program is executable for a set of consecutive timeslices.
  • the computer program product may be one further operable to ensure correct synchronization of a plurality of simulated processors, the plurality of simulated processors runnable on a plurality of cores, the computer program product operable to apply to a timeslice of the plurality of simulated processors running on the plurality of cores, the computer program product operable to:
  • the computer program product may be one further operable to:
  • the computer program product may be one further operable to complete a timeslice of a simulation of a plurality of processors running on a plurality of cores, in which a plurality of processors have been suspended, operable to:
  • the computer program product may be one operable to:
  • the computer program product may be one further operable to timeslice instruction sets for a plurality of processors to be simulated using a plurality of cores, operable to:
  • the computer program product may be one further operable to:
  • the computer program product may be one wherein a time period is user-defined.
  • the computer program product may be one wherein a time period is pre-defined.
  • the computer program product may be one wherein a single core runs a single processor's instruction list at any one time.
  • a computer including a multi-core microprocessor system of any aspect of the second aspect of the invention.
  • Figure 1 shows a schematic example of instruction sets for each of n Processors (PI— Pn).
  • Figure 2 shows a schematic example in which instruction sets are split into timeslices which represent different numbers of instructions per processor.
  • Figure 3 shows an example of a simple algorithm for the allocation of simulated processors to the available cores to run for a given timeslice.
  • Figure 4 shows an example of a modified algorithm to deal with synchronisation of processors.
  • Figure 5 shows an example of running a sweep pass for suspended processors.
  • Each of the processors included in the simulation has an instruction set associated with it. See Figure 1 for example.
  • the instruction set is split into a number of time periods or "timeslices". Each timeslice represents a different number of instructions for each processor. See Figure 2 for example.
  • a timeslice period can be either user defined or set by the system.
  • each simulated processor's instruction list is run on one of the cores available within the machine or machines on which the simulation is to be run.
  • a single core runs a single processor's instruction list at any one time.
  • the instruction list is allocated to one of the cores available 310. If the number of available cores is greater than the number of simulated processors then all the simulated processors will be run concurrently, with each instruction set being run as an independent process, each on a different core. If, as is more likely, the number of simulated processors exceeds the number of cores available then an alternative technique needs to be employed. In this case, if there are M cores and N simulated processors, the first M processors will be run through the first timeslice. Each of the simulated processors is run in a process on a separate core in the machine.
  • each processor can run independently until the end of the timeslice. As each of the simulated processors reaches the end of the set of instructions allocated to it for that timeslice, it is marked as complete and the state of the simulated processor is saved 320. Once this process is complete, a new set of instructions for the same timeslice but for a different simulated processor is allocated to that core. This continues until all of the simulated processors' instruction sets have been run 330. If a particular core reaches the end of the instruction set for a given timeslice and there are no further processor instructions sets to be simulated for that timeslice, then the core process sleeps until all the other active cores have completed the instruction sets for that timeslice. When all instruction sets for a given timeslice have been completed, the simulation will repeat the process for the next timeslice 340.
  • a simulated processor may need to communicate with another by writing to a communication channel, an example of which could be a shared memory or a FIFO (First In, First Out). In this case, the order in which the data is read and written needs to be managed carefully to ensure that the correct data is read. It is also possible that one or more of the simulated processors may need to perform some input or output to the overall system or a simulated processor may also need to update critical simulator structures such as the allocation, or reallocation, of memory. In each of these cases, and any other cases requiring synchronisation, an additional step must be followed to ensure that all simulated processors are correctly synchronised with the rest of the system. See Figure 4 for example.
  • the initial steps for a timeslice containing a synchronisation event are identical to those without such an event.
  • First the instruction list for each processor is determined for the timeslice 400.
  • processors which have not been simulated in this timeslice are allocated to run on any available cores 410. This runs either until completion of the instruction list for that processor within the given timeslice as before 430 or until a synchronisation event is encountered 440. If a synchronisation event is found within the instruction list for any given processor then that processor runs just to just before the synchronisation event and is suspended 440.
  • the simulation state and time at the point of suspension are recorded. This frees this core and, just as in the simple algorithm, it now checks to see if there are any further processors which need to be simulated. If there are, the next one is allocated to the core which has just completed the process with the synchronisation event; if not the core process sleeps.
  • This sweep pass is performed for each of the suspended processors in turn. See Figure 5 for example.
  • Each of these processors is run consecutively on a single core to ensure data structure consistency.
  • the suspended processors will still have instructions for the current timeslice to complete 500, as they have been suspended before reaching the end of the timeslice.
  • the simulation must verify whether there are suspended processors or not and run the sweep pass on each one until all have run to the list of instructions allocated for the timeslice 510.
  • the simulation time of each suspended processor was saved along with the simulation state as the processor was suspended.
  • the simulator will compare the saved simulation times 520, at which each processor was suspended, to find the one that has the earliest simulation time 530. This processor will be the one which had the first synchronisation event.
  • the processor will then be removed from the list of those which still need to be run. If the processor has a further synchronisation event then it will again suspend just prior to that synchronisation event 570, as it did in the initial run, and simulation time and state will be saved. The suspended processor will then be re -added to the list of those which need to complete a sweep pass with new simulation time and state data. This sequence will be repeated until all the simulated processors have completed the timeslice. Once all of the sweep passes have been completed, this is the end of the timeslice and simulation will move to the next timeslice 560 and begin the process again until all the timeslices complete, marking the end of the simulation.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
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Abstract

Le domaine de l'invention concerne des procédés de simulation d'une pluralité de processeurs fonctionnant sur une pluralité de cœurs, des systèmes de microprocesseur multicœur dans lesquels de tels procédés peuvent être réalisés, et des produits programme d'ordinateur configurés pour réaliser une simulation d'une pluralité de processeurs, fonctionnant sur une pluralité de cœurs. Selon un premier aspect, l'invention concerne un procédé de fonctionnement d'une pluralité de processeurs simulés sur une pluralité de cœurs, dans lequel la simulation des processeurs est réalisée en parallèle sur la pluralité de cœurs.
PCT/GB2014/053113 2013-10-18 2014-10-16 Simulation multiprocesseur sur une machine multicœur WO2015056021A1 (fr)

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US15/030,216 US11574087B2 (en) 2013-10-18 2014-10-16 Multi-processor simulation on a multi-core machine
US18/105,554 US20230185991A1 (en) 2013-10-18 2023-02-03 Multi-processor simulation on a multi-core machine

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US10038744B1 (en) * 2015-06-29 2018-07-31 EMC IP Holding Company LLC Intelligent core assignment
WO2024165828A1 (fr) 2023-02-07 2024-08-15 Imperas Software Ltd Procédés mis en œuvre par ordinateur de vérification de la conception d'un processeur étudié, et systèmes associés

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US11574087B2 (en) 2023-02-07
GB201318473D0 (en) 2013-12-04
GB2522098A (en) 2015-07-15
GB201418383D0 (en) 2014-12-03
US20160275220A1 (en) 2016-09-22
US20230185991A1 (en) 2023-06-15

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