WO2015051835A1 - An iterative decoder and method for improved error rate performance - Google Patents
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/45—Soft decoding, i.e. using symbol reliability information
- H03M13/451—Soft decoding, i.e. using symbol reliability information using a set of candidate code words, e.g. ordered statistics decoding [OSD]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
- H03M13/2978—Particular arrangement of the component decoders
- H03M13/2987—Particular arrangement of the component decoders using more component decoders than component codes, e.g. pipelined turbo iterations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/3707—Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
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Abstract
The present invention describes a decoder arrangement and method for decoding an iteratively decodable code such as a turbo code or an LDPC code. The invention comprises a first iterative decoder having channel reliability metrics as input and arranged to provide a first estimated codeword as output and to store intermediate reliability metrics, a reload and modify unit arranged to reload reliability metrics of a best candidate iteration and modify the reloaded reliability metrics, and a subsequent iterative decoder having modified reliability metrics as input and arranged to provide a subsequent estimated codeword as output.
Description
AN ITERATIVE DECODER AND METHOD FOR IMPROVED ERROR RATE PERFORMANCE
Technical field
The present invention relates to an iterative decoder and a method for improved error floor performance of iteratively decodable codes.
Background
Forward error correction (FEC) codes with iterative decoding, e.g. low density parity check (LDPC) and turbo codes, are used in a variety of different transmission systems, comprising optical transport applications, microwave radio links and mobile radio access networks, to provide reliable transmission over noisy transmission channels.
Fig. 1 illustrates the block diagram of a known digital communication system employing LDPC or turbo codes. On the transmitter side, an information message is first encoded by an LDPC or a turbo encoder. The purpose of the encoder is to add redundancy to the information sequence so that any errors introduced by the transmission channel can be corrected on the receiver side. For each information message, e.g. a bit sequence of a certain length, the encoder outputs a corresponding codeword. The codeword is mapped to a continuous waveform signal by the modulator and fed to a TX block, comprising radio-hardware for up-converting the waveform signal to a radio frequency (RF). The TX block is further connected to an antenna for transmitting the RF signal. On the receiver side, an antenna for receiving the RF signal is connected to an RX block, comprising radio-hardware for down-converting the received RF signal to baseband. The received baseband signal is demodulated and soft information, i.e. channel reliability metrics, is passed on to the decoder. Ideally, the decoder finds the codeword closest to the received sequence; however, for most codes of interest optimal decoding is an intractable problem. The iterative decoders of LDPC and turbo codes instead use a heuristic decoding approach based on the well-known sum-product algorithm. Figs. 2A and 2B show schematic block diagrams of known iterative decoders of turbo and LDPC codes, respectively. For a detailed description on how the sum-product algorithm relates to the BCJR units of the turbo decoder and the check nodes and variable nodes of the LDPC decoder we refer to the following reference: F.R. Kschisschang, B. Frey, and H-A Loeli- ger, "Factor Graphs and the Sum-Product Algorithm," IEEE Transactions on Information Theory, VOL. 47, NO. 2, Feb. 2001 .
Common for the different iterative decoding techniques is the idea of approaching the computationally intractable problem of maximum likelihood (ML) decoding by dealing with marginal probabilities and the computation of these in an iterative manner where the updated marginal probabilities depend only on the quantities computed at the previous step. While these techniques make the decoding problem tractable, the price to be paid is that the decoder now works with a local view of the code and therefore may arrive at a non-optimal solution. Decoding failures of the iterative decoder will normally fall into three main categories: 1 ) Convergence to a codeword which is not the transmitted one, i.e. identical to the failure mode of a ML decoder, 2) Oscillatory behavior of the bit error performance with increasing number of iterations, and 3) Error prone structures of the code that traps the iterative decoder into a metastable state which is a condition with a high number of failed bit errors and parity errors. The performance of LDPC and turbo codes is determined in terms of error rate, normally bit error rate (BER) or frame error rate (FER). Performance curves, showing the error rate versus signal-to-noise-ratio (SNR), are typically characterized, on the one hand, by the so-called waterfall region with a steep rate of improvement in the error rate with increasing SNR, and on the other hand, the error floor region with a much less pro- nounced rate of improvement with increasing SNR. The error floor is often due to peculiar error events which expose structural weaknesses of the code, when decoded with an iterative decoding algorithm.
Several techniques are known in the literature for countering these structural weakness- es. In the case of LDPC codes, one approach relies on analysis of the given code and aims at identifying the error-prone structure, either using exhaustive enumeration techniques or partial enumeration techniques in the case of moderate to long block length (greater than 1000 bits). The knowledge of the error prone structures of the code, identified in literature as trapping sets, stopping sets, absorbing sets, near codewords and a number of other denominations, is then exploited in the decoder. This can be achieved by suitable modifications of the decoding algorithm which takes into account the known error-prone structures. The drawback of this approach is that an exhaustive enumeration is an impossible proposition for moderate length codes, and that a partial identification of the error-prone structures will result in undetected errors that this method cannot correct.
Another approach for LDPC codes is based on the examination of the decoder state when a decoding failure is detected. In this approach the analysis of the error structure is
done a-posteriori in the decoder by observing the decoder input and its state when a failure is detected. Based on this info, the decoding algorithm is invoked in a second phase with modified inputs, whose selection is based on the observed error structure, possibly in conjunction to modifications to the decoding algorithm itself. There are two problems with this approach; the first one concerns the observation of error-prone structures in the event of decoding failure, since due to the chaotic behavior of the decoding process there is no guarantee that the observed patterns are actually the source of the decoder failures. The second problem concerns the idea of assigning to one or more variables a high reliability, since this would increase the probability of introducing decod- er errors if the choice of the variables is at fault.
The behavior of turbo codes at high SNR is mostly connected to the turbo code free distance and oscillatory behavior of the iterative decoder (i.e. the first two categories of decoding failure above). In practical implementations the error floor of turbo codes may al- so be affected by the maximum number of iterations, which is limited due to hardware complexity and throughput requirements.
However, the above methods do not provide sufficient mitigation to decoding failures for transmission systems operating under very strict performance requirements. For exam- pie, due to their error floors, turbo codes and LDPC codes may sometimes be left aside in favor of less powerful codes when BER requirements of 10~10 or less is required.
Hence, there is a need for an improved iterative decoder design that can handle and mitigate the performance degradation of the above-mentioned decoding failures. Summary
It is an object of the present invention to remedy, or at least alleviate, some of these drawbacks and to improve the performance of the decoding of LDPC and turbo codes. This is provided in a number of aspects of the present invention described below.
In a first aspect, the invention describes a decoder arrangement for improved decoding of an iteratively decodable code. The decoder arrangement comprises a first iterative decoder having channel reliability metrics as input and being arranged to store intermediate reliability metrics of at least one iteration in a memory and provide an estimated codeword to a control and output unit. The decoder arrangement also comprises a reload and modify unit arranged to reload best candidate reliability metrics from the stored intermediate reliability metrics and to modify the best candidate reliability metrics to ob-
tain modified reliability metrics. Moreover, the decoder arrangement comprises a subsequent iterative decoder having modified reliability metrics as input and arranged to provide a subsequent estimated codeword to a control and output unit. A control and output unit is having at least one estimated codeword as input and is arranged to output, when the at least one estimated codeword comprises a valid codeword, the information message associated with the valid codeword. The control and output unit may be further arranged to output, when the at least one estimated codeword comprises no valid codeword, the information message associated with one of the at least one estimated codeword or the information message associated with the best candidate reliability metrics.
In another aspect, the present invention describes a method in a decoder arrangement for decoding of iteratively decodable codes. The method comprises the step of decoding the iteratively decodable code, in which an iterative decoder is initiated by channel reliability metrics and arranged for storing intermediate reliability metrics of at least one itera- tion in a memory and providing a first estimated codeword. The method also comprises the step of checking if the first estimated codeword is a valid codeword. Moreover, the method comprises the steps of loading and modifying, when the first estimated codeword is not a valid code-word, the best candidate reliability metrics to obtain modified reliability metrics and subsequently decoding the iteratively decodable code, in which a subsequent iterative decoder is initiated by the modified reliability metrics and configured to provide a subsequent estimated codeword. The method also comprises the step of outputting the information message associated with the valid codeword when the first estimated codeword and the subsequent estimated codeword comprise a valid codeword. The step of outputting may further comprise outputting, when the at least one es- timated codeword comprises no valid codeword, the information message of one of the at least one estimated codewords or the information message associated with the best candidate reliability metrics.
The above decoder arrangement and method avoid repeated decoding failures and thus provides an improved error floor performance that will allow turbo and LDPC codes to be used in systems with more strict BER performance requirements.
Brief description of the drawings Fig. 1 shows schematically in a block diagram a conventional communication system employing LDPC/turbo encoding and iterative decoding,
Fig. 2A shows schematically in a block diagram a conventional iterative decoder of a turbo code,
Fig. 2B shows schematically in a block diagram a conventional iterative decoder of an LDPC code,
Fig. 3 shows schematically in a block diagram a first embodiment of the invention, Fig. 4 shows schematically in a block diagram a second embodiment of the invention, Fig. 5 shows schematically in a block diagram a third embodiment of the invention, Fig. 6 shows schematically in a flow chart a fourth embodiment of the invention, Fig. 7 shows schematically in a flow chart of a fifth embodiment of the invention, Fig. 8 shows schematically an exemplary hardware implementation of the present invention.
The drawings are not necessarily to scale and the dimensions of certain features may have been exaggerated for the sake of clarity, emphasis is instead being placed upon illustrating the principle of the embodiments herein.
Detailed description
In the following, five embodiments of the present invention are described in detail with reference to Figs. 3-8. A first, a second and a third embodiment of the present invention relate to a decoder arrangement 300, 400, 500 for improved decoding of an iteratively decodable code. A fourth and a fifth embodiment of the present invention relate to a method in a decoder arrangement 300, 400, 500 for decoding of an iteratively decodable code. It should be noted that the scope of the present invention is not limited to the par- ticular embodiments described herein, but only limited by the appended claims.
The first, the second and the third embodiment of the present invention relate to a decoder arrangement 300, 400, 500 for decoding iteratively decodable codes such as low density parity check (LDPC) and turbo codes. Common elements of the three embodi- ments of the decoder arrangement 300, 400, 500 are at least one iterative decoder
31 OA, 410, 51 OA, a reload and modify unit 330, 430, 530B and a control and output unit 320, 420, 520. The decoder arrangement 300, 400, 500 is having channel reliability metrics M1 as input, and provides an estimated codeword, or the information message associated with the estimated codeword, as output U1 . The channel reliability metrics M1 may be bit probabilities, log-likelihood ratios or any other type of reliability measure. Common for the three embodiments is the condition that the iterative decoder 31 OA, 410, 51 OA stores intermediate reliability metrics of the iterations in a memory 31 1 , 41 1 ,
51 1 or alternatively, stores intermediate reliability metrics of a best candidate iteration in a memory 31 1 , 41 1 , 51 1 . Here the intermediate reliability metrics refer to the reliability metrics of any iteration of the iterative decoding. Storing the intermediate reliability metrics of an iteration allows us to restore the iterative decoder to this iteration at a later 5 stage if desired. For example, if the intermediate reliability metrics of the iterative decoder is stored for the 10th iteration, it is possible to exactly restore the iterative decoder to the state of the 10th iteration by reloading the intermediate reliability metrics of the 10th iteration. As mentioned, an alternative to storing intermediate reliability metrics for all iterations is storing intermediate reliability metrics just for a best candidate iteration in the 10 memory 31 1 , 41 1 , 51 1 . A best candidate iteration may in this case be determined by different types of qualitative measures. For example, in case of an LDPC code, a best candidate iteration may be the iteration with the highest number of satisfied parity checks. In case of a turbo code, a best candidate iteration may be determined based on the lowest number of bit flips between successive iterations. The stored intermediate reliability meti s rics can now be used when the iterative decoder fails to output a valid codeword.
The reload and modify unit 330, 430, 530B, common for the three embodiments, is arranged to reload the best candidate reliability metrics M2 from the stored intermediate reliability metrics in the memory 31 1 , 41 1 , 51 1 and modify the metrics to obtain modified
20 reliability metrics M2'. It should be noted that a modification of the reliability metrics M2 is necessary; otherwise the next stage of the iterative decoding will not have any improved chances of finding a valid codeword. Without any modification the next stage of the iterative decoding is likely to end up with the same type of decoding failure as the first stage. Various types of modifications of the best candidate reliability metrics M2 can
25 be considered. As the modification of the best candidate reliability metrics M2 can be viewed as adding noise, one should try to limit the number of bit positions for which the reliability metrics are modified. A simple approach is to randomly select a small number of bit positions and modify the corresponding reliability metrics. Another approach is to change the stored reliability metrics for bit positions that are deemed potentially faulty. In
30 any of the approaches, the reliability metrics can be changed to have a lower reliability, which can be seen as equivalent to soft erasing some information, or the reliability metrics can be changed to have a higher reliability if the confidence of the value for a specific bit position is high. The reliability metrics could also be reversed in sign (i.e. a probability changes from 0 to a 1 , or vice versa). The modified reliability metrics M2' will serve
35 as input to a subsequent iterative decoder.
In a first embodiment of the present invention, shown schematically in Fig. 3, the decoder arrangement 300 comprises a first iterative decoder 31 OA having channel reliability metrics M1 as input. The iterative decoder 31 OA may here constitute any type of iterative decoder configured to decode an LDPC or a turbo code. An additional condition of the first iterative decoder 31 OA is that the intermediate reliability metrics are stored in a memory 31 1 , or alternatively, that the intermediate reliability metrics of a best candidate iteration is stored in a memory 31 1 . Hence, the iterative decoder 31 OA is arranged to store intermediate reliability metrics of at least one iteration to the memory 31 1 . The iterative decoder 31 OA is also arranged to provide an estimated codeword C1 as output, which is passed on to a control and output unit 320. The control and output unit 320 checks whether the estimated codeword C1 is a valid codeword or not. This can be done by checking whether all the parity check constraints of the linear code are satisfied or not. Only if all parity check constraints of the parity check matrix are satisfied, the estimated codeword C1 is a valid codeword. The control and output unit 320 is further ar- ranged to provide the estimated codeword or the information message (i.e. information bits) associated with the estimated codeword 01 as output U1 when the estimated codeword is a valid codeword.
A reload and modify unit 330 is arranged to reload the best candidate reliability metrics M2 of a best candidate iteration from the memory 31 1 and to modify the reloaded reliability metrics to obtain modified reliability metrics M2'. The modified reliability metrics M2' are passed on to the input of a subsequent iterative decoder 31 OB. The intermediate reliability metrics and the modified reliability metrics may be bit probabilities, log-likelihood ratios or any other type of reliability measure. The subsequent iterative decoder 31 OB is arranged to provide a subsequent estimated codeword 02 as output. The subsequent estimated codeword 02 is then passed on to the control and output unit 320. It should be noted that the subsequent iterative decoder 31 OB may constitute any type of iterative decoder configured to decode an LDPC or a turbo code. The control and output unit 320 is configured to check whether the subsequent estimated codeword 02 is a valid code- word or not. The control and output unit 320 is further configured to provide the estimated codeword 02 or the information message associated with the estimated codeword 02 as output U1 if the second estimated codeword 02 is a valid codeword. If neither the first estimated codeword 01 nor the subsequent estimated codeword 02 is a valid codeword, the control and output unit 320 may output the information message associated with the first estimated codeword 01 or the information message associated with the subsequent estimated codeword 02 or an information message associated with a combination of the first estimated codeword 01 and the subsequent estimated codeword 02. Alternatively,
if neither the first estimated codeword C1 nor the subsequent estimated codeword C2 is a valid codeword, the control and output may output the information message associated with the best candidate reliability metrics M2. The decoder arrangement may also report a decoding failure if no valid codeword is obtained.
In a second embodiment of the present invention, shown schematically in Fig. 4, the decoder arrangement 400 comprises an iterative decoder 410 serving as a first iterative decoder and having channel reliability metrics M1 as input. The iterative decoder 410 may here constitute any type of iterative decoder configured to decode an LDPC or a turbo code. An additional condition of the first iterative decoder 410 is that the intermediate reliability metrics are stored in a memory 41 1 , or alternatively, that the intermediate reliability metrics of a best candidate iteration is stored in a memory 41 1 . Hence, the iterative decoder 410 is arranged to store intermediate reliability metrics of at least one iteration to the memory 41 1 . The iterative decoder 410 is also arranged to provide an estimated codeword C1 as output, which is passed on to a control and output unit 420. The control and output unit 420 is arranged to check whether the estimated codeword C1 is a valid codeword or not, and is further arranged to provide the estimated codeword C1 or its associated information message as output U1 when the estimated codeword is a valid codeword.
A reload and modify unit 430 is arranged to reload the best candidate reliability metrics M2 of a best candidate iteration from the memory 31 1 and to modify the reloaded reliability metrics to obtain modified reliability metrics M2'. The intermediate reliability metrics and the modified reliability metrics may here be bit probabilities, log-likelihood ratios or any other type of reliability measure. The modified reliability metrics M2' are passed on to the iterative decoder 410 which now serves as a subsequent iterative decoder. No changes are necessary to the iterative decoder 410 to operate as a subsequent iterative decoder except a change of the input to the modified reliability metrics M2'. The iterative decoder is here arranged to provide a subsequent estimated codeword C2 as output. The subsequent estimated codeword C2 is passed on to the control and output unit 420, which is configured to check whether the subsequent estimated codeword C2 is a valid codeword and further configured to provide the estimated codeword C2 or the associated information message as output U1 if the subsequent estimated codeword C2 is a valid codeword. If neither of the first estimated codeword C1 and the subsequent estimated codeword C2 are valid codewords, the above procedure of the iterative decoder 410 operating as a subsequent iterative decoder may be repeated until a valid code codeword is obtained or may be stopped after a fixed number of cycles. For the N-1 cycle, modified
reliability metrics MN' are passed on to the iterative decoder which then provides a subsequent estimated codeword CN as output. The control and output unit 420 is configured to provide the information message associated with any estimated codeword that is a valid codeword as output U1 . The decoder arrangement 400 may also be configured to report a decoding failure if no valid codeword is obtained.
In a third embodiment of the present invention, shown schematically in Fig. 5, the decoder arrangement 500 comprises a first iterative decoder 51 OA having channel reliability metrics M1 as input. The iterative decoder 510 may constitute any type of iterative decoder configured to decode an LDPC or a turbo code. An additional condition of the first iterative decoder 51 OA is that the intermediate reliability metrics are stored in a memory 51 1 , or alternatively, that the intermediate reliability metrics of a best candidate iteration is stored in a memory 51 1 . Hence, the iterative decoder 51 OA is arranged to store intermediate reliability metrics of at least one iteration to the memory 51 1 . The iter- ative decoder 51 OA is arranged to provide an estimated codeword C1 as output, which is passed on to a control and output unit 520. The control and output unit 520 is arranged to check whether the estimated codeword C1 is a valid codeword or not, and also arranged to provide the information message of the estimated codeword C1 as output U1 when the estimated codeword is a valid codeword.
A subsequent decoding stage comprises a reload and modify unit 530B which is arranged to reload the stored reliability metrics M2 of a best candidate iteration from the memory 51 1 and to modify the reloaded reliability metrics to obtain modified reliability metrics M2'. The modified reliability metrics M2' are passed on to a subsequent iterative decoder 510B which is arranged to provide a subsequent estimated codeword C2 as output. An additional condition of the subsequent iterative decoder 510B is that the intermediate reliability metrics are stored in a memory 51 1 , or alternatively, that the intermediate reliability metrics of a best candidate iteration is stored in a memory 51 1 . The second estimated codeword C2 is passed on to the control and output unit 520. The control and output unit 520 is configured to check whether the subsequent estimated codeword C2 is a valid codeword and also configured to provide the associated information message as output U1 when C2 is a valid codeword.
If necessary, further subsequent decoding stages may follow, as is shown schematically in Fig. 5. For the N-1 decoding stage, a reload and modify unit 530N is arranged to reload the best candidate reliability metrics MN from the memory and modify the best candidate reliability metrics to obtain modified reliability metrics MN'. The modified reliability
metrics are passed on to a subsequent iterative decoder 51 ON arranged to output and pass on an estimated codeword CN to the control and output unit 520. The control and output unit 520 is configured to check whether the estimated codeword CN is a valid codeword and further configured to provide the associated information message of CN as output U1 if the estimated codeword CN is a valid codeword. If none of the estimated codewords C1 , C2, CN are valid codeword, the control and output unit 520 control and output unit 520 may be configured to provide the information message associated with one of the estimated codewords or a combination of at least two of the estimated codewords as output U1 .
The fourth and the fifth embodiments of the present invention relate to a method in a decoder arrangement 300, 400, 500 for decoding of an iteratively decodable code. The two embodiments are described with reference to the elements of the first, second and third embodiments of the present invention. Both embodiments are initialized by receiving and demodulating a received signal and passing the channel reliability metrics to the decoder arrangement 300, 400, 500. The fourth and fifth embodiments comprise the common steps of:
- decoding 600, 600A the iteratively decodable code, in a first stage, in which an iterative decoder 310,410,510 is initiated by channel reliability metrics M1 and arranged for storing intermediate reliability metrics of the iterations in a memory 31 1 , 41 1 , 51 1 and furthermore producing a first estimated codeword C1 .
- checking 610 codeword validity, by checking whether all the parity check constraints of the linear code's parity check matrix are satisfied. The estimated codeword C1 is a valid codeword only if all parity check constraints of the parity check matrix are satisfied.
- reloading and modifying 620 best candidate reliability metrics M2, when the first estimated codeword is not a valid codeword, wherein reloading and modifying 620 comprises reloading the stored best candidate reliability metrics M2 and modifying the best candidate reliability metrics M2 to obtain modified reliability metrics M2'.
- outputting 630, when the first estimated codeword is a valid codeword, the information message (i.e. the information bits) of the valid codeword.
The fourth embodiment of the present invention, shown schematically in the flowchart of Fig. 6, comprises the common steps described above, wherein the step of reloading and modifying 620, when the first estimated codeword is not a valid codeword, is followed by decoding 600B the iteratively decodable code, in a second stage, in which the iterative decoder 310, 410, 510 is initiated by the modified channel reliability metrics M2' and ar-
ranged for producing a subsequent estimated codeword C2, and the step of outputting 630 further comprises outputting, when the subsequent estimated codeword C2 is a valid codeword, the information message (i.e. the information bits) of the valid codeword. The fifth embodiment of the present invention, shown schematically in the flowchart of Fig. 7, comprises the common steps described above, wherein the step of reloading and modifying 620, when no estimated codeword (first or subsequent) is a valid codeword, returns to the previous step of decoding 600 in which the iterative decoder 410, 510 is initiated by modified channel reliability metrics M2', MN' and arranged for producing a subsequent estimated codeword C2, CN, and the step of outputting 630 further comprises outputting, when any of the subsequent estimated codeword C2, CN is a valid codeword, the information message of the valid codeword.
An implementation aspect of the five embodiments above relates to the size of the memory 31 1 , 41 1 , 51 1 . In the straightforward approach, the intermediate reliability metrics of all iterations are stored to the memory. This approach may, however, not be suitable for low-cost and area-efficient hardware architectures. A better approach would be to only store the intermediate reliability metrics of the intermediate reliability metrics when it may comprise the best candidate reliability metrics M2. By this approach, it is sufficient to only store intermediate reliability metrics of one iteration.
The first iterative decoder is in this case arranged to check, for each iteration, if the intermediate reliability metrics are the best candidate reliability metrics so far; and further arranged to overwrite the previously stored best candidate reliability metrics if the current iteration is identified as having the best candidate reliability metrics so far. For example, in case of an LDPC code, if the n-th iteration has a higher number of satisfied parity checks than all previous iterations, the intermediate reliability metrics of the n-th iteration will be stored to the memory 31 1 , 41 1 , 51 1 .
Another implementation aspect of the five embodiments above relate to decoding laten- cy. To avoid unnecessary decoding latency, the control and output unit 320, 420, 520 may be arranged to terminate the decoding and output the information message of a valid codeword as soon as the at least one estimated codeword C1 , C2, CN of the input comprises a valid codeword. Hence, in general, the control and output unit 320, 420, 520, having at least one estimated codeword C1 , C2, CN as input, is arranged to provide the information message associated with the valid codeword C1 , C2, CN as output U1 when the at least one estimated codeword comprises a valid codeword. The control and output unit 320, 420, 520 may further be configured to activate the reload and modify
unit 330 when the at least one estimated codeword C1 , C2, CN of the input comprises no valid codeword.
In another aspect, the present invention describes a communication system comprising the decoder arrangement 300, 400, 500. The communication system may here be a radio link transceiver, a base station, a user equipment (UE), a storage system or a computer system.
Fig. 8 illustrates yet another aspect of the present invention, where an iterative decoder arrangement 800, e.g. the decoder arrangement 300, 400, 500 described above, may be implemented as a processing unit 801 , a memory 802, input/output (I/O) unit 803 and a clock 804. The processing unit 801 , the memory 802, the I/O unit 803 and the clock 804 may be interconnected. The processing unit 801 may comprise a central processing unit (CPU), digital signal processor (DSP), multiprocessor system, programmable logic, field programmable gate array (FPGA) or application specific integrated circuit (ASIC) or any other type of logic. The memory 802 may comprise random access memory (RAM), read only memory (ROM) or any other type of volatile or non-volatile memory. The I/O unit 803 may comprise circuitry for controlling and performing signal conversions on I/O data. It should be emphasized that the term "comprises/comprising" when used in this specification is taken to specify the presence of stated features, integers, steps or components, but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof. It should also be noted that the words "a" or "an" preceding an element do not exclude the presence of a plurality of such elements.
It should also be emphasized that the steps of the method may, without departing from the embodiments herein, be performed in another order than the order in which they appear.
Claims
1 . A decoder arrangement (300, 400, 500) for improved decoding of an iteratively de- codable code, the decoder arrangement comprising:
- A first iterative decoder (31 OA, 410, 51 OA) having channel reliability metrics (M1 ) as input and arranged to store intermediate reliability metrics of at least one iteration in a memory (31 1 , 41 1 , 51 1 ) and provide an estimated codeword (C1 ) to a control and output unit (320, 420, 520),
- a reload and modify unit (330, 430, 530B) arranged to reload best candidate reliability metrics (M2) from the stored intermediate reliability metrics and to modify the best candidate reliability metrics to obtain modified reliability metrics (Μ2'),
- a subsequent iterative decoder (310B, 410, 510B) having modified reliability metrics (Μ2', ΜΝ') as input and arranged to provide a subsequent estimated codeword (C2, CN) to the control and output unit (320, 420, 520),
- a control and output unit (320, 420, 520) having at least one estimated codeword (C1 , C2, CN) as input and arranged to output, when the at least one estimated codeword comprises a valid codeword, an information message associated with the valid codeword.
2. The decoder arrangement (300, 400, 500) of claim 1 , wherein the control and output unit (320, 420, 520) is further arranged to output, when the at least one estimated codeword comprises no valid codeword, the information message associated with one of the at least one estimated codeword (C1 , C2, CN).
3. The decoder arrangement (300, 400, 500) of claim 1 , wherein the control and output unit (320, 420, 520) is further arranged to output, when the at least one estimated codeword comprises no valid codeword, the information message associated with the best candidate reliability metrics.
4. The decoder arrangement (300, 400, 500) of any of claims 1 -3, wherein the control and output unit (320, 420, 520) is further arranged to terminate the decoding when the at least one estimated codeword comprises a valid codeword.
5. The decoder arrangement (300, 400, 500) of any of claims 1 -4, wherein the first iterative decoder (31 OA, 410, 51 OA) is arranged to only store the intermediate reliability metrics of iterations that may comprise the best candidate reliability metrics (M2).
6. The decoder arrangement (300, 400, 500) of any of claims 1 -5, wherein the iterative- ly decodable code is an LDPC code and the best candidate reliability metrics (M2) are the intermediate reliability metrics of the iteration with the highest number of sat- isfied parity checks.
7. The decoder arrangement (300, 400, 500) of any of claims 1 -5, wherein the iterative- ly decodable code is a turbo code and the best candidate reliability metrics (M2) are the intermediate reliability metrics of the iteration with the lowest number of bit flips between successive iterations.
8. The decoder arrangement (300, 400, 500) of any of claims 1 -7, wherein the channel reliability metrics, the intermediate reliability metrics and the modified reliability metrics are at least one of bit probabilities or log-likelihood ratios.
9. A method in a decoder arrangement (300, 400, 500) for decoding of an iteratively decodable code, the method comprising the steps of:
- decoding (600, 600A) the iteratively decodable code, in which an iterative decoder (31 OA, 410, 51 OA) is initiated by channel reliability metrics (M1 ) and arranged for storing intermediate reliability metrics of at least one iteration in a memory (31 1 , 41 1 , 51 1 ) and provide an estimated codeword (C1 ),
- checking (610) if the estimated codeword (C1 ) is a valid codeword,
- loading and modifying (620), when the first estimated codeword is not a valid code- word, the best candidate reliability metrics (M2) to obtain modified reliability metrics
(Μ2') and subsequently decoding (600, 600B) the iteratively decodable code, in which a subsequent iterative decoder (310B, 410, 510B) is initiated by the modified reliability metrics (Μ2') and configured to provide a subsequent estimated codeword (C2),
- outputting (620) an information message associated with the valid codeword when the first estimated codeword (C1 ) and the subsequent estimated codeword (C2) comprise a valid codeword.
10. The method of claim 9, wherein outputting (610) further comprises outputting the in- formation message associated with one of the estimated codewords when the first estimated codeword (C1 ) and the subsequent estimated codeword (C2) comprises no valid codeword.
1 1 . The method of claim 9, wherein outputting (610) further comprises outputting the information message associated with the best candidate reliability metrics (M2) when the at least one estimated codeword comprises no valid codeword.
12. The method of any of claims 9-1 1 , wherein storing the intermediate reliability metrics comprises storing only the intermediate reliability metrics of iterations that may comprise the best candidate reliability metrics (M2).
13. The method of any of claims 9-12, wherein the iteratively decodable code is an
LDPC code and the best candidate reliability metrics (M2) are the intermediate reliability metrics of the iteration with the highest number of satisfied parity checks.
14. The method of any of claims 9-12, wherein the iteratively decodable code is a turbo code and the best candidate reliability metrics (M2) are the intermediate reliability metrics of the iteration with the lowest number of bit flips between successive iterations.
15. The method of any of claims 9-14, wherein the channel reliability metrics, the inter- mediate reliability metrics and the modified reliability metrics are at least one of bit probabilities or log-likelihood ratios.
16. A communication system comprising a decoder arrangement (300, 400, 500) for improved decoding of an iteratively decodable code, the decoder arrangement com- prising:
- A first iterative decoder (31 OA, 410, 51 OA) having channel reliability metrics (M1 ) as input and arranged to store intermediate reliability metrics of at least one iteration in a memory (31 1 , 41 1 , 51 1 ) and provide an estimated codeword (C1 ) to a control and output unit (320, 420, 520),
- a reload and modify unit (330, 430, 530B) arranged to reload best candidate reliability metrics (M2) from the stored intermediate reliability metrics and to modify the best candidate reliability metrics to obtain modified reliability metrics (Μ2'),
- a subsequent iterative decoder (310B, 410, 510B) having modified reliability metrics (Μ2', ΜΝ') as input and arranged to provide a subsequent estimated codeword (C2,
CN) to the control and output unit (320, 420, 520),
- a control and output unit (320, 420, 520) having at least one estimated codeword (C1 , C2, CN) as input and arranged to output, when the at least one estimated codeword comprises a valid codeword, an information message associated with the valid codeword.
17. The system of claim 16, wherein the communication system is a radio link transceiver, a base station, a UE, a storage system or a computer system.
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