WO2015044999A1 - Memory control device, information processing device, and memory control method - Google Patents

Abstract

A memory control device (2) is provided with: an access history storage unit (15) in which a history of access to a first storage device (4) is stored; and a control unit (7) which updates the access history stored in the access history storage unit (15) each time the first storage device (4) is accessed, and which stores, in a second storage device (3), data that is stored in the first storage device (4) and that has an access count equal to or less than a predetermined value, on the basis of the access history stored in the access history storage unit (15).

Description

MEMORY CONTROL DEVICE, INFORMATION PROCESSING DEVICE, AND MEMORY CONTROL METHOD

The present invention relates to a memory control device, an information processing device, and a memory control method.

In the information processing apparatus, a dual inline memory module (DIMM) is used as a temporary storage device. A memory control large scale integration (LSI) may be used to back up the DIMM data to another storage device such as a solid state drive (SSD).
FIG. 10 is a diagram schematically illustrating a hardware configuration of a conventional information processing apparatus 101.

The information processing apparatus 101 is, for example, an information processing apparatus having a server function, and includes a central processing unit (CPU) 110, a memory control LSI 102, an SSD 103, and a DIMM 104.
The information processing apparatus 101 is, for example, a core server, and once it is written, such as customer information (for example, the customer's name and date of birth), information that is hardly updated thereafter is stored in the DIMM 104. Read and write to it.

The CPU 110 is a processing device that performs various controls and operations, and implements various functions by executing an operating system (OS) and programs stored in the DIMM 104.
The DIMM 104 temporarily stores programs executed by the CPU 110, various data (hereinafter also referred to as user data), data obtained by the operation of the CPU 110, and the like.

The SSD 103 is a non-volatile storage device for backup of data stored in the DIMM 104.
The memory control LSI 102 is an LSI that controls the DIMM 104. Further, the memory control LSI 102 backs up the data by copying the data stored in the DIMM 104 to the SSD 103 via a control intellectual property (IP) core 105 and a user logic control 106 described later. Then, the memory control LSI 102 writes back (restores) the data backed up in the SSD 103 to the DIMM 104 via the control IP core 105 and the user logic control 106.

The memory control LSI 102 includes a control IP core 105, a user logic control 106, a memory controller 109, and management information 111.
The memory controller 109 controls reading of user data from the DIMM 104 (Read) and writing of user data to the DIMM 104 (Write).
The control IP core 105 and the user logical control 106 are interfaces that control communication between the SSD 103 and the DIMM 104. Specifically, the control IP core 105 communicates with the SSD 103, and the user logic control 106 communicates with the memory controller 109.

Here, the IP core is a block of frequently used circuits to improve the reusability of design assets in the development of Field Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC). It is a circuit block and there are various IP cores. Use of the IP core facilitates FPGA and ASIC design and debugging. In other words, the IP core corresponds to a library in software development. Here, the control IP core 105 is an SSD control IP core.

The user logical control 106 is an interface that controls communication between the SSD 103 and the DIMM 104 in accordance with the format of user data.
The management information 111 is information used for managing the memory control LSI 102 and is stored in, for example, a non-illustrated nonvolatile memory in the memory control LSI 102. The management information 111 stores information indicating whether a data unit stored in the DIMM 104 (hereinafter, this unit is referred to as a data set) is backed up.

Here, for example, in order to shorten the backup time, the memory controller 109 employs a method of identifying a part that is not backed up from the DIMM 104 to the SSD 103 and backing up the part to the SSD 103.
FIG. 11 is a flowchart (steps S101 to S105) showing the operation of the memory control LSI 102 shown in FIG.

In step S <b> 101, the memory control LSI 102 reads the management information 111 for each data set in the DIMM 104.
In step S102, the memory control LSI 102 determines whether data in the DIMM 104 is backed up based on the management information 111 read in step S101.

When the data in the DIMM 104 is not backed up (see NO route in step S102), in step S104, the memory control LSI 102 backs up all data sets in the DIMM 104 to the SSD 103. Thereafter, the processing moves to step S105.
On the other hand, when the data in the DIMM 104 is backed up (see YES route in step S102), in step S103, the memory control LSI 102 updates the data in the DIMM 104 after the previous backup is performed based on the management information 111. Determine whether or not.

When the data in the DIMM 104 has been updated after the previous backup (see YES route in step S103), in step S104, the memory control LSI 102 backs up the updated data set in the DIMM 104 to the SSD 103. Thereafter, the processing moves to step S105.
On the other hand, if the data in the DIMM 104 has not been updated since the previous backup (see NO route in step S103), the process returns to step S101 described above.

In step S105, it is determined whether the operation of the information processing apparatus 101 is continued.
When the operation of the information processing apparatus 101 is continued (see YES route in step S105), the process returns to step S101.
If the operation of the information processing apparatus 101 has ended (see NO route in step S105), the process ends.

When the information processing apparatus 101 is a backbone server or the like, there may be a lot of data that is updated only once in the DIMM 104.
In such a case, there is a considerable amount of frequently updated data in the DIMM 104 and data that has been updated only once (that is, data that has been written once and has not been updated since then).

Japanese Patent No. 4126706

Here, in the backup method shown in FIG. 11, if the data in the DIMM 104 has been updated, the data is backed up to the SSD 103. For this reason, when there is a considerable amount of data that has been updated only once (that is, data that has been written once and has not been updated since then) and data that is frequently updated, the data in the DIMM 104 is immediately after backup to the SSD 103. It is often updated. For this reason, the backup time is wasted.

Furthermore, since the number of writable times of the SSD 103 is limited, if the backup is frequently performed, the life of the SSD 103 is shortened.
In view of the above problems, in one aspect, the present invention aims to shorten the backup time of memory data.
In addition, the present invention is not limited to the above-described object, and other effects of the present invention can be achieved by the functions and effects derived from the respective configurations shown in the embodiments for carrying out the invention which will be described later. It can be positioned as one of

For this reason, the memory control device stores an access history in the access history storage unit that stores an access history to the first storage device, and in the access history storage unit every time the first storage device is accessed. A control unit that stores, in the second storage device, data having a number of accesses equal to or less than a predetermined value among the data in the first storage device based on the access history stored in the access history storage unit; I have it.

The information processing apparatus accesses the first storage device, the second storage device, an access history storage unit that stores an access history to the first storage device, and the first storage device. Each time the access history is stored in the access history storage unit, and based on the access history stored in the access history storage unit, of the data in the first storage device, the number of accesses is a predetermined value or less. And a control unit for storing the information in the second storage device.

Further, the memory control method records an access history to the access every time the first storage device is accessed in the access history storage unit, and based on the access history stored in the access history storage unit. Of the data stored in the first storage device, data having the number of accesses equal to or smaller than a predetermined value is stored in the second storage device.

According to the disclosed technology, the backup time of memory data can be shortened.

It is a figure which shows typically the hardware constitutions of the information processing apparatus as an example of embodiment. It is a mimetic diagram showing an example of circuit composition of a precedence saving part in an information processor as an example of an embodiment. It is a figure which illustrates the block management table as an example of embodiment. It is a schematic diagram which shows the circuit structural example of the advance evacuation determination part as an example of embodiment. It is a figure which illustrates the operation | movement logic of the counter in the information processing apparatus as an example of embodiment in a table format. It is a schematic diagram which shows the circuit structural example of the reference time extraction part as an example of embodiment. 6 is a flowchart illustrating an operation of a memory control LSI as an example of an embodiment. It is a flowchart which shows the advance evacuation process by the advance evacuation part as an example of embodiment. It is a flowchart which shows the reference time extraction process by the reference time extraction part as an example of embodiment. It is a figure which shows typically the hardware constitutions of the conventional information processing apparatus. It is a flowchart which shows operation | movement of the conventional memory control LSI.

(A) Hardware Configuration Hereinafter, a memory control device, an information processing device, and a memory control method as examples of the present embodiment will be described with reference to the drawings.
First, the configuration of the information processing apparatus 1 will be described.
FIG. 1 is a diagram schematically illustrating a hardware configuration of an information processing apparatus 1 as an example of an embodiment.

The information processing device 1 is, for example, an information processing device having a server function, and includes a CPU 10, a memory control LSI (memory control device) 2, an SSD (second storage device) 3, and a DIMM (first storage device). 4 is provided.
The information processing apparatus 1 as an example of the present embodiment is, for example, a backbone server, and once customer information (for example, customer name, date of birth, etc.) is written once, it is almost updated thereafter. No information is read from or written to the DIMM 4.

The CPU 10 is a processing device that performs various controls and operations, and implements various functions by executing an OS and programs stored in the DIMM 4. For example, a known CPU can be used as the CPU 10.
The DIMM 4 temporarily stores programs executed by the CPU 10, various data (hereinafter also referred to as user data), data obtained by the operation of the CPU 10, and the like. For example, a known memory such as a RAM can be used as the DIMM 4.

The SSD 3 is a non-volatile storage device for backup of data stored in the DIMM 4. A known SSD can be used as SSD3.
The memory control LSI 2 is an LSI that controls the DIMM 4. Further, the memory control LSI 2 backs up the data by copying the data stored in the DIMM 4 to the SSD 3 via the control IP core 5 and the user logic control 6 described later. Then, the memory control LSI 2 writes back (restores) the data backed up in the SSD 3 to the DIMM 4 via the control IP core 5 and the user logic control 6.

The memory control LSI 2 as an example of this embodiment does not back up frequently updated data stored in the DIMM 4 during normal operation, but backs up the DIMM 4 when the information processing apparatus 1 is powered off. Back up only when an instruction is issued.
On the other hand, the memory control LSI 2 backs up the data stored in the DIMM 4 that has been updated only once within a predetermined time (that is, not updated after being written once) in the background during normal operation. To do. Hereinafter, the process of backing up data updated only once within a predetermined time is referred to as “advance saving”.

For this reason, the memory control LSI 2 as an example of the present embodiment monitors the update state of the DIMM 4 in block units in the background of the normal operation of the information processing apparatus 1 and only blocks that have passed the reference time after being updated once. Are saved in advance in the SSD 3.
Here, the block is a unit when the memory control LSI 2 accesses the SSD 3, and for example, one block is 4 kilobytes (KB). Since the memory control LSI 2 performs backup (copy) of data from the DIMM 4 to the SSD 3 in units of blocks, the access of the DIMM 4 is also monitored in units of blocks.

The normal operation of the information processing apparatus 1 refers to a state in which the information processing apparatus 1 is used for a target job by the user after the information processing apparatus 1 is turned on and completely activated.
The memory control LSI 2 includes a control IP core 5, a user logic control 6, a preceding saving unit (control unit) 7, a reference time extraction unit (extraction unit) 8, and a memory controller 9.

The memory controller 9 controls reading of user data from the DIMM 4 (Read) and writing of user data to the DIMM 4 (Write).
The control IP core 5 and the user logical control 6 are interfaces that control communication between the SSD 3 and the DIMM 4. Specifically, the control IP core 5 communicates with the SSD 3, and the user logic control 6 communicates with the memory controller 9.

The user logic control 6 is an interface that controls communication between the SSD 3 and the DIMM 4 in accordance with the format of user data.
A known memory interface can be used as the control IP core 5 and the user logic control 6.
The advance saving unit 7 monitors the update of data in the DIMM 4 every predetermined time, and identifies a block in which data is saved in advance in the SSD 3 among all the blocks of the DIMM 4.

FIG. 2 is a schematic diagram illustrating a circuit configuration example of the advance saving unit 7 in the information processing apparatus 1 as an example of the embodiment.
The advance save unit 7 executes advance save processing, which will be described later with reference to FIG. 8, and is updated only once within a predetermined time out of the data stored in the DIMM 4 (that is, updated after being written once). No) Back up data in the background during normal operation. The advance saving unit 7 executes the advance saving process at predetermined time intervals during normal operation. The execution interval of this advance saving process can be appropriately set by a system administrator or the like according to the operation of the information processing apparatus 1.

The advance save unit 7 includes a block management table 15 and a advance save determination unit 16.
The block management table 15 is a table for managing the update status (access history) of data to the DIMM 4 as an update flag for each block of the DIMM 4. The block management table 15 is stored in a volatile memory such as a static RAM (SRAM) (not shown) in the memory control LSI 2, for example. An example of the data structure of the block management table 15 will be described later with reference to FIG.

The advance save determination unit 16 reads an update flag from a block management table 15 to be described later, and determines whether to save data to the SSD 3 for each block in the DIMM 4 based on the read update flag. In other words, the advance save determination unit 16 keeps the state of each block updated once (that is, only written once) in the DIMM 4 (that is, the block data is not updated thereafter), and the reference time Determine if it has passed. The detailed configuration and function of the advance retraction determining unit 16 will be described later with reference to FIG.

FIG. 3 is a diagram illustrating a block management table 15 as an example of the embodiment.
The block management table 15 stores an update flag indicating the update status of data of all blocks of the DIMM 4.
In the example of FIG. 3, the block management table 15 sets the update flag of the blocks 1 and 2 of the DIMM 4 to the address ADRS_1, the update flag of the blocks 3 and 4 to the address ADRS_2, the update flag of the blocks 5 and 6 to the address ADRS_3, and so on. , Each storing. That is, for each address in the block management table 15, an update flag for two blocks of the DIMM 4 is stored.

The block management table 15 is updated by the advance saving determination unit 16.
The data length of the update flag of each block is, for example, 2 bits. For example, for each block of DIMM 4, “00” is displayed if the block has not been updated, “01” if the block has been updated only once, and “11” if the block has been updated more than once. Are stored in the block management table 15 as update flags for the block.

FIG. 4 is a schematic diagram illustrating a circuit configuration example of the advance evacuation determination unit 16 as an example of the embodiment.
The advance save determination unit 16 includes a reference time register 17, a comparison unit 18, a counter 19, a register 20, and logical operation units 21 and 22.
The reference time register 17 is a register that stores the reference time extracted by the reference time extraction unit 8 described above with reference to FIG.

The comparison unit 18 compares the value of the reference time register 17 and the value of the counter 19, for example, LOW (for example, “0”) when the two do not match, and HIGH (for example, “1”) when the two match. Is output to a register 20 to be described later.
The counter 19 is a counter that counts an elapsed time since the block of the DIMM 4 was first updated. Specifically, when the value of the 2-bit update flag in the block update table 15 indicates “01”, the counter 19 receives HIGH from a logic operation unit 21 described later and starts counting up. Thereafter, the counter 19 counts up, for example, every hour. That is, the counter 19 starts counting up when the first write to the DIMM 4 occurs, and is incremented by 1 every hour.

The counter 19 is cleared by inputting LOW when the counter value reaches the reference time value.
FIG. 5 illustrates the operation logic of the counter 19 in a tabular form.
When LOW is input to the counter 19, the counter 19 is reset and the counter value is set to "000" as shown in the diagram of FIG.

Then, when the value of the update flag of the block in the block management table 15 becomes “01”, the counter 19 starts counting up, for example, the counter value is incremented by 1 every hour.
The register 20 in FIG. 4 is a register that holds the update flag (2 bits) read from the block update table 15 and the comparison result (1 bit) of the comparison unit 18.

The logic operation unit 21 is an AND circuit in the example of FIG. The logical operation unit 21 outputs LOW to the counter 19 when the 2-bit value of the update flag value of the register 20 is other than “01”. When the 2-bit value of the update flag value of the register 20 is “01”, the logical operation unit 21 outputs HIGH to the counter 19 to start counting up.
The logic operation unit 22 is an AND circuit in the example of FIG. When the logical operation unit 22 detects the passage of the reference time, it outputs HIGH.

That is, the circuit of FIG. 4 determines whether the block in the DIMM 4 has not been updated (that is, updated only once) until the reference time has elapsed after the block is first written. If the block has never been updated by the lapse of the reference time after the first writing (that is, updated only once), the logical operation unit 22 outputs HIGH, for example, and precedes the block with the SSD 3. It instructs the preceding saving unit 7 that it is a target to be saved.

Referring to FIG. 1 again, the reference time extraction unit 8 extracts a reference time used when the preceding saving unit 7 determines whether or not the data in the DIMM 4 has been updated only once within a predetermined time.
FIG. 6 is a schematic diagram illustrating a circuit configuration example of the reference time extraction unit 8 as an example of the embodiment.
The reference time extraction unit 8 measures the time required for writing to the DIMM 4 a predetermined number of times, and determines (extracts) the measured time as the reference time. This reference time is used when the advance saving unit 7 determines whether the data in the DIMM 4 has been updated only once within a predetermined time. The reference time extraction unit 8 includes a relative clock 11, a comparison unit 12, a threshold register 13, and a WRITE_ENABLE (WE) counter 14.

The relative clock 11 is a timer used for the reference time extraction process. The relative clock 11 starts counting up when the information processing apparatus 1 is powered on or reset (power-on reset), and is stopped by the comparison unit 12. Then, the relative clock 11 extracts the counter value of the relative clock 11 at the time when it is stopped by the comparison unit 12 as the reference time, performs conversion as necessary, and then, for example, the reference time register 17 (see FIG. 4). ).

The comparison unit 12 compares the value of a threshold register 13 described later with the value of the WE counter 14. When both match, the comparison unit 12 outputs HIGH, for example, and stops the countdown of the relative timepiece 11.
The threshold register 13 is a register that holds a threshold to be compared with the value of the WE counter 14. The threshold set in the threshold register 13 is set to any appropriate value by the threshold of the number of times of writing to the DIMM 4, for example, by a system administrator or the like.

The WE counter 14 is a counter that counts the number of times the data of the block of the DIMM 4 is updated. When the WE counter 14 receives a WRITE_ENABLE signal that permits writing to the DIMM 4, for example, the WE counter 14 increments the counter by one.
(B) Operation Next, the operation of the memory control LSI 2 as an example of the embodiment will be described.

FIG. 7 is a flowchart (steps S1 to S14) showing the operation of the memory control LSI 2 as an example of the embodiment.
In step S1, the information processing apparatus 1 is turned on, and normal operation of the information processing apparatus 1 is started.
In step S2, the advance saving unit 7 clears the block management table 15, and resets the update flags of all blocks of the DIMM 4 to “00”.

In step S3, the advance save determination unit 16 waits for an access command to the DIMM 4 and determines whether the command has been received.
If no command has been received (see NO route in step S3), the process returns to step S3.
On the other hand, when an instruction is received (see YES route in step S3), in step S4, the advance save determination unit 16 determines whether the received instruction is a backup instruction.

In the case of a backup command (see YES route in step S4), since the command received in step S3 is a backup command at the time of power-off, in step S5, the advance saving unit 7 reads all blocks of DIMM 4 from the block management table 15. Read the update flag.
In step S6, the advance saving unit 7 saves (backs up) the data of the block of the DIMM 4 whose update flag value in the block management table 15 is other than “00” to the SSD 3.

In step S7, the advance saving unit 7 sets the value of the corresponding update flag in the block management table 15 to “00” for all the blocks saved in the SSD 3 in step S6. Thereafter, the power source of the information processing apparatus 1 is turned off, and the normal operation ends.
On the other hand, when the command received in step S3 is not a backup command (see NO route in step S4), in step S8, the advance save determination unit 16 determines whether the command received in step S3 is a memory write command.

If the command received in step S3 is not a memory write command (see NO route in step S8), the command is a memory read command. Therefore, in step S9, the memory controller 9 executes a memory read command for the DIMM 4, and then returns to step S3 to wait for the next command.
On the other hand, when the instruction received in step S3 is a memory write instruction (see YES route in step S8), in step S10, the memory controller 9 executes memory write to the DIMM 4.

After executing the memory write in step S10, the process returns to step S3 and the normal operation is continued. In parallel with this, the advance saving unit 7 starts the flag update processing of steps S11 to S14 in the background of normal operation.
In step S11, the advance saving determination unit 16 reads the value of the update flag in the block management table 15 corresponding to the block written to the DIMM 4 in step S10.

In step S12, the advance save determination unit 16 determines whether or not the value of the update flag read into the register 20 is “00”. As described above, “00” is the initial value of the update flag, and the block in which this value is set in the update flag has not been updated yet after the information processing apparatus 1 is started (data is not written). )
When the value of the update flag is “00” (see YES route in step S12), in step S13, the advance save determination unit 16 sets the value of the corresponding update flag in the block management table 15 only once for the corresponding block. It is set to “01” indicating that it has been updated, and the flag update process is terminated (normal operation is continued).

When the value of the update flag is other than “00” (refer to the NO route in step S12), in step S14, the advance evacuation determination unit 16 sets the value of the corresponding update flag in the block management table 15 twice for the corresponding block. The value is set to “11”, which indicates that data has been written, and the flag update process is terminated (normal operation is continued).
FIG. 8 is a flowchart (steps S21 to S24) showing the advance saving process by the advance saving unit 7 as an example of the embodiment.

The advance saving process is executed in the background in parallel with the normal operation process during the normal operation.
In step S <b> 21, the advance saving unit 7 determines whether or not the information processing apparatus 1 is powered off.
When the information processing apparatus 1 is powered off (see YES route in step S21), the preceding saving unit 7 ends the preceding saving process.

If the information processing apparatus 1 is not powered off (see NO route in step S21), the advance saving unit 7 reads the all update flag from the block management table 15 in step S22. Then, it is determined whether or not there is a block in which the reference time extracted by the reference time extraction unit 8 has elapsed since the value of the read update flag is “01” and the update flag is set to the value “01”. judge.

If there is no block that satisfies the condition in step S22 (that is, data that has not been updated since it was written once) (see NO route in step S22), the advance save unit 7 returns to step S21 and performs the advance save process. repeat.
On the other hand, if there is a block that satisfies the condition in step S22 (see YES route in step S22), in step S23, the advance saving unit 7 has the update flag value “01” and the update flag value “01”. The data of all the blocks whose reference time has elapsed since being set to “” are copied to the SSD 3.

Next, in step S24, the advance saving unit 7 clears the update flag of the block update table 15 corresponding to the block copied to the SSD 3 in step S23 (that is, sets “00”). Thereafter, the preceding saving unit 7 returns to step S21 and repeats the preceding saving process.
FIG. 9 is a flowchart (steps S31 to S37) showing a reference time extraction process by the reference time extraction unit 8 as an example of the embodiment.

The reference time extraction unit 8 executes the reference time extraction process whenever the information processing apparatus 1 is powered on. Then, the latest reference time extracted by the reference time extraction unit 8 is used in step S22 of FIG.
In step S31, the reference time extraction unit 8 resets the relative clock 11.
Next, in step S32, the relative clock 11 starts a timer operation (timekeeping).

In step S33, the reference time extraction unit 8 monitors the write access (such as WRITE_ENABLE) of the DIMM 4, and counts up the WE counter 14 when the write access is observed.
In step S <b> 34, the comparison unit 12 determines whether or not the counter value of the WE counter 14 has reached the access count threshold value of the DIMM 4 stored in the threshold value register 13.

If the counter value of the WE counter 14 has not reached the threshold value (see NO route in step S34), the process returns to step S33, and the reference time extraction unit 8 continues to monitor access to the DIMM 4.
On the other hand, when the counter value of the WE counter 14 reaches the threshold value (see YES route in step S34), the reference time extraction unit 8 clears the WE counter 14 in step S35.

In step S36, the comparison unit 12 stops the relative clock 11, and the reference time extraction unit 8 extracts the timer value of the relative clock 11 as the reference time.
In step S37, the relative clock 11 applies the timer value extracted in step S36 as a reference time (for example, after converting the unit of time as necessary, stores it in the reference time register 17 in FIG. 4).

Thereafter, the process returns to step S31, and the reference time extraction unit 8 repeats the above-described reference time extraction process.
(C) Effect As described above, according to the example of the above-described embodiment, the advance saving unit 7 monitors the update state of the data in the DIMM 4 and records the update state in the block management table 15 in units of blocks of the DIMM 4. . Based on the block management table 15, the advance save unit 7 saves only the data of the block that has been updated only once (that is, has not been updated since being written once) to the SSD 3. To do.

That is, frequently updated data is not saved during normal operation, but is saved only when a backup command for the DIMM 4 is issued, such as when the information processing apparatus 1 is powered off. On the other hand, data that has been updated only once within a predetermined time (that is, data that has been written once and has not been updated since then) is subjected to advance evacuation in the background during normal operation.
As a result, when a backup command is issued to the DIMM 4 such as when the information processing apparatus 1 is powered off, only the blocks for which a value other than “00”, for example, is set in the update flag of the block management table 15 are displayed. Just backup to SSD3. For this reason, backup of data of the DIMM 4 is accelerated. For example, a backup that conventionally took 10 minutes is completed in about one minute in the example of this embodiment.

For example, in the information processing apparatus 1 having a memory space of 128 GB for the entire DIMM 4, the actual use area of the DIMM 4 is about 32 GB in total, and data that is updated only once accounts for about 60% of the entire DIMM 4. Percent of data is saved in advance during normal operation. When the DIMM 4 is backed up in the event of a failure of the information processing apparatus 1 and the like, data that is updated only once is first copied to the SSD 3 first, so the remaining capacity to be backed up is 12.8 GB. For this reason, the backup time of the DIMM 4 can be greatly shortened.

In addition, since the advance save unit 7 performs this advance save in the background of the normal operation, the normal operation is not hindered by the advance save.
Further, since the memory space of the DIMM 4 is divided into blocks, the access management efficiency of the DIMM 4 is improved. Further, useless saving to the SSD 3 can be reduced, and the backup time is shortened at the time of backup such as when the information processing apparatus 1 is powered off due to an error.

Further, the reference time extraction unit 8 always executes the reference time extraction process, and obtains the reference time used for the determination of the advance evacuation to the SSD 3 according to the data access status to the DIMM 4. For this reason, the frequency of advance evacuation can be optimized according to the data access status to the DIMM 4.
By monitoring the data update frequency of the DIMM 4 and specifying the block to be backed up in advance, the number of writes to the SSD 3 can be suppressed, and the life of the SSD 3 can be extended.

(D) Others The disclosed technique is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present embodiment.
For example, in the example of the above-described embodiment, the SSD 3 is used as a memory backup medium. However, another nonvolatile storage device may be used as the backup medium.

Alternatively, in the above embodiment, the contents of the DIMM 4 are backed up to the SSD 3, but the contents of other memories of the information processing apparatus 1 may be backed up to the SSD 3.
Alternatively, in the example of the above-described embodiment, the block data of the DIMM 4 that has passed for one hour after the first update is preliminarily saved in the SSD 3, but the system management is performed according to the operation status of the information processing apparatus 1 or the like. Any other waiting time may be set by a person or the like. For example, in the example of the above embodiment, the counter 19 is incremented by 1 every hour, but the counter 19 may be incremented by 1 every 7 hours.

Alternatively, the structure of the block management table 15 shown in FIG. 3 is merely an example, and another data structure may be adopted for the block management table 15.
Furthermore, in the example of the above-described embodiment, the advance save unit 7, the reference time extraction unit 8, and the advance save determination unit 16 are implemented by hardware, but at least one of these is implemented by software and / or firmware. May be implemented.

A program for realizing the functions of the advance save unit 7, the reference time extraction unit 8, and the advance save determination unit 16 when the advance save unit 7, the reference time extraction unit 8, and the advance save determination unit 16 are implemented by software. For example, flexible disk, CD (CD-ROM, CD-R, CD-RW, etc.), DVD (DVD-ROM, DVD-RAM, DVD-R, DVD + R, DVD-RW, DVD + RW, HD DVD, etc.), Blu-ray The recording medium is provided in a form recorded on a computer-readable recording medium such as a disk, a magnetic disk, an optical disk, or a magneto-optical disk. The information processing apparatus 1 reads the program from the recording medium via a drive device (not shown), transfers the program to an internal recording device or an external recording device, and uses it. Alternatively, the program may be recorded in a storage device (recording medium) such as a magnetic disk, an optical disk, or a magneto-optical disk, and provided from the storage device to the information processing apparatus 1 via a communication path.

When realizing the functions as the advance saving unit 7, the reference time extraction unit 8, and the advance saving determination unit 16, a program stored in a recording medium (not shown) is executed by a microprocessor (CPU 10 or the like) of the information processing apparatus 1. Executed. At this time, the information processing apparatus 1 may read and execute the program recorded on the recording medium.

DESCRIPTION OF SYMBOLS 1 Information processing apparatus 2 Memory control LSI (memory control apparatus)
3 SSD (second storage device)
4 DIMM (first storage device)
5 Control IP core 6 User logic control 7 Advance save unit (control unit)
8 reference time extraction unit (extraction unit)
9 Memory controller 10 CPU
DESCRIPTION OF SYMBOLS 11 Relative clock 12 Comparison part 13 Threshold register 14 WE counter 15 Block management table 16 Advance save determination part 17 Reference time register 18 Comparison part 19 Counter 20 Register 21, 22 Logic operation part

Claims (15)

1. An access history storage unit for storing an access history to the first storage device;
   Each time access to the first storage device is performed, an access history is stored in the access history storage unit, and based on the access history stored in the access history storage unit, data of the first storage device is stored. Among them, a control unit that stores data in which the number of accesses is a predetermined value or less in the second storage device;
   A memory control device characterized by comprising:
2. 2. The memory control device according to claim 1, wherein the control unit stores, in the second storage device, data that is written only once in the first storage device based on the access history. .
3. Based on the access history, the control unit writes only one time to the first storage device and performs a reference time after the one write to the first storage device is performed. 3. The memory control device according to claim 2, wherein only data that has passed is stored in the second storage device.
4. 4. The memory control according to claim 3, further comprising an extraction unit that measures a time required for the writing to the first storage device a predetermined number of times and determines the measured time as the reference time. apparatus.
5. When the backup instruction of the data in the first storage device is performed, the control unit stores all the data other than the data stored in the second storage device among the data in the first storage device. The memory control device according to any one of claims 1 to 4, wherein the memory control device is stored in a second storage device.
6. A first storage device;
   A second storage device;
   An access history storage unit for storing an access history to the first storage device;
   Each time access to the first storage device is performed, an access history is stored in the access history storage unit, and based on the access history stored in the access history storage unit, data of the first storage device is stored. Among them, a control unit that stores data in which the number of accesses is a predetermined value or less in the second storage device;
   An information processing apparatus characterized by comprising:
7. The information processing apparatus according to claim 6, wherein the control unit stores, in the second storage device, data that is written only once in the first storage device based on the access history. .
8. Based on the access history, the control unit writes only one time to the first storage device and performs a reference time after the one write to the first storage device is performed. 8. The information processing apparatus according to claim 7, wherein only the data that has passed is stored in the second storage device.
9. 9. The information processing apparatus according to claim 8, further comprising an extraction unit that measures a time required for the writing to the first storage device to be performed a predetermined number of times and determines the measured time as the reference time. apparatus.
10. When the backup instruction of the data in the first storage device is performed, the control unit stores all the data other than the data stored in the second storage device among the data in the first storage device. 10. The information processing apparatus according to claim 6, wherein the information processing apparatus is stored in a second storage device.
11. Each time the first storage device is accessed, the access history for the access is recorded in the access history storage unit,
    Based on the access history stored in the access history storage unit, among the data stored in the first storage device, data having a number of accesses equal to or less than a predetermined value is stored in the second storage device. Control method.
12. 12. The memory control method according to claim 11, wherein data that is written only once in the first storage device is stored in the second storage device based on the access history.
13. Based on the access history, only data that has been written to the first storage device only once and a reference time has elapsed since the first write to the first storage device was performed. The memory control method according to claim 12, wherein the memory is stored in the second storage device.
14. 14. The memory control method according to claim 13, wherein a time required for the writing to the first storage device to be performed a predetermined number of times is measured, and the measured time is determined as the reference time.
15. When a backup instruction for data in the first storage device is performed, all data other than data stored in the second storage device among the data in the first storage device is stored in the second storage device. 15. The memory control method according to claim 11, wherein the memory control method is stored in the memory.

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