WO2015039710A1 - Procédé et dispositif pour un contrôle de redondance cyclique de bout en bout sur de multiples unités de données - Google Patents

Procédé et dispositif pour un contrôle de redondance cyclique de bout en bout sur de multiples unités de données Download PDF

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Publication number
WO2015039710A1
WO2015039710A1 PCT/EP2013/072373 EP2013072373W WO2015039710A1 WO 2015039710 A1 WO2015039710 A1 WO 2015039710A1 EP 2013072373 W EP2013072373 W EP 2013072373W WO 2015039710 A1 WO2015039710 A1 WO 2015039710A1
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Prior art keywords
data units
cyclic redundancy
redundancy check
payload
multiple data
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PCT/EP2013/072373
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English (en)
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Yuval Elad
Alex Tal
Rami Zecharia
Alex UMANSKY
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Huawei Technologies Co., Ltd.
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Publication of WO2015039710A1 publication Critical patent/WO2015039710A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control

Definitions

  • the present invention relates to methods and devices for computing and verifying an end- to-end cyclic redundancy check (CRC) over multiple data units.
  • CRC cyclic redundancy check
  • aspects of the invention relate to physical fabric planes that interconnect multiple endpoints through a packet-based switching architecture.
  • a PCI Express backplane that interconnects multiple servers that are co-located under a shared physical enclosure such as a blade chassis or a rack.
  • a fundamental attribute of such physical planes is the need for high reliability which implies, among others, the ability to detect a data corruption event within a packet that has occurred while it was traversing the fabric.
  • PCI Express The Peripheral Component Interconnect Express PCI Express, as defined by the PCI Express Base Specification is fast becoming a widely used standard across the computer industry as a high-speed data communication link.
  • PCI Express specifies three discrete logical layers: the Transaction Layer, the Data Link Layer, and the Physical Layer.
  • the Transaction Layer is the upper layer and its primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs).
  • TLPs Transaction Layer Packets
  • TLPs Transaction Layer Packets
  • TLPs Transaction Layer Packets
  • Table 1 shows the conceptual flow of transaction level packet information through the layers. Framing Framing
  • a Transaction Layer Packet In PCI Express, a Transaction Layer Packet (TLP) is a kind of data unit that is created by a data-source at the "edge" of the PCI Express domain and transmitted between a transmission side and a receiving side. There are many types of transactions that are sent from device to device over a PCI-Express interconnect, each of which is in a transaction layer packet (TLP).
  • PCI Express supports the following basic transaction types: Memory, I/O, Configuration, and Messages. Take the Memory transaction as an example, it may comprises the memory read, memory write, and read Completion.
  • the Completion is a Packet used to terminate, or to partially terminate, a transaction sequence. A Completion always corresponds to a preceding Request, and, in some cases, includes data.
  • the PCI Express specification defines two types of packet CRCs as data reliability mechanisms - a 32bit link CRC (LCRC) which is a link level mandatory CRC and a 32bit End-to-End CRC (ECRC) which is an optional CRC that provides end-to-end protection. Both CRCs are calculated separately and independently for each TLP (Transaction Layer Packet).
  • LCRC link CRC
  • ECRC End-to-End CRC
  • the LCRC is re-calculated on each hop that the PCIe packet traverses on its route while the ECRC is calculated once, by the Transaction Layer in the source component, and later checked by the ultimate PCI Express Receiver (and optionally also by intermediate Receivers.)
  • the ECRC ensures end-to-end data integrity detection in systems that require high data reliability. It is needed since data corruption may occur internally to a PCIe Switch, and the regeneration of a good LCRC for corrupted data would mask the existence of such errors.
  • the ECRC is generated by the Transaction Layer in the source component, and checked (if supported) by the ultimate PCI Express Receiver and optionally by intermediate Receivers. ECRC protects both packet payload as well as packet header fields which are guaranteed to be unmodified by intermediate switches, i.e. fields that do not change as the TLP traverses the path. Until today most chipsets and endpoints did not implement ECRC, mainly due to its negative impact on link utilization.
  • End-to-End CRC is a feature that allows increasing the degree of reliability of packet transfer as it provides protection for the packet's payload through the entire route between the source point and the destination point.
  • the End-to-End CRC (ECRC) that is defined as part of the PCI Express specification supports this protection by adding an additional CRC field over the existing link level CRC (LCRC) for each protected packet, i.e. ECRC is calculated and applied for each Transaction Layer Packet independently. While this support does provide the basic end-to-end protection it is expensive in terms of net link utilization as it adds 32bit of CRC for each packet (on top of the 32bit of the mandatory LCRC). This has a negative impact on link utilization especially when considering the typically moderate sizes of PCIe TLPs.
  • the PCIE spec does not provide an option to make a selective decision on when to insert the ECRC as the spec states that if a device function is enabled to generate ECRC, it must calculate and apply ECRC for all TLPs originated by the function.
  • Another disadvantage of the existing support is that it does not allow detecting a silent drop of a single TLP within a set of TLPs which are logically grouped as a single group.
  • the invention is based on the finding that a technique for an improved error protection in a packet-based switching architecture can be achieved by allowing a source that generates TLPs to treat a group of TLPs which have logical association between them as a single logical unit for CRC computation and calculate CRC over the entire payload of all these TLPs.
  • the CRC result is then appended to the end of the last transmitted TLP within the group.
  • the packets are marked in a way that allows the sink point to associate a packet to a group, properly calculate CRC over the entire group and make a pass/fail decision for that group according to the calculation result.
  • Calculating CRC once over a group of TLPs has the following benefits: It allows increasing the effective PCIe link utilization. For example calculating end-to-end CRC globally on a group of 64B completions that correspond to a single 4KB read request would increase the effective link utilization from 94% to 99%.
  • the technique can be used as a mechanism for detecting an otherwise silently dropped TLP.
  • PCIExpress Peripheral Component Interconnect Express, e.g. according to PCIe
  • versions 1 .0, 1 .1 , 2.0, 2.1 , 3.0, 4.0 or higher is a high-speed serial computer expansion bus standard.
  • TLP Transaction Layer Packet, e.g. as specified in PCIe® Base 3.0
  • CRC Cyclic Redundancy Check.
  • a CRC is an error-detecting code, e.g. for usage in digital communication networks and storage devices to detect accidental changes to raw data. Blocks of data entering these systems get a short check value attached, e.g. based on the remainder of a polynomial division of their contents, on retrieval the calculation is repeated, and corrective action can be taken against presumed data corruption if the check values do not match.
  • GECRC Group End-to-End CRC.
  • IP Internet Protocol
  • Unit a unit of collocated data, e.g. a data frame or a data packet.
  • a data unit may be uniformly processed.
  • a TLP is an example for a data unit.
  • group a group of data units, e.g. TLPs which have a logical association between them as a single logical unit.
  • the invention relates to a method for computing an end-to-end cyclic redundancy check over multiple data units, the method comprising: computing a cyclic redundancy check over a payload of a logical group; mapping the payload to the multiple data units; appending a result of the cyclic redundancy check to a predetermined one of the data units; and transmitting the multiple data units individually.
  • Calculating CRC once over a group of data units allows increasing the effective link utilization. For example calculating end-to-end CRC globally on a group of 64B completions that correspond to a single 4KB read request would increase the effective PCIe link utilization from 94% to 99%.
  • the technique can be used as a mechanism for detecting an otherwise silently dropped data units.
  • the method comprises: appending the result of the cyclic redundancy check to a last one of the data units.
  • the transmitting side can already transmit data units which CRC has been calculated.
  • the CRC result can be appended to the last data unit not yet transmitted. This improves efficiency of the data link.
  • the method comprises: transmitting the data units by preserving a transmission order of the data units.
  • the receiving side can verify CRC over received data units without the requirement of buffering the received data units. By that, time delays in processing can be reduced thereby improving efficiency of data transmission.
  • the method comprises: transmitting a first part of the data units over which payload the cyclic redundancy check has been computed while computing the cyclic redundancy check over the remaining payload.
  • both tasks can be processed in parallel. This improves efficiency of data transmission.
  • the method comprises: transmitting the multiple data units over a PCI Express link.
  • a PCI Express link By transmitting the multiple data units over a PCI Express link, any standard device implementing the PCI Express standard can be used for implementing the method.
  • the method can be efficiently implemented. Costs for designing specific hardware components can be reduced.
  • the method comprises: marking the data units with a group identifier configured for identifying the logical group of the payload.
  • the data units By marking the data units with a group identifier, the data units can be easily detected and assigned to the respective logical group they belong to.
  • the method comprises: marking a first one and a last one of the data units configured for detecting a head and a tail of the data units.
  • the receiving side can detect a start and an end of the CRC computation and thus efficiently allocate and release buffers for CRC processing.
  • the invention relates to a method for verifying an end-to- end cyclic redundancy check over multiple data units, the method comprising: receiving multiple data units; computing a cyclic redundancy check over a payload of the multiple data units; and verifying a result of the cyclic redundancy check with a desired result appended to one of the data units.
  • Calculating CRC once over a group of data units allows increasing the effective link utilization. For example calculating end-to-end CRC globally on a group of 64B
  • the method comprises: computing the cyclic redundancy check over a payload of a first part of the data units while receiving a remaining part of the data units.
  • computing the cyclic redundancy check over a payload of a first part of the data units while receiving a remaining part of the data units both tasks can be processed in parallel. This improves efficiency of data reception.
  • the method comprises: grouping the received data units to a payload of a logical group by checking a group identifier the data units are marked with. By checking the group identifier of the data units, the data units can be easily detected and assigned to the respective logical group they belong to.
  • the method comprises: detecting a head and a tail of the data units by checking a marking of a first one and a marking of a last one of the received data units.
  • the receiving side can detect a start and an end of the CRC computation and thus efficiently allocate and release buffers for CRC processing.
  • the method comprises: computing a new cyclic redundancy check over a payload of the multiple data units when detecting a head of the data units; and verifying a result of the cyclic redundancy check with a desired result appended to the tail of the data units when detecting the tail of the data units.
  • the invention relates to a transmission device for computing an end-to-end cyclic redundancy check over multiple data units, the transmission device comprising: a first unit configured for computing a cyclic redundancy check over a payload of a logical group; a second unit configured for mapping the payload to multiple data units; a third unit configured for appending a result of the cyclic redundancy check to a predetermined one of the data units; and a fourth unit configured for transmitting the multiple data units individually.
  • the device comprises an appending unit configured for appending the result of the cyclic redundancy check to a last one of the data units.
  • the transmitting side can already transmit data units which CRC has been calculated.
  • the CRC result can be appended to the last data unit not yet transmitted. This improves efficiency of the data link.
  • the device comprises a transmission unit configured for transmitting the data units by preserving a transmission order of the data units.
  • the receiving side can verify CRC over received data units without the requirement of buffering the received data units. By that, time delays in processing can be reduced thereby improving efficiency of data transmission.
  • the device comprises a transmission unit configured for transmitting a first part of the data units over which payload the cyclic redundancy check has been computed while computing the cyclic redundancy check over the remaining payload.
  • the device comprises a transmission unit configured for transmitting the multiple data units over a PCI Express link.
  • the device comprises a marking unit configured for marking the data units with a group identifier configured for identifying the logical group of the payload. By marking the data units with a group identifier, the data units can be easily detected and assigned to the respective logical group they belong to.
  • the device comprises a marking unit configured for marking a first one and a last one of the data units configured for detecting a head and a tail of the data units.
  • the receiving side can detect a start and an end of the CRC computation and thus efficiently allocate and release buffers for CRC processing.
  • the invention relates to a receiving device for verifying an end-to-end cyclic redundancy check over multiple data units, the receiving device comprising: a first unit configured for receiving multiple data units; a second unit configured for computing a cyclic redundancy check over a payload of the multiple data units; a third unit configured for verifying a result of the cyclic redundancy check with a desired result appended to a predetermined one of the data units.
  • the device comprises a computing unit configured for computing the cyclic redundancy check over a payload of a first part of the data units while receiving a remaining part of the data units.
  • both tasks can be processed in parallel. This improves efficiency of data reception.
  • the device comprises an grouping unit configure for grouping the received data units to a payload of a logical group by checking a group identifier the data units are marked with.
  • the data units can be easily detected and assigned to the respective logical group they belong to.
  • the device comprises a detection unit configured for detecting a head and a tail of the data units by checking a marking of a first one and a marking of a last one of the received data units.
  • the receiving side can detect a start and an end of the CRC computation and thus efficiently allocate and release buffers for CRC processing.
  • the device comprises a computing unit configured for computing a new cyclic redundancy check over a payload of the multiple data units when detecting a head of the data units; and verifying a result of the cyclic redundancy check with a desired result appended to the tail of the data units when detecting the tail of the data units.
  • the invention relates to a system, in particular a rack or a chassis, comprising: at least one transmission device according to the third aspect; and at least one receiving device according to the fourth aspect, wherein the at least one transmission device and the at least one receiving device are interconnected by a packet- based switching architecture, in particular by a PCI Express backplane.
  • a system one or more transmission devices and one or more receiving devices allows effective error protection in the whole system, e.g. in a whole rack or chassis where the devices are used.
  • the invention relates to a transmission device, which includes a processor configured for computing a cyclic redundancy check over a payload of a logical group; mapping the payload to the multiple data units; appending a result of the cyclic redundancy check to a predetermined one of the data units, and an interface configured for transmitting multiple data units individually.
  • the processor is further configured for performing the method according to any
  • the invention relates to a receiving device, which includes an interface configured for receiving multiple data units, and a processor configured for computing a cyclic redundancy check over a payload of the multiple data units; and verifying a result of the cyclic redundancy check with a desired result appended to one of the data units.
  • the processor is further configured for performing the method according to any
  • the invention relates to a system, in particular a rack or a chassis, comprising: at least one transmission device according to the sixth aspect per se or any implementation form of the sixth aspect; and at least one receiving device according to the seventh aspect per se or any implementation form of the seventh aspect, wherein the at least one transmission device and the at least one receiving device are interconnected by a packet-based switching architecture, in particular by a PCI Express backplane.
  • DSP Digital Signal Processor
  • ASIC application specific integrated circuit
  • the invention can be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations thereof, e.g. in available hardware of conventional mobile devices or in new hardware dedicated for processing the methods described herein.
  • Fig. 1 shows a schematic diagram of a method 100 for computing an end-to-end cyclic redundancy check over multiple data units according to an implementation form
  • Fig. 2 shows a schematic diagram of a method 200 for verifying an end-to-end cyclic redundancy check over multiple data units according to an implementation form
  • Fig. 3 shows a schematic diagram of a logical group 300 of data units according to an implementation form
  • Fig. 4 shows a block diagram of a system 400 including a transmission device 410 and a receiving device 420 interconnected by a PCI fabric 401 according to an implementation form
  • Fig. 5 shows a block diagram of a system 500 including a transmission device 510 and a receiving device 520 interconnected by a PCI fabric 401 according to another
  • Fig. 1 shows a schematic diagram of a method 100 for computing an end-to-end cyclic redundancy check over multiple data units according to an implementation form.
  • the method 100 may include computing 101 a cyclic redundancy check over a payload of a logical group 300, e.g. a logical group 300 as described below with respect to Fig. 3.
  • a logical group 300 e.g. a logical group 300 as described below with respect to Fig. 3.
  • a logical group 300 e.g. a logical group 300 as described below with respect to Fig. 3.
  • the big data is called a payload of the logical group.
  • the big data i.e. the payload of the logical group, is usually segmented into several small data and encapsulated into several packets and transferred over packet switching domain.
  • the big data is normally segmented into several TLPs, the logical group comprises multiple TLPs.
  • the logical group of TLPs comprises multiply TLPs
  • the payload of the logical group is a sum of the payloads of the logical group of TLPs.
  • the 8 TLPs have a logical association between them, all of them belong to the same logical group.
  • the method 100 may include mapping 103 the payload of the logical group to multiple data units 301 , 303, 305, 307, e.g. multiple TLP as described below with respect to Fig. 3.
  • the method 100 may include appending 105 a result 309 of the cyclic redundancy check, e.g. a result GECRC 309 as described below with respect to Fig. 3, to a predetermined one of the data units, e.g. a predetermined data unit 307 as described below with respect to Fig. 3.
  • the method 100 may include transmitting 107 the multiple data units 301 , 303, 305, 307 individually.
  • the method 100 may include appending 105 the result 309 of the cyclic redundancy check to a last one 307 of the data units.
  • the method 100 may include transmitting 107 the data units 301 , 303, 305, 307 by preserving a transmission order of the data units.
  • the method 100 may include transmitting 107 a first part 301 of the data units over which payload the cyclic redundancy check has been computed while computing the cyclic redundancy check over the remaining payload 303, 305, 307.
  • the method 100 may include transmitting 107 the multiple data units 301 , 303, 305, 307 over a PCI Express link 405, e.g.
  • the method 100 may include marking the data units 301 , 303, 305, 307 with a group identifier configured for identifying the logical group 300 of the payload.
  • the method 100 may include marking a first one 301 and a last one 307 of the data units 301 , 303, 305, 307 configured for detecting a Head 301 and a Tail 307 of the data units 301 , 303, 305, 307, e.g. a Head data unit 301 and a Tail data unit 307 as described below with respect to Fig. 3.
  • the method 100 is implemented in a transmission device 410 as described below with respect to Fig. 4 or Fig. 5.
  • the method 100 allows a source, e.g. a root port or an endpoint that generates data units, e.g. PCI Express TLPs as described below with respect to Fig. 3, to calculate and apply end-to-end CRC over a group of data units, e.g. TLPs, instead of applying it to each data unit, e.g. TLP, separately.
  • This CRC will be referred to in this text as GECRC (Group End- to-End CRC).
  • the method 100 may be applied to a use case where an originator of data units, e.g. TLPs, can group multiple data units, e.g. TLPs, to a single logical group in a way that is agreed both by the source and the destination, i.e., the final target, of the data units.
  • an originator of data units e.g. TLPs
  • TLPs multiple data units
  • a single logical group in a way that is agreed both by the source and the destination, i.e., the final target, of the data units.
  • One example for such a case is the completion packets that compose a full response for a read request, e.g. a read request according to the PCI Express specification.
  • Another example for such a case is a single logical packet of data that is artificially split into multiple Write TLPs as it is injected into the PCIe bus, for example in order to comply with MPS requirements. In both cases, if data corruption occurs, e.g.
  • the entire transaction is deemed erroneous.
  • the CRC for the entire payload that corresponds to the logical group and attach the final result only to the last data unit, e.g. last TLP, within that group.
  • the Memory transaction may comprise the Memory Read, Memory Write, and Read Completion.
  • the Completion is a Packet used to terminate, or to partially terminate, a transaction sequence.
  • a Completion always corresponds to a preceding Request, and, in some cases, includes data.
  • the payload of the logical group may be transferred via multiple Memory Write Request TLPs or via multiple Memory Read Completion TLPs.
  • a Memory Write Request TLP includes a header and a payload.
  • the payload is used to carry the small data as shown in Fig. 3, the header includes the following fields as shown in Table 2.
  • Fmt - Format of TLP indicates the number of Double Words (DW) header, with or without data, such as the value "000b" of the Fmt fields indicates "3DW header, no data".
  • the Fmt can also indicates the presence of one or more TLP Prefixes, which is additional information that may be optionally prepended to a TLP.
  • TLP Prefixes are either Local or End-End.
  • a TLP can have multiple TLP Prefixes.
  • Type - Type of TLP like Memory Read Request (MRd), Memory Write Request (MWr), I/O Read Request (lORd), I/O Write Request (lOWr), Completion without Data (Cpl), Completion with Data (CpID), etc.
  • TC - Traffic Class this field allows differentiation of transactions into different classes, like Best Effort service class or Differentiated service classes based on Weighted-Round- Robin and/or Priority.
  • Attr - Attributes the Attributes field is used to provide additional information that allows modification of the default handling of Transactions.
  • TPH TLP Processing Hints
  • TD - It is used to indicate presence of TLP digest in the form of a single DW at the end of the TLP.
  • EP - indicates the TLP is poisoned, i.e., error forwarded.
  • AT - Address Type (AT) field indicates the address type contained in the Address Translation Services Specification.
  • Requestor ID The combination of a Requester's Bus Number, Device Number, and Function Number that uniquely identifies the Requester.
  • Tag - A number assigned to a given Non-posted Request to distinguish Completions for that Request from other Requests. Requester ID and Tag combined form a global identifier, i.e., Transaction ID for each Transaction within a Hierarchy.
  • Last DW BE- Last DW Byte Enable indicates to read or write the last Nth byte of Data.
  • 1 st DW BE - First DW Byte Enable indicates to read or write the first Nth byte of Data.
  • Fig. 2 shows a schematic diagram of a method 200 for verifying an end-to-end cyclic redundancy check over multiple data units according to an implementation form.
  • the method 200 may include receiving 201 multiple data units, e.g. multiple data units 301 , 303, 305, 307 as described below with respect to Fig. 3.
  • the method 200 may include computing 203 a cyclic redundancy check over a payload of the multiple data units.
  • the method 200 may include verifying 205 a result of the cyclic redundancy check with a desired result 309, e.g. a desired result 309 as described below with respect to Fig. 3, appended to a predetermined one of the data units, e.g. a predetermined one 307 of the data units 301 , 303, 305, 307 as described below with respect to Fig. 3.
  • the method 200 may include computing 203 the cyclic redundancy check over a payload of a first part of the data units, e.g. a first part 301 of the data units 301 , 303, 305, 307 as described below with respect to Fig. 3, while receiving a remaining part of the data units, e.g. a remaining part 303, 305, 307 as described below with respect to Fig. 3.
  • the method 200 may include associating the received data units to a payload of a logical group 300, e.g. a logical group 300 as described below with respect to Fig. 3, by checking a group identifier the data units are marked with.
  • the method 200 may include detecting a head and a tail of the data units, e.g. a head data unit 301 and a tail data unit 307 as described below with respect to Fig. 3, by checking a marking of a first one and a marking of a last one of the received data units, e.g. a marking of a first one 301 and a marking of a last one 307 of the received data units 301 , 303 , 305, 307 as described below with respect to Fig. 3.
  • a head and a tail of the data units e.g. a head data unit 301 and a tail data unit 307 as described below with respect to Fig. 3.
  • the method 200 may include computing 203 a new cyclic redundancy check over a payload of the multiple data units when detecting a head of the data units; and verifying 205 a result of the cyclic redundancy check with a desired result 309 appended to the tail 307 of the data units when detecting the tail 307 of the data units, e.g. a desired result 309 appended to the tail 307 of the received data units 301 , 303 , 305, 307 as described below with respect to Fig. 3.
  • the method 200 may be applied on a receiving side together with the method 100 as described above with respect to Fig. 1 applied on a transmission side.
  • the method 200 is implemented in a receiving device 420 as described below with respect to Fig. 4 or Fig. 5.
  • Fig. 3 shows a schematic diagram of a logical group 300 of data units according to an implementation form.
  • Fig. 3 illustrates a logical group 300 of data units, e.g. TLPs.
  • Fig. 3 depicts only a single group 300 out of a plurality of such groups.
  • Each group 300 contains a first TLP 301 , also called Head TLP 301 , a last TLP 307, also called Tail TLP 307 and zero or more Middle TLP 303, 305.
  • the TLPs may be compliant to the TLP Prefix specification of PCI SIG engineering change notice with respect to PCIe Base specification 2.0, published Dec.
  • Each of the TLPs 301 , 303, 305, 307 includes a header and a payload section.
  • the last TLP 307, also called tail TLP includes a CRC check field 309, denoted as GECRC (Group End-to-End CRC).
  • the CRC check field 309 may be appended at an end of the last TLP 307 or at any other predetermined location which is known at the receiving side.
  • the Head TLP 301 and the Tail TLP 307 are actually the same packet. In such a case the GECRC collapses to a regular ECRC.
  • Fig. 4 shows a block diagram of a system 400 including a transmission device 410 and a receiving device 420 interconnected by a PCI fabric 401 according to an implementation form.
  • the system 400 may be implemented as a rack or a chassis.
  • the transmission device 410 and the receiving device 420 are interconnected by a packet-based switching architecture 401 , e.g. a PCI Express backplane.
  • the transmission device 410 can be used for computing an end-to-end cyclic redundancy check over multiple data units, e.g. data units 301 , 303, 305, 307 as described above with respect to Fig. 3.
  • the transmission device 410 may include a first unit 41 1 configured for computing a cyclic redundancy check over a payload of a logical group 300, e.g. a logical group 300 as described above with respect to Fig. 3.
  • the transmission device 410 may include a second unit 412 configured for mapping the payload to payloads of multiple data units, e.g. data units 301 , 303, 305, 307 as described above with respect to Fig. 3.
  • the transmission device 410 may include a third unit 413 configured for appending a result of the cyclic redundancy check, e.g. a result 309 as described above with respect to Fig. 3, to a predetermined one 307 of the data units, e.g. a predetermined one 307 as described above with respect to Fig. 3.
  • the transmission device 410 may include a fourth unit 414 configured for transmitting the multiple data units 301 , 303, 305, 307 individually.
  • the receiving device 420 can be used for verifying an end-to-end cyclic redundancy check over multiple data units, e.g. data units 301 , 303, 305, 307 as described above with respect to Fig. 3.
  • the receiving device 420 may include a first unit 421 configured for receiving multiple data units, e.g. multiple data units 301 , 303, 305, 307 as described above with respect to Fig. 3.
  • the receiving device 420 may include a second unit 422 configured for computing a cyclic redundancy check over a payload of the multiple data units.
  • the computation of CRC may use an initial value for the first data unit, and store the computation result for the CRC computation of the remaining data unit.
  • the receiving device 420 may include a third unit 423 configured for verifying a result of the cyclic redundancy check with a desired result, e.g. a desired result 309 as described above with respect to Fig. 3, appended to a predetermined one of the data units, e.g. a
  • predetermined data unit 307 as described above with respect to Fig. 3. If the calculated CRC result is the same as the GECRC carried in the last TLP, a pass decision is made, otherwise, a fail decision is made.
  • the system 400 may include a plurality of such transmission devices 410 and a plurality of such receiving devices 420.
  • the figure shows a single direction. Both devices 410, 420 may also operate with respect to the opposite direction.
  • the transmission device 410 includes a PCI Express device 405 and the receiving device 420 includes a further PCI Express device 403.
  • the operation at the source point 410 may comprise the following steps.
  • the source device 410 may calculate a CRC over the entire payload that corresponds to the logical group.
  • the source device 410 may map the payload to a set of TLPs that including a Head TLP 301 , Middle TLPs 303, 305 and a Tail TLP 307, e.g.
  • the TLPs are marked with a group identifier that allows the sink point 420 to associate them to their logical group and to detect the Head and Tail TLPs 301 , 307.
  • the CRC result that was calculated may be appended to the Tail TLP 307.
  • all TLPs may be individually sent on the PCIe link 405 according to the correct payload order. All steps may be performed in parallel such that a cut-through operation may be achieved in which a TLP may be injected into the PCI fabric while the GECRC may be calculated over the rest of the data units.
  • the receiver may perform the following steps for each incoming TLP: Via PCTe link the receiver 420 receives TLPs sent from the transmission device 410.
  • the receiver may compute a GECRC calculation if a Head TLP is detected.
  • the receiver may associate the TLP with a group and continue GECRC calculation using group's CRC state parameters if a TLP is detected that is not a Head TLP.
  • the receiver may perform the previous steps if a Tail TLP is detected and then compare the calculated GECRC result with the GECRC that is extracted from the Tail TLP.
  • the receiver may make a pass/fail decision for the entire group according to the compare result.
  • the GECRC check allows the receiver to detect the event of one or more Middle TLPs that are dropped somewhere along the path.
  • the GECRC check will typically fail if such an event occurred.
  • Fig. 5 shows a block diagram of a system 500 including a transmission device 510 and a receiving device 520 interconnected by a PCI fabric 401 according to another implementation form of the invention.
  • the system 500 in particular a rack or a chassis, comprises: at least one transmission device 510; and at least one receiving device 520.
  • the at least one transmission device 510 and the at least one receiving device 520 are interconnected by a packet-based switching architecture, in particular by a PCI Express backplane.
  • the PCTe links and the PCIe fabric 401 shown in Fig. 5 correspond to the PCTe links, and the PCIe fabric 401 of Fig. 4, respectively.
  • the transmission device 510 and the receiving device 520 may also comprise a PCI Express device (no shown) as shown in Fig. 4, the PCI Express device is coupled to the interface 521 and 51 1 , respectively.
  • the transmission device 510 which includes a processor 512 configured for computing a cyclic redundancy check over a payload of a logical group; mapping the payload to the multiple data units; appending a result of the cyclic redundancy check to a predetermined one of the data units, and an interface 51 1 configured for transmitting multiple data units individually.
  • the processor may be further configured for performing the method 100 with respect to Fig. 1 .
  • the receiving device 520 which includes an interface 521 configured for receiving multiple data units, and a processor 522 configured for computing a cyclic redundancy check over a payload of the multiple data units; and verifying a result of the cyclic redundancy check with a desired result appended to one of the data units.
  • the receiving device 520 may be further configured for performing the method 200 with respect to Fig. 2.
  • Several methods for grouping TLPs to a logical group and for marking the Head and Tail TLPs can be used, including the following methods:
  • the existing PCIe mechanisms can be used for Head/Tail detection and for group association.
  • the Length field can be used for Head/Tail detection and the Tag field can be used for group association.
  • the Byte Count field can also be used for Head/Tail detection. According to a possible implementation form, the Byte Count field and the Length field used for Head/Tail detection is shown Table 3 below.
  • Table 3 H field occupy one bit of the Length field, like bit 9, indication of a Head TLP of a logical group.
  • T field occupy one bit of the Byte Count field, like bit 1 1 , indication of a Tail TLP of a logical group.
  • LGID Local group ID
  • the Length field, the Byte Count field, the Tag field and other fields of the Completion TLP Header are as same as the PCIe® Base Specification, like PCIe® Base v 3.0 Specification.
  • the TLPs may be associated with a logical group using several methods, according to a possible implementation form, the Completion TLPs (as shown in Table 3) are associated with a TLPs logical group using the Completer ID and Tag in the received packet.
  • the logical group ID therefore can globally and uniquely indicate each logical group from each Completer, i.e., transmission device,
  • the reception device is enabled to uniquely and globally identify each logical group from each transmission device.
  • bits in the TLP header can be allocated for marking the Head and Tail TLPs and for adding a unique group identifier (ID).
  • ID unique group identifier
  • the Tag field which is unused in Memory Write requests according to the PCIe Base specification can be used for accommodating some of the required bits.
  • the Tag field used for marking the Head/Tail TLP and for indicating the Local group ID in a Memory Write TLP header is shown Table 4 below.
  • the Tag field comprises the H, T and GLID fields.
  • H field occupy one bit of the Tag field, like bit 7, indication of a Head TLP of a logical group.
  • T field occupy one bit of the Tag field, like bit 6, indication of a Tail TLP of a logical group.
  • LGID field occupy five bits of the Tag field, like bits 5:0, identifier of a local group segmented by the Write Requester, i.e. the transmission device, it is allocated when the transmission device segments and maps the big data to a logical group.
  • the Memory Write TLPs (as shown in Table 4) are associated with a logical group of TLPs using Requester ID and LGID from received packet.
  • the LGID uniquely identifies the logical group segmented and mapped by the Write Requester
  • the logical group ID therefore can globally and uniquely indicate each logical group from each Requester, i.e., transmission device
  • the reception device is enabled to uniquely and globally identify each logical group from each transmission device.
  • the Tag field of the Memory Write TLP header and other fields show in Table 4 are as same as the PCIe® Base Specification, like version 3.0.
  • the attachment of a "suffix" field for each TLP is supported.
  • the suffix can be used to store any TLP meta-data including the GECRC field.
  • the TLP suffix can be standardized as part of a separate PCIe
  • the TLP suffix may have attributes similar to the existing TLP prefix feature but it may be located after the end of the TLP payload (as opposed to the TLP prefix which may be located before the TLP header).
  • Table 5 shows a generic TLP consisting of one or more optional TLP Prefixes, a TLP header, a data payload (for some types of packets), and an optional TLP digest.
  • the presence of the TLP Suffix such as the GECRC, is signaled through a SuffixPresent bit in the TLP header.
  • the TLP suffix is carried in the TLP digest field, the SuffixPresent bit might be a Reserved bit R in the TLP header as shown in Table 5.
  • TLP Digest in the form of a single DW at the end of the TLP used for carrying the TLP suffix.
  • SuffixPresent field one bit, a Reserved bit in the TLP header.
  • the ECRC field may be used to store the GECRC.
  • the TD bit may be set for a Tail TLP that includes a GECRC.
  • This method may require adding another bit in the TLP header to indicate whether ECRC or GECRC is included in the case that the TD bit is set.
  • the TLP digest field is used for carrying the GECRC, the TD and new bit in TLP header indicates the present of GECRC as shown in Table 6.
  • TLP Digest in the form of a single DW at the end of the TLP, used for carrying the GECRC.
  • the receiving device 420/520 is also called receiver, or sink point, or destination.
  • the transmission device 410/510 is also called transmitter, or sender, or source.
  • the TLP is used mere as an example of the data unit, the invention applies to also to other kinds of data units. From the foregoing, it will be apparent to those skilled in the art that a variety of methods, systems, computer programs on recording media, and the like, are provided.
  • the present disclosure also supports a computer program product including computer executable code or computer executable instructions that, when executed, causes at least one computer to execute the performing and computing steps described herein.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

L'invention concerne un procédé (100) pour calculer un contrôle de redondance cyclique de bout en bout sur de multiples unités de données, le procédé (100) consistant à : calculer (101) un contrôle de redondance cyclique sur des données utiles d'un groupe logique (300); mapper (103) les données utiles à de multiples unités de données (301, 303, 305, 307); ajouter (105) un résultat (309) du contrôle de redondance cyclique à une unité de données prédéterminée (307) parmi des unités de données; et transmettre (107) les multiples unités de données (301, 303, 305, 307) individuellement.
PCT/EP2013/072373 2013-09-19 2013-10-25 Procédé et dispositif pour un contrôle de redondance cyclique de bout en bout sur de multiples unités de données WO2015039710A1 (fr)

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