WO2015038177A1 - Convertisseur de capacitance en code à haute résolution - Google Patents

Convertisseur de capacitance en code à haute résolution Download PDF

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Publication number
WO2015038177A1
WO2015038177A1 PCT/US2013/076596 US2013076596W WO2015038177A1 WO 2015038177 A1 WO2015038177 A1 WO 2015038177A1 US 2013076596 W US2013076596 W US 2013076596W WO 2015038177 A1 WO2015038177 A1 WO 2015038177A1
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WIPO (PCT)
Prior art keywords
capacitor
charge
comparator
control unit
current generator
Prior art date
Application number
PCT/US2013/076596
Other languages
English (en)
Inventor
Roman Ogirko
Hans Klein
Andriy Maharyta
Original Assignee
Cypress Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/097,138 external-priority patent/US8836669B1/en
Application filed by Cypress Semiconductor Corporation filed Critical Cypress Semiconductor Corporation
Priority to CN201380080204.4A priority Critical patent/CN105849680B/zh
Publication of WO2015038177A1 publication Critical patent/WO2015038177A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Definitions

  • the present disclosure relates generally to sensing systems, and more particularly to capacitance-sensing systems configurable to determine locations of touches on the capacitive-sensing systems.
  • Capacitance sensing systems can sense electrical signals generated on electrodes that reflect changes in capacitance. Such changes in capacitance can indicate a touch event (i.e., the proximity of an object to particular electrodes).
  • Capacitive sense elements may be used to replace mechanical buttons, knobs and other similar mechanical user interface controls. The use of a capacitive sense element allows for the elimination of complicated mechanical switches and buttons, providing reliable operation under harsh conditions.
  • capacitive sense elements are widely used in modern customer applications, providing user interface options in existing products. Capacitive sense elements can range from a single button to a large number arranged in the form of a capacitive sense array for a touch-sensing surface.
  • Transparent touch screens that utilize capacitive sense arrays are ubiquitous in today' s industrial and consumer markets. They can be found on cellular phones, GPS devices, set-top boxes, cameras, computer screens, MP3 players, digital tablets, and the like.
  • the capacitive sense arrays work by measuring the capacitance of a capacitive sense element, and looking for a delta in
  • capacitance indicating a touch or presence of a conductive object.
  • a conductive object e.g., a finger, hand, or other object
  • the capacitance changes of the capacitive touch sense elements can be measured by an electrical circuit.
  • the electrical circuit converts the measured capacitances of the capacitive sense elements into digital values.
  • a touch panel has a distributed load of capacitance of both types (1) and (2) and Cypress' touch solutions sense both capacitances either uniquely or in hybrid form with its various sense modes.
  • Figure 1 is a block diagram illustrating one embodiment of an electronic system having a processing device, including an charge to code converter.
  • Figure 2 is a block diagram of a charge to code converter, according to one embodiment.
  • Figure 3 is a diagram of a charge to code converter, according to another embodiment.
  • Figure 4 is a diagram illustrating signal waveforms of a charge to code converter circuit, according to one embodiment.
  • Figure 5 is a diagram of a charge to code converter, according to another embodiment.
  • Figure 6 is a flow diagram of a method of charge to code conversion, according to an embodiment.
  • Figure 7 is a flow diagram of a method of charge to code conversion, according to another embodiment.
  • FIG. 1 is a block diagram illustrating one embodiment of an electronic system having a processing device, including an charge to code converter. Details regarding the charge to code converter 120 are described in more detail with respect to Figures 2-7.
  • the processing device 110 is configured to detect one or more touches detected proximate to a touch-sensing device, such as capacitive sense array 125.
  • the processing device 110 can detect conductive objects, such as touch objects 140 (fingers or passive styluses, an active stylus 130, or any combination thereof).
  • the capacitance-sensing circuit 101 can measure touch data created by a touch using the capacitive sense array 125.
  • the touch may be detected by a single or multiple sensing cells, each cell representing an isolated sense element or an intersection of sense elements (e.g., electrodes) of the capacitive sense array 125.
  • the touch data is used to generate a 2D capacitive image of the capacitive sense array 125.
  • the capacitance-sensing circuit 101 measures mutual capacitance of the touch-sensing device (e.g., using capacitive sense array 125)
  • the capacitance-sensing circuit 101 acquires a 2D capacitive image of the touch-sensing object and processes the data for peaks and positional information.
  • the processing device 110 is a microcontroller that obtains a capacitance touch signal data set from application processor 150, such as from capacitive sense array 125, and finger detection firmware executing on the microcontroller identifies data set areas that indicate touches, detects and processes peaks, calculates the coordinates, or any combination therefore.
  • the microcontroller can report the precise coordinates to an application processor, as well as other information.
  • Electronic system 100 includes processing device 110, capacitive sense array 125, stylus 130, and application processor 150.
  • the capacitive sense array 125 may include capacitive sense elements that are electrodes of conductive material, such as copper.
  • the sense elements may also be part of an indium tin oxide (ITO) panel.
  • the capacitive sense elements can be used to allow the capacitance-sensing circuit 101 to measure self-capacitance, mutual capacitance, or any combination thereof.
  • the electronic system 100 includes the capacitive sense array 125 coupled to the processing device 110 via bus 122.
  • the capacitive sense array 125 may include a multi-dimension capacitive sense array.
  • the multi-dimension sense array includes multiple sense elements, organized as rows and columns.
  • the multi-dimension sense array operates as an all-points-addressable ("APA") mutual capacitive sense array.
  • the capacitive sense array 125 is non-transparent capacitive sense array (e.g., PC touchpad).
  • the capacitive sense array 125 may be disposed to have a flat surface profile.
  • the capacitive sense array 125 may have non-flat surface profiles.
  • other configurations of capacitive sense arrays may be used.
  • the capacitive sense array 125 may have a hexagon arrangement, or the like, as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure.
  • the capacitive sense array 125 may be included in an ITO panel or a touch screen panel.
  • the processing device 1 10 is configurable to detect a presence of the touch object 140, a presence of a stylus 130 on the capacitive sense array 125, or any combination thereof. If the touching object is an active stylus, in one embodiment, the active stylus 130 is configurable to operate as the timing "master," and the processing device 1 10 adjusts the timing of the capacitive sense array 125 to match that of the active stylus 130 when the active stylus 130 is in use. In one embodiment, the capacitive sense array 125 capacitively couples with the active stylus 130, as opposed to conventional inductive stylus applications. It should also be noted that the same assembly used for the capacitive sense array 125, which is configurable to detect touch objects 140, is also used to detect and track a stylus 130 without an additional PCB layer for inductively tracking the active stylus 130.
  • the processing device 110 includes analog and/or digital general purpose input/output ("GPIO") ports 107.
  • GPIO ports 107 may be programmable.
  • GPIO ports 107 may be coupled to a Programmable
  • Interconnect and Logic which acts as an interconnect between GPIO ports 107 and a digital block array of the processing device 1 10 (not shown).
  • the digital block array may be configurable to implement a variety of digital logic circuits (e.g., DACs, digital filters, or digital control systems) using, in one embodiment, configurable user modules ("UMs").
  • the digital block array may be coupled to a system bus.
  • Processing device 1 10 may also include memory, such as random access memory (“RAM”) 105 and program flash 104.
  • RAM 105 may be static RAM (“SRAM”)
  • program flash 104 may be a non-volatile storage, which may be used to store firmware (e.g., control algorithms executable by processing core 102 to implement operations described herein).
  • Processing device 1 10 may also include a memory controller unit ("MCU") 103 coupled to memory and the processing core 102.
  • the processing core 102 is a processing element configured to execute instructions or perform operations.
  • the processing device 1 10 may include other processing elements as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure.
  • the memory may be internal to the processing device or external to it. In the case of the memory being internal, the memory may be coupled to a processing element, such as the processing core 102. In the case of the memory being external to the processing device, the processing device is coupled to the other device in which the memory resides as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure.
  • the processing device 1 10 may also include an analog block array (not shown)(e.g., field-programmable analog array).
  • the analog block array is also coupled to the system bus.
  • Analog block array may also be configurable to implement a variety of analog circuits (e.g., ADCs or analog filters) using, in one embodiment, configurable UMs.
  • the analog block array may also be coupled to the GPIO 107.
  • capacitance-sensing circuit 101 may be integrated into processing device 110.
  • Capacitance-sensing circuit 101 may include analog I/O for coupling to an external component, such as touch-sensor pad (not shown), capacitive sense array 125, touch-sensor slider (not shown), touch-sensor buttons (not shown), and/or other devices.
  • the capacitance-sensing circuit 101 may be configurable to measure capacitance using mutual-capacitance sensing techniques, self-capacitance sensing technique, charge coupling techniques or the like.
  • capacitance-sensing circuit 101 operates using a charge accumulation circuit, a capacitance modulation circuit, or other capacitance sensing methods known by those skilled in the art.
  • the capacitance-sensing circuit 101 is of the Cypress TMA-3xx, TMA-4xx, or TMA-xx families of touch screen controllers. Alternatively, other capacitance-sensing circuits may be used.
  • the mutual capacitive sense arrays, or touch screens, as described herein, may include a transparent, conductive sense array disposed on, in, or under either a visual display itself (e.g. LCD monitor), or a transparent substrate in front of the display.
  • the TX and RX electrodes are configured in rows and columns, respectively. It should be noted that the rows and columns of electrodes can be configured as TX or RX electrodes by the capacitance-sensing circuit 101 in any chosen combination.
  • the TX and RX electrodes of the sense array 125 are configurable to operate as a TX and RX electrodes of a mutual capacitive sense array in a first mode to detect touch objects, and to operate as electrodes of a coupled-charge receiver in a second mode to detect a stylus on the same electrodes of the sense array.
  • the stylus which generates a stylus TX signal when activated, is used to couple charge to the capacitive sense array, instead of measuring a mutual capacitance at an intersection of a RX electrode and a TX electrode (a sense element) as done during mutual-capacitance sensing.
  • An intersection between two sense elements may be understood as a location at which one sense electrode crosses over or overlaps another, while maintaining galvanic isolation from each other.
  • the capacitance associated with the intersection between a TX electrode and an RX electrode can be sensed by selecting every available combination of TX electrode and RX electrode.
  • a touch object such as a finger or stylus
  • the object causes a decrease in mutual capacitance between some of the TX/RX electrodes.
  • the presence of a finger increases the capacitance of the electrodes to the environment (Earth) ground, typically referred to as self-capacitance change.
  • the location of the finger on the capacitive sense array 125 can be determined by identifying the RX electrode having a decreased coupling capacitance between the RX electrode and the TX electrode to which the TX signal was applied at the time the decreased capacitance was measured on the RX electrode. Therefore, by sequentially determining the capacitances associated with the intersection of electrodes, the locations of one or more touch objects can be determined. It should be noted that the process can calibrate the sense elements (intersections of RX and TX electrodes) by
  • the capacitance-sensing circuit 101 includes the charge to code converter 120. Additional details of the charge to code converter 120 are described below with respect to Figures 2-7.
  • Processing device 110 may include internal oscillator/clocks 106 and communication block ("COM") 108.
  • the processing device 110 includes a spread- spectrum clock (not shown).
  • the oscillator/clocks block 106 provides clock signals to one or more of the components of processing device 110.
  • Communication block 108 may be used to communicate with an external component, such as an application processor 150, via application interface ("I/F") line 151.
  • Processing device 110 may reside on a common carrier substrate such as, for example, an integrated circuit ("IC") die substrate, a multi-chip module substrate, or the like. Alternatively, the components of processing device 110 may be one or more separate integrated circuits and/or discrete components.
  • processing device 1 10 is the Programmable System on a Chip (PSoC®) processing device, developed by Cypress Semiconductor
  • processing device 110 may be one or more other processing devices known by those of ordinary skill in the art, such as a microprocessor or central processing unit, a controller, special-purpose processor, digital signal processor ("DSP"), an application specific integrated circuit (“ASIC”), a field programmable gate array (“FPGA”), or the like.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • processing device 1 10 may also be done in the application processor.
  • Capacitance-sensing circuit 101 may be integrated into the IC of the processing device 110, or alternatively, in a separate IC. Alternatively, descriptions of capacitance-sensing circuit 101 may be generated and compiled for
  • behavioral level code describing the capacitance-sensing circuit 101 may be generated using a hardware descriptive language, such as VHDL or Verilog, and stored to a machine-accessible medium (e.g., CD-ROM, hard disk, floppy disk, etc.).
  • a hardware descriptive language such as VHDL or Verilog
  • the behavioral level code can be compiled into register transfer level (“RTL") code, a netlist, or even a circuit layout and stored to a machine- accessible medium.
  • RTL register transfer level
  • the behavioral level code, the RTL code, the netlist, and the circuit layout may represent various levels of abstraction to describe capacitance- sensing circuit 101.
  • components of electronic system 100 may include all the components described above. Alternatively, electronic system 100 may include some of the components described above.
  • the electronic system 100 is used in a tablet computer.
  • the electronic device may be used in other applications, such as a notebook computer, a mobile handset, a personal data assistant ("PDA"), a keyboard, a television, a remote control, a monitor, a handheld multi-media device, a handheld media (audio and/or video) player, a handheld gaming device, a signature input device for point of sale transactions, an eBook reader, global position system (“GPS”) or a control panel.
  • PDA personal data assistant
  • the embodiments described herein are not limited to touch screens or touch-sensor pads for notebook implementations, but can be used in other capacitive sensing implementations, for example, the sensing device may be a touch-sensor slider (not shown) or touch-sensor buttons (e.g., capacitance sensing buttons). In one embodiment, these sensing devices include one or more capacitive sensors or other types of capacitance-sensing circuitry.
  • the operations described herein are not limited to notebook pointer operations, but can include other operations, such as lighting control (dimmer), volume control, graphic equalizer control, speed control, or other control operations requiring gradual or discrete adjustments.
  • capacitive sensing implementations may be used in conjunction with non-capacitive sensing elements, including but not limited to pick buttons, sliders (ex. display brightness and contrast), scroll-wheels, multi-media control (ex. volume, track advance, etc.) handwriting recognition, and numeric keypad operation.
  • FIG. 2 is a block diagram of a charge to code converter, according to one embodiment.
  • the charge to code converter 120 includes an attenuator circuit 220, an integration circuit 230, and a converter 240.
  • the converter 240 is a charge-balancing converter as described herein.
  • other circuits can be used to convert an input signal into a digital value.
  • the charge to code converter 120 may be part of a touchscreen controller coupled to an indium-tin-oxide (ITO) panel (or other sense array, like capacitive sense array 125, described above).
  • ITO indium-tin-oxide
  • the touch screen controller measures input current from the capacitive sense array 125 and based on input current, calculates the touch position.
  • the signals received from the capacitive sense array 125 can be attenuated by the attenuator circuit 220 before being input into the integration circuit 230.
  • the integration circuit 230 integrates the attenuated signal and inputs the resulting signal into the converter 240.
  • the converter 240 converts the integrated signal into a digital value, for example digital output code 250. This digital value can be processed further by the processing device 110 or the application processor 150.
  • the digital value represents a capacitance measured on the capacitive sense array 125 for purposes of detecting touches on the capacitive sense array 125 by one or more conductive objects, as well as positions of the touches, gestures by
  • FIG. 3 is a diagram of a charge to code converter, according to another embodiment.
  • Charge to code converter 120 includes an attenuator circuit 220, an integration circuit 230, and a converter 240.
  • Attenuator circuit 220 receives a signal from capacitive sense array 125.
  • Attenuator circuit 220 attenuates the signal to produce an attenuated output charge at an attenuator output 312.
  • the attenuated output charge is integrated at a first capacitor 321 (i.e., integrate/sample), creating a first capacitor voltage.
  • the first capacitor 321 is switched from position Intl 353 to Ball 352 in order to disconnect the first capacitor 321 from attenuator circuit 220, and connect the first capacitor 321 to comparator 331.
  • the first capacitor voltage of the first capacitor 321 is compared to a reference voltage (Vref 320).
  • Comparator 331 produces a first comparator output at comparator output 340 based on the comparison.
  • the control unit 332 receives the first comparator output from comparator 331.
  • the control unit 332 signals the current generator 333 to either charge or discharge (i.e., balance) the first capacitor 321.
  • the charge balancing period is the length of time a capacitor is charged or discharged.
  • the control unit 332 measures the time the current generator 333 charges or discharges the first capacitor 321 to an original voltage (i.e., a charge balancing period).
  • the charge balancing period can be measured by counter 360 and converted to a digital output code 250.
  • counter 360 may be part of control unit 332.
  • the charge-balancing is achieved in two phases.
  • a first phase e.g., sampling phase
  • an attenuated output charge from attenuator output 312 is stored on a first capacitor 321.
  • the first capacitor 321 is rebalanced (e.g., first capacitor 321 to position Ball 352) to its original value using a constant current source (e.g., current generator 333).
  • integration circuit 230 contains a first capacitor 321 and a second capacitor 322.
  • Charge to code converter 120 is configured to alternately integrate charge (i.e., sample) on one of the first capacitor 321 or second capacitor 322 while balancing charge on the other of the first capacitor 321 or second capacitor 322.
  • the charge balancing period is measured for each of the first capacitor 321 and the second capacitor 322.
  • Counter 360 converts the charge balancing period into a digital output code 250.
  • charge to code converter 120 can be said to comprise of two converters.
  • a first converter e.g., using a first capacitor 321 samples an attenuated signal from attenuator circuit 220 in one phase, while the second converter balances a previously sampled charge on second capacitor 322, and vice versa (i.e., ping-pong operation).
  • the dual nature of the charge to code converter 120 allows for continuous integration of an input signal, for example attenuated signal from attenuator circuit 220. Ping-pong operation is advantageous for narrow receiver bandwidth, and offers much improved noise rejection over a single-converter implementation.
  • Attenuator circuit 220 charges the integrating capacitors, first capacitor 321 or second capacitor 322, for rising and falling excitation signals edges separately.
  • a balancing circuit contains current generator 333 having two current sources (e.g., Ibalp 334 and Ibaln 335), and switch SW1 336. Switch SW1 336 is controlled by the control unit 332.
  • the balancing current direction (sourcing or sinking) of current generator 333 is defined by the output of comparator 331 at the outset of the balancing phase and controlled by control unit 332.
  • the charge balancing period stops after the comparator changes its state, synchronously latched by the system clock, e.g., clock 341.
  • the input signal from attenuator circuit 220 to the integration circuit 230 is provided by a programmable current-mode attenuator circuit, delivering an incoming charge signal onto an integrating (e.g., sampling) capacitor (e.g., the first capacitor 321).
  • an integrating (e.g., sampling) capacitor e.g., the first capacitor 321.
  • the combination of a current-mode signal from attenuator circuit 220 stored onto a capacitor (e.g., first capacitor 321) forms an integrator.
  • Making attenuator circuit 220 programmable provides for an adaptive mechanism to deal with small and large signals from capacitive sense array 125.
  • charge to code converter 120 can implement physically small integrating capacitors (e.g., first capacitor 321 and second capacitor 322), decreasing the physical RX channel size significantly, thus reducing cost.
  • charge-balancing allows the integration circuit 230 to use nonlinear capacitors, such as capacitors based on MOS gate-oxide capacitance. Capacitors based on such MOS capacitance are typically much smaller than linear (e.g., metal-metal) capacitors, and results in further die-size reduction.
  • the programmable attenuator for example, attenuator circuit 220, scales an incoming current from capacitive sense array 125.
  • the output of attenuator circuit 220 behaves like a current source, which by definition is a circuit delivering the expected output current regardless of the voltage at its output (i.e., a high output impedance circuit).
  • Such current-mode output allows the attenuator circuit 220 to be used as part of an active integrator.
  • the attenuator circuit 220 can charge a capacitance (e.g., the first capacitor 321 and second capacitor 322) with current, which is equivalent to a capacitor charged by an opamp-based integrator, but without the need for an opamp, thus saving area and power.
  • a capacitance e.g., the first capacitor 321 and second capacitor 322
  • charge to code converter 120 allows for the accumulation of the quantization error of each individual conversion to carrying over to the next conversion (e.g., accumulating a quantization error over successive charge balancing periods). Accumulating quantization error allows charge to code converter 120 to increase converter resolution proportional to total conversion time (i.e., the sum of all previous conversions, until eventually the converter system is reset).
  • residual error of an individual charge-balancing action is accumulated on the integration capacitor (e.g., first capacitor 321 and second capacitor 322), rather than reset (e.g., to "zero" or reference voltage 320), as is typically done with conventional converters.
  • the integration capacitor e.g., first capacitor 321 and second capacitor 322
  • reset e.g., to "zero" or reference voltage 320
  • the accumulation technique equates to a single conversion error out rather than the sum of all previous conversion errors. This translates into a small LSB error, such as one count out of 10,000.
  • the balancing duration (e.g., charge balancing period) is synchronized with the system clock (e.g., clock 341).
  • the current generator 333 generates a certain constant charge packet for every clock period; which is equivalent to a quantization step (i.e., an LSB).
  • the charge- balancing period stops when the comparator input crosses the reference voltage.
  • the balancing period may be one count too long. This means that the balancing current does not perfectly balance the charge on the first capacitor 321 or second capacitor 322, and leaves a small error.
  • the integrating capacitor (e.g., first capacitor 321 and second capacitor 322) stores a residual charge which is the difference between the incoming charge and quantized balancing charge. Then, at the next conversion cycle, the integration circuit 230 collects a new incoming charge plus the previous quantization error. In other words, every following conversion contains a quantization error from the previous conversion. Thus, subsequent conversions will eventually make up for the sum of all previous quantization errors, except for the very last conversion. This means that charge to code converter 120 will have a quantization error of typically just 1 count (1 LSB). The longer the total number of subsequent conversions, the larger the total signal count.
  • quantization error accumulation of charge to code converter 120 allows the converter resolution to increase proportionally to total accumulation time.
  • the charge balancing period is measured by a counter 360, such as a high-speed counter (e.g. using 48 MHz system clock).
  • any subsequent conversions can be added up (accumulated) so as to form one major data point.
  • charge to code converter 120 collects samples from 50 TX (i.e., transmission) cycles (thus 100 edges), all accumulated in a single total count, for example, 10,000.
  • converter 240 includes two comparators (not shown). This configuration may be called the "dual-comparator" approach.
  • each of the two comparators is coupled to one of the capacitors of integration circuit 230.
  • a first comparator operates for first capacitor 321
  • a second comparator operates for second capacitor 322.
  • some of the parasitic effects on the input node of a comparator are reduced when the respective capacitors (e.g., first capacitor 321 and second capacitor 322) are balanced.
  • capacitive sense array 125 is represented by an equivalent circuit that, for illustration, mimics the RX and TX lines resistances and self-capacitances (Rrx, Crx, Rtx and Ctx, respectively) of an actual sensor panel. Additionally, control unit 332 forms all control signals in the converter and also generates the excitation signal TX. Control unit 332 is synchronized by the system clock, e.g., clock 341.
  • FIG. 4 is a diagram illustrating signal waveforms of a charge to code converter circuit, according to one embodiment.
  • the two integrating capacitors, first capacitor 321 and second capacitor 322 are connected to the attenuator output 312 or to the comparator input 343, sequentially.
  • the two switches, SW2 323 and SW3 324, are toggling the two integrating capacitors (e.g., first capacitor 321 and second capacitor 322) between the attenuator output 312 and comparator input 343.
  • the toggling is controlled by signal Ball 352, Bal2 354, Intl 353 and Int2 354 coming from a state machine of the control unit 332.
  • Intx (e.g., Intl 353 and Int2 355) represents a signal for which the capacitor (e.g., first capacitor 321 and second capacitor 322) is connected to the attenuator output 312.
  • the Balx (e.g., Ball 352 and Bal2 354) represents a signal for which the capacitor (e.g., first capacitor 321 and second capacitor 322) is connected to comparator input 343.
  • the signals Ball 352 and Int2 355 are in phase.
  • the signals Bal2 354 and Intl 353 are in an opposite phase to that of Ball 352 and Int2 355.
  • the different phases of integration and balancing allow the charge to code converter 120 to separate the processes of integrating and balancing.
  • the different phases allow the charge to code converter 120 to perform balancing without incoming noise from the sensor.
  • the integrating capacitors are connected to attenuator output 312 synchronous to a corresponding TX (i.e., transmission) edge and disconnected from the attenuator output 312 before a following TX edge.
  • TX i.e., transmission
  • the bold part of the voltage waveforms for the integrating capacitors depict the interaction of these capacitors (i.e., first capacitor 321 and second capacitor 322) with the attenuator output 312 during charge integration.
  • the balancing current direction of Ibal 350 is directly dependent on the comparator state (e.g., comparator 331).
  • the balancing current is controlled by signal Bins 344 from control unit 332.
  • charge to code converter 120 contains two switches, SW4 355 and SW5 356, that connect the attenuator output 312 and comparator input 343 to the reference voltage source (i.e., Vref 320).
  • the control of SW4 355 and SW5 356 is performed by control unit 332 with signals Res 357 and Init 351.
  • Switch SW4 355 on the attenuator output 312 is dedicated to prevent charge sharing between the attenuator circuit 220 and integrating capacitor (e.g., first capacitor 321 and second capacitor 322) after toggling the capacitors (e.g., first capacitor 321 and second capacitor 322). In normal operation, the capacitor (e.g., first capacitor 321 and second capacitor 322) connected to comparator 331 is nearly completely discharged.
  • the voltage at attenuator output 312 differs from the reference voltage (Vref 320) at the TX pulse end.
  • attenuator output 312 has a parasitic capacitance to ground. Consequently, voltage at the attenuator output 312 does not change after disconnecting the integrating capacitor (e.g., first capacitor 321 and second capacitor 322).
  • Attenuator output 312 is connected to the reference voltage (i.e. Vref 320) for a short time to discharge the parasitic capacitance. Consequently, charge on the parasitic capacitance at the attenuator output 312 is constant after every conversion. A subsequent conversion is not disturbed by a charge remaining on the parasitic capacitance from a previous conversion.
  • the duration of signal Init 351 can be used to reduce the integration time, resulting in a change of the channel frequency response.
  • the second switch, SW5 356 optionally allows charge to code converter 120 to change converter behavior when an overload occurs.
  • Overload means a situation when the balancing duration is longer than the TX half-period.
  • the integrating capacitor e.g., first capacitor 321 and second capacitor 322 contains a charge after the balancing period is stopped but before the following TX edge.
  • overload occurs when an external noise charges the integrating capacitor.
  • the integrating capacitor (e.g., first capacitor 321 and second capacitor 322) of the charge to code converter 120 is never reset (i.e., balancing option A).
  • the integrating capacitor (e.g., first capacitor 321 and second capacitor 322) of the charge to code converter 120 is tested after an overload situation (i.e., balancing option B) and reset based on a detected overload.
  • FIG. 5 is a diagram of a charge to code converter, according to another embodiment.
  • Charge to code converter 500 has been configured to allow for the measuring of sensor self-capacitance (e.g., capacitive sense array 125).
  • the charge to code converter 120 is supplemented with two voltage sources (Vbias_l 510, Vbias_h 51 1) and switch SW6 512.
  • Switch SW6 512 is controlled by the excitation control signal (e.g., control signal 570) and toggles between the two voltage sources (i.e., Vbias_l 510 and Vbias_h 51 1).
  • the switching of SW6 512 modulates the attenuator circuit 220 with a swing equal to Vbias_h 511 less Vbias_l 510.
  • Every edge of the modulation leads to a recharging of the sensor self-capacitance (e.g., of capacitive sense array 125).
  • the recharging current is mirrored at the attenuator output stage (e.g., attenuator output 312).
  • the attenuator output current charges the integrating capacitor (e.g., first capacitor 321 and second capacitor 322) with charge that is proportional to charge variation in the sensor (e.g., capacitive sense array 125).
  • the integrating capacitor e.g., first capacitor 321 and second capacitor 322
  • the switching and balancing of the integrating capacitors is the same operation that was described previously in Figure 3 and 4.
  • the attenuator modulation voltage (i.e., Vbias_l 510 and Vbias_h 511) transfers through the TX buffer (i.e., Txbuf 380, an element with unity gain , note that the TX buffer may be called a Shield Buffer) to the sensor TX electrodes (e.g., of capacitive sense array 125).
  • TX buffer i.e., Txbuf 380, an element with unity gain , note that the TX buffer may be called a Shield Buffer
  • the configuration creates the same voltage on both sides of the sensor' s (e.g., capacitive sense array 125) mutual capacitances and excludes the mutual capacitance values from being charged.
  • the sensing capacitance of capacitive sense array 125 is significantly reduced and side effects of sensor mutual capacitance variation are removed.
  • Figure 6 is a flow diagram of a method 600 of charge to code
  • the method 600 may be performed by processing logic that may comprise hardware (circuitry, dedicated logic, etc.), software (such as is run on a general purpose computing system or a dedicated machine), firmware (embedded software), or any combination thereof.
  • the processing device 110 performs the method 600.
  • the charge to code converter 120 performs method 600.
  • other components of the electronic system 100 perform some or all of the operations of method 600.
  • Method 600 begins at block 605 wherein an attenuator circuit 220 attenuates an input charge from for example, capacitive sense array 125, to produce an attenuated output charge at the attenuator output 312, according to one embodiment.
  • Method 600 continues to block 610 by supplying the attenuated output charge to first capacitor 321.
  • first capacitor 321 integrates the attenuated output charge from attenuator 311.
  • the first capacitor voltage on the first capacitor 321 is compared to a reference voltage (e.g., Vref 320) at comparator 331 to produce a first comparator output based on a first comparison.
  • Vref 320 reference voltage
  • First capacitor 321 is switched from the attenuator output 312 to comparator input 343 by switch SW2 323.
  • the current generator 333 balances charge on the first capacitor 321 based on the first comparator output of the first comparison.
  • Current generator 333 may either sink charge or source charge.
  • Control unit 332 controls current generator 333 based on the output of comparator 331.
  • control unit 332 measures a charge balancing period based on the charge balancing on the first capacitor 321 by the current generator 333.
  • the control unit 332 controls the charge balancing on the first capacitor 321 by current generator 333, by control signal, Bins 344.
  • the control unit 332 controls the current generator 333 based on the first comparator output of comparator 331.
  • a quantization error is accumulated over successive charge balancing periods on the integration capacitors (e.g., first capacitor 321 and second capacitor 322).
  • the charge balancing period is converted into a digital output code 250.
  • the charge balancing period is counted by a high-speed counter, for example counter 360.
  • the method 600 may be used with two integrating capacitors (e.g., first capacitor 321 and second capacitor 322).
  • Charge to code converter 120 may alternately integrate charge on one of the first capacitor 321 or the second capacitor 322 while balancing charge on another of the first capacitor 321 or the second capacitor 322.
  • FIG. 7 is a flow diagram of a method of charge to code conversion, according to an embodiment.
  • the method 700 may be performed by processing logic that may comprise hardware (circuitry, dedicated logic, etc.), software (such as is run on a general purpose computing system or a dedicated machine), firmware (embedded software), or any combination thereof.
  • the processing device 110 performs the method 700.
  • the charge to code converter 120 performs the method 700.
  • other components of the electronic system 100 perform some or all of the operations of method 700.
  • the method 700 describes the balancing of multiple integrating capacitors (e.g., first capacitor 321 and second capacitor 322).
  • Method 700 shows two main "event tracks" applied to charge to code converter 120, illustrating the "ping-pong" method mentioned before.
  • an input charge is received from a capacitive sense array 125.
  • the input charge is attenuated at attenuator circuit 220 and transformed to an attenuated output charge.
  • the first capacitor track begins by connecting the first capacitor 321 to attenuator circuit 220 and
  • the second capacitor track starts in the opposite manner.
  • the second capacitor 322 begins by being balanced by the current generator 333 while the first capacitor 321 is being integrated.
  • the second capacitor 322 is disconnected from current generator 333 and either continues proceeding to block 735 or ends.
  • the first capacitor 321 is disconnect from the attenuator output 312 and reconnected to the current generator 333.
  • the second capacitor 322 is connected to the attenuator output 312 and integrates the attenuated input signal.
  • the first capacitor 321 is charged or discharged by the current generator 333 and the charge balancing period is measured by the control unit 332.
  • the second capacitor 322 is disconnected from the attenuator circuit 220. In one embodiment, the second capacitor 322 may continue the second capacitor track.
  • the first capacitor 321 is disconnected from the current generator 333 and either continues the sampling and balancing operation or ends.
  • FIGS . 6 through 7 are flow diagrams illustrating methods for charge to code conversion.
  • the methods are depicted and described as a series of acts.
  • the operations of the methods herein are shown and described in a particular order, such order does not mean that such operations are necessarily performed in that order.
  • Operations in accordance with this disclosure can occur in various orders and/or concurrently, and with other acts not presented and described herein. Certain operations may be performed, at least in part, concurrently with other operations and certain operations may be performed in an inverse order to that shown or described.
  • the capacitive touch screen controller is the TrueTouch® capacitive touchscreen controller, such as the CY8CTMA3xx family of TrueTouch® Multi-Touch All- Points touchscreen controllers, developed by Cypress Semiconductor Corporation of San Jose, California.
  • the TrueTouch® capacitive touchscreen controllers sensing technology to resolve touch locations of multiple fingers and a stylus on the touch-screens, supports operating systems, and is optimized for low-power multi-touch gesture and all-point touchscreen functionality.
  • the touch position calculation features may be implemented in other touchscreen controllers, or other touch controllers of touch-sensing devices.
  • the touch position calculation features may be implemented with other touch filtering algorithms as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure.
  • the embodiments described herein may be used in various designs of mutual-capacitance sensing arrays of the capacitance sensing system, or in self- capacitance sensing arrays.
  • the capacitance sensing system detects multiple sense elements that are activated in the array, and can analyze a signal pattern on the neighboring sense elements to separate noise from actual signal.
  • the embodiments described herein are not tied to a particular capacitive sensing solution and can be used as well with other sensing solutions, including optical sensing solutions, as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure.
  • example or “exemplary” are used herein to mean serving as an example, instance or illustration. Any aspect or design described herein as “example' or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words “example” or “exemplary” is intended to present concepts in a concrete fashion.
  • the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, "X includes A or B" is intended to mean any of the natural inclusive permutations.
  • Embodiments descried herein may also relate to an apparatus for performing the operations herein.
  • This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer.
  • a computer program may be stored in a non-transitory computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, flash memory, or any type of media suitable for storing electronic instructions.
  • computer-readable storage medium should be taken to include a single medium or multiple media (e.g., a centralized or distributed database and/or associated caches and servers) that store one or more sets of instructions.
  • the term “computer- readable medium” shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by the machine and that causes the machine to perform any one or more of the methodologies of the present embodiments.
  • the term “computer-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, magnetic media, any medium that is capable of storing a set of instructions for execution by the machine and that causes the machine to perform any one or more of the methodologies of the present embodiments.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

L'invention concerne un circuit d'intégration comprenant un premier condensateur et couplé fonctionnellement à un comparateur. Le comparateur est configuré pour comparer une tension de premier condensateur du premier condensateur à une tension de référence et pour produire une première sortie de comparateur basée sur la comparaison. Un générateur de courant est couplé fonctionnellement au circuit d'intégration et configuré pour équilibrer la charge sur le premier condensateur. Une unité de commande est couplée fonctionnellement au comparateur et au générateur de courant, et est configurée pour équilibrer la charge sur le premier condensateur en détectant la première sortie de comparateur et pour commander le générateur de courant en se basant sur la première sortie de comparateur.
PCT/US2013/076596 2013-09-13 2013-12-19 Convertisseur de capacitance en code à haute résolution WO2015038177A1 (fr)

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US11531424B2 (en) * 2017-09-07 2022-12-20 Cypress Semiconductor Corporation Nano-power capacitance-to-digital converter

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US20120043971A1 (en) * 2008-02-27 2012-02-23 Cypress Semiconductor Corporation Methods and circuits for measuring mutual and self capacitance

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US20120043971A1 (en) * 2008-02-27 2012-02-23 Cypress Semiconductor Corporation Methods and circuits for measuring mutual and self capacitance

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CN113691251A (zh) * 2020-05-19 2021-11-23 上海复旦微电子集团股份有限公司 电容式感测设备及感测电容的方法

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