WO2015033422A1

WO2015033422A1 - Programmable apparatus power supply voltage management method and programmable apparatus

Info

Publication number: WO2015033422A1
Application number: PCT/JP2013/073948
Authority: WO
Inventors: 豪一小野; 雄介菅野; 長崎　文彦; 則貴小杉; 長田　健一
Original assignee: 株式会社日立製作所
Priority date: 2013-09-05
Filing date: 2013-09-05
Publication date: 2015-03-12

Abstract

Provided are a programmable apparatus and a method for managing the power supply voltage thereof wherein characteristic fluctuations can be compensated for while the area overhead of a monitor circuit for detecting the characteristic fluctuations can be suppressed. For this purpose, first circuit data, which include a monitor circuit for detecting a characteristic parameter having a power supply voltage dependency, and second circuit data including a user circuit are stored into a memory circuit unit (103). Initially, the first circuit data are configured in a programmable circuit (FPGA) (101), and after the monitor circuit detects the characteristic parameter, the second circuit data, instead of the first circuit data, are configured, so that the user circuit operates. The power supply voltage when the user circuit operates is determined on the basis of a detection result of the monitor circuit.

Description

Power supply voltage management method for programmable device and programmable device

The present invention relates to a power supply voltage management method for a programmable device and a programmable device, for example, a power supply voltage management method for a programmable device including an FPGA (Field Programmable Gate Array).

For example, Patent Document 1 discloses a method of monitoring the delay of an LSI critical path and controlling the power supply voltage based on the monitoring result. In Patent Document 2, a ring oscillator for generating a monitoring clock signal and a frequency comparison circuit are provided in the LSI, and the frequency of the monitoring clock signal is compared with the frequency of a reference clock signal input from the outside. A system for controlling the power supply voltage according to the comparison result is shown.

JP 2010-123807 A JP 2008-147274 A

In recent years, with the miniaturization of LSI (Large Scale Integration), transistor variations have increased. Due to the characteristic variation of the LSI caused by this device variation, the operation margin of the LSI is reduced, making it difficult to design compared to the conventional case. In addition, there is a concern that the power consumption increases as the leakage current of the high-speed operation product increases. As one of countermeasures against such a problem, for example, by using a technique such as Patent Document 1 or Patent Document 2, the power supply voltage of the LSI is controlled according to the characteristic variation to compensate for the characteristic variation of the LSI. Conceivable.

The methods such as Patent Document 1 and Patent Document 2 are effective from the viewpoint of compensating for the characteristic variation of the LSI. However, since the monitor circuit for detecting the characteristic variation is mounted on the same LSI in addition to the user circuit for realizing the original function of the LSI, the overhead of the area due to the monitor circuit becomes a problem. In recent years, in programmable devices used in various fields, represented by FPGAs, monitor circuits are less integrated than ASIC (Application Specific Integrated Circuit) and the structure of logic basic cells is determined. In particular, the area of the monitor circuit becomes a problem because the area of the monitor circuit increases excessively.

The present invention has been made to solve such a problem, and one of the purposes is to compensate for characteristic variation while suppressing area overhead of a monitor circuit for detecting characteristic variation. To provide a programmable device and a power supply voltage management method thereof.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

Among the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows.

The programmable device according to the present embodiment includes a programmable circuit that mounts an arbitrary circuit on itself according to circuit data, and a power supply circuit that supplies a power supply voltage to the programmable circuit. The power supply voltage management method for the programmable device includes first to fourth steps. The first step is a step of configuring first circuit data including a first monitor circuit for detecting a characteristic parameter having power supply voltage dependency into a programmable circuit. The second step is a step of detecting the characteristic parameter using the first monitor circuit mounted on the programmable circuit in a state where the first power supply voltage is supplied by the power supply circuit. The third step is a step of configuring the second circuit data including the user circuit that performs a predetermined process into a programmable circuit instead of or in addition to the first circuit data. The fourth step is a step of performing a predetermined process using a user circuit mounted on the programmable circuit in a state where the second power supply voltage is supplied by the power supply circuit. At this time, the second power supply voltage is determined based on the characteristic parameter detected by the first monitor circuit in the second step.

The effects obtained by the representative embodiments of the invention disclosed in the present application will be briefly described. In the programmable device, the characteristic variation is compensated while suppressing the area overhead of the monitor circuit that detects the characteristic variation. Is possible.

In the programmable device by Embodiment 1 of this invention, it is the schematic which shows the structural example of the principal part. It is the schematic which shows the structural example of the monitor circuit mounted in the programmable circuit (FPGA) of FIG. FIG. 3 is a schematic diagram illustrating a configuration example of a variation detection circuit in the monitor circuit of FIG. 2. It is the schematic which shows the structural example of the ring oscillator circuit in FIG. It is the schematic which shows the structural example of the user circuit part mounted in the programmable circuit (FPGA) of FIG. FIG. 2 is a flowchart showing an example of a power supply voltage management method in the programmable device of FIG. 1. FIG. 2 is a schematic diagram illustrating a configuration example of a memory circuit unit in FIG. 1. FIG. 8 is a schematic diagram illustrating a configuration example different from that of FIG. 7 of the memory circuit unit in FIG. 1. 7 and 8 are explanatory diagrams showing an example of variation information stored in the memory circuit unit. In the programmable device of Embodiment 2 by this invention, it is the schematic which shows the structural example of the user circuit part mounted in the programmable circuit. It is the schematic which shows the structural example of the aged deterioration monitor circuit in FIG. In the programmable device of Embodiment 3 by this invention, it is the schematic which shows the structural example of the principal part. It is a flowchart which shows an example of the processing content which the microcomputer performs in the programmable device of FIG. It is the schematic which shows the structural example of the information system which applied it in the programmable device by Embodiment 3 of this invention.

In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted.
(Embodiment 1)
<< Schematic configuration of programmable device >>

FIG. 1 is a schematic diagram showing a configuration example of a main part of a programmable device according to Embodiment 1 of the present invention. A programmable device 104 illustrated in FIG. 1 includes a programmable circuit 101 represented by an FPGA, a variable power supply circuit (PWR) 102, and a memory circuit unit (MEM) 103. The variable power supply circuit 102 generates a power supply voltage to be supplied to the programmable circuit (FPGA) 101. In this example, the value of the power supply voltage is adjusted by a control signal output from the programmable circuit (FPGA) 101.

The memory circuit unit (MEM) 103 includes, for example, a non-volatile memory such as a flash memory, and has a configuration capable of writing and reading from the programmable circuit (FPGA) 101. As will be described in detail later, the memory circuit unit (MEM) 103 has storage areas for storing first circuit data including a monitor circuit and second circuit data including a user circuit unit (and a user circuit), respectively. And a storage area for storing information from the monitor circuit. The monitor circuit detects a characteristic parameter having power supply voltage dependency, and the user circuit performs a predetermined process determined by the user.

The programmable circuit (FPGA) 101, the variable power supply circuit 102, and the memory circuit unit (MEM) 103 can be realized in various forms. For example, three circuits each composed of three devices, three circuits integrated into one device, or two circuits integrated into one device, The form which comprised the remaining circuit with one device is mentioned. Each device is mounted on the same wiring board, for example. The programmable circuit 101 is not necessarily limited to the FPGA, and may be any reconfigurable circuit that can mount an arbitrary circuit on itself according to circuit data.

In such a configuration, the power supply voltage of the programmable device of FIG. 1 is generally managed as follows. First, first circuit data including a monitor circuit (first monitor circuit) is configured in the programmable circuit (FPGA) 101, and the monitor circuit detects the above-described characteristic parameter. After that, the second circuit data including the user circuit unit (and the user circuit) is configured in the programmable circuit (FPGA) 101 instead of the first circuit data, and the user circuit performs a predetermined process. When the user circuit performs a predetermined process, the variable power supply circuit 102 supplies a power supply voltage determined based on the characteristic parameter detected by the monitor circuit to the programmable circuit (FPGA) 101. This power supply voltage is determined by the programmable circuit (FPGA) 101 in the example of FIG.
<Programmable circuit configuration>

FIG. 2 is a schematic diagram showing a configuration example of a monitor circuit mounted on the programmable circuit (FPGA) of FIG. As described above, the monitor circuit (first monitor circuit) 201 in FIG. 2 is obtained by configuring the first circuit data stored in the memory circuit unit (MEM) 103 in FIG. 1 into a programmable circuit (FPGA). Circuit. The monitor circuit 201 includes a variation detection circuit 202 and a memory controller 203.

The variation detection circuit 202 detects a characteristic parameter having power supply voltage dependency. For example, the characteristic parameter is a delay time of a signal transmitted in the programmable circuit (FPGA) 101, and the variation detection circuit 202 detects variation in the delay time. The characteristic parameter having power supply voltage dependency may be, for example, a power supply current value. However, especially in an FPGA or the like, it is desirable to configure the variation detection circuit 202 with a logic circuit, and therefore, from this point of view, it is beneficial to use a signal delay time.

The variation detection circuit 202 detects the variation in the delay time of the signal and sends the detection result to the memory controller 203. The memory controller 203 writes variation information 205 as a detection result of the variation detection circuit 202 in the memory circuit unit 103 while controlling access to the memory circuit unit 103 by the memory control signal 204. The memory control signal 204 can select which storage area in the memory circuit unit 103 is to be accessed.

FIG. 5 is a schematic diagram showing a configuration example of a user circuit unit mounted on the programmable circuit (FPGA) of FIG. As described above, the user circuit unit 510 in FIG. 5 is a circuit obtained by configuring the second circuit data stored in the memory circuit unit (MEM) 103 in FIG. 1 into a programmable circuit (FPGA). The user circuit unit 510 includes a user circuit 501 that performs processing arbitrarily determined by the user, a memory controller 502, and a variable power supply controller 503. A reset signal 512 is input to the user circuit 501.

The memory controller 502 reads the variation information 509 stored in the memory circuit unit 103 while controlling access to the memory circuit unit 103 by the memory control signal 508. The memory control signal 508 can select which storage area in the memory circuit unit 103 is to be accessed.

The variable power supply controller 503 includes a voltage determination unit 504 and a power supply interface unit 505. The voltage determination unit 504 determines the value of the power supply voltage based on the variation information 509 acquired via the memory controller 502. The power supply interface unit 505 instructs the power supply voltage determined by the voltage determination unit 504 to the variable power supply circuit (PWR) 102 in FIG. 1 via the voltage control signal 507. The voltage setting completion signal 511 is a signal for notifying the outside that the power supply voltage has been changed.
<< Power supply voltage management method for programmable devices >>

FIG. 6 is a flowchart showing an example of the power supply voltage management method in the programmable device of FIG. In the power supply voltage management process of FIG. 6, a series of processing contents executed from the start of the programmable circuit (FPGA) 101 until the power supply voltage is controlled to operate the user circuit is shown. The power supply voltage management process in FIG. 6 is performed at an arbitrary timing that requires compensation for characteristic variation of the programmable circuit (FPGA) 101 after the manufacture of the programmable device 104 in FIG. 1, for example.

In FIG. 6, first, the variable power supply circuit 102 supplies the programmable circuit (FPGA) with a predetermined standard power supply voltage (first power supply voltage) to the programmable circuit (FPGA) 101 and the memory circuit unit 103. 101 is activated (step S101). Next, when the programmable circuit (FPGA) 101 is activated, the first circuit data including the monitor circuit 201 stored in the memory circuit unit 103 is written to the configuration memory in the programmable circuit (FPGA) 101. With this configuration, the monitor circuit 201 of FIG. 2 is mounted on the programmable circuit (FPGA) 101.

Subsequently, the monitor circuit 201 is supplied with the standard value power supply voltage (first power supply voltage) as described above with reference to a predetermined characteristic parameter (here, the programmable circuit (FPGA) 101) (see here). A variation in delay time is detected (step S103). Then, the monitor circuit 201 writes the variation information 205 as the detection result in the memory circuit unit 103 (step S104).

Next, in place of the first circuit data in step S102, the second circuit data including the user circuit unit 510 stored in the memory circuit unit 103 is written into the configuration memory in the programmable circuit (FPGA) 101. (Step S105). With this configuration, the user circuit unit 510 (and user circuit 501) of FIG. 5 is mounted on the programmable circuit (FPGA) 101, and the monitor circuit 201 is completely erased.

Subsequently, the variable power controller 503 in the user circuit unit 510 reads the variation information stored in step S104 from the memory circuit unit 103 via the memory controller 502. The voltage determination unit 504 in the variable power supply controller 503 determines the value of the power supply voltage (second power supply voltage) based on the variation information (step S106).

Next, the power supply interface unit 505 in the variable power supply controller 503 instructs the determined power supply voltage (second power supply voltage) to the variable power supply circuit 102 via the voltage control signal 507 (step S107). In response to this, the variable power supply circuit 102 generates the power supply voltage (second power supply voltage). Further, the variable power supply controller 503 notifies the outside that the power supply voltage has been changed via the voltage setting completion signal 511.

For example, in response to the voltage setting completion signal 511, the reset signal 512 input to the user circuit 501 in the user circuit unit 510 is canceled. Thereby, the user circuit 501 starts the operation in a state where the power supply voltage (second power supply voltage) set in step S107 is supplied (step S108).

By using the power supply voltage management method as described above, the characteristic variation of the programmable circuit (FPGA) 101 can be adjusted by adjusting the power supply voltage without causing the monitor circuit 201 and the user circuit 501 to reside in the programmable circuit (FPGA) 101 at the same time. It becomes possible to compensate. That is, the area overhead of the monitor circuit 201 with respect to the user circuit 501 that can occur in the case of the above-described Patent Document 1 and Patent Document 2 can be eliminated. As a result, the circuit scale that can be used in the user circuit 501 can be relatively increased, and a situation in which power is consumed in the monitor circuit 201 when the user circuit 501 operates can be prevented.

In this example, the optimum power supply voltage (second power supply voltage) is determined and instructed by the variable power supply controller 503 in FIG. 5, but the present invention is not necessarily limited thereto. For example, a circuit unit having a function similar to that of the variable power supply controller 503 may be provided outside the programmable circuit (FPGA) 101. A detailed example thereof will be described later with reference to FIG. 12, and the external circuit unit determines a power supply voltage (second power supply voltage) according to variation information, and then the programmable circuit (FPGA) 101 has a user. Based on the premise that the circuit 501 is mounted, the determined power supply voltage is instructed to the variable power supply circuit 102.

Alternatively, a circuit unit having the same function as the voltage determination unit 504 in the variable power supply controller 503 may be inserted between the variation detection circuit 202 and the memory controller 203 in FIG. In this case, the memory controller 203 in FIG. 2 stores the power supply voltage (second power supply voltage) determined by the circuit unit in the memory circuit unit 103 instead of or in addition to the variation information 205. Then, the power interface 505 in the variable power controller 503 of FIG. 5 simply reads the power voltage stored in the memory circuit unit 103 via the memory controller 502 and sets the power voltage for the variable power circuit 102. .

Further, various methods other than these methods are conceivable. That is, as long as the variable power supply circuit 102 can supply a power supply voltage (second power supply voltage) determined based on the detection result of the monitor circuit 201 in FIG. Any method may be used.
<Configuration of variation detection circuit>

FIG. 3 is a schematic diagram showing a configuration example of the variation detection circuit in the monitor circuit of FIG. The variation detection circuit 202 in FIG. 3 is a circuit that detects variations in signal delay time, as described in FIG. The variation detection circuit 202 includes a ring oscillator block 301, a selector 302, a statistical processing unit 303, a data memory 304, and a control unit 305. Ring oscillator block 301 includes a plurality of ring oscillator circuits RO [1] to RO [n].

The control unit 305 controls operations of the ring oscillator block 301, the selector 302, the statistical processing unit 303, and the data memory 304. The selector 302 selects one of the output signals (that is, clock signals) of the plurality of ring oscillator circuits RO [1] to RO [n], and outputs the selected output signal to the statistical processing unit 303. The statistical processing unit 303 detects the frequency (in other words, the signal delay time) by counting the clock signal output from the selector 302 for a certain period.

The selector 302 sequentially selects the output signals of the plurality of ring oscillator circuits RO [1] to RO [n], and in response to this, the statistical processing unit 303 selects each ring oscillator circuit RO [1] to RO [n]. Are sequentially detected (signal delay time). The statistical processing unit 303 obtains average values and standard deviations of the frequencies detected from all the ring oscillator circuits RO [1] to RO [n], and outputs both values to the data memory 304. The data memory 304 stores the average value and standard deviation of the frequency and outputs the information as variation information. The average value of the frequency represents the characteristic variation between chips, and the standard deviation of the frequency represents the characteristic variation in the chip.

In FIG. 3, a plurality of ring oscillator circuits are provided in the variation detection circuit 202. However, if at least one ring oscillator circuit is provided, the power supply is based on one detection result (frequency (delay time)). It is possible to determine the voltage. However, in this case, for example, random variations in delay time that occur regularly depending on the placement in the chip due to variations in processing dimensions, etc., and randomness regardless of the placement in the chip due to RTN (Random Telegraph Noise) etc. In addition, it may be difficult to detect variations in delay time that occur randomly on the time axis. As a result, the power supply voltage may become insufficient depending on the arrangement in the chip, or in order to prevent this, an excessive margin is provided in the voltage voltage, and the power consumption becomes unnecessarily large. May occur.

Therefore, in order to detect such a variation in delay time that occurs regularly or randomly, it is beneficial to provide a plurality of ring oscillator circuits RO [1] to RO [n] as shown in FIG. As a result, the degree of variation in delay time that regularly occurs depending on the arrangement in the chip and the degree of variation in delay time that occurs randomly regardless of the arrangement in the chip can be detected by the standard deviation. In order to more fully detect the degree of variation in delay time that occurs randomly on the time axis, for example, the operation of sequentially detecting the frequencies of the plurality of ring oscillator circuits RO [1] to RO [n] is fixed. It is also beneficial to calculate the average value and the standard deviation for all the detection results by repeating a plurality of times at intervals.

As shown in FIG. 3, in order to mount the variation detection circuit 202 that can provide a useful detection result on the programmable circuit (FPGA) 101, it is necessary to secure a large mounting area. For example, in the systems such as Patent Document 1 and Patent Document 2 in which the variation detection circuit and the user circuit are resident at the same time, when the monitor circuit is increased in size, problems in area overhead and power consumption for the user circuit may occur. Such a problem does not occur in the system of the form. For this reason, the variation detection circuit 202 as shown in FIG. 3 can be mounted without any problem. In some cases, a plurality of ring oscillator circuits RO [1] to RO [n] are distributed substantially uniformly in the chip. It is also possible. As a result, it is possible to prevent the situation where the power supply voltage is insufficient due to the arrangement in the chip as described above, and the situation where the power consumption becomes excessive by giving the power supply voltage an excessive margin, and the optimality with higher validity. It is possible to determine a correct power supply voltage (second power supply voltage).

Here, an example of a method for determining the optimum power supply voltage (second power supply voltage) will be described. For example, the voltage determination unit 504 in FIG. 5 generates a power supply voltage (frequency average value and standard deviation) according to variation information (frequency average value and standard deviation) obtained from the variation detection circuit 202 in FIG. 3 based on a predetermined table or relational expression. Second power supply voltage) is determined. The table or relational expression is not particularly limited, but the relationship between the average value of the frequency and the power supply voltage required accordingly (referred to as the first relationship), the standard deviation of the frequency, and the response The relationship between the required power supply voltage and the minimum voltage margin (referred to as the second relationship) is shown.

In the first relationship, the lower the average frequency value (in other words, the longer the delay time), the higher the required power supply voltage. In the second relationship, the higher the standard deviation of the frequency, the more necessary. The power supply voltage margin becomes larger. For example, the voltage determination unit 504 receives the average value of the frequencies included in the variation information, determines the power supply voltage based on the first relationship, and further receives the standard deviation of the frequencies included in the variation information, Based on the relationship of 2, the final power supply voltage (second power supply voltage) is determined by adding a predetermined voltage margin to the determined power supply voltage.

FIG. 4 is a schematic diagram showing a configuration example of the ring oscillator circuit in FIG. For example, to configure a ring oscillator circuit with an FPGA, it is common to connect a plurality of lookup tables (LUTs) 401 in a chain. However, when the lookup table (LUT) 401 is chain-connected, logic basic cells are used as many as the number of chain connections, so that each ring oscillator circuit RO [1] to RO [n] (ring oscillator block 301) The area of becomes larger. When the method of this embodiment is used, there is no particular problem even if the area of the ring oscillator block 301 is increased as described above. For example, when the scale of the FPGA is very small, one ring oscillator circuit is used. A smaller area is desirable. For example, if the area of one ring oscillator circuit can be reduced, the number of ring oscillator circuits can be increased correspondingly, and more useful detection results can be obtained.

Therefore, the ring oscillator circuit RO shown in FIG. 4 includes a lookup table (LUT) 401 and a wiring 402. In the lookup table (LUT) 401, for example, a 2-input NAND function is realized, and one of the two inputs of the 2-input NAND function is an enable that controls activation / inactivation of the operation of the ring oscillator circuit RO. A signal EN is input. Further, the output of the lookup table (LUT) 401 is fed back to the other of the two inputs after passing through the wiring 402.

The wiring 402 is realized by wiring inside the FPGA, but actually includes not only the wiring but also a transistor such as a buffer for driving a wiring load or a wiring changeover switch. For the wiring 402, a short-distance wiring near the lookup table (LUT) 401 or a long-distance wiring for connecting to a LUT far from the lookup table (LUT) 401 is used. With the configuration of FIG. 4, the function as a ring oscillator circuit can be realized even with one lookup table (LUT) 401.
<Configuration of memory circuit section>

FIG. 7 is a schematic diagram showing a configuration example of the memory circuit unit in FIG. A memory circuit unit 103 illustrated in FIG. 7 includes a microcomputer 702 and a nonvolatile memory 703 such as a flash memory. The nonvolatile memory 703 includes a first storage area AR [1] for storing the first circuit data including the monitor circuit 201 and a second storage area AR for storing the second circuit data including the user circuit unit 510. [2] and a third storage area AR [3] for storing variation information.

The microcomputer 702 communicates with the programmable circuit (FPGA) 701 using each signal (CFG_CLK, CFG_DATA, CFG_CTL, VER_CLK, VER_DATA, VER_SEL). Signals (CFG_CLK, CFG_DATA, CFG_CTL) are signals for accessing the configurable memory of the programmable circuit (FPGA) 701. The signals (VER_CLK, VER_DATA, VER_SEL) are signals for addressing the nonvolatile memory 703 and transferring variation information.

First, the microcomputer 702 designates the first address of the first storage area AR [1], reads the first circuit data (monitor circuit 201) from the nonvolatile memory 703, and transfers it to the programmable circuit (FPGA) 701. After detecting the variation, the monitor circuit 201 in FIG. 2 changes the signal VER_SEL and starts storing variation information in the nonvolatile memory 703. In response to this, the microcomputer 702 designates the head address of the third storage area AR [3]. When the storage of the variation information in the nonvolatile memory 703 is completed, the microcomputer 702 designates the start address of the second storage area AR [2] and receives the second circuit data (user circuit unit 510) from the nonvolatile memory 703. Read and transfer to programmable circuit (FPGA) 701.

As described above, the microcomputer 702 has a function of appropriately determining the head address of the nonvolatile memory 703 according to each stage of the processing flow of FIG. As one configuration method of the FPGA, there is a method in which the FPGA reads circuit data from the head address of the external nonvolatile memory in response to a configuration start command. In such an FPGA, the memory address cannot be arbitrarily designated, and it may be difficult to use a plurality of circuit data properly. Note that the microcomputer 702 may be replaced with, for example, another FPGA or DSP as long as it has a similar function.

FIG. 8 is a schematic diagram showing a configuration example different from FIG. 7 of the memory circuit portion in FIG. The memory circuit unit 103 illustrated in FIG. 8 includes a nonvolatile memory 802 such as a flash memory. The nonvolatile memory 802 has first to third storage areas AR [1] to AR [3] as in the case of FIG. The programmable circuit (FPGA) 801 communicates with the nonvolatile memory 802 using signals (CFG_CLK, CFG_DATA, CFG_ADDR, CFG_CTL).

First, the programmable circuit (FPGA) 801 specifies the start address of the first storage area AR [1] by the signal CFG_ADDR, reads the first circuit data (monitor circuit 201) from the nonvolatile memory 802, and configures its own configuration. Transfer to the storage memory. Next, after detecting the variation, the monitor circuit 201 in FIG. 2 designates the leading address of the third storage area AR [3] by the signal CFG_ADDR and writes the variation information in the nonvolatile memory 802. Thereafter, the programmable circuit (FPGA) 801 specifies the start address of the second storage area AR [2] by the signal CFG_ADDR, reads the second circuit data (user circuit unit 510) from the nonvolatile memory 802, and configures its own configuration. Transfer to the storage memory.

As another configuration method of the FPGA, there is a method in which the FPGA reads circuit data in a state in which the head address of the external nonvolatile memory is arbitrarily designated. In such a case, the configuration example of FIG. 8 can be applied.

FIG. 9 is an explanatory diagram showing an example of variation information stored in the memory circuit unit in FIGS. 7 and 8. The variation information stored in the third storage area AR [3] has information such as storage number (#), inter-chip variation, intra-chip variation, temperature, power supply voltage, and the like. The storage number (#) is assigned a young number in the oldest order at the time of data acquisition. As described above, the inter-chip variation is an average value of the frequencies detected by the variation detection circuit 202 in FIG. 3, and the intra-chip variation is a standard deviation of the frequency.

The temperature is information from, for example, an FPGA temperature sensor. Since the frequency (delay time of the signal) has temperature dependence, in order to improve accuracy, for example, the average value of the detected frequency is converted into a value at a predetermined temperature, and after this conversion It is desirable to determine the final power supply voltage (second power supply voltage) based on the value of. In this case, for example, temperature information may be included in the variation information 205 in FIG. 2, and a conversion table or conversion formula for converting this temperature into a predetermined temperature may be provided in the voltage determination unit 504 in FIG.

Similarly, the power supply voltage is information from the power supply voltage sensor of the FPGA. The frequency (signal delay time) has power supply voltage dependency in addition to temperature dependency. As shown in the processing flow of FIG. 6, the monitor circuit 201 operates at a predetermined standard power supply voltage (first power supply voltage), but the standard voltage voltage set by the variable power supply circuit 102 and the FPGA are actually set. There may be an error in the power supply voltage supplied. Also, this error may vary in time series. Therefore, in order to further improve the accuracy, the average value of the frequency detected by the monitor circuit 201 with the actual power supply voltage or the like can be converted into a value with the standard power supply voltage, as in the case of temperature dependence. desirable. The specific conversion method and the reflection method are the same as in the case of temperature dependence.

Further, as shown in FIG. 9, the variation information detected by the monitor circuit 201 is sequentially left in a log for each storage number (#), so that the plurality of logs can be used as reference information for system management when a problem occurs, for example. Can be used. However, of course, from the viewpoint of executing the processing flow of FIG. 6, the configuration may be such that one log is used instead of a plurality of logs, and the one log is updated with the latest detection result by the monitor circuit 201. Good.

As described above, the power supply voltage management method of the programmable device according to the present embodiment prepares the circuit to be mounted on the programmable circuit separately for the monitor circuit and the user circuit, and first mounts the monitor circuit to reduce the variation. This is a method of detecting and then mounting a user circuit to control the power supply voltage. As a result, typically, it is possible to compensate for variations in the characteristics of the programmable circuit while suppressing the area overhead of the monitor circuit.

Here, a method of configuring the second circuit data including the user circuit unit (and the user circuit) instead of the first circuit data including the monitor circuit is shown. As a result, the area overhead can be suppressed as described above. For example, when there is a margin in the circuit area, the second circuit data can be configured in addition to the first circuit data. Is possible. In recent years, in a FPGA or the like, it is possible to separately mount a new circuit (that is, a user circuit unit) in a region other than a region where a monitor circuit is mounted, using a function called partial reconfiguration. ing. In this case, when the user circuit unit is mounted, the monitor circuit is not particularly required to operate. Therefore, in order to reduce power consumption, for example, a signal for stopping the operation of the monitor circuit is output to the user circuit unit. You may comprise.
(Embodiment 2)
<< Configuration of programmable circuit (user circuit section) (application example) >>

FIG. 10 is a schematic diagram showing a configuration example of a user circuit unit mounted on the programmable circuit in the programmable device according to the second embodiment of the present invention. In the second embodiment, the user circuit unit 1001 is provided with an aging deterioration monitor circuit (second monitor circuit) 1005, thereby generating a trigger for instructing execution of the power supply voltage management process of FIG. Since the configuration other than the user circuit unit (the configuration of the programmable device 104 in FIG. 1 and the monitor circuit (first monitor circuit) 201 in FIG. 2 and the like) is the same as that in the first embodiment, detailed description thereof is omitted.

The user circuit unit 1001 illustrated in FIG. 10 has a configuration in which an aged deterioration monitor circuit (second monitor circuit) 1005 is added as compared to the user circuit unit 510 illustrated in FIG. Since the configuration in the user circuit unit 1001 other than this is the same as that in the case of FIG. The aging monitor 1005 operates at all times or at regular intervals when the user circuit 501 operates, and monitors aging of characteristic parameters having power supply voltage dependency. The aging deterioration monitor 1005 outputs an alarm signal 1002 when the aging deterioration reaches a certain level. The power supply voltage management process in FIG. 6 may be performed when the alarm signal 1002 is issued.
<Aging deterioration monitor circuit configuration>

FIG. 11 is a schematic diagram showing a configuration example of the aging monitoring circuit in FIG. The aging monitor circuit 1005 includes a ring oscillator circuit (RO) 1101, a frequency measurement unit 1102, a register 1103, and a comparison unit 1104. The ring oscillator circuit 1101 has, for example, the configuration of FIG. 4 as in the case of the variation detection circuit 202 of FIG. The frequency of the output signal (that is, the clock signal) of the ring oscillator circuit 1101 is measured by the frequency measuring unit 1102. The register 1103 stores a frequency reference value. The comparison unit 1104 compares the measurement result of the frequency measurement unit 1102 with the reference value of the register 1103, and outputs an alarm signal 1002 according to the comparison result.

Here, the reference value stored in the register 1103 is the same as that shown in FIG. 11 at the initial stage of step S108 after the user circuit unit 1001 of FIG. 10 is mounted on the programmable circuit (FPGA) 101 in step S105 of FIG. The measurement result (that is, the frequency) by the frequency measurement unit 1102 can be obtained. In this case, the value of the register 1103 is not changed until the processing flow of FIG. 6 is executed again. For example, the measurement result by the frequency measuring unit 1102 is stored in the nonvolatile memory, and is loaded into the register 1103 from the nonvolatile memory. It is good also as composition to do.

The comparison unit 1104 generates an alarm signal 1002 when the fluctuation range between the measurement result by the frequency measurement unit 1102 and the reference value exceeds a predetermined value with the reference value set in the register 1103. . That is, the aging deterioration monitor circuit 1005 has a measurement result (ie, frequency) detected by the aging deterioration monitor circuit 1005 that is greater than or equal to a predetermined width compared to the latest time when the second circuit data including the user circuit unit 1001 is configured. The alarm signal 1002 is generated in the case of transition to.

In addition, the reference value stored in the register 1103 can be a fixed value that represents the allowable maximum frequency and the minimum frequency in some cases. In this case, the comparison unit 1104 generates an alarm signal 1002 when the measurement result (ie, frequency) by the frequency measurement unit 1102 deviates from the range of the minimum frequency to the maximum frequency. When the reference value is a fixed value, unlike the case where the measurement result of the frequency measurement unit 1102 is reflected on the reference value described above, the measurement error generated in the frequency measurement unit 1102 is not reflected on the reference value. For this reason, although the fluctuation range until it reaches the state determined to be degraded from the initial state may occur for each programmable circuit (FPGA) 101, the frequency measurement unit 1102 for each programmable circuit (FPGA) 101 may have different situations. There is no particular problem when the measurement variation is small to some extent.

Since the aging monitor circuit (second monitor circuit) 1005 is resident at the same time as the user circuit 501 unlike the variation detection circuit (first monitor circuit) 202 of FIG. 3, as shown in FIG. It is desirable to configure with a circuit scale smaller than the variation detection circuit (first monitor circuit) 202. From this point of view, it is also useful to apply the configuration example of FIG. 4 to the ring oscillator circuit 1101. The aging deterioration monitor circuit 1005 does not need to obtain various information for determining the optimum power supply voltage value like the variation detection circuit 202, and simply needs to detect the degree of deterioration with a not so high accuracy. Even a configuration including one ring oscillator circuit 1101 can sufficiently achieve the object.

Further, when the alarm signal 1002 is issued, the power supply voltage management process shown in FIG. 6 can be performed in accordance with the alarm signal 1002. As described above, when reflecting the frequency of the ring oscillator circuit 1101 in the register 1103, the power supply voltage management process of FIG. 6 is performed in the same manner as in the first embodiment except for the process of step S108. That is, when the user circuit 501 starts operation in step S108, the aging deterioration monitor circuit 1005 also starts operation, and the frequency of the ring oscillator circuit 1101 at the initial stage is stored in the register 1103. During operation of the user circuit, the aging monitor circuit 1005 operates continuously or periodically, and outputs an alarm signal 1002 when detecting aging deterioration.

As described above, by using the programmable device and the power supply voltage management method according to the second embodiment, in addition to the various effects described in the first embodiment, when the user circuit 501 operates, the deterioration of the aging is further improved. The occurrence can be detected. As a result, it is possible to obtain an opportunity to compensate for the aging deterioration by the method of the first embodiment (that is, the power supply voltage management process of FIG. 6).
(Embodiment 3)
<< Schematic configuration of programmable device (application example) >>

FIG. 12 is a schematic diagram showing a configuration example of the main part of the programmable device according to the third embodiment of the present invention. The programmable device illustrated in FIG. 12 includes a programmable circuit (FPGA) 1201, a variable power supply circuit (PWR) 102, a nonvolatile memory 1203, and a microcomputer (device management unit) 1202. As in the case of FIGS. 7 and 8, the microcomputer 1202 and the nonvolatile memory 1203 constitute the memory circuit unit 103, and the nonvolatile memory 1203 includes the first to third storage areas AR [1] to AR [3. ] Is provided.

Here, the microcomputer 1202 includes a variable power supply controller 1205 having the same function as the variable power supply controller 503 in FIGS. 5 and 10. Accordingly, in the second circuit data stored in the second storage area AR [2] of the nonvolatile memory 1203, the variable power controller 503 and the variation information 509 are deleted from the user circuit unit 1001 in FIG. A user circuit section is included. Further, the first circuit data stored in the first storage area AR [1] of the nonvolatile memory 1203 includes the monitor circuit 201 of FIG. 2 as in the case of the first embodiment.

FIG. 13 is a flowchart showing an example of processing contents performed by the microcomputer in the programmable device of FIG. The microcomputer (device management unit) 1202 executes a system management process as shown in FIG. In FIG. 13, the microcomputer 1202 monitors the alarm signal 1002 from the programmable circuit (FPGA) 1201 in which the user circuit unit is mounted (step S201), and when the alarm signal 1002 is issued, the power supply voltage shown in FIG. Management processing (steps S101 to S108) is automatically executed.

Specifically, the microcomputer (device management unit) 1202 first instructs a standard power supply voltage (first power supply voltage) to the variable power supply circuit 102, and then uses the configuration signal 1204 to program the programmable circuit (FPGA). ) 1201 is configured with the first circuit data (monitor circuit 201) (steps S101 and S102). Thereafter, similarly to the case of the first embodiment, the processes of steps S103 and S104 are performed. Subsequently, the microcomputer 1202 configures the second circuit data (user circuit unit) in the programmable circuit (FPGA) 1201 using the configuration signal 1204 (step S105).

Next, the microcomputer 1202 uses the variable power supply controller 1205 to determine the power supply voltage (second power supply voltage) based on the variation information stored in the third storage area AR [3] of the nonvolatile memory 1203, and to change the power supply voltage (second power supply voltage). An instruction is given to the power supply circuit 102 (steps S106 and S107). Thereafter, in step S108, as described in the second embodiment, the user circuit 501 in the user circuit unit starts operating, and the aging monitor circuit 1005 also starts operating. When the microcomputer 1202 detects the alarm signal 1002 in the course of the operation of the aging deterioration monitor circuit 1005, the microcomputer 1202 automatically executes the above-described steps S101 to S108 again.

The microcomputer 1202 may be replaced with, for example, another FPGA or DSP as long as it has the same function.
<< Examples of application of programmable devices >>

FIG. 14 is a schematic diagram showing a configuration example of an information system to which the programmable apparatus according to Embodiment 3 of the present invention is applied. The information system in FIG. 14 is, for example, an information processing system such as a server, an information communication system such as a router or a switch, or the like.

The information system shown in FIG. 14 includes a device [A] 1401, a device [B] 1408, and a device switching unit 1415. The apparatus [A] 1401 includes a plurality of boards (wiring boards) 1402, 1403, and 1404. On the boards 1403 and 1404, programmable circuits (FPGAs) 1405 and 1406 on which the user circuit units described in the respective embodiments are mounted are mounted. The board 1402 includes a reliability management unit 1407 for managing the programmable circuits (FPGAs) 1405 and 1406.

Similarly, the apparatus [B] 1408 includes a plurality of boards (wiring boards) 1409, 1410, and 1411. On the

boards

1410 and 1411, programmable circuits (FPGAs) 1412 and 1413 on which user circuit units are mounted are mounted, respectively. The board 1409 is equipped with a reliability management unit 1414 for managing the programmable circuits (FPGAs) 1412 and 1413. The device switching unit 1415 controls activation / deactivation of the device [A] 1401 and the device [B] 1408, respectively.

The information system shown in FIG. 14 is a system including, for example, a device [A] 1401 and a device [B] 1408 from the viewpoint of load distribution and redundancy. Here, if the system processing is distributed and processed by the device [A] 1401 and the device [B] 1408, the programmable circuit (FPGA) 1405 in the board 1403 of the device [A] 1401 is described above. Assume that the generated alarm signal 1002 is generated.

In this case, the alarm signal 1002 is transmitted to the reliability management unit 1407 and further transmitted to the device switching unit 1415. In response to this, the device switching unit 1415 degenerates the system processing to the device [B] 1408, for example, and the reliability management unit 1407 recovers the programmable circuit (FPGA) 1405 during that time. For example, the reliability management unit 1407 automatically adjusts the power supply voltage supplied to the programmable circuit (FPGA) 1405 by including the microcomputer (device management unit) 1202 described in FIG. When the adjustment of the power supply voltage is completed, the device switching unit 1415 again distributes the system processing to the device [A] 1401 and the device [B] 1408.

Further, the information system shown in FIG. 14 is a system including a device [B] 1408 as a backup of the device [A] 1401 from the viewpoint of redundancy, for example. Here, if the device [A] 1401 is processing the system, the programmable circuit (FPGA) 1405 in the board 1403 of the device [A] 1401 receives the alarm signal 1002 in the same manner as described above. Assume that it occurs. In this case, the reliability management unit 1407 restores the programmable circuit (FPGA) 1405 in the same manner as described above, and the device switching unit 1415 switches the system processing to the device [B] 1408. When the recovery of the programmable circuit (FPGA) 1405 (that is, adjustment of the power supply voltage) is completed, the device switching unit 1415 switches the system processing to the device [A] 1401 again, or the device [B] 1408 generates an alarm signal. The system [B] 1408 is caused to perform system processing until 1002 occurs.

As described above, in addition to the various effects described in the first and second embodiments by using the information system and the system management method thereof according to the third embodiment, when the aging deterioration occurs, The system can be recovered without stopping the operation. As a result, a highly reliable system can be realized.

As described above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

101,701,801,1201,1405,1406,1412,1413 Programmable circuit (FPGA)
DESCRIPTION OF SYMBOLS 102 Variable power supply circuit 103 Memory circuit part 104 Programmable device 201 Monitor circuit 202 Variation detection circuit 203,502 Memory controller 204,508 Memory control signal 205,509 Variation information 301 Ring oscillator block 302 Selector 303 Statistical processing unit 304 Data memory 305 Control unit 401 Lookup table (LUT)
402 Wiring 501

User circuit

503, 1205 Variable power controller 504 Voltage determination unit 505 Power interface 507

Voltage control signal

510, 1001 User circuit unit 511 Voltage setting completion signal 512

Reset signal

702, 1202

Microcomputer

703, 802, 1203 Non-volatile memory 1002 Alarm Signal 1005 Aging monitor circuit 1101 Ring oscillator circuit 1102 Frequency measurement unit 1103 Register 1104 Comparison unit 1204

Configuration signal

1401 and 1408 Devices 1402 to 1404 and 1409 to 1411

Boards

1407 and 1414 Reliability management unit 1415 Device switching unit AR [1] AR [3] Storage area RO, RO [1] to RO [n] Ring oscillator circuit

Claims

A programmable circuit that mounts an arbitrary circuit on itself according to circuit data;
A power supply circuit for supplying a power supply voltage to the programmable circuit;
A power supply voltage management method for a programmable device comprising:
A first step of configuring the programmable circuit with first circuit data including a first monitor circuit for detecting a characteristic parameter having power supply voltage dependency;
A second step of detecting the characteristic parameter using the first monitor circuit mounted on the programmable circuit in a state where the first power supply voltage is supplied by the power supply circuit;
A third step of configuring the second circuit data including a user circuit for performing a predetermined process in the programmable circuit instead of or in addition to the first circuit data;
A fourth step of performing a predetermined process using the user circuit mounted on the programmable circuit in a state where the second power supply voltage is supplied by the power supply circuit;
Have
The second power supply voltage is determined based on the characteristic parameter detected by the first monitor circuit in the second step.
A power supply voltage management method for a programmable device.
In the power supply voltage management method of the programmable device of Claim 1,
The first monitor circuit includes a ring oscillator circuit,
The characteristic parameter is an oscillation frequency of the ring oscillator circuit.
A power supply voltage management method for a programmable device.
In the power supply voltage management method of the programmable device of Claim 1,
In the third step, in addition to the user circuit, the second circuit data including a second monitor circuit for detecting the characteristic parameter is configured in the programmable circuit,
The second monitor circuit is smaller in circuit scale than the first monitor circuit, and the value of the characteristic parameter detected by the second monitor circuit is greater than or equal to a predetermined width compared to the latest execution time of the third step. Generate an alarm signal when
A power supply voltage management method for a programmable device.
In the power supply voltage management method of the programmable device of Claim 3,
The first monitor circuit includes a plurality of ring oscillator circuits,
The second monitor circuit includes a smaller number of ring oscillator circuits than the first monitor circuit,
The characteristic parameter is an oscillation frequency of the ring oscillator circuit.
A power supply voltage management method for a programmable device.
In the power supply voltage management method of the programmable device according to claim 4,
The power supply voltage management method for a programmable device, wherein the second power supply voltage is determined based on an average value and a standard deviation of a plurality of oscillation frequencies detected by the plurality of ring oscillator circuits in the first monitor circuit.
In the power supply voltage management method of the programmable device of Claim 3,
A power supply voltage management method for a programmable device, further comprising a fifth step of monitoring the alarm signal from the second monitor circuit and performing the first to fourth steps when the alarm signal is detected.
In the power supply voltage management method of the programmable device of Claim 1,
In the second step, the characteristic parameter detected using the first monitor circuit is stored in a memory,
In the third step, the second circuit data including a power supply control circuit in addition to the user circuit is configured in the programmable circuit,
In the fourth step, the power supply control circuit determines the second power supply voltage based on the characteristic parameter stored in the memory, and instructs the second power supply voltage to the power supply circuit.
A power supply voltage management method for a programmable device.
A memory for storing circuit data;
A programmable circuit for mounting an arbitrary circuit on itself according to the circuit data read from the memory;
A power supply circuit for supplying a power supply voltage to the programmable circuit;
A programmable device comprising:
The memory is
First circuit data including a first monitor circuit for detecting a characteristic parameter having power supply voltage dependency;
Second circuit data including a user circuit for performing a predetermined process;
Remember
The programmable circuit detects the characteristic parameter using the first monitor circuit by configuring the first circuit data from the memory, and then replaces or adds the first circuit data from the memory. The second circuit data is configured to perform the predetermined process using the user circuit,
The power supply circuit supplies a first power supply voltage when detection using the first monitor circuit is performed, and the detection is performed by the first monitor circuit when processing by the user circuit is performed. Supplying a second power supply voltage determined based on the characteristic parameter;
Programmable device.
The programmable device of claim 8, wherein
The first monitor circuit includes a ring oscillator circuit,
The characteristic parameter is an oscillation frequency of the ring oscillator circuit.
Programmable device.
The programmable device of claim 8, wherein
In addition to the user circuit, the second circuit data includes a second monitor circuit for detecting the characteristic parameter,
The second monitor circuit has a smaller circuit scale than the first monitor circuit, and the value of the characteristic parameter detected by the second monitor circuit is smaller than the latest time when the second circuit data is configured. Generate an alarm signal when it exceeds a predetermined width,
Programmable device.
The programmable device of claim 10, wherein
The first monitor circuit includes a plurality of ring oscillator circuits,
The second monitor circuit includes a smaller number of ring oscillator circuits than the first monitor circuit,
The characteristic parameter is an oscillation frequency of the ring oscillator circuit.
Programmable device.
The programmable device of claim 11, wherein
The programmable device, wherein the second power supply voltage is determined based on an average value and a standard deviation of a plurality of oscillation frequencies detected by the plurality of ring oscillator circuits in the first monitor circuit.
The programmable device of claim 10, wherein
The programmable device further includes a device management unit that monitors the alarm signal from the second monitor circuit,
When the device management unit detects the alarm signal from the second monitor circuit,
Configuring the first circuit data from the memory to the programmable circuit;
A second step of instructing the first power supply voltage to the power supply circuit and causing the first monitor circuit to detect the characteristic parameter;
A third step of determining a second power supply voltage based on the characteristic parameter detected by the first monitor circuit;
A fourth step of configuring the second circuit data from the memory to the programmable circuit;
Instructing the second power supply voltage to the power supply circuit, and causing the user circuit to perform the predetermined process;
A programmable device that performs
The programmable device of claim 8, wherein
The first monitor circuit stores the detected characteristic parameter in the memory,
The second circuit data includes a power supply control circuit in addition to the user circuit,
The power supply control circuit reads the characteristic parameter from the memory, determines the second power supply voltage based on the characteristic parameter, and instructs the power supply circuit of the second power supply voltage;
Programmable device.