WO2015027754A1

WO2015027754A1 - Multi-channel first-in first-out cache queue controller and access method

Info

Publication number: WO2015027754A1
Application number: PCT/CN2014/081719
Authority: WO
Inventors: 郑述乾; 李天林; 区树雄
Original assignee: 华为技术有限公司
Priority date: 2013-08-30
Filing date: 2014-07-07
Publication date: 2015-03-05
Also published as: CN103455442B; CN103455442A

Abstract

Embodiments of the present invention provide a multi-channel FIFO queue controller and an access method for the multi-channel FIFO queue. The multi-channel FIFO queue controller comprises an address determining circuit and a control circuit. The address determining circuit is used for determining a physical address of a block to be accessed in a data cache according to an identification of a service, the data cache comprising multiple blocks, each of the blocks comprising m storage units, and m being a positive integer; and determining a physical address of data to be accessed in the data cache according to the physical address of the block to be accessed and an address of the data to be accessed in the block to be accessed. The control circuit is used for accessing the data to be accessed according to the physical address determined by the address determining circuit, of the data to be accessed in the data cache. The solution helps multiple services share the data cache, and helps to reduce the occupancy of resources of the FIFO queue, and the reliability is higher.

Description

Multi-channel FIFO cache queue controller and access method

The present invention relates to the field of data transmission technologies, and in particular, to a multi-channel FIFO buffer queue

(first in first out queue , FIFO queue ) controller and access method.

Background technique

In the field of transmission, as the transmission bandwidth is getting larger (for example, 100G, 200G or 400G), Field Programmable Gate Array (FPGA) in communication equipment often uses multiple channels when processing multiple services. The low-bandwidth service is transformed into a time-division signal with a uniform bit width (such as 640 bits). The bandwidth corresponding to multiple services may change over time. When adapting between different business processes, a FIFO queue is needed to cache the data of the service. In a large-width scenario, the resources of the FIFO queue may be very consumed. Specifically, the random access memory (RAM) resource corresponding to the FIFO queue, the Look Up Table (LUT) resource, and the routing resource may be consumed.

An existing solution (referred to as scenario 1) is shown in Figure 1. Option 1 encapsulates multiple large-bit wide FIFO entities together as a multi-service channel FIFO entity. On the data input side, the incoming data stream is distributed to the corresponding FIFO entity according to the channel number of the service; on the data output side, data is read from different FIFO entities according to the channel number of the service.

In the foregoing solution 1, the RAM buffer and the control circuit corresponding to different service channels in the multi-service channel FIFO queue cannot be shared, and the size of the RAM used by the multi-service channel FIFO queue must be designed according to the size of the largest service bandwidth particle, when the service channel When the number is large (for example, >=64), the RAM resource consumption is quite large, for example, a 640-bit width, 80 service channels, and a maximum of 128 units of multi-service channel FIFO per service channel, requiring nearly 400 RAMs on the FPGA. The total RAM resources on a larger FPGA are more than 2,000. In addition, in a practical application scenario, only a very small number of service channels have large bandwidth services, and other service channels are idle (the total bandwidth is constant, some service channels have large bandwidth, and other service channels are available. Inevitably, the bandwidth is small or not, which causes waste of RAM resources.

Another solution (Scheme 2 is briefly described below) is shown in FIG. 2. In the solution 2, all service channels share a large cache, and each service channel allocates space according to the size of the service particle, and the space of each service channel passes. A circular linked list is organized. Each service channel has its own linked list pointer, and each service channel performs cache read and write operations through the current read and write pointers.

The space of all the service channels in the scheme 2 is organized in the form of a circular linked list. When an abnormality occurs in the pointer of the linked list, an error that cannot be recovered is caused, and the reliability is poor. Summary of the invention

The embodiment of the invention provides a multi-channel FIFO cache queue controller and a multi-channel FIFO cache queue access method, which helps to reduce the problem of FIFO queue resource occupation when processing multiple services. .

In a first aspect, a multi-channel FIFO queue controller is provided, including: an address determining circuit and a control circuit;

The address determining circuit is configured to:

Determining, according to the identifier of the service, a physical address of the block to be accessed in the data cache, where the data buffer includes a plurality of blocks, each block includes m storage units, and m is a positive integer;

Determining, according to the physical address of the to-be-accessed block and the data to be accessed, an address in the to-be-accessed block, a physical address of the data to be accessed in the data cache;

The control circuit is used to:

And the data to be accessed is accessed by the physical address of the data to be accessed determined by the address determining circuit in the data cache.

In a first possible implementation manner of the first aspect, the address determining circuit is specifically configured to: determine, according to the identifier of the service, a logical address and a location of the to-be-accessed block An address of the data to be accessed in the block to be accessed;

According to the logical address of the block to be accessed, and the physical address of the block to be accessed by the block to be accessed;

And determining, according to the physical address of the block to be accessed and the address of the to-be-accessed data in the block to be accessed, a physical address of the data to be accessed in the data cache.

According to the first possible implementation manner of the first aspect, in the second possible implementation manner of the first aspect, the address determining circuit is specifically configured to:

Querying a logical address table according to the identifier of the service, and acquiring a logical address of the data to be accessed;

Obtaining, according to the logical address of the data to be accessed, a first rendition address of the block to be accessed, a logic blk addr, and an intra-block offset address, a logic_shift_addr;

Querying the first block address table according to the identifier of the service, and obtaining a logical address of the first block of the plurality of blocks occupied by the service, first blk_addr;

Querying a block address table according to a second logical address of the block to be accessed, obtaining a physical address of the block to be accessed, where a second logical address of the block to be accessed is equal to a sum of logic blk addr and first_blk_addr;

Determining, according to the physical address of the to-be-accessed block and the intra-block offset address, a physical address of the data to be accessed in the data cache;

The block address table records the identifier of the service, and the mapping relationship between the second logical address of the multiple blocks occupied by the service and the physical addresses of the multiple blocks occupied by the service, where the service is occupied. Corresponding to the second logical address of the plurality of blocks and the physical address of the plurality of blocks occupied by the service, the second logical address of the block to be accessed is [first_blk_addr, first-blk_addr Any integer in +n, where n is the number of blocks in the service occupancy data cache; The identifier of the service is recorded in the first block address table, and a logical address of a first block of the plurality of blocks occupied by the service;

The logical address table records the identifier of the service, and the logical address of the data to be accessed, and the value of the logical address of the data to be accessed is [0, mx the number of blocks occupied by the service] Any integer in .

According to a first possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the address determining circuit is specifically configured to:

Obtaining, according to the logical address of the data to be accessed, the address of the block to be accessed, the logical blk addr and the intra-block offset address logic_shift_addr;

Determining a block remapping table according to the identifier of the service and the logical address of the block to be accessed, logic_blk_addr, to obtain a physical address of the block to be accessed; according to the physical address and location of the block to be accessed Determining an intra-block offset address, determining a physical address of the data to be accessed in the data cache;

The logical address table records the identifier of the service, and the logical address of the data to be accessed, and the logical address of the data to be accessed takes the value of [0, mx the block occupied by the service. Any number in the number];

The block remapping table records the identifier of the service, and the mapping relationship between the logical address of the multiple blocks occupied by the service and the physical addresses of the multiple blocks occupied by the service, and multiple blocks occupied by the service Corresponding to the logical address of the plurality of blocks occupied by the service, the logical address of the block to be accessed is any integer of [0, n], and the n is occupied by the service. The number of blocks in the data cache.

According to the second possible implementation manner of the first aspect, or the third possible implementation manner, in the fourth possible implementation manner of the first aspect, the address determining circuit is further configured to:

After the control circuit accesses the data to be accessed, using the service for the next access The logical address of the data replaces the logical address of the data to be accessed in the logical address table. In a second aspect, a method for accessing a multi-channel FIFO queue is provided, including: determining, according to an identifier of a service, a physical address of a block to be accessed in a data cache, where the data cache includes a plurality of blocks, each block includes m Storage unit, m is a positive integer;

Determining, according to the physical address of the to-be-accessed block and the data to be accessed, the physical address of the data to be accessed in the data cache;

In a first possible implementation manner of the second aspect, the determining, by the physical address of the data to be accessed in the data cache, includes:

Determining, according to the identifier of the service, a logical address of the to-be-accessed block and an address of the to-be-accessed data in the to-be-accessed block;

Determining a physical address of the block to be accessed according to a logical address of the block to be accessed, and a mapping relationship between a logical address of the block to be accessed and a physical address of the block to be accessed;

Determining, according to the physical address of the to-be-accessed block and the address of the to-be-accessed data, the physical address of the data to be accessed in the data cache.

According to the first possible implementation manner of the second aspect, in a second possible implementation manner of the second aspect, determining, according to the identifier of the service, a logical address of the to-be-accessed block and the to-be-accessed Determining, by the address in the block to be accessed, the physical address of the block to be accessed according to the mapping relationship between the logics of the to-be-accessed block, according to the physical address and location of the block to be accessed Determining, by the address in the block to be accessed, the physical address of the data to be accessed in the data cache, which includes:

Querying a logical address table according to the identifier of the service, and acquiring a logical address of the data to be accessed; Obtaining, according to the logical address of the data to be accessed, a first logical address of the block to be accessed, a logic blk addr, and an intra-block offset address, a logic shift addr;

Querying a block address table according to a second logical address of the block to be accessed, obtaining a physical address of the block to be accessed, where a second logical address of the block to be accessed is equal to logic_blk_addr and first_blk_addr with;

Determining, according to the physical address of the block to be accessed and the intra-block offset address, a physical address of the data to be accessed in the data cache;

The block address table records the identifier of the service, and the mapping relationship between the second logical address of the multiple blocks occupied by the service and the physical addresses of the multiple blocks occupied by the service, where the service is occupied. Corresponding to the second logical address of the plurality of blocks and the physical address of the plurality of blocks occupied by the service, the second logical address of the block to be accessed is [first_blk_addr, first-blk_addr Any integer in +n, where n is the number of blocks in the service occupancy data cache;

The identifier of the service is recorded in the first block address table, and a logical address of a first block of the plurality of blocks occupied by the service;

According to a first possible implementation manner of the second aspect, in a third possible implementation manner of the second aspect, determining, by the identifier of the service, a logical address of the to-be-accessed block and the to-be-accessed Determining, by the address in the block to be accessed, the physical address of the block to be accessed according to the mapping relationship between the logics of the to-be-accessed block, according to the physical address and location of the block to be accessed Determining the waiting for the address of the data to be accessed in the block to be accessed The physical address of the accessed data in the data cache, specifically including:

Querying a logical address table according to the identifier of the service, and acquiring a logical address of the to-be-accessed data;

Obtaining, according to the logical address of the data to be accessed, a logical address logical blk addr of the block to be accessed and an intra-block offset address logic_shift_addr;

Obtaining a physical address of the block to be accessed according to the identifier of the service and the logical address logic of the block to be accessed, blk_addr, querying the block remapping table;

According to a third possible implementation of the second aspect, or a fourth possible implementation of the second aspect, in a fifth possible implementation of the second aspect, the control circuit accesses the to-be-accessed After the data, it also includes:

Replacing the logical address of the data to be accessed in the logical address table with the logical address of the data accessed next time by the service

Advantageous effects of embodiments of the present invention include:

The embodiment of the invention provides a multi-channel FIFO queue controller and a multi-channel FIFO queue access method. Multi-channel FIFO queue controller packet address determination circuit and control circuit. The data buffer is divided into a plurality of blocks, and the address determining circuit can determine the physical location of the block to be accessed according to the identifier of the service. Address. The address determining circuit can further determine the physical address of the data to be accessed in the data cache accordingly. The control circuit can access the data to be accessed according to the physical address of the data to be accessed determined by the address determining circuit in the data cache. Therefore, the foregoing technical solution helps the sharing of data caches by multiple services, and helps reduce the occupation of resources of the FIFO queue. In addition, an embodiment of the present invention provides a method for determining a physical address of data to be accessed. That is, the physical address of the block to be accessed is determined according to the identifier of the service, and the physical address of the data to be accessed in the data cache is determined according to the physical address of the block to be accessed and the data to be accessed in the block to be accessed. The data to be accessed is accessed according to the physical address in the data cache according to the data to be accessed. In the foregoing technical solution, in the process of determining the physical address of the data to be accessed in the data cache, there is no need to rely on the linked list pointer, and the reliability is high. DRAWINGS

1 is a schematic diagram of FIFO queue read and write data in the prior art scheme 1;

2 is a schematic diagram of reading and reading data of a FIFO queue in the prior art scheme 2;

3 is a schematic structural diagram of a multi-channel FIFO queue controller according to an embodiment of the present invention; FIG. 4 is a schematic structural diagram of a multi-channel FIFO queue controller and a data cache according to an example of the present invention;

FIG. 5 is a schematic diagram of association between CH—BLK—MAP—TBL and other tables according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a working process of an automatic refreshing unit of an entry according to an embodiment of the present invention; FIG. 7 is a logic block diagram of a multi-channel FIFO queue controller provided by the first embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a multi-channel FIFO queue controller and a data cache according to an example 2 according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a data structure of a block remapping table in the second embodiment according to an embodiment of the present invention; FIG. 10 is a content of a BLK REMAP TBL in an example according to an embodiment of the present invention; Schematic diagram

FIG. 11 is a flowchart of a multi-channel FIFO queue access method according to an embodiment of the present invention. detailed description

A specific implementation manner of a multi-channel FIFO buffer controller and a multi-channel FIFO cache queue access method according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

The service involved in the embodiment of the present invention may be carried in at least one of the first layer to the seventh layer defined by the Open Systems Interconnection Reference Model (OSI reference model). For example, the service may be a service carried at a third layer or a service carried at a fourth layer. The service carried in the third layer may be an Internet Protocol (IP) service. The service carried in the fourth layer may be a Transmission Control Protocol (TCP) service or a User Datagram Protocol (UDP) service. The service may be a video transmission service, an audio transmission service, or a text transmission service.

First, the multi-channel FIFO queue controller provided by the embodiment of the present invention is described in detail. As shown in FIG. 3, the FIFO queue controller provided by the embodiment of the present invention includes: an address determining circuit 301 and a control circuit 302;

The address determination circuit 301 is used to:

Determining, according to the identifier of the service, a physical address of the block to be accessed in the data cache; determining, according to the physical address of the block to be accessed and the address of the to-be-accessed data in the block to be accessed, the data to be accessed is The physical address in the data cache;

In the embodiment of the present invention, the data cache includes a plurality of blocks, each of which contains m storage units, m is a positive integer, and the data cache may be RAM or other commonly used memory.

Control circuit 302 is used to:

The data to be accessed determined by the address determining circuit 302 is in the data cache The physical address in the accesses the data to be accessed.

The above-mentioned access operation may be, for example, a read and/or write operation, data to be accessed, that is, data to be read or written, and a block to be accessed, that is, a block in which data to be read or written is located.

In the embodiment of the present invention, the data cache is divided into a plurality of blocks (the total number of blocks > the maximum possible number of services in the application scenario of the multi-service application in the embodiment of the present invention, the total number of blocks is not less than 2) Each block of m units, the size of m can be designed according to the minimum bandwidth requirement in multi-service. Since the total service bandwidth is unchanged, when the multi-channel FIFO entity processes the large-bandwidth service, the inevitable service channel is relatively small, so that for each service, its corresponding service channel can be allocated more blocks; In the case of a small bandwidth service, there are many service channels. For each service, its corresponding service channel can still be allocated to the block that meets the requirements. In a multi-service application scenario, the number of blocks allocated for each service can be determined according to the size of the bandwidth actually occupied by the service. The blocks occupying more bandwidth can be allocated more blocks. Otherwise, fewer blocks can be allocated. The change in bandwidth requirements of each service adjusts the number of blocks allocated for each service in real time.

The address determining circuit 301 may be implemented by an integral circuit module in a specific implementation, or may be separately configured on two different circuit modules according to different access requirements, such as a read operation and a write operation. The address determining function of the read operation and the address determining function of the write operation, the specific circuit implementation manner belongs to the prior art, and details are not described herein again.

Similarly, the foregoing control circuit 302 can be implemented by an integral circuit module in a specific implementation, or can be divided into two different circuit modules according to different access requirements, such as a read operation and a write operation requirement. To achieve control of read and write operations, respectively.

In the foregoing multi-channel FIFO queue controller provided by the embodiment of the present invention, the address determining circuit 301 is further configured to determine, according to an identifier of the service, such as a channel number corresponding to the service, a logical address of the to-be-accessed block, and the The address of the data to be accessed in the block to be accessed; and according to the logical address of the block to be accessed, and the logical address of the block to be accessed and the physical address of the block to be accessed Mapping a relationship, determining a physical address of the block to be accessed; Determining, according to the physical address of the to-be-accessed block and the address of the to-be-accessed data, the physical address of the data to be accessed in the data cache.

Further, the address determining circuit 301 determines, according to the identifier of the service (for example, the channel number corresponding to the service, etc.), the logical address of the to-be-accessed block and the address of the to-be-accessed data in the block to be accessed. According to the logical address of the block to be accessed, and the physical address of the block to be accessed; according to the physical address of the block to be accessed and the data to be accessed in the block to be accessed The address of the data to be accessed in the data cache is determined. In a specific implementation, there are two specific implementation manners, which are specifically described as follows:

The first way:

The address determining circuit searches the logical address table according to the identifier of the service (for example, the channel number corresponding to the service), and obtains the logical address of the data to be accessed;

Querying a block address table according to a second logical address of the block to be accessed, obtaining a physical address of the block to be accessed, where a second logical address of the block to be accessed is equal to a sum of logic blk addr and first_blk_addr (ie: logic blk Addr+first blk addr );

The block address table includes: an identifier of the service, and a mapping relationship between a second logical address of the multiple blocks occupied by the service and a physical address of multiple blocks occupied by the service, where the service is occupied a second logical address of the plurality of blocks and a physical location of the plurality of blocks occupied by the service Address-correspondingly, the second logical address of the to-be-accessed block is any integer of [first_blk_addr, first-blk_addr+n], and the n is in the service occupation data cache. The number of blocks;

The first block address table records: an identifier of the service, and a logical address of a first block of the plurality of blocks occupied by the service;

The logical address table includes: an identifier of the service, and a logical address of the data to be accessed, where a logical address of the data to be accessed is a value of [0, mx, the number of blocks occupied by the service Any integer in .

For a multi-service application scenario, the foregoing block address table may record the identifiers of multiple services, the second logical address of all blocks occupied by each service, and the mapping relationship between physical addresses of all blocks occupied by each service. .

Similarly, in the first block address table, the identifiers of the plurality of services and the logical addresses of the first blocks of all the blocks occupied by each service may be recorded.

Similarly, in the above logical address table, the identifiers of the plurality of services and the logical addresses of the data to be accessed by each service (the logical addresses involved in the current access operation) may be recorded.

The logical address of the data to be accessed, the first logical address of the block to be accessed, the logical address of the first block, and the second logical address of the block to be accessed are linear, and are to be accessed by a certain service A. The logical address of the data is 29, and each block has 10 storage units as an example. The address determining circuit obtains the first logical address of the block to be accessed, logic_blk_addr, according to the logical address (29) of the data to be accessed. And the process of the offset address logic_shift_addr in the block is actually obtained by dividing the logical address of the data to be accessed by the number of memory cells of each block, that is: the first logical address of the block to be accessed (logic- Blk_add) is equal to the logical address (29) of the data to be accessed divided by the quotient (2) obtained by the number of storage units (10) of each block, and the intra-block offset address (logic_shift_addr) is equal to the to-be-accessed The logical address of the data (29) is divided by the remainder of the number of memory cells per block (10) (9).

For a multi-service scenario, the blocks in the data cache occupied by each service are different. If all the blocks in the data cache are designed in a linear manner to their logical addresses (for example, 0, 1, 2, 3, ...), in the first block address table, the first of all the blocks occupied by each service. For example, if the logical address of the block is different, the service A is used as an example. For example, if the address of the first block of all blocks occupied by the service A is 12, the second logical address of the block to be accessed is equal to 14 (12+ 2), according to the mapping relationship between the second logical address and the physical address of each block in the block address table, the physical address of the block to be accessed can be found.

In the above description, for the convenience of description, the logical address of the block to be accessed is referred to by the first logical address and the second logical address respectively. In fact, the first logical address represents all occupied by a certain service. In the block, the block to be accessed is the first block. The logical address of the data to be accessed by a certain service A is 29, and each block has 10 storage units as an example. The first logical address of the block to be accessed (logic-blk) – add ) equal to 2, meaning that the block to be accessed is the second block of all blocks occupied by the service A (counting from the 0th block), and the second logical address represents all blocks in the entire data cache. For example, what is the actual logical address? For example, when the logical address of the first block of all blocks occupied by service A is 12, since the logical address is linear, the second logical address of the block to be accessed by service A is 14 .

The second way:

The address determining circuit queries the logical address table according to the identifier of the service (for example, the channel number corresponding to the service), and obtains the logical address of the data to be accessed;

Obtaining, according to the logical address of the data to be accessed, a recurring address of the block to be accessed, a logic blk addr, and an intra-block offset address, a logic_shift_addr; according to the identifier of the service and the block to be accessed The logical address logic_blk_addr queries the block remapping table to obtain the physical address of the block to be accessed; determining the to-be-accessed according to the physical address of the block to be accessed and the intra-block offset address The physical address of the data in the data cache;

The logical address table records the identifier of the service, and the logical address of the data to be accessed, and the logical address of the data to be accessed takes the value of [0, mx Any of the number of blocks used];

The second way differs from the first one in that the second method uses a block remapping table instead of the block address table and the first block address table.

For a multi-service application scenario, the foregoing logical address table may record identifiers of multiple services and logical addresses of data to be accessed by each service (logical addresses involved in current access operations).

Similarly, in the above block remapping table, the identifiers of the plurality of services, and the mapping relationship between the logical addresses of all the blocks occupied by each service and the physical addresses of all the blocks occupied by each service may be described.

For the block remapping table, it records the logical address and corresponding physical address of each block occupied by each service, and in the specific implementation, the table can be a two-dimensional table of n*x size ( n is the total number of chunks of the data cache, X is the total number of services), there are several records, each record records the physical address of the jth block of the i-th service, and the value of i is (0~X) Any integer, j is any integer from (0~n).

In the second mode, the address determining circuit queries the logical address table according to the identifier of the service (for example, the channel number corresponding to the service), acquires the logical address of the data to be accessed, and the logic according to the data to be accessed. The step of obtaining the logical address of the to-be-accessed block, the data-blk_addr, and the in-block offset address, the data-shift-add, is the same as the first method, and is not described here.

In order to better illustrate the structure and function of the above multi-channel FIFO queue controller provided by the embodiment of the present invention, the following details are described in two specific examples: Example 1:

As shown in FIG. 4, in the multi-channel FIFO queue controller of the first example, the address determining circuit is implemented by two independent circuit modules: a FIFO write address remapping unit 401 (responsible for determining the address of the write operation) and a FIFO. The read address remapping unit 402 (which is responsible for determining the address of the read operation), the control circuit (not shown in FIG. 4) controls the data buffer (RAM) 403 by issuing a RAM read/write enable signal (ram wr en, ram_rd_en ), respectively. The operation of reading and writing data.

The functions of the FIFO write address remapping unit 401 and the FIFO read address remapping unit 402 are independent of each other. For the entire multi-channel FIFO queue controller, only the read or write operation of the RAM 403 can be performed currently, or the RAM read can be performed simultaneously. And write operations.

The RAM 403 is divided into n (n > maximum possible number of service channels) blocks, each of which is m units, and the size of m can be designed according to the minimum bandwidth requirement in each service channel.

The access address of RAM 403 is divided into two levels: logical address and physical address. The logical address is linear in the space of a certain FIFO service channel. For example, the logical address of the block in the RAM is 0, 1, 2, 3, ..., etc.; through this logical address, the data buffer can be generated to be full. The status alarm and whether the alarm information such as the set water line is reached, the physical address is the actual access address in the RAM.

As shown in FIG. 4, for the FIFO write address remapping unit 401 and the FIFO read address remapping unit 402, respectively, four tables are included: a block number table (BLK_NUM_TBL), a first block address table (FIRST_BLK_ADDR_TBL), The logical address table (LOGIC ADDR TBL) and the block address table (BLK_ADDR_TBL), the FIFO write address remapping unit 401 and the FIFO read address remapping unit 402 complete the logical address to the physical address by respectively querying the respective included tables. Re-mapping (i.e., determining the physical address of the current service channel read and write access), the above process is similar for the FIFO write address remapping unit 401 and the FIFO read address remapping unit 402. The following addresses are remapped for read and write addresses. The process is described in a unified manner.

Each of the FIFO write address remapping unit 401 and the FIFO read address remapping unit 402 The contents of the table are as follows:

Block quantity table (BLK_NUM_TBL): In the multi-application scenario, the size of the table is the maximum possible number of services X, and the content is the number of buffers (BUFFER) blocks occupied by each service. For example, the content of the fifth address space is 6, indicating that the service, for example, the service channel number 5, shares 6 blocks.

The first address table ( FIRST — BLK — ADDR — TBL ): In the multi-application scenario, the table size is the maximum possible number of services, the address is the service channel number, and the block address occupied by the service with the content of each service channel number is BLK — ADDR — The first address in the TBL table (ie the logical address of the first block in all blocks occupied).

Logical Address Table ( LOGIC — ADDR — TBL ): The table size is the maximum possible number of services x, the address is the service channel number, and the content is the linear logical address of the data to be read (written) by the service. Logical address range = any integer in (0, m* occupied block number). In other words, the content of the logical address table included in the FIFO write address remapping unit 401 is a linear logical address to be written by each service, and the content of the logical address table included in the FIFO read address remapping unit 402 is the linear logic to be read by each service. Address, logical address can be used to determine the status of the data cache, such as empty, water line and so on.

Block Address Table (BLK_ADDR_TBL): The table size is the number of blocks n of RAM 403, which records the actual block address (ie physical address) of all blocks occupied by each service.

As shown in FIG. 4, in the first example, in addition to the FIFO write address remapping unit 401 and the FIFO read address remapping unit 402, the multi-channel FIFO queue controller may further include: an entry automatic refresh unit 404, the entry automatically The refresh unit 404 is respectively connected to the FIFO write address remapping unit 401 and the FIFO read address remapping unit 402 for generating and refreshing the FIFO write address remapping unit 401 and the FIFO read respectively for the channel-block mapping table (CH BLK MAP TBL ) The table of the block number table (BLK_NUM_TBL), the block address table (BLK_ADDR_TBL), and the first block address table ( FIRST BLK ADDR TBL ) included in the address remapping unit 402.

The content of CH BLK MAP TBL is preset according to the user's needs. The size is the number of blocks of RAM n, and the content is the service channel number. For example, the service channel number is 2 (referred to as service channel). The traffic of channel 2) occupies the 2nd and 3rd blocks, and the content of the 2nd and 3rd address spaces of CH BLK MAP TBL is 2. In this example, the data cache (RAM) number of the multi-channel FIFO entity is 12, the maximum number of services is 6, and only 3 services (corresponding service channel numbers are 0, 2, 5) are actually used, where:

The service of service channel 0 occupies blocks of 0, 3, 6, and 9;

The service of service channel 2 occupies blocks of 1, 4, 7, and 10;

The service of service channel 5 occupies blocks of 2, 5, 8, and 11;

As shown in Figure 5, in CH-BLK-MAP-TBL, different fill patterns represent one service channel, and blocks filled with right-hand diagonal lines are blocks occupied by services with channel number 0 (0, 3, 6, 9) The block that fills the left-hand slant line is the block occupied by the service with the service channel number 2 (1, 4, 7, and 10), and the block that fills the cross-grid line is the block occupied by the service with the service channel number of 5 ( 2, 5, 8, 11).

In BLK-NUM-TBL, the number of blocks occupied by services with service channel numbers 0, 2, and 5 is 4, and the number of blocks occupied by other services is 0. The number of blocks occupied by these three services is correspondingly used. Fill pattern display.

In the BLK-ADDR-TBL, the physical address of the block occupied by each service is recorded. For example, the physical address of the block occupied by the service with the service channel number 0 is 0, 3, 6, and 9, and the service channel number 2 is occupied. The physical addresses of the blocks whose physical addresses are 1, 4, 7, and 10, and the services with service channel number 5 are 2, 5, 8, and 11.

Correspondingly, in FIRST-BLK-ADDR-TBL, the address of the first block of all the blocks occupied by the service with the service channel number 0 is 0, and the first block of all the blocks occupied by the service with the service channel number 2 is The address of the service is 4, and the address of the first block of the service with channel number 5 is 8.

FIFO write address remapping unit 401 and FIFO read address remapping unit 402 read and write addresses The process of remapping is as follows:

According to the service channel number sent by the previous stage, query the block quantity table (BLK_NUM_TBL), the first block The address table ( FIRST_BLK_ADDR_TBL ) and the logical address table ( LOGIC ADDR TBL ), the number of blocks occupied by the service of the service channel number (blk_num), the logical address of the block to be read and written by the service (logic_blk_addr), and the intra-block bias The address (logic_shift_addr), the logical address of the first block in all blocks occupied by the service (first_blk_addr).

Query the number of blocks (blk_num) occupied by the service, and learn the logical address range of the block occupied by the service. When the logical address of the block to be read or written is in the logical address range, that is, the service When the logical address of the block to be read or written does not exceed the upper limit of the logical address range, continue to query the block address table (BLK_ADDR_TBL) according to logic_blk_addr+first-blk_addr to obtain the service to be read and written. The physical address of the block (phy-blk_addr) determines that the service is to be read or written according to the physical address (phy-blk_addr) of the block to be read and written by the service and the offset_addr in the block. The physical address (phy_addr) of the data in the data cache completes the mapping of the logical address to the physical address. At the same time, {logic-blk_addr, logic_shift_addr} + 1 is written back to the logical address of the next read/write operation (logic addr next ) ( LOGIC_ADDR_TBL ), and the logical address table is updated.

As the read and write operations progress, the logical address recorded in the logical address table is continuously pushed forward, and the address range of the block whose logical address exceeds the service may occur. To prevent the read/write operation from accessing the cache space corresponding to the service. In the embodiment of the present invention, the FIFO write address remapping unit 401 and the FIFO read address remapping unit 402, if querying the respective logical address table, determine that the logical address of the block to be read or written by the service exceeds the upper limit of the range of the logical address. The logical address of the block to be read or written in the logical address table is set to 0, which means that the current read and write needs to start from the first block occupied by the service, and the read and write operations are guaranteed to be performed in the block occupied by the service. .

There is also a case where, if the number of blocks of the service occupied data buffer read by the FIFO write address remapping unit 401 and the FIFO read address remapping unit 402 is 0 during the above address remapping, the service of the service is determined. The channel number is illegal, and the read/write control unit controls the read and write enable of the service to be 0 according to the situation.

In the first example, an empty alarm and water are also provided according to the logical address to be read and written by the service. The mechanism of the line alarm is specifically implemented by the FIFO alarm unit 405. At the same time, in addition to the linear logical address of the data to be read and written for each service, the logical address table includes the symbols for reading and writing the current service. Bit, thus, the data structure of the logical address table is {write address sign bit (1 bit), write address}, {read address sign bit (1 bit), read address}.

The above write address sign bit (read address sign bit) indicates whether the logical address of the current service write (read) is increased to a bit equal to the occupied space size.

The write address sign bit (read address sign bit) in the logical address table is toggled when the write (read) address sign bit occurs once the logical address of the data to be written (read) increases to equal the size of the space. Flip (inverted from the current value, 0 → or 1 → 0, the initial value is 0), and the logical address of the data to be written (read) will be zero.

The FIFO alarm unit 405 calculates the waterline value for each service by:

1. The logical address of the data to be read (hereinafter referred to as the read logical address) is greater than the logical address of the data to be written (hereinafter referred to as the write logical address), the water line value = the address space size - (read logical address - write logical address) );

2. When the read address is less than the write address, the water line value = write logical address - read logical address;

High water line alarm: When the water line value is greater than the preset high water line value, the high water line alarm is reported, otherwise the alarm is cancelled;

Low water line alarm: When the water line value is less than the preset low water line value, the low water line alarm is reported, otherwise the alarm is cancelled;

Empty alarm: When the read address sign bit = write address sign bit, and the read logical address = write logical address, the null alarm is valid, otherwise it is invalid;

Full alarm: Read address symbol bit write address sign bit, and read logical address = write logical address, full alarm is valid, otherwise invalid;

Write overflow alarm: Read address symbol bit 地址 write address sign bit, and read logical address <write logic address, write overflow alarm is valid, otherwise invalid;

Read overflow alarm: When read address sign bit = write address sign bit, and read logical address > write logic Address, read overflow alarm is valid, otherwise invalid.

Since the above block quantity table (BLK NUM TBL ), the block address table (BLK_ADDR_TBL ), and the first block address table ( FIRST — BLK — ADDR — TBL ) are automatically generated according to the service channel-block mapping table (CH BLK MAP TBL ), When the user updates the content of the CH BLK MAP TBL in real time according to the requirements, the embodiment of the present invention further provides a corresponding mechanism for refreshing the entry. Further, the automatic entry refreshing unit 404 is further configured to use the service channel-block that is pre-configured by the user. The mapping table generates a block quantity table, a first block address table, and a block address table as a main table for querying by the FIFO write address remapping unit and the FIFO read address remapping unit, and backing up the block quantity table, the first block address table, and the block address The table serves as a backup form.

Since the user may update the content of the CH-BLK-MAP-TBL in real time according to the requirements, the above-mentioned entry automatic refreshing unit is also used to periodically configure the content of the service channel-block mapping table according to the content of the user. The table, the first address table, and the table of the block address table are refreshed, and the refreshed table is switched to the corresponding master table for query by the FIFO write address remapping unit and the FIFO read address remapping unit.

The working process of the table item automatic refresh unit is as shown in FIG. 6, and the BLK_NUM_TBL, FIRST_BLK_ADDR_TBL and BLK_ADDR-TBL in the FIFO write address remapping unit and the FIFO read address remapping unit are generated. The main table and the standby table are operated by the multi-channel FIFO working logic. The table item automatically refreshes the unit operation standby table and performs real-time table refresh and active/standby switching.

The automatic refresh unit of the entry can ensure the consistency of the information of the active and standby tables, and the operation of refreshing the entry does not affect the read and write process of the multi-channel FIFO queue controller, and dynamically adds and deletes services according to the needs of the user, and does not There is business impact.

The process of generating each table by the table item refreshing unit and refreshing each table is actually the same. To simplify the description, the following is a detailed description of the process of refreshing each table as follows:

Traversing the service channel-block mapping table every y cycles, the y=n*x, n is the number of blocks of the data cache, and X is the number of services (the maximum number of possible services); in y cycles, just all over CH-BLK-MAP-TBL x times.

Each time traversing, for each service, the number of blocks occupied by the service is accumulated, the number of blocks occupied by each service is counted, and the block quantity table to be refreshed is written (prepared table);

Each time traversing, for each block in the data cache, the physical address corresponding to the block is written into the block address table to be refreshed (prepared table);

Each time the traversal, for each block in the data cache, when it is the first block corresponding to the occupied service, the logical address of the block is written into the first block address table (prepared table) to be refreshed.

FIG. 7 is a logic block diagram of the multi-channel FIFO queue controller provided in the first embodiment. The data buffer is divided into n blocks, each service block shares a data cache, and the address remapping logic (for example, can be implemented by an address remapping unit). According to the service channel number of reading and writing, the access address of the read/write operation in the data cache can be determined, and the empty state generating logic (for example, can be implemented by the FIFO alarm unit) generates a state alarm that the service storage space is full according to the logical address. The remapping entry refresh logic (by the table entry auto-refresh unit) refreshes the entries required for remapping.

Example 2:

The structure and working principle of the multi-channel FIFO queue controller provided in the second embodiment are similar to the multi-channel FIFO queue controller provided in the first example. As shown in FIG. 8, the multi-channel FIFO queue controller also includes a FIFO write address remapping unit. 801 (address responsible for determining the write operation) and FIFO read address remapping unit 802 (responsible for determining the address of the read operation), data cache 803, read and write control unit (not illustrated in FIG. 8), table entry automatic refresh unit 804, and The FIFO alarm unit 805 differs in that the FIFO write address remapping unit 801 and the FIFO read address remapping unit 802 contain entries different from the first example.

Specifically, as shown in FIG. 8, the FIFO write address remapping unit 801 and the FIFO read address remapping unit 802 respectively include a quantity table (BLK_NUM_TBL), a logical address table (LOGIC ADDR TBL), and a block remapping. Table (BLK REMAP TBL), where:

The contents of the block quantity table and the logical address table are the same as those of the first embodiment, and will not be described here. The data structure of the block remapping table is as shown in FIG. 9. The table is a two-dimensional table of n*x size (n The number of blocks for RAM, x is the maximum number of possible services, and the content is the jth value of j for a service whose service channel number is i (i is any integer in (0~x)) Is the physical address of any block in (0~n).

In fact, the BLK-REMAP-TBL in the second example realizes the function of the FIRST-BLK-ADDR-TBL+BLK ADDR TBL in the first instance in the remapping process of the address, and the storage space ratio occupied by the table. A single FIRST-BLK-ADDR-TBL or a single BLK ADDR TBL is larger, which is another way to reduce the complexity of the space.

Or the number of data RAM blocks is 12, the maximum possible number of services is 6, and only 3 channels (channel numbers 0, 2, 5) are actually used. For example, the content of BLK-REMAP-TBL is shown in Figure 10. Channel 0 occupies blocks of 0, 3, 6, and 9; channel 2 occupies blocks of 1, 4, 7, and 10; channel 5 occupies blocks of 2, 5, 8, and 11. The space filled with X in Fig. 11 indicates the block corresponding to the channel that does not exist.

Correspondingly, in the second example, the process of remapping the read/write address by the FIFO write address remapping unit 801 and the FIFO read address remapping unit 802 is also different from that of the first example, as follows:

The FIFO write address remapping unit 801 and the FIFO read address remapping unit 802 respectively query the block number table (BLK NUM TBL) and the logical address table based on the service channel number sent from the previous stage.

( LOGIC — ADDR — TBL ), obtain the number of blocks occupied by the service ( blk — num ), the logical address ( logic_blk_addr ) of the block to be read and written by the service, and the offset address ( logic_shift_addr ) in the block;

The FIFO write address remapping unit 801 and the FIFO read address remapping unit 802 can learn the logical address range of the block occupied by the service by querying the number of blocks (blk_num) occupied by the service, and the service is to be read and written. When the logical address of the block is in the logical address range, the block remapping table (BLK_REMAP_TBL) is queried according to the service channel number of the service and the logical address (logic_blk_addr) of the block to be read or written by the service. Get the physical address of the block to be read or written by the service

(phy blk addr ), according to the physical address (phy-blk_addr) of the block to be read and written by the service and the offset address (logic_shift_addr) in the block, determining that the data to be read and written by the service is in the data cache of The physical address (phy_addr); and {logic_blk_addr, logic_shift_addr}+l is used as the logical address of the data to be accessed by the service to update the logical address table (LOGIC_ADDR_TBL).

Similarly, the FIFO write address remapping unit 801 and the FIFO read address remapping unit 902, if the respective logical address table is queried to determine that the logical address of the block to be read or written by the service exceeds the upper limit of the range of the logical address, the logical address table is The logical address of the block to be read or written by this service is set to zero.

If the number of blocks of the service occupied data cache read by the FIFO write address remapping unit and the FIFO read address remapping unit is 0 during the above address remapping, it is determined that the service channel number of the service is illegal, read and write. According to this situation, the control unit controls the read and write enable of the service to be 0.

For the FIFO alarm unit 805 in the second embodiment, the specific working principle is the same as that in the first embodiment, and details are not described herein again.

For the entry automatic refresh unit 804 in the second embodiment, similar to the first example, respectively, the FIFO write address remapping unit 801 and the FIFO read address remapping unit 802 are connected, respectively, for the channel-block mapping table (CH) according to the user pre-configuration. BLK MAP TBL ), respectively generates a block quantity table (BLK NUM TBL ) and a block remapping table (BLK_REMAP_TBL) included in the FIFO write address remapping unit and the FIFO read address remapping unit as a main table for FIFO writing The address remapping unit 801 and the FIFO read address remapping unit 802 perform a query and back up the block number table and the block remapping table as a standby table.

The table item automatic refreshing unit 804 may also periodically refresh the table of the block quantity table and the block remapping table according to the content of the configuration of the service channel-block mapping table by the user, and switch the refreshed table. The corresponding main table is queried by the FIFO write address remapping unit and the FIFO read address remapping unit.

Further, the foregoing table item refreshing unit 804 specifically refreshes each table by: traversing the service channel-block mapping table every y cycles, where y=n*x, n is the number of blocks of the data cache, and X is The number of services (the maximum number of possible services);

Each time traversing, for each service, the number of blocks occupied by the service is accumulated, the number of blocks occupied by each service is counted, and the block quantity table to be refreshed is written; Each time the traversal, for each service, the physical address of each block occupied by the service is written into the block remapping table to be refreshed.

The process of generating the block quantity table and the block remapping table by the foregoing table item refreshing unit is the same as the process of refreshing the block quantity table and the block remapping table, and details are not described herein again.

The above multi-channel FIFO queue controller provided by the embodiment of the present invention can be implemented by various hardware circuit units, for example, by a common FPGA.

The multi-channel FIFO queue controller provided by the embodiment of the present invention can realize that multiple services share the same data cache, which greatly saves the resources occupied by the RAM of the super-large bit-width multi-channel FIFO entity, and has been experimentally proved that the number of services is In the case of a multi-channel FIFO with a minimum service depth requirement of 16 storage units and a maximum service depth requirement of 128 storage units, if it is designed according to the existing scheme 1, approximately 400 RAMs are required, and the application is required. The implementation of the above multi-channel FIFO queue controller provided by the embodiment of the invention requires only no more than 80 pieces of RAM (including additional entries), which saves about 80% from the RAM resource, and other resources can also be saved. It can also save nearly 70%, and the resources saved are still very impressive.

Based on the same inventive concept, the embodiment of the present invention further provides a multi-channel FIFO queue access method. The principle of the method is similar to the foregoing multi-channel FIFO queue controller. Therefore, the implementation of the method can be referred to the foregoing multi-channel. The implementation of the FIFO queue controller will not be repeated here.

The access method of the multi-channel FIFO queue provided by the embodiment of the present invention, as shown in FIG. 11, includes the following steps:

51101. Determine, according to an identifier of the service, a physical address of a block to be accessed in a data cache, where the data cache includes multiple blocks, each block includes m storage units, where m is a positive integer;

S102, determining, according to the physical address of the to-be-accessed block and the data to be accessed, the physical address of the data to be accessed in the data cache;

51103. Access the data to be accessed according to the physical address of the to-be-accessed data determined by the address determining circuit in the data cache. In the above S1101, the determining the physical address of the data to be accessed in the data cache may be implemented by:

Further, determining, according to the identifier of the service, the logical address of the to-be-accessed block and the address of the to-be-accessed data in the to-be-accessed block, according to the block address to be accessed a mapping relationship, determining a physical address of the to-be-accessed block, determining the to-be-accessed data according to the physical address of the to-be-accessed block and the address of the to-be-accessed data in the to-be-accessed block The physical address in the data cache can be implemented in the following two ways:

method one:

Obtaining, according to the logical address of the data to be accessed, a first logical address (logic_blk_addr) and an intra-block offset address (logic_shift_addr) of the block to be accessed;

Querying the first block address table according to the identifier of the service, and obtaining a logical address (first_blk_addr) of the first block of the plurality of blocks occupied by the service;

Querying a block address table according to a second logical address of the block to be accessed, obtaining a physical address of the block to be accessed, where a second logical address of the block to be accessed is equal to a sum of logic_blk_addr and first blk addr; Determining, according to the physical address of the to-be-accessed block and the intra-block offset address, a physical address of the data to be accessed in the data cache;

The block address table records the identifier of the service, and the mapping relationship between the second logical address of the multiple blocks occupied by the service and the physical addresses of the multiple blocks occupied by the service, where the service is occupied. a second logical address of the plurality of blocks and a physical address of the plurality of blocks occupied by the service

- correspondingly, the second logical address of the block to be accessed takes any integer in [first_blk_addr, first-blk_addr+n], and the n is in the service occupation data cache. The number of blocks;

Method 2:

Different from the first method, in the second method, determining the physical address of the data to be accessed in the data cache needs to query the logical address table and the block remapping table. Specifically, the process is as follows: according to the identifier of the service Querying a logical address table to obtain a logical address of the data to be accessed;

Obtaining, according to the logical address of the data to be accessed, a logical address (logic blk addr ) and an intra-block offset address (logic_shift_addr ) of the block to be accessed;

The block remapping table records the identifier of the service, and the mapping relationship between the logical address of the multiple blocks occupied by the service and the physical addresses of the multiple blocks occupied by the service, and multiple blocks occupied by the service Corresponding to the logical address of the plurality of blocks occupied by the service, the logical address of the block to be accessed is any integer of [0, n], and the n is occupied by the service. The number of blocks in the data cache, the specific data structure can be seen in Figure 8 above.

After the step S10102 determines the physical address of the data to be accessed in the data cache, the access method of the multi-channel FIFO queue provided by the embodiment of the present invention may also perform the following steps:

Update the logical address table with {logic-blk_addr, logic_shift_addr}+l as the logical address of the next data to be accessed by the service.

Further, in the foregoing manners 1 and 2, when the logical address of the to-be-accessed data is obtained by querying the logical address table according to the identifier of the service, the step of querying the block quantity table may be performed according to the service identifier. The block quantity table records the service identifier of multiple services, the number of blocks of the data cache occupied by each service, and the purpose of querying the block quantity table, the number of blocks of the data cache occupied by the service can be known, and then the logical address of the service is determined. The range of the data to be accessed in the logical address table is set to 0 when it is determined that the logical address of the data to be accessed by the service exceeds the upper limit of the logical address range.

Further, in the foregoing manners 1 and 2, when the number of blocks occupied by the service is 0 according to the service channel number, the service channel number of the service is determined to be illegal, and the read/write of the service is controlled. Can be 0 (ie blocking the read and write operations of the business;).

Further, in the access method of the multi-channel FIFO queue provided by the embodiment of the present invention, the logical address table further records the symbol bits of the current read and write addresses of each service, and the symbol bits are data representing the data to be read and written by each service. Whether the logical address is increased to a bit equal to the size of the occupied space; in the process of accessing the data cache (read and/or write operation), the alarm of the data cache empty and the alarm of the waterline can also be implemented, and the specific process is as follows: For each service, when the logical address of the data to be read (hereinafter referred to as the read logical address) is larger than the logical address of the data to be written (hereinafter referred to as the write logical address), the watermark value = address space size is calculated - (read Logical address - write logical address), when the read logical address is less than the write logical address, calculate the watermark value = write logical address - read logical address;

And, when the water line value is higher than the preset high water line value, the high water line alarm is reported; when the water line value is less than the set low water line value, the low water line alarm is reported;

When the read address sign bit = the write address sign bit, and the current read logical address = write logical address, the alarm is reported as empty;

When the read address sign bit writes the address sign bit, and the read logical address = write logical address, then the upper is 满 full alarm;

When the read address sign bit writes the address sign bit, and the read logical address <write logical address, the overflow alarm is written.

When the read address sign bit = write address sign bit, and the read logical address > write logical address, the overflow alarm is read.

Further, the block quantity table, the first block address table, and the block address table used in the query in the foregoing manner 1 are generated by:

Generating a block quantity table, a first block address table, and a block address table as a main table for query according to the service channel-block mapping table configured by the user; wherein, the service channel-block mapping table records each block and the data cache The mapping relationship between the occupied services (using the service channel number as the identifier).

Preferably, after the block number table, the first block address table, and the block address table are generated as the main table, the embodiment of the present invention may further perform the following steps:

Backing up the block quantity table, the first block address table, and the block address table as a backup table;

Periodically refreshing the block quantity table, the first block address table, and the block address table as the standby table according to the content of the configuration of the service channel-block mapping table by the user, and switching the refreshed tables to the corresponding main table. For inquiry.

Further, refreshing the block quantity table, the first block address table, and the block address table as the standby table, Specifically achieved through the following process:

The service channel-block mapping table is traversed every y cycles, where y=n*x, n is the number of blocks of the data cache, and X is the number of services;

Each time traversing, for each service, the number of blocks occupied by the service is accumulated, the number of blocks occupied by each service is counted, and the block quantity table to be refreshed is written;

Each time traversing, for each block in the data cache, the physical address corresponding to the block is written into the block address table to be refreshed;

Each time the traversal, for each block in the data cache, when it is the first block corresponding to the occupied service, the logical address of the block is written into the first block address table to be refreshed.

Further, the block quantity table and the block remapping table used in the query in the foregoing mode 2 are generated in the following manner:

Generating a block quantity table and a block remapping table as a main table for query according to the service channel-block mapping table configured by the user; wherein the service channel-block mapping table records each block in the data cache and the occupied service The mapping relationship between.

Preferably, after the block number table and the block remapping table are generated as the main table, the embodiment of the present invention may further perform the following steps:

Backing up the block quantity table and the block remapping table as a backup table;

Periodically, according to the content of the configuration of the service channel-block mapping table by the user, the block quantity table and the block remapping table as the standby table are refreshed, and the refreshed tables are switched to the corresponding main table for query.

Further, refreshing the block quantity table and the block remapping table as the standby table is specifically implemented by the following process:

The multi-channel FIFO queue controller and the access method thereof provided by the embodiment of the invention, the multi-channel FIFO queue controller packet address determining circuit and the control circuit. The data buffer is divided into a plurality of blocks, and the address determining circuit can determine the physical address of the block to be accessed based on the identity of the service. The address determining circuit can further determine the physical address of the data to be accessed in the data cache based on this. The control circuit can access the data to be accessed according to the physical address of the data to be accessed determined by the address determining circuit in the data cache. Therefore, the above technical solution helps the sharing of data caches by multiple services, which helps to reduce the occupation of resources of the FIFO queue. Furthermore, embodiments of the present invention provide a method of determining the physical address of data to be accessed. That is, the physical address of the block to be accessed is determined according to the identifier of the service, and the physical address of the data to be accessed in the data cache is determined according to the physical address of the block to be accessed and the data to be accessed in the in-block address to be accessed. The data to be accessed is accessed according to the physical address in the data cache according to the data to be accessed. In the above technical solution, in the process of determining the physical address of the data to be accessed in the data cache, there is no need to rely on the linked list pointer, and the reliability is high.

Further, the multi-channel FIFO queue controller and the access method thereof are provided by the embodiment of the present invention, and the access address of the data cache is divided into two levels, a logical address and a physical address, and a mapping relationship between the two is established, and the logic is established. The address is used to determine the corresponding physical address. Since the logical address is linear in the data buffer space, the logical address can be used to identify the empty state of the current data buffer and whether the current water line reaches the preset high and low water line. This makes up for the shortcomings of the prior art, such as Scheme 1 and Scheme 2, which do not recognize the data cache storage state.

Further, in the multi-channel FIFO queue controller and the access method thereof provided by the embodiment of the present invention, the block quantity table, the first block address table, and the block address table (or the block quantity table) according to the determination of the read/write address of each service are determined. And the block remapping table) are generated and refreshed according to the content of the service channel-block mapping table configured by the user. Therefore, the reliability of determining the physical address of the data to be read and written of each service is almost equivalent to the user configuration. The reliability of the entries, the bandwidth of the business and other differences Often unrelated, further ensuring the reliability of multi-channel FIFO read and write operations.

In addition, the multi-channel FIFO queue controller and the access method thereof provided by the embodiment of the present invention, the block quantity table, the first block address table, and the block address table according to the determination of the address of the data to be read and written for each service (or The block quantity table and the block remapping table are periodically refreshed, and an active/standby switching mechanism is provided to implement dynamic changes such as additions and deletions of services without affecting the read and write operations of service data. The spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and modifications of the invention

Claims

Rights request

1. A multi-channel first-in-first-out buffer queue FIFO queue controller, characterized by including: an address determination circuit and a control circuit;

The address determination circuit is used for:

Determine the physical address of the block to be accessed in the data cache according to the identifier of the service. The data cache contains multiple blocks, each block contains m storage units, and m is a positive integer;

Determine the physical address of the data to be accessed in the data cache according to the physical address of the block to be accessed and the address of the data to be accessed in the block to be accessed;

The control circuit is used for:

The data to be accessed is accessed according to the physical address of the data to be accessed in the data cache determined by the address determination circuit.

2. The FIFO queue controller according to claim 1, wherein the address determination circuit is specifically used for:

According to the identification of the service, determine the logical address of the block to be accessed and the address of the data to be accessed in the block to be accessed;

According to the logical address of the block to be accessed, and the physical address of the block to be accessed;

The physical address of the data to be accessed in the data cache is determined according to the physical address of the block to be accessed and the address of the data to be accessed in the block to be accessed.

3. The FIFO queue controller according to claim 2, characterized in that the address determination circuit is specifically used for: Query the logical address table according to the identifier of the service to obtain the logical address of the data to be accessed;

Obtain the first edit address logic blk addr and the intra-block offset address logic_shift_addr of the block to be accessed according to the logical address of the data to be accessed;

Query the first block address table according to the identifier of the service to obtain the logical address of the first block among the multiple blocks occupied by the service first_blk_addr;

Query the block address table according to the second logical address of the block to be accessed to obtain the physical address of the block to be accessed. The second logical address of the block to be accessed is equal to the sum of logic blk addr and first_blk_addr;

Determine the physical address of the data to be accessed in the data cache according to the physical address of the block to be accessed and the offset address within the block;

Wherein, the identifier of the service is recorded in the block address table, as well as the mapping relationship between the second logical addresses of the multiple blocks occupied by the service and the physical addresses of the multiple blocks occupied by the service. The second logical addresses of the plurality of blocks correspond to the physical addresses of the plurality of blocks occupied by the service. The value of the second logical address of the block to be accessed is [first_blk_addr, first_blk_addr +n], where n is the number of blocks in the data cache occupied by the service;

The first block address table records the identifier of the service and the logical address of the first block among the multiple blocks occupied by the service;

The logical address table records the identifier of the service and the logical address of the data to be accessed. The value of the logical address of the data to be accessed is [0, m x the number of blocks occupied by the service] any integer.

4. The FIFO queue controller according to claim 2, wherein the address determination circuit is specifically used for:

Query the logical address table according to the identifier of the service to obtain the logical address of the data to be accessed; According to the logical address of the data to be accessed, the return address logic blk addr and the intra-block offset address logic_shift_addr of the block to be accessed are obtained; according to the identifier of the service and the block to be accessed The logical address logic_blk_addr queries the block remapping table to obtain the physical address of the block to be accessed; determine the block to be accessed based on the physical address of the block to be accessed and the offset address within the block. The physical address of the data in the data cache;

Wherein, the identifier of the service and the logical address of the data to be accessed are recorded in the logical address table. The value of the logical address of the data to be accessed is [0, m x the value of the block occupied by the service. quantity] any integer;

The block remapping table records the identification of the service and the mapping relationship between the logical addresses of the multiple blocks occupied by the service and the physical addresses of the multiple blocks occupied by the service. The multiple blocks occupied by the service are recorded in the block remapping table. The logical address corresponds to the physical addresses of the multiple blocks occupied by the service. The logical address of the block to be accessed is any integer in [0, n], where n is the service occupied. The number of blocks in the data cache.

5. The FIFO queue controller according to claim 3 or 4, characterized in that the address determination circuit is also used to:

After the control circuit accesses the data to be accessed, the logical address of the data to be accessed in the logical address table is replaced with the logical address of the data to be accessed next by the service.

6. A multi-channel first-in-first-out cache queue FIFO queue access method, which is characterized by including:

According to the identification of the service, determine the physical address of the block to be accessed in the data cache. The data cache contains multiple blocks, each block contains m storage units, and m is a positive integer;

7. The method of claim 6, wherein determining the physical address of the data to be accessed in the data cache includes:

Determine the physical address of the block to be accessed according to the logical address of the block to be accessed, and according to the mapping relationship between the logical address of the block to be accessed and the physical address of the block to be accessed;

8. The method according to claim 7, characterized in that, according to the identifier of the service, the logical address of the block to be accessed and the address of the data to be accessed in the block to be accessed are determined, According to the logical address of the block to be accessed, and according to the logical physical address of the block to be accessed, according to the physical address of the block to be accessed and the data to be accessed within the block to be accessed address, determining the physical address of the data to be accessed in the data cache, specifically including:

Query the logical address table according to the identifier of the service to obtain the logical address of the data to be accessed;

Obtain the first logical address logic blk addr and the intra-block offset address logic shift addr of the block to be accessed according to the logical address of the data to be accessed;

Query the first block address table according to the identifier of the service to obtain the logical address of the first block among the multiple blocks occupied by the service first-blk-addr;

Query the block address table according to the second logical address of the block to be accessed to obtain the physical address of the block to be accessed. The second logical address of the block to be accessed is equal to the relationship between logic_blk_addr and first_blk_addr. and;

According to the physical address of the block to be accessed and the offset address within the block, the block to be accessed is determined. The physical address of the requested data in the data cache;

Wherein, the identifier of the service is recorded in the block address table, as well as the mapping relationship between the second logical addresses of the multiple blocks occupied by the service and the physical addresses of the multiple blocks occupied by the service. Second logical addresses of multiple blocks and physical addresses of multiple blocks occupied by the service

——Correspondingly, the value of the second logical address of the block to be accessed is any integer in [first-blk-addr, first-blk-addr+n], where n is the number in the service occupied data cache number of blocks;

9. The method according to claim 7, characterized in that, according to the identifier of the service, the logical address of the block to be accessed and the address of the data to be accessed in the block to be accessed are determined, According to the logical address of the block to be accessed, and according to the logical physical address of the block to be accessed, according to the physical address of the block to be accessed and the data to be accessed within the block to be accessed address, determining the physical address of the data to be accessed in the data cache, specifically including:

According to the logical address of the data to be accessed, the logical address logic_blk_addr and the intra-block offset address logic_shift_addr of the block to be accessed are obtained;

Query the block remapping table according to the identifier of the service and the logical address logic_blk_addr of the block to be accessed, and obtain the physical address of the block to be accessed;

The block remapping table records the identification of the service, and the mapping relationship between the logical addresses of the multiple blocks occupied by the service and the physical addresses of the multiple blocks occupied by the service. The multiple blocks occupied by the service The logical address corresponds to the physical addresses of the multiple blocks occupied by the service. The logical address of the block to be accessed is any integer in [0, n], where n is the service occupied. The number of blocks in the data cache.

10. The method according to claim 8 or 9, characterized in that, after the control circuit accesses the data to be accessed, it further includes:

The logical address of the data to be accessed in the logical address table is replaced with the logical address of the data to be accessed next by the service.