WO2015024452A1

WO2015024452A1 - Branch predicting method and related apparatus

Info

Publication number: WO2015024452A1
Application number: PCT/CN2014/083882
Authority: WO
Inventors: 侯锐; 冯煜晶; 郭旭斌; 张乾龙
Original assignee: 华为技术有限公司
Priority date: 2013-08-21
Filing date: 2014-08-07
Publication date: 2015-02-26
Also published as: CN104423929B; CN104423929A

Abstract

A branch predicting method and a related apparatus. Applied in a server, the processor comprises: a first BTAC that stores information about a mapping between a register identifier and a predicted target jump-to address, and a second BTAC that stores information about a mapping between a field of a program counter and a predicted target jump-to address. The brand predicting method comprises: reading an instruction from an instruction buffer; if determining that the instruction satisfies a register prediction condition, obtaining a predicted target jump-to address of the instruction from the first BTAC according to a register identifier of the instruction; and if determining that the instruction does not satisfy the register prediction condition, obtaining a predicted target jump-to address of the instruction from the second BTAC according to a program counter of the instruction. Therefore, the problem that branch prediction accuracy is affected during BTAC sharing is effectively solved.

Description

The present invention claims the priority of a Chinese patent application filed on August 21, 2013 by the Chinese Patent Office, the application number is 201310367653.9, and the invention is entitled "a branch prediction method and related device". The entire contents are incorporated herein by reference.

Technical field

The present invention relates to the field of computer systems, and in particular, to a branch prediction method and related apparatus.

Background technique

Current processors use a pipelined architecture that allows sequential execution of instruction streams to be executed concurrently. This way of processing instructions greatly improves the execution efficiency of the processor. Ideally, each stage of the pipeline (that is, the pipeline layer) takes only one clock cycle, so one instruction can be completed per clock cycle. But the actual situation is not so ideal, because there may be mutual dependencies between instructions that affect the degree of parallelism of instruction execution. For example, data dependencies, control dependencies (such as branch instructions), resource contention, and interrupts all affect the parallelism of instructions.

The actual program includes branch instructions. The branching behavior of the branch instruction is often determined until the back end of the pipeline. Therefore, the branch instruction may cause a control risk and cause the pipeline to stall. At the same time, the processor cannot determine from which address to take an instruction. Until this branch instruction is executed. Most processors use different forms of branch prediction mechanism, so that the target branch direction and target jump address of the conditional branch instruction can be predicted at the front end of the pipeline, so that the processor can predictively fetch instructions and execute instructions. . If the branch prediction is correct or the correct rate is high, the performance and power consumption of the processor can be greatly improved. If the branch prediction is wrong, it means that the instruction fetched cannot be executed, the wrong instruction needs to be cleared from the buffer, and then Re-fetch the instruction from the correct address and execute it. The Branch Target Address Cache (BTAC) is used to predict the target jump address of the indirect branch instruction. BTAC uses the structure of the cache, with part of the program counter (PC, Program Counter) as the index (ie index), and part of it as the tag (ie label), such as the lower 8 bits of the PC as the index, and the high 8 of the PC. Bit as a tag. Each Entry (ie, entry) of the BTAC corresponds to an index and a tag, and each Entry of the BTAC is set with a valid bit for recording whether the Entry stores valid history information (historical information is predicted) The target jump address), where the target jump address stored in the entry is a virtual address (VA, Virtual Address). If the BTAC is full, like Cache, it is also necessary to determine which of the least recently used entries can be replaced according to a certain replacement algorithm.

In a multi-threaded processor, there are two ways to set up BTAC:

One is shared BTAC. Multiple threads share the same BTAC. Each thread uses its own PC to index the contents stored in BTAC. Although this method saves the area, since the index address of BTAC is the PC of each thread, and the PCs of different threads may be the same, the historical information between different threads is stored in the same BTAC, which will affect the branch prediction. Accuracy rate

The other is the exclusive BTAC, where each thread sets up a BTAC, and the BTAC provides the service for predicting the branch target jump address for the corresponding thread. Although this method improves the prediction accuracy to some extent compared with the shared method, it greatly wastes hardware resources and area.

Whether it is a shared BTAC or an exclusive BTAC, they have one thing in common: As long as the BTAC is not satisfied, the PC with the branch instruction is used as an index to record all the history information related to the branch instruction. However, in the actual program, there is a high probability that there are many different branch instructions that jump to the same target address, such as the standard library function like "Printf" in C++, compiled by the compiled version. As you can see from the instructions, different branch instructions always jump to the same destination address. Then, using the traditional BTAC architecture, these different branch instructions, while jumping to the same destination address, will still occupy multiple entries in the BTAC to record their relevant history information.

As can be seen from the above, in the multi-threaded processor, BTAC resource sharing, branch prediction The contradiction between accuracy rates is extremely prominent.

Summary of the invention

Aspects of the present invention provide a branch prediction method and related apparatus for solving the problem of affecting the accuracy of branch prediction when sharing BTAC.

In order to solve the above technical problems, the following technical solutions are provided:

A first aspect of the present invention provides a branch prediction method, which is applied to a processor, where the processor includes: a first branch target address prediction buffer and a second branch target address prediction buffer, and the first branch target address prediction cache. The storage device stores: a correspondence identifier of the register identifier and the predicted target jump address, wherein the second branch target address prediction buffer stores: correspondence information between the field of the program counter and the predicted target jump address, where The above branch prediction method includes: reading an instruction from an instruction cache;

If it is determined that the above read command satisfies the register prediction condition, then:

Obtaining, from the first branch target address prediction buffer, a predicted target jump address of the read instruction according to the read register identifier of the instruction;

If it is determined that the above-mentioned instruction read does not satisfy the above register prediction condition, then:

And acquiring, according to the read program counter of the above instruction, the predicted target jump address of the read instruction from the second branch target address predictor buffer;

The above register prediction conditions include: The type of the instruction is an unconditional indirect jump branch instruction.

Based on the first aspect, in a first possible implementation manner, the foregoing register prediction condition further includes: the register identifier in the instruction is a specific register identifier;

The above-mentioned instructions determined to be read satisfy the register prediction condition, specifically:

When the type of the above instruction is an unconditional indirect jump branch instruction, and the register identifier in the above instruction is a specific register identifier, it is determined that the read instruction satisfies the register prediction condition;

The foregoing determining that the read instruction does not satisfy the foregoing register prediction condition, specifically: when the type of the instruction is not an unconditional indirect jump branch instruction, or the above instruction When the register identifier in the register is not identified by a specific register, it is determined that the above-mentioned instruction read does not satisfy the register prediction condition.

Based on the first aspect, or the first possible implementation manner of the first aspect, in the second possible implementation manner, the foregoing reading the instruction from the instruction cache includes:

The instruction to be read is pre-decoded to obtain the type information of the instruction to be read; the reading instruction further includes: determining, according to the type information of the instruction obtained above, whether the type of the currently read instruction is an unconditional indirect jump Transfer branch instructions.

Based on the first aspect, or the first possible implementation of the first aspect, or the second possible implementation of the first aspect, in a third possible implementation, before the reading instruction, if The function called when the high-level language is compiled is a standard library function. Then, the type of the compiled instruction is specified as an unconditional indirect jump branch instruction.

A second aspect of the present invention provides a branch prediction apparatus, which is applied to a processor, where the processor includes: a first branch target address prediction buffer and a second branch target address prediction buffer, and the first branch target address prediction cache. The device stores: a correspondence identifier of the register identifier and the predicted target jump address, and the second branch target address prediction buffer stores: correspondence information between the partial field of the program counter and the predicted target jump address, or And the corresponding relationship information of all the fields of the program counter and the predicted target jump address, wherein the branch prediction device includes:

a reading unit, configured to read an instruction from the instruction cache;

a prediction acquiring unit, configured to: when determining that the instruction read by the reading unit satisfies a register prediction condition, acquire the read from the first branch target address prediction buffer according to the register identifier of the instruction read by the reading unit Taking the prediction target jump address of the above instruction read by the unit; when it is determined that the instruction read by the reading unit does not satisfy the register prediction condition, the program counter of the instruction read according to the reading unit is from the second Obtaining, in the branch target address prediction buffer, a predicted target jump address of the above instruction read by the reading unit;

The foregoing register prediction condition includes: The type of the instruction is an unconditional indirect jump branch instruction. According to the second aspect of the present invention, in a first possible implementation, the foregoing register prediction condition further includes: the register identifier in the instruction is a specific register identifier;

The above branch prediction device further includes:

a determining unit, configured to: when the type of the instruction read by the reading unit is an unconditional indirect branch branch instruction, and the register identifier in the instruction read by the reading unit is a specific register identifier, determining the reading unit to read The fetched instruction satisfies the register prediction condition; when the type of the instruction read by the read unit is not an unconditional indirect jump branch instruction, or the register identifier in the instruction read by the read unit is not a specific register identifier, It is determined that the above instruction read does not satisfy the register prediction condition.

Based on the second aspect of the present invention, or the first possible implementation of the second aspect of the present invention, in the second possible implementation, the branch prediction apparatus further includes:

a pre-decoding unit, configured to pre-decode an instruction to be read by the reading unit, to obtain type information of an instruction to be read by the reading unit;

The determining unit is configured to determine, after the reading unit reads the instruction, whether the type of the instruction currently read by the reading unit is an unconditional indirect branch branch instruction according to the type information of the instruction obtained by the pre-decoding unit.

Based on the second aspect of the present invention, or the first possible implementation of the second aspect of the present invention, in a third possible implementation, the foregoing branch prediction apparatus further includes:

a compilation unit for compiling high-level languages;

The specifying unit is configured to specify the type of the compiled instruction as an unconditional indirect jump branch instruction when the function called when the above compiling unit compiles the high-level language is a standard library function.

It can be seen that, in the embodiment of the present invention, the first BTAC and the second BTAC are set, and the register identifier is used as the index in the first BTAC (that is, the correspondence relationship between the register identifier and the predicted target jump address is stored in the first BTAC) The second BTAC uses the PC as an index (ie, stores the correspondence information between the partial field of the program counter and the predicted target jump address in the second BTAC), and uses the first when the read instruction satisfies the register prediction condition. The BTAC performs branch prediction, otherwise, the second BTAC is used for branch prediction. By The target jump addresses of the unconditional indirect jump branch instructions with the same register identifier are necessarily the same, so that even the history information of the plurality of unconditional indirect jump branch instructions having the same target jump address is stored in the same Entry of the first BTAC. The accuracy of the branch prediction is also not affected. In other words, the technical solution provided by the present invention can not affect the accuracy of the branch prediction when sharing the first BTAC, thereby implementing the BTAC under the premise of ensuring the accuracy of the branch prediction. Resource sharing is possible.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description of the drawings used in the embodiments or the prior art description will be briefly made. Obviously, the drawings in the following description It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.

1 is a schematic flow chart of an embodiment of a branch prediction method according to the present invention; FIG. 2 is a schematic flowchart of another embodiment of a branch prediction method according to the present invention; FIG. 3 is a schematic diagram of a branch prediction method provided by the present invention. FIG. 4 is a schematic structural diagram of an embodiment of a branch prediction apparatus according to the present invention; FIG. 5 is a schematic structural diagram of another embodiment of a branch prediction apparatus according to the present invention.

detailed description

Embodiments of the present invention provide a branch prediction method and related apparatus.

The technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. The embodiments are merely a part of the embodiments of the invention, and not all of the embodiments. Based on the embodiments of the present invention, various other embodiments obtained by those skilled in the art without creative efforts are within the scope of the present invention.

A branch prediction method provided by an embodiment of the present invention is described below. The branch prediction method in the embodiment is applied to the processor, where the processor includes: a first BTAC and a second BTAC, where the first BTAC stores: correspondence information between the register identifier and the predicted target jump address, the foregoing The BTAC stores: a correspondence between the field of the PC and the predicted target jump address, optionally, the correspondence information of the partial field of the PC and the predicted target jump address is stored in the second BTAC, or Corresponding relationship information of all the fields of the PC and the predicted target jump address is stored in the second BTAC. Referring to FIG. 1, a branch prediction method in an embodiment of the present invention includes:

101. Reading an instruction from an instruction cache;

In the embodiment of the present invention, the instruction read by step 101 may be a branch instruction or a non-branch instruction. Generally, the branch instruction can be divided into the following two ways: One is to divide the type of the branch instruction into a conditional branch instruction and an unconditional branch instruction for the jump condition, wherein the conditional branch instruction performs the branch jump when a certain condition is met. The unconditional branch instruction does not need to satisfy any condition, and always performs a branch jump; the other is to divide the type of the branch instruction into a direct jump branch instruction and an indirect jump branch instruction for the target jump address, where The offset of the target jump address indicated by the jump branch is directly specified in the instruction with an immediate value (that is, the number given in the immediate addressing mode instruction), and the target jump address is the PC plus the branch instruction itself. The offset of the immediate branch is calculated, and the target jump address of the indirect jump branch instruction is specified in the register.

An instruction needs to pre-decode the instruction before it is accessed from the L2 cache or internal to the instruction cache, so that the partial pre-decoded result of the instruction is used as a guide for branch prediction. For example, when the branch instruction is accessed from the L2 cache or the internal cache to the instruction cache, the type of the branch instruction (such as whether it is a conditional branch instruction, an indirect jump branch instruction, etc.) needs to be identified through the pre-decoding stage. The corresponding branch prediction is performed according to the type of the branch instruction. After pre-decoding, the pre-decoded result (such as the type information of the instruction) and the instruction are stored together in the instruction cache. It should be noted that the foregoing pre-decoding operation on the instruction may be performed by the branch prediction device, or may be performed by other devices, which is not limited herein.

Wherein, the above register prediction conditions include: the type of the instruction is an unconditional indirect jump Instructions.

102. When the read instruction satisfies the register prediction condition, obtain the predicted target jump address of the read instruction from the first BTAC according to the register identifier in the read instruction.

103. When the read instruction does not satisfy the register prediction condition, obtain the predicted target jump address of the read instruction from the second BTAC according to the program counter in the read command.

In the embodiment of the present invention, the first BTAC is set in the processor. For convenience of description, the first BTAC is described as SBTAC, and the second BTAC is simply referred to as BTAC. The hardware structure of SBTAC is similar to that of BTAC. The difference is that BTAC is indexed by a part of the PC field or all fields, and SBTAC is indexed by register identifier. Since the SBPAC stores the correspondence information of the register identifier and the predicted target jump address, the branch prediction device can find the predicted target jump address corresponding to the register identifier from the SBTAC according to the register identifier in the above instruction. .

In an application scenario, before step 101, if the function called when compiling the high-level language is a standard library function, the branch prediction device specifies the type of the compiled instruction as an unconditional indirect jump branch instruction, such as The type of the compiled instruction is specified as a branch and link register (BLR) instruction. The BLR instruction is an unconditional indirect branch instruction. It is caused by a subroutine call or function call and will return. The address is stored in the Link Register. It should be noted that the high-level language in the embodiment of the present invention is mainly related to the assembly language, which is a program that is closer to the natural language and the mathematical formula, and is basically separated from the machine system, and is written in a more understandable way. program. The high-level language in the embodiment of the present invention does not specifically refer to a specific language, and may include a plurality of programming languages, such as java, c, C++, C#, pascal, python, lisp, prolog, FoxPro, VC, easy language, etc. Etc., the standard library function in the embodiment of the present invention refers to a library composed of some basic functions pre-written according to high-level language standards.

It should be noted that the register identifier in the embodiment of the present invention may be a register number, or The register identifier may also be other codes or symbols that can be used to indicate the register. The branch prediction method in the embodiment of the present invention may be applied to a multi-thread processor, and may also be applied to a single-thread processor. limited.

It can be seen that, in the embodiment of the present invention, the first BTAC and the second BTAC are set, and the register identifier is used as the index in the first BTAC (that is, the correspondence relationship between the register identifier and the predicted target jump address is stored in the first BTAC) The second BTAC uses the PC as an index (ie, stores the correspondence information between the partial field of the program counter and the predicted target jump address in the second BTAC), and uses the first when the read instruction satisfies the register prediction condition. The BTAC performs branch prediction, otherwise, the second BTAC is used for branch prediction. Since the target jump addresses of the unconditional indirect jump branch instructions with the same register identifier are necessarily the same, the history information of the plurality of unconditional indirect jump branch instructions having the same target jump address can be stored in the same Entry of the first BTAC without Affect the accuracy of branch prediction, so that the resource sharing of BTAC can be realized under the premise of ensuring the accuracy of branch prediction.

In the above embodiment, the register identifier of all the registers is used as the index of the predicted target jump address in the SBTAC. In the embodiment of the present invention, only the register identifier of the partial register may be used as the index of the predicted target jump address in the SBTAC. The prediction condition further includes: the register identifier in the instruction is a specific register identifier, and the read is determined when the type of the read instruction is an unconditional indirect jump branch instruction, and the register identifier in the read instruction is a specific register identifier. The instruction satisfies the register prediction condition. When the type of the read instruction is not an unconditional indirect branch instruction, or the register identifier in the read instruction is not a specific register identifier, it is determined that the read instruction does not satisfy the register prediction. condition. As shown in FIG. 2, the branch prediction method in the embodiment of the present invention includes:

201. Read an instruction from an instruction cache.

An instruction needs to pre-decode the instruction before it is accessed from the L2 cache or internal to the instruction cache, so that the partial pre-decoded result of the instruction is used as a guide for branch prediction. For example, when a branch instruction is accessed from the L2 cache or internal to the instruction cache, the type of the branch instruction needs to be identified through the pre-decoding stage (such as whether it is a conditional branch instruction, whether it is an indirect jump). The branch instruction, etc.), to perform the corresponding branch prediction according to the type of the branch instruction. After precoding, the predecoded result and instructions are saved together in the instruction cache. It should be noted that the foregoing pre-decoding operation on the instruction may be performed by the branch prediction device, or may be performed by other devices, which is not limited herein.

202. When the type of the read instruction is an unconditional indirect jump branch instruction, determining whether the register identifier in the read instruction is a specific register identifier;

If the branch prediction device determines that the register identifier in the read command is a specific register identifier, step 203 is executed, and if the branch prediction device determines that the register identifier in the read command is not a specific register identifier, execute Step 204.

203. Obtain a predicted target jump address of the read command from the first BTAC according to the register identifier in the read command.

The first BTAC stores: correspondence information between the register identifier and the predicted target jump address.

204. When the type of the read instruction is not an unconditional indirect jump branch instruction, the predicted target jump address of the read instruction is obtained from the second BTAC according to the program counter in the read command.

In an application scenario, before step 201, if the function called when the high-level language is compiled is a standard library function, the branch prediction device specifies the type of the compiled instruction as an unconditional indirect jump branch instruction, such as The type of the compiled instruction is specified as a BLR instruction. The BLR instruction is an unconditional indirect branch instruction. It is caused by a subroutine call or function call and must be returned. The returned address is stored in the Link Register. It should be noted that the high-level language in the embodiment of the present invention is mainly related to the programming language, which is a program that is closer to the natural language and the mathematical formula, and is basically separated from the machine system, and is written in a more understandable way. program. The high-level language in the embodiment of the present invention does not specifically refer to a specific language, and may include a plurality of programming languages, such as java, c, C++, C#, pascal, python, lisp, prolog, FoxPro, VC, easy language, etc. Etc., the standard library function in the embodiment of the present invention refers to a base pre-written according to high-level language standards. A library of this function.

It should be noted that the register identifier in the embodiment of the present invention may be a register number, or the register identifier may be other codes or symbols that can be used to indicate a register, etc. The branch prediction method in the embodiment of the present invention may be applied to multiple The thread processor can also be applied to a single-thread processor, which is not limited herein.

It can be seen that, in the embodiment of the present invention, the first BTAC and the second BTAC are set, and the register identifier is used as the index in the first BTAC (that is, the correspondence relationship between the register identifier and the predicted target jump address is stored in the first BTAC) The second BTAC uses the PC as an index (ie, stores the correspondence information between the partial field of the program counter and the predicted target jump address in the second BTAC), and uses the first when the read instruction satisfies the register prediction condition. The BTAC performs branch prediction, otherwise, the second BTAC is used for branch prediction. Since the target jump addresses of the unconditional indirect jump branch instructions having the same register identifier are necessarily the same, even if the history information of the plurality of unconditional indirect jump branch instructions having the same target jump address is stored in the same Entry of the first BTAC The accuracy of the branch prediction is also not affected. In other words, the technical solution provided by the present invention can not affect the accuracy of the branch prediction when sharing the first BTAC, thereby implementing the BTAC under the premise of ensuring the accuracy of the branch prediction. Resource sharing is possible.

For the branch instruction under the standard library function, the target jump address of the branch instruction usually does not change. Therefore, in order to ensure that the content of the SBTAC does not appear to be updated or invalid due to the switching of the software process, the standard in the embodiment of the present invention The branch instruction under the library function uses the SBTAC to perform branch prediction. As shown in FIG. 3, the branch prediction method in the embodiment of the present invention includes:

301. Compile a high-level language.

302. Determine whether to call a standard library function.

During the compilation process, it can be determined whether the standard library function is called. If the standard library function is not called, step 303 is executed. If the standard library function is called, step 304 is performed.

303. Specify the type of the compiled instruction as another instruction stored in the second level cache or Save in.

304. Specify the type of the compiled instruction as the BLR instruction is stored in the second level cache or in the memory.

The steps 305-308 are similar to the steps 201-204 in the embodiment shown in FIG. 2, and the specific implementation manners may refer to the description in the corresponding steps, and details are not described herein again.

The embodiment of the present invention further provides a branch prediction apparatus, which is applied to a processor, where the processor includes: a first BTAC and a second BTAC, where the first BTAC stores: a register identifier and a predicted target jump address. Corresponding relationship information, the second BTAC stores: correspondence information between the field of the PC and the predicted target jump address, optionally, storing the partial field of the PC and the predicted target jump address in the second BTAC - - correspondence relationship information, or storing all fields of the PC and the predicted target hop in the second BTAC As shown in FIG. 4, the branch prediction apparatus 400 in the embodiment of the present invention includes:

a reading unit 401, configured to read an instruction from the instruction cache;

An instruction needs to pre-decode the instruction before it is accessed from the L2 cache or internal to the instruction cache, so that the partial pre-decoded result of the instruction is used as a guide for branch prediction. For example, when the branch instruction is accessed from the L2 cache or the internal cache to the instruction cache, the type of the branch instruction (such as whether it is a conditional branch instruction, an indirect jump branch instruction, etc.) needs to be identified through the pre-decoding stage. The corresponding branch prediction is performed according to the type of the branch instruction. After pre-decoding, the pre-decoded result (such as the type information of the instruction) and the instruction are stored together in the instruction cache. In an implementation, the foregoing pre-decoding operation on the instruction may be performed by the branch prediction device, and the branch prediction device in the embodiment of the present invention may further include: a pre-decoding unit, configured to read the reading unit 401 The fetching instruction is pre-decoded to obtain the type information of the instruction to be read; the determining unit is configured to determine, after the reading unit 401 reads the instruction, the type information of the instruction obtained by the pre-decoding unit, Whether the type is an unconditional indirect jump branch instruction. Of course, the foregoing pre-decoding operation of the instruction to be read by the reading unit 401 can also be performed by other devices, which is not limited herein.

The prediction obtaining unit 402 is configured to: when determining that the instruction read by the reading unit 401 satisfies the register prediction condition, acquire the read unit 401 from the first BTAC according to the register identifier in the instruction read by the reading unit 401 The predicted target jump address of the instruction. When it is determined that the instruction read by the reading unit 401 does not satisfy the above-described register prediction condition, the predicted target jump address of the instruction read by the reading unit 401 is acquired from the second BTAC according to the PC of the instruction read by the reading unit 401. The above register prediction conditions include: The type of the instruction is an unconditional indirect jump branch instruction.

Optionally, the foregoing register prediction condition further includes: the register identifier in the instruction is a specific register identifier. The branch prediction apparatus 400 further includes: a determining unit, wherein the type of the instruction read by the reading unit 401 is an unconditional indirect branch branch instruction, and the register identifier in the instruction read by the reading unit 401 is a specific register identifier. When the reading unit 401 is determined The read instruction satisfies the register prediction condition; when the type of the instruction read by the reading unit 401 is not an unconditional indirect jump branch instruction, or the register identifier in the instruction read by the reading unit 401 is not a specific register identifier , to determine that the read instruction does not meet the register prediction condition.

In an application scenario, when compiling a high-level language, if the function called when the high-level language is compiled is a standard library function, the branch prediction device specifies the type of the compiled instruction as the BLR. Then, on the basis of the branch prediction apparatus shown in FIG. 4, the branch prediction apparatus may further include: a compiling unit for compiling the high-level language; and a specifying unit for calling the function when the compiling unit compiles the high-level language. When the standard library function is used, the type of the compiled instruction is specified as an unconditional indirect jump branch instruction, such as specifying the type of the compiled instruction as a BLR instruction. It should be noted that the high-level language in the embodiment of the present invention is mainly related to the assembly language, which is a program that is closer to the natural language and the mathematical formula, and is basically separated from the hardware system of the machine, and the program is written in a more understandable way. . The high-level language in the embodiment of the present invention does not specifically refer to a specific language, and may include many programming languages, such as java, c, C++, C#, pascal, python, lisp, prolog, FoxPro, VC, easy language, etc. The standard library function in the embodiment of the present invention refers to a library composed of some basic functions pre-written according to a high-level language standard.

It should be noted that the branch prediction apparatus in the embodiment of the present invention may be used as the branch prediction apparatus in the foregoing method embodiment, and may be used to implement all the technical solutions in the foregoing method embodiments, and the functions of the respective functional modules may be according to the foregoing method. The method in the embodiment is specifically implemented. For the specific implementation process, reference may be made to the related description in the foregoing method embodiments, and details are not described herein again.

It can be seen that, in the embodiment of the present invention, the first BTAC and the second BTAC are set, and the register identifier is used as an index in the first BTAC (that is, the register identifier is stored in the first BTAC) And the predicted correspondence address of the target jump address, the second BTAC uses the PC as an index (ie, the correspondence information of the partial field of the program counter and the predicted target jump address is stored in the second BTAC), when When the read command satisfies the register prediction condition, the first BTAC is used for branch prediction, otherwise, the second BTAC is used for branch prediction. Since the target jump addresses of the unconditional indirect jump branch instructions having the same register identifier are necessarily the same, even if the history information of the plurality of unconditional indirect jump branch instructions having the same target jump address is stored in the same Entry of the first BTAC The accuracy of the branch prediction is also not affected. In other words, the technical solution provided by the present invention can not affect the accuracy of the branch prediction when sharing the first BTAC, thereby implementing the BTAC under the premise of ensuring the accuracy of the branch prediction. Resource sharing is possible.

The embodiment of the present invention further provides a computer storage medium, wherein the computer storage medium stores a program, and the program execution includes some or all of the arrangements of a branch prediction method and a branch prediction device described in the foregoing method embodiments.

The embodiment of the present invention provides another branch prediction apparatus. As shown in FIG. 5, the branch prediction apparatus 500 in the embodiment of the present invention includes:

The input device 501, the output device 502, the memory 503, and the processor 504 (the number of processors of the branch prediction device may be one or more, and FIG. 5 takes a processor as an example). In some embodiments of the present invention, the input device 501, the output device 502, the memory 503, and the processor 504 may be connected by a bus or other means, as exemplified by a bus connection as shown in FIG. The memory 503 is used to store data input from the input device 502, and may also store information such as necessary files processed by the processor 504; the input device 501 and the output device 502 may include ports through which the branch prediction device 500 communicates with other devices, and Output devices external to the branch prediction device 500, such as a display, a keyboard, a mouse, and a printer, etc., may also be included. Specifically, the input device 502 may include a mouse and a keyboard, etc., and the output device 501 includes a display or the like.

The processor 504 includes: a first BTAC and a second BTAC, where the first BTAC stores: a correspondence between a register identifier and a predicted target jump address, where the foregoing The BTAC stores: a correspondence between the field of the PC and the predicted target jump address, optionally, the correspondence information of the partial field of the PC and the predicted target jump address is stored in the second BTAC, or Corresponding relationship information of all the fields of the PC and the predicted target jump address is stored in the second BTAC.

Processor 504 performs the following steps:

Reading instructions from the instruction cache;

Optionally, the foregoing register prediction condition further includes: the register identifier in the instruction is a specific register identifier.

It can be seen that, in the embodiment of the present invention, the first BTAC and the second BTAC are set, and the register identifier is used as the index in the first BTAC (that is, the correspondence relationship between the register identifier and the predicted target jump address is stored in the first BTAC) , using PC in the second BTAC For indexing (ie, storing the correspondence information between the partial field of the program counter and the predicted target jump address in the second BTAC), when the read instruction satisfies the register prediction condition, the first BTAC is used for branch prediction, otherwise, Branch prediction is performed using the second BTAC. Since the target jump addresses of the unconditional indirect jump branch instructions having the same register identifier are necessarily the same, even if the history information of the plurality of unconditional indirect jump branch instructions having the same target jump address is stored in the same Entry of the first BTAC The accuracy of the branch prediction is also not affected. In other words, the technical solution provided by the present invention can not affect the accuracy of the branch prediction when sharing the first BTAC, thereby implementing the BTAC under the premise of ensuring the accuracy of the branch prediction. Resource sharing is possible.

It should be noted that, for the foregoing method embodiments, for the sake of brevity, they are all described as a series of action combinations, but those skilled in the art should understand that the present invention is not limited by the described action sequence. Because certain steps may be performed in other sequences or concurrently in accordance with the present invention. Further, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

In the above embodiments, the descriptions of the various embodiments are different, and the parts that are not detailed in an embodiment can be referred to the related descriptions of other embodiments.

A person of ordinary skill in the art may understand that all or part of the steps in the foregoing embodiments may be completed by a program to instruct related hardware, and the program may be stored in a computer readable storage medium, for example, the storage medium may be Includes: Read Only Memory, Random Access Memory, Disk or CD, and more.

A branch prediction method and related device provided by the present invention are described in detail above. For those skilled in the art, according to the idea of the embodiment of the present invention, there are changes in the specific implementation manner and application scope. The contents of this specification are not to be construed as limiting the invention.

Claims

claims

1. A branch prediction method, characterized in that it is applied to a processor, and the processor includes: a first branch target address prediction cache and a second branch target address prediction cache, the first branch target address prediction The cache stores: Correspondence information between the register identifier and the predicted target jump address, The second branch target address prediction cache stores: Correspondence information between the program counter field and the predicted target jump address, Among them, the branch prediction method includes:

Read instructions from the instruction cache;

If it is determined that the instruction read satisfies the register prediction condition, then:

According to the read register identifier of the instruction, obtain the predicted target jump address of the read instruction from the first branch target address prediction cache;

If it is determined that the read instruction does not meet the register prediction condition, then:

Then, according to the program counter of the read instruction, obtain the predicted target jump address of the read instruction from the second branch target address prediction cache;

Wherein, the register prediction conditions include: the type of instruction is an unconditional indirect jump branch instruction.

2. The method according to claim 1, characterized in that,

The register prediction condition also includes: the register identifier in the instruction is a specific register identifier; and it is determined that the read instruction satisfies the register prediction condition, specifically:

When the type of the instruction is an unconditional indirect jump branch instruction, and the register identifier in the instruction is a specific register identifier, it is determined that the read instruction satisfies the register prediction condition;

It is determined that the instruction read does not satisfy the register prediction condition, specifically:

When the type of the instruction is not an unconditional indirect jump branch instruction, or the register identifier in the instruction is not a specific register identifier, it is determined that the read instruction does not meet the register prediction condition.

3. The method according to claim 1 or 2, characterized in that,

Reading instructions from the instruction cache includes:

Pre-decode the instruction to be read to obtain the type information of the instruction to be read; the reading instruction includes: based on the obtained instruction type information, determine whether the type of the currently read instruction is Unconditional indirect jump branch instructions.

4. The method according to any one of claims 1 to 3, characterized in that,

Before the read instruction, if the function called when compiling a high-level language is a standard library function, Then, specify the type of the compiled instruction as an unconditional indirect jump branch instruction.

5. A branch prediction device, characterized in that it is used in a processor, and the processor includes: a first branch target address prediction buffer and a second branch target address prediction buffer, the first branch target address prediction The cache stores: Correspondence information between the register identifier and the predicted target jump address. The second branch target address prediction cache stores: Correspondence information between some fields of the program counter and the predicted target jump address. , or, correspondence information between all fields of the program counter and the predicted target jump address, where the branch prediction device includes:

Read unit, used to read instructions from the instruction cache;

A prediction acquisition unit configured to, when it is determined that the instruction read by the reading unit satisfies the register prediction condition, determine the first branch target from the first branch target according to the register identification of the instruction read by the reading unit. When the instruction read by the read unit does not satisfy the register prediction condition, the read unit is obtained from the second branch target address prediction buffer according to the program counter of the instruction read by the read unit. The predicted target jump address of the instruction read;

6. The branch prediction device according to claim 5, characterized in that,

The register prediction condition also includes: the register identifier in the instruction is a specific register identifier; the branch prediction device also includes:

Determining unit, configured to determine when the type of instruction read by the reading unit is an unconditional indirect jump branch instruction and the register identifier in the instruction read by the reading unit is a specific register identifier. The instruction read by the fetch unit satisfies the register prediction condition; when the type of instruction read by the fetch unit is not an unconditional indirect jump branch instruction, or the register identifier in the instruction read by the fetch unit is not a specific When the register identifier is specified, it is determined that the read instruction does not meet the register prediction condition.

7. The branch prediction device according to claim 5 or 6, characterized in that,

The branch prediction device also includes:

A pre-decoding unit, used to pre-decode the instructions to be read by the reading unit and obtain the type information of the instructions to be read by the reading unit;

A determination unit, configured to determine whether the type of instruction currently read by the reading unit is unconditional based on the type information of the instruction obtained by the pre-decoding unit after the reading unit reads the instruction. Indirect jump branch instructions.

8. The branch prediction device according to claim 5 or 6, characterized in that,

The branch prediction device also includes:

Compilation unit, used to compile high-level languages;

The designation unit is used to designate the type of the compiled instruction as an unconditional indirect jump branch instruction when the function called by the compilation unit when compiling a high-level language is a standard library function.