WO2015013895A1

WO2015013895A1 - Method and device for jump processing of a command

Info

Publication number: WO2015013895A1
Application number: PCT/CN2013/080442
Authority: WO
Inventors: 毕波; 刘强
Original assignee: 华为技术有限公司
Priority date: 2013-07-30
Filing date: 2013-07-30
Publication date: 2015-02-05
Also published as: CN104541243A

Abstract

The present invention provides a method and device for jump processing of a command, the method comprising: if the current command is a jump command, pre-fetching from external memory the destination address of the jump corresponding to the current command, and caching in the cache the destination address of the jump corresponding to the current command; if the jump result of the current command is determined to be a jump, performing jump processing on the current command according to the destination address in the cache and of the jump corresponding to the current command.

Description

Instruction jump processing method and device

Technical field

The present invention relates to computer technology, and in particular, to a method and apparatus for processing jumps of instructions. Background technique

At present, when the jump of the instruction is a conditional jump, the overhead of the jump of the instruction mainly comes from three aspects: In the first aspect, the jump instruction generates a beat from the PC (P-stage) to generate a jump. The overhead caused by the destination address, that is, the overhead caused by the execution of the instruction (E-stage); the second aspect, the overhead caused by the jump instruction jump, that is, from the current instruction (jump instruction) to the destination address The overhead caused by the jump; In the third aspect, the overhead caused by the cache miss may occur when the instruction of the destination address takes a value.

In the prior art, the processor generally adopts a Branch Target Buffer (BTB) technology to reduce the overhead generated by the first aspect and the second aspect. In addition, the processor prefetches the existing instruction prefetching function mainly in accordance with the execution order of the instructions, so as to reduce the overhead generated by the third aspect. Specifically, the process of prefetching according to the execution order of the instruction is mainly: prefetch logic (prefetch) when the cache block (also called cache line) in which the Nth instruction is being executed is hit (hit) Logic) pre-fetches the N+1 line, or N+1 to N+2 line, or N+1 to N+4 line, etc. according to different prefetch strategies. It should be noted that the prefetch logic generally initiates the prefetch operation at the I-stage.

However, if you only use BTB technology or perform sequential prefetching, there are still jump costs in the following three cases:

In the first case, when the jump instruction jumps and the branch prediction is correct (that is, the predicted destination address is the same as the generated destination address), and the destination address of the jump exceeds the existing prefetch range, Three aspects of the cost;

In the second case, when the jump instruction jumps and the branch prediction error (that is, the predicted destination address is different from the generated destination address), and the destination address of the jump exceeds the existing prefetch range, Three aspects of overhead. Summary of the invention

The present invention provides a method and apparatus for processing jumps of instructions for effectively reducing the overhead of the entire jump.

A first aspect of the present invention provides a method for processing a jump of an instruction, including:

When the current instruction is a jump instruction, the destination address of the jump corresponding to the current instruction is prefetched from the external memory, and the destination address corresponding to the current instruction is cached in the cache;

When it is determined that the jump result of the current instruction is a jump, the current instruction is subjected to a jump processing according to the destination address of the jump corresponding to the current instruction in the cache.

In a first possible implementation manner of the first aspect, when the current instruction is a jump instruction, the destination address of the jump corresponding to the current instruction is pre-fetched from the external memory, including:

When the current instruction is a jump instruction, querying, acquiring, from the BTB, a prefetch address corresponding to the current instruction;

The destination address of the jump corresponding to the prefetch address is prefetched from the external memory.

With the first aspect or the first possible implementation of the first aspect, in a second possible implementation manner of the first aspect, when the current instruction is a jump instruction, the method further includes:

Prefetching a next hop address of the address of the current instruction from the external memory; and buffering a next hop address of the address of the current instruction in the cache.

In conjunction with the second possible implementation of the first aspect, in a third possible implementation of the first aspect, the next hop address of the address of the current instruction is prefetched from the external memory and the current instruction is corresponding to Before the destination address of the jump, the method further includes:

Performing branch prediction processing on the current instruction to predict whether the jump result of the current instruction is a jump or not;

Then, the next hop address of the address of the current instruction and the destination address of the jump corresponding to the current instruction are pre-fetched from the external memory, including:

When predicting that the jump result of the current instruction is a jump, prefetching a destination address of the jump corresponding to the current instruction from the external memory, and prefetching the external memory from the external memory after a preset period The next hop address of the address of the current instruction;

Prefetching a next hop address of an address of the current instruction from the external memory when predicting a jump result of the current instruction as not jumping, and from the external memory after the preset period Prefetching the destination address of the jump corresponding to the current instruction. In conjunction with the second possible implementation of the first aspect, in a fourth possible implementation of the first aspect, the method further includes:

When it is determined that the jump result of the current instruction is no jump, the current instruction is subjected to jump processing according to the next hop address of the address of the current instruction in the cache.

A second aspect of the present invention provides a jump processing apparatus for an instruction, including:

a prefetching module, configured to prefetch a destination address of the jump corresponding to the current instruction from an external memory when the current instruction is a jump instruction;

a cache module, configured to cache a destination address corresponding to the current instruction jump;

a jump processing module, configured to perform a jump processing on the current instruction according to a destination address of a jump corresponding to the current instruction in the cache module when determining that the jump result of the current instruction is a jump .

In a first possible implementation manner of the second aspect, the prefetching module includes:

a query obtaining unit, configured to: when the current instruction is a jump instruction, obtain a prefetch address corresponding to the current instruction from the BTB;

And a prefetching unit, configured to prefetch a destination address of the jump corresponding to the prefetch address from an external memory.

In conjunction with the first possible implementation of the second aspect, in a second possible implementation of the second aspect, the prefetching unit is further configured to prefetch an address of the current instruction from the external memory. Next hop address;

The cache module is further configured to cache a next hop address of an address of the current instruction.

In combination with the second possible implementation of the second aspect, in a third possible implementation of the second aspect, the method further includes:

a prediction module, configured to perform branch prediction processing on the current instruction, to predict whether the jump result of the current instruction is a jump or not;

The prefetching unit is specifically configured to prefetch a destination address of the jump corresponding to the current instruction from the external memory when the prediction module predicts that the jump result of the current instruction is a jump, and Prefetching a next hop address of the address of the current instruction from the external memory after a preset period; or

The prefetching unit is specifically configured to prefetch a next hop address of an address of the current instruction from the external memory when the prediction module predicts that the jump result of the current instruction is no jump, and And pre-fetching a destination address of the jump corresponding to the current instruction from the external memory after the preset period.

With the second possible implementation of the second aspect, in a fourth possible implementation manner of the second aspect, the jump processing module is further configured to: when determining that the current instruction jump result is not jumping And performing a jump process on the current instruction according to a next hop address of an address of the current instruction in the cache module.

A third aspect of the present invention provides a computer, comprising: a memory for storing an instruction; a processor coupled to the memory, the processor configured to execute an instruction stored in the memory, and The processor is configured as a jump processing method for executing an instruction as described above.

The technical effect of the present invention is: when the current instruction is a jump instruction, prefetching the destination address of the jump corresponding to the current instruction from the external memory, and buffering the destination address of the jump of the current instruction in the cache, and When it is determined that the jump result of the current instruction is a jump, the current instruction is jumped according to the destination address of the jump corresponding to the current instruction in the cache. Since the destination address of the jump corresponding to the current instruction is cached in the cache when the current instruction is a jump instruction, the overhead of the entire jump can be effectively reduced without relying on branch prediction. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a flow chart of an embodiment of a method for processing a twist in accordance with the present invention;

2 is a flow chart of another embodiment of a method for processing a twist in accordance with the present invention;

3 is a flow chart of still another embodiment of a method for processing a twist in accordance with the present invention;

Figure 4 is a diagram showing the structure of an embodiment of the twirling processing apparatus of the present invention;

FIG. 5 is a flowchart of another embodiment of a method for processing a call forwarding according to the present invention. FIG. 1 is a flowchart of an embodiment of a method for processing a jump of an instruction according to the present invention. As shown in FIG. Includes:

Step 101: When the current instruction is a jump instruction, prefetch the destination address of the jump corresponding to the current instruction from the external memory, and cache the destination address of the jump corresponding to the current instruction in the cache.

In this embodiment, when the currently executed instruction is a jump instruction, the current instruction may be in the P The P-stage initiates a prefetch operation and simultaneously issues two commands (command) in the P+1 stage, where one command is used to prefetch in accordance with the current program counter (current PC). That is, the next hop address of the current instruction address is prefetched from the external memory; the other command starts prefetching according to the target program counter (Target PC) in the BTB, that is, prefetching the jump corresponding to the current instruction from the external memory Destination address. For example, if the address of the current instruction is N, the next hop address of the current instruction address is N+1, and the destination address of the jump corresponding to the current instruction may be N+100.

Step 102: When it is determined that the jump result of the current instruction is a jump, perform a jump processing on the current instruction according to the destination address of the jump corresponding to the current instruction in the cache.

In this embodiment, the overhead of the instruction jump mainly comes from three aspects: The first aspect (which can be expressed as a), the jump instruction generates a beat from the PC (P-stage) to the destination address of the generated jump The overhead, that is, the overhead caused by the execution of the instruction (E-stage); the second aspect (which can be expressed as b), the overhead caused by the jump instruction jump, that is, from the current instruction (jump instruction) to the destination address The overhead caused by the jump; the third aspect (which can be expressed as c), the overhead caused by the cache miss may occur when the destination address is fetched.

In addition, in this embodiment, for the first case in the prior art, that is, the jump instruction jumps, the branch prediction is correct (that is, the predicted destination address is the same as the generated destination address), and the purpose of the jump When the address exceeds the existing prefetch range, the overhead of the implementation may be c-1 (2 or 3) cycles.

For the second case in the prior art, that is, a jump instruction jump, a branch prediction error

(The predicted destination address is different from the generated destination address), and the destination address of the jump exceeds the existing prefetch range. With the technical solution of this implementation, the overhead of the entire jump can be Max{(a+b). ), (cl(2 or 3))}cycles ₀ where 1(2 or 3) means 1 or 2 or 3.

In this embodiment, when the current instruction is a jump instruction, prefetching the destination address of the jump corresponding to the current instruction from the external memory, and buffering the destination address of the jump of the current instruction in the cache, and determining When the jump result of the current instruction is a jump, the current instruction is jumped according to the destination address of the jump corresponding to the current instruction in the cache. Since the destination address of the jump corresponding to the current instruction is cached in the cache when the current instruction is a jump instruction, the branch prediction can be eliminated, and the overhead of the entire jump can be effectively reduced.

2 is a flow chart of another embodiment of a jump processing method of an instruction of the present invention, in the above figure On the basis of the above example shown in FIG. 2, a specific implementation manner of step 101 is as follows: Step 101a: When the current instruction is a jump instruction, query and obtain a prefetch corresponding to the current instruction from the BTB. address.

In this embodiment, the prefetch address is the destination address of the jump corresponding to the current instruction.

Step 101b: Prefetch the destination address of the jump corresponding to the prefetch address from the external memory. Step 101c: Cache the destination address corresponding to the current instruction in the cache.

Optionally, the method may further include:

Step 103: Prefetch the next hop address of the address of the current instruction from the external memory; and cache the next hop address of the address of the current instruction in the cache.

In this embodiment, it should be noted that the next hop address of the current instruction address and the destination address of the jump corresponding to the current instruction may be pre-fetched from the external memory, and the current instruction is cached in the cache. The next hop address of the address and the destination address of the jump corresponding to the current instruction may also prefetch the next hop address of the current instruction address and the destination address of the jump corresponding to the current instruction from the external memory.

FIG. 3 is a flowchart of still another embodiment of a method for processing a jump of an instruction according to the present invention. As shown in FIG. 3, the method includes:

Step 201: When the current instruction is a jump instruction, perform branch prediction processing on the current instruction to predict whether the jump result of the current instruction is a jump or not; if the jump result of the current instruction is predicted to be a jump Then, step 202 is performed; if the result of the jump of the current instruction is predicted to be no jump, step 203 is performed.

Step 202: Prefetch and cache the destination address of the jump corresponding to the current instruction from the external memory, and prefetch and cache the next hop address of the current instruction address from the external memory after the preset period. Then step 204 is performed.

In this embodiment, optionally, a specific implementation manner of step 202 is:

Obtaining a prefetch address corresponding to the current instruction from the BTB, and prefetching a destination address of the jump corresponding to the current instruction from the external memory;

The next hop address of the address of the current instruction is prefetched from the external memory after a preset period. Step 203: Prefetch and cache the next hop address of the current instruction address from the external memory, and prefetch and cache the destination address of the jump corresponding to the current instruction from the external memory after the preset period. In this embodiment, optionally, a specific implementation manner of step 203 is: prefetching a next hop address of the current instruction address from the external memory;

After the preset period, the prefetch address corresponding to the current instruction is obtained from the BTB, and the destination address of the jump corresponding to the current instruction is prefetched from the external memory.

In addition, the preset period may be any period between 1 and 2 periods.

Step 204: Determine whether the jump result of the current instruction is a jump or no jump. When it is determined that the jump result of the current instruction is a jump, perform step 205; when determining that the jump result of the current instruction is not jumping Then, step 206 is performed.

Step 205: Perform a jump process on the current instruction according to the destination address of the jump corresponding to the current instruction in the cache. End.

Step 206: Perform a jump process on the current instruction according to the next hop address of the address of the current instruction in the cache.

One of ordinary skill in the art will appreciate that all or a portion of the steps to implement the various method embodiments described above can be accomplished by hardware associated with the program instructions. The aforementioned program can be stored in a computer readable storage medium. The program, when executed, performs the steps including the foregoing method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

4 is a schematic structural diagram of an embodiment of a jump processing device of the present invention. As shown in FIG. 4, the device includes: a prefetch module 11, a cache module 12, and a jump processing module 13; wherein, the prefetch module 11 For pre-fetching the destination address of the jump corresponding to the current instruction from the external memory when the current instruction is a jump instruction; the cache module 12 is configured to cache the destination address of the jump corresponding to the current instruction; When it is determined that the jump result of the current instruction is a jump, the current instruction is jumped according to the destination address of the jump corresponding to the current instruction in the cache module 12.

The jump processing device of the instruction of this embodiment can perform the technical solution of the method embodiment shown in FIG. 1 , and the implementation principles thereof are similar, and details are not described herein again.

In this embodiment, in the embodiment, when the current instruction is a jump instruction, the destination address of the jump corresponding to the current instruction is prefetched from the external memory, and the jump of the current instruction is cached in the cache. The destination address, and when it is determined that the jump result of the current instruction is a jump, the current instruction is jumped according to the destination address of the jump corresponding to the current instruction in the cache. Because when When the pre-instruction is a jump instruction, the destination address of the jump corresponding to the current instruction is cached in the cache. Therefore, the branch prediction can be eliminated, and the overhead of the entire jump can be effectively reduced.

FIG. 5 is a schematic diagram showing the result of another embodiment of the jump processing device of the present invention. On the basis of the embodiment shown in FIG. 4, as shown in FIG. 5, the prefetch module 11 includes: a query obtaining unit 111 and The prefetching unit 112 is configured to: when the current instruction is a jump instruction, obtain a prefetch address corresponding to the current instruction from the BTB; the prefetch unit 112 is configured to prefetch from the external memory. The destination address of the jump corresponding to the prefetch address.

Optionally, the device further includes: a prediction module 14 configured to perform branch prediction processing on the current instruction to predict whether the jump result of the current instruction is a jump or not;

The prefetching unit 112 is specifically configured to: when the prediction module 14 predicts that the jump result of the current instruction is a jump, prefetch the destination address of the jump corresponding to the current instruction from the external memory, and after the preset period Prefetching the next hop address of the address of the current instruction from the external memory; or, the prefetching unit 112 is specifically configured to: when the prediction module 14 predicts that the jump result of the current instruction is not jumping, from the external The next hop address of the address of the current instruction is prefetched in the memory, and the destination address of the jump corresponding to the current instruction is prefetched from the external memory after the preset period.

Optionally, the jump processing module 13 is further configured to: when determining that the jump result of the current instruction is not jumping, skipping the current instruction according to a next hop address of an address of the current instruction in the cache module Transfer processing.

The jump processing device of the instruction of this embodiment may perform the technical solution of the method embodiment shown in FIG. 2 or FIG. 3, and the implementation principles thereof are similar, and details are not described herein again.

The present invention also provides a computer comprising a memory and a processor; wherein the memory is for storing instructions; the processor is coupled to the memory, the processor is configured to execute instructions stored in the memory, and the processor is The implementation of the jump processing method for executing the instructions of any of the following FIG. 1 to FIG. 3 is similar to the implementation principle, and details are not described herein again.

Finally, it should be noted that the above embodiments are only for explaining the technical solutions of the present invention, and are not intended to be limiting thereof; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that The technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently replaced; and the modifications or substitutions do not deviate from the technical solutions of the embodiments of the present invention. range.

Claims

claims

1. An instruction jump processing method, characterized by including:

When the current instruction is a jump instruction, prefetch the destination address of the jump corresponding to the current instruction from the external memory, and cache the destination address of the jump corresponding to the current instruction in the cache;

When it is determined that the jump result of the current instruction is a jump, jump processing is performed on the current instruction according to the jump destination address corresponding to the current instruction in the cache.

2. The instruction jump processing method according to claim 1, wherein when the current instruction is a jump instruction, prefetching the jump destination address corresponding to the current instruction from the external memory includes: :

When the current instruction is a jump instruction, query and obtain the prefetch address corresponding to the current instruction from the BTB;

Prefetch the jump destination address corresponding to the prefetch address from the external memory.

3. The instruction jump processing method according to claim 1 or 2, characterized in that when the current instruction is a jump instruction, the method further includes:

Prefetch the next hop address of the address of the current instruction from the external memory; and cache the next hop address of the address of the current instruction in the cache.

4. The instruction jump processing method according to claim 3, characterized in that, the next jump address of the address of the current instruction and the purpose of the jump corresponding to the current instruction are prefetched from the external memory. Before the address, the method also includes:

Perform branch prediction processing on the current instruction to predict whether the jump result of the current instruction will be a jump or not;

Then, prefetching the next jump address of the address of the current instruction and the destination address of the jump corresponding to the current instruction from the external memory include:

When the jump result of the current instruction is predicted to be a jump, the destination address of the jump corresponding to the current instruction is prefetched from the external memory, and the destination address of the jump corresponding to the current instruction is prefetched from the external memory after a preset period. The next hop address of the address of the current instruction;

When the jump result of the current instruction is predicted to be no jump, the next jump address of the address of the current instruction is prefetched from the external memory, and after the preset cycle, the next jump address of the address of the current instruction is fetched from the external memory. Prefetch the destination address of the jump corresponding to the current instruction.

5. The instruction jump processing method according to claim 3, further comprising: When it is determined that the jump result of the current instruction is not to jump, jump processing is performed on the current instruction according to the next jump address of the address of the current instruction in the cache.

6. An instruction jump processing device, characterized in that it includes:

A prefetch module, used to prefetch the jump destination address corresponding to the current instruction from the external memory when the current instruction is a jump instruction;

A cache module, used to cache the destination address of the jump corresponding to the current instruction;

A jump processing module, configured to perform jump processing on the current instruction according to the destination address of the jump corresponding to the current instruction in the cache module when it is determined that the jump result of the current instruction is a jump. .

7. The instruction jump processing device according to claim 6, characterized in that the prefetch module includes:

A query acquisition unit, configured to query and acquire the prefetch address corresponding to the current instruction from the BTB when the current instruction is a jump instruction;

The prefetch unit is used to prefetch the jump destination address corresponding to the prefetch address from the external memory.

8. The instruction jump processing device according to claim 7, wherein the prefetch unit is further used to prefetch the next hop address of the address of the current instruction from the external memory; The cache module is also used to cache the next hop address of the address of the current instruction.

9. The instruction jump processing device according to claim 8, further comprising: a prediction module, configured to perform branch prediction processing on the current instruction to predict the jump result of the current instruction as a jump To jump or not to jump;

Then the prefetch unit is specifically configured to prefetch the destination address of the jump corresponding to the current instruction from the external memory when the prediction module predicts that the jump result of the current instruction is a jump, and Prefetch the next hop address of the address of the current instruction from the external memory after a preset period; or,

The prefetch unit is specifically configured to prefetch the next jump address of the address of the current instruction from the external memory when the prediction module predicts that the jump result of the current instruction is no jump, and After the preset period, the destination address of the jump corresponding to the current instruction is prefetched from the external memory.

10. The instruction jump processing device according to claim 8, characterized in that: the jump The transfer processing module is also configured to perform jump processing on the current instruction according to the next jump address of the address of the current instruction in the cache module when it is determined that the jump result of the current instruction is not to jump. .

11. A computer, characterized in that it includes: a memory for storing instructions; a processor coupled to the memory, the processor being configured to execute instructions stored in the memory, and the processor A jump processing method configured to execute instructions according to any one of claims 1 to 5.