WO2015006866A1 - Dual-band high efficiency doherty amplifiers with hybrid packaged power devices - Google Patents
Dual-band high efficiency doherty amplifiers with hybrid packaged power devices Download PDFInfo
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- WO2015006866A1 WO2015006866A1 PCT/CA2014/050655 CA2014050655W WO2015006866A1 WO 2015006866 A1 WO2015006866 A1 WO 2015006866A1 CA 2014050655 W CA2014050655 W CA 2014050655W WO 2015006866 A1 WO2015006866 A1 WO 2015006866A1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
- H03F3/602—Combinations of several amplifiers
- H03F3/604—Combinations of several amplifiers using FET's
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/111—Indexing scheme relating to amplifiers the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
Definitions
- Multi- standard and multi-band radio Base stations represent one solution that may reduce the cost of these products as well as the cost of the future wireless network infrastructures.
- the software defined radio appears to be the leading technology that will drive the future multi- standard base stations.
- Another enabling component for these converged products is the Multi-band transceiver.
- a power amplifier included a Multi-band transceiver may be required to operate in a multitude of frequency bands.
- the broadband/multiband Power Amplifiers should be highly efficient. This requirement for high efficiency represents another challenge for network operators and base station vendors.
- an amplifying structure includes a main amplifier configured to amplify a first signal; and a peak amplifier configured to amplify a second signal, each of the main amplifier and the peak amplifier including, respectively, a hybrid power device, each of the hybrid power devices including, respectively, a first power transistor die configured to amplify signals of a first frequency, and a second power transistor die configured to amplify signals of a second frequency different than the first frequency.
- the amplifying structure may be a Doherty amplifier.
- Sizes of the first and second power transistor dies of the main amplifier may be the same as sizes of the first and second power transistor dies of the peak amplifier, respectively. Sizes of the first and second power transistor dies of the main amplifier may be smaller than sizes of the first and second power transistor dies of the peak amplifier, respectively.
- the first and second power transistor dies of the main amplifier and the first and second power transistor dies of the peak amplifier may each include a laterally diffused metal oxide semiconductor (LDMOS) structure.
- LDMOS laterally diffused metal oxide semiconductor
- the first and second power transistor dies of the main amplifier and the first and second power transistor dies of the peak amplifier may each include a Gallium Nitride (GaN) structure.
- GaN Gallium Nitride
- the first and second power transistor dies of the main amplifier and the first and second power transistor dies of the peak amplifier may each include one or more high heterojunction bipolar transistors (HBT).
- HBT high heterojunction bipolar transistors
- the first and second power transistor dies of the main amplifier and the first and second power transistor dies of the peak amplifier may each include one or more pseudomorphic heterojunction pHEMT power transistors.
- the second frequency may be higher than the first frequency
- the first power transistor dies of the main amplifier and the peak amplifier may each include a laterally diffused metal oxide semiconductor (LDMOS) structure
- the second power transistor dies of the main amplifier and the peak amplifier may each include a Gallium Nitride (GaN) structure.
- LDMOS laterally diffused metal oxide semiconductor
- GaN Gallium Nitride
- a difference between the first frequency and the second frequency may be in between 200MHz and 1000MHz.
- the hybrid power device of the main amplifier may include a first input internal matching network configured to operate at the first frequency, where the first input internal matching network includes a first capacitor and being configured to transform an input impedance of the first power transistor die of the hybrid device of the main amplifier, and the hybrid power device of the main amplifier may include a second input internal matching network configured to operate at the second frequency, where the second input internal matching network includes a second capacitor and being configured to transform an input impedance of the second power transistor die of the hybrid device of the main amplifier.
- the first input internal matching network may include a first plurality of inner bonding wires connecting the first capacitor to the first power transistor die of the hybrid device of the main amplifier and a first plurality of outer bonding wires connecting the first capacitor to a first gate lead
- the second input internal matching network may include a second plurality of inner bonding wires connecting the second capacitor to the second power transistor die of the hybrid device of the main amplifier and a second plurality of outer bonding wires connecting the second capacitor to a second gate lead.
- the hybrid power device of the main amplifier may include a first output internal matching network configured to operate at the first frequency, where the first output internal matching network includes a first capacitor and being configured to transform an output impedance of the first power transistor die of the hybrid device of the main amplifier, and the hybrid power device of the main amplifier may include a second output internal matching network configured to operate at the second frequency, where the second output internal matching network includes a second capacitor and being configured to transform an output impedance of the second power transistor die of the hybrid device of the main amplifier.
- the first output internal matching network may include a first plurality of inner bonding wires connecting the first capacitor to the first power transistor die of the hybrid device of the main amplifier and a first plurality of outer bonding wires connecting the first capacitor to a first drain lead
- the second output internal matching network may include a second plurality of inner bonding wires connecting the second capacitor to the second power transistor die of the hybrid device of the main amplifier and a second plurality of outer bonding wires connecting the second capacitor to a second drain lead.
- the hybrid power device of the peak amplifier may include a first input internal matching network configured to operate at the first frequency, where the first input internal matching network includes a first capacitor and being configured to transform an input impedance of the first power transistor die of the hybrid device of the peak amplifier, and the hybrid power device of the peak amplifier may include a second input internal matching network configured to operate at the second frequency, where the second input internal matching network includes a second capacitor and being configured to transform an input impedance of the second power transistor die of the hybrid device of the peak amplifier.
- the first input internal matching network may include a first plurality of inner bonding wires connecting the first capacitor to the first power transistor die of the hybrid device of the peak amplifier and a first plurality of outer bonding wires connecting the first capacitor to a first gate lead
- the second input internal matching network may include a second plurality of inner bonding wires connecting the second capacitor to the second power transistor die of the hybrid device of the peak amplifier and a second plurality of outer bonding wires connecting the second capacitor to a second gate lead.
- the hybrid power device of the peak amplifier may include a first output internal matching network configured to operate at the first frequency, where the first output internal matching network includes a first capacitor and being configured to transform an output impedance of the first power transistor die of the hybrid device of the peak amplifier, and the hybrid power device of the peak amplifier may include a second output internal matching network configured to operate at the second frequency, where the second output internal matching network includes a second capacitor and being configured to transform an output impedance of the second power transistor die of the hybrid device of the peak amplifier.
- the first output internal matching network may include a first plurality of inner bonding wires connecting the first capacitor to the first power transistor die of the hybrid device of the peak amplifier and a first plurality of outer bonding wires connecting the first capacitor to a first drain lead
- the second output internal matching network may include a second plurality of inner bonding wires connecting the second capacitor to the second power transistor die of the hybrid device of the peak amplifier and a second plurality of outer bonding wires connecting the second capacitor to a second drain lead.
- One or more of the hybrid device of the main amplifier and the hybrid device of the peak amplifier may include one or more low-temperature co-fired creaming (LTCC) integrated circuits for implementing integrated input and output matching networks with both or either of the main and the peak hybrid power devices.
- LTCC low-temperature co-fired creaming
- FIG. 1A illustrates a Doherty amplifier structure according to at least one example embodiment.
- FIG. IB illustrated a Doherty amplifier structure including a digital signal processor (DSP) according to at least one example embodiment.
- DSP digital signal processor
- FIG. 2 illustrates a hybrid packaged power device structure of a Doherty amplifier according to at least one example embodiment.
- FIG. 3 illustrates a circuit diagram of a portion of the hybrid packaged power device of FIG. 2 that corresponds to a first transistor die.
- FIG. 4 illustrates a circuit diagram of a portion of the hybrid packaged power device of FIG. 2 that corresponds to a second transistor die.
- FIG. 5 illustrates an asymmetric variation of the hybrid packaged power device of FIG. 2 according to at least one example embodiment.
- Embodiments of the present invention overcome deficiencies of the conventional Doherty amplifiers when used in multi-band applications by providing a hybrid packaged power device.
- the hybrid packaged power devices according to example embodiments are configured to perform amplification over two different frequencies, which may be substantially separated from one another, while still allowing the Doherty amplifier to exhibit Doherty behavior.
- both the main and peak power amplifiers of a Doherty amplifier may be implemented by the hybrid packaged power devices according to example embodiments.
- the Doherty amplifiers of the present invention may be embodied in a base station in a wireless communication system that provides wireless connectivity to a number of end uses.
- the Doherty amplifiers may amplify signals to be transmitted to the end uses.
- the Doherty amplifiers of the present invention may be embodied in other types of devices such as W- CDMA, UMTS, LTE or WiMAX base stations, base transceiver stations, base station routers, WiFi access points, or any other device that provides the radio baseband functions for data and/ or voice connectivity between a network and one or more end users.
- the end users may include but are not limited to end user (EU) equipment, fixed or mobile subscriber units, receivers, cellular telephones, personal digital assistants (PDA), personal computers, or any other type of user device capable of operating in a wireless environment.
- EU end user
- PDA personal digital assistants
- a Doherty amplifier is a multi-band power amplifier including a hybrid package power device capable of operating with respect to at least two different frequencies, simultaneously. These embodiments are discussed with reference to FIGS. 1 -4 of the present application.
- FIG. 1A illustrates a structure of a Doherty amplifier 100 according to at least one example embodiment.
- the Doherty amplifier 100 includes a dual-band input splitter 105 configured to split an input signal into a first signal and a second signal, a main amplifier 1 1 OA for amplifying the first signal, a peak amplifier 1 1 OB for selectively amplifying the second signal, a dual-band phase compensator 130 for shifting a phase of the second signal, a dual-band Doherty combiner 140 for combining the output of the main amplifier 1 1 OA and the peak amplifier 1 1 OB, and a dual-band impedance transformer 150 configured to perform the impedance transformation of the combining node load R L impedance to output load impedance of the Doherty 3 ⁇ 4.
- the dual-band input splitter 105 generally divides the input signal into first and second signals and is capable of operating at two different frequencies.
- the dual-band input splitter 105 may have the structure of any known dual- band Doherty power splitter.
- the dual-band input splitter 105 may receive an input signal.
- the dual- band input splitter 105 may provide the first signal through a connection to an input of the main amplifier 1 1 OA, and provide the second signal though a connection to an input of the peak amplifier 1 10B via the phase compensator 130.
- the phase compensator 130 is connected between the dual band input splitter 105 and the input of the peak amplifier 1 10B.
- the phase compensator 130 is configured to compensate for the phase change introduced by the dual-band Doherty combiner 140.
- the phase compensator 130 may be based, for example, on a three transmission line arrangement in a "pi" structure as is illustrated in FIG. 1A. Though FIG. 1A illustrates an example in which the phase compensator 130 may have the "pi" structure, the dual -band phase compensator 130 may have the structure of any known dual-band Doherty phase compensator.
- the phase compensator 130 may be omitted.
- FIG. IB shows the Doherty amplifier 100 including a digital signal processor (DSP) 170 for implementing dual-band digital Doherty.
- DSP digital signal processor
- the phase compensator 130 may be omitted.
- the first and second signals are then amplified, respectively, by the main amplifier 1 1 OA, or the combination of the main amplifier 1 10A and the peak amplifier 1 10B, as discussed below.
- the peak amplifier 1 1 OB is selectively operable to operate at selected times in combination with the main amplifier 1 1 OA. That is, the peak amplifier 1 1 OB may be kept off until power requirements call for a higher power output from the whole Doherty power amplifier 100, at which time the peak amplifier 1 1 OB is turned on and operates to contribute to the output power increase of the Doherty power amplifier 100.
- the peak amplifier 1 10B amplifies the second signal at higher peak envelopes where the signal strength of the second signal is above a threshold level.
- the term "selectively operable" indicates the amplifier operational state changes in response to the input signal. Otherwise, if the signal strength of the second signal is below the threshold level, the peak amplifier 1 1 OB is turned OFF and only the main amplifier 1 1 OA operates to amplify the first signal.
- the main amplifier 1 10A includes a dual band main input matching network (IMN) 1 12A, a main hybrid packaged power device 1 14A and a dual band main output matching network (OMN) 1 16A. Signals are input to the main amplifier 1 1 OA through the dual band main input matching network (IMN) 1 12 A, and output from the main amplifier 1 1 OA through the output matching network (OMN) 1 16A.
- the main hybrid packaged power device 1 14A includes two dies, a first main die MD l and a second main die MD2.
- the first and second main dies MD l and MD2 include power transistors configured to operate at different frequencies, respectively.
- a first output of the dual-band main IMN 1 12A is connected to an input of the first main die MD 1 , and an output of the first main die MD l is connected to a first input of the dual-band main OMN 1 16A.
- a second output of the dual-band main IMN 1 12 A is connected to an input of the second main die MD2, and an output of the second main die MD2 is connected to a second input of the dual-band main OMN 1 16A.
- the real impedance Ro can be 50 ⁇ or any intermediary value that eases the design of the dual-band matching network IMN 1 12 A.
- the real impedance R m can be 50 ⁇ or any intermediary value that ease the design of the Dual-band output matching network OMN 1 16A.
- a variable using the format 'Zx' denotes an impedance x
- 'ax' denotes a resistance component of a corresponding impedance Zx
- 3 ⁇ 4x' denotes a reactance component of a corresponding impedance Zx
- 'j' is the imaginary unit.
- the main dies MD l and MD2 use integrated circuit technology including, for example, low-temperature co-fired ceramic (LTCC) or other similar technologies to allow highly integrated matching networks topologies that allow the design of internal matching circuitry that provide real input and output device impedances.
- LTCC low-temperature co-fired ceramic
- the dual-band main input matching network IMN 1 12A transforms the 2 real input impedances Rimi and Ri m 2 presented by the dies MD l and MD2, respectively, to an intermediate real impedance Ro.
- the real impedance Ro can be, for example, 50 ⁇ or any intermediary value that eases the design of the Dual-band matching network IMN 1 12A.
- the dual band OMN 1 16A transforms the 2 real output impedances R om i and R om 2 presented by the dies MD l and MD2, respectively, to a real impedance 2 x R m at power back-off (peak stage is off) and to a real impedance R m at peak power (peak running at full power) .
- the real impedance R m can be, for example, 50 ⁇ or any intermediary value that ease the design of the Dual-band output matching network OMN 1 16A.
- the peak amplifier 1 1 OB includes a structure similar to that discussed above with respect to the main amplifier 1 1 OA.
- the peak amplifier 1 1 OB includes a dual band peak input matching network (IMN) 1 12B, a peak hybrid packaged power device 1 14B and a dual band main output matching network (OMN) 1 16B. Signals are input to the peak amplifier 1 10B through the dual band peak input matching network (IMN) 1 12B, and output from the peak amplifier H OB through the output matching network (OMN) 1 16B.
- the peak hybrid packaged power device 1 14B includes two dies, a first peak die PD 1 and a second peak die PD2.
- the first and second peak dies PD 1 and PD2 include power transistors configured to operate at different frequencies, respectively.
- a first output of the dual-band peak IMN 1 12B is connected to an input of the first peak die PD 1 , and an output of the first peak die PD 1 is connected to a first input of the dual-band peak OMN 1 16B.
- a second output of the dual-band peak IMN 1 12B is connected to an input of the second peak die PD2, and an output of the second peak die PD2 is connected to a second input of the dual-band peak OMN 1 16B.
- the real impedance Ro can be, for example, 50 ⁇ or any intermediary value that eases the design of the Dual-band matching network IMN 1 12B.
- the real impedance Ro can be, for example, 50 ⁇ or any intermediary value that ease the design of the Dual-band matching network OMN 1 16B.
- the peak dies PD l and PD2 uses integrated circuit technology like LTCC or other similar technologies to allow highly integrated matching network topologies that allow the design of internal matching circuitry that provide real input and output device impedances.
- the dual-band peak input matching network IMN 1 12B transforms the 2 real input impedances Ri P i and Ri P 2 presented by the dies PD l and PD2, respectively, to an intermediate real impedance Ro.
- the real impedance Ro can be, for example, 50 ⁇ or any intermediary value that eases the design of the dual-band matching network IMN 1 12B.
- the dual band peak OMN 1 16B transforms the 2 real output impedances R op i and R op 2 presented by the dies PD l and PD2, respectively, to an intermediate real impedance Ro.
- the real impedance Ro can be, for example, 50 ⁇ or any intermediary value that ease the design of the Dual-band matching network OMN 1 16B.
- the outputs of the main amplifier 1 1 OA and the peak amplifier 1 1 OB are respectively connected to the dual-band main offset line 120A and the dual- band peak offset line 120B.
- the dual-band main offset line 120A receives the first signal and the dual-band peak offset line 120B receives the second signal.
- the purpose of the dual-band main offset line 120A is to ensure that the main stage load impedance at power back-off 2 x R m is located in a high or peak efficiency area on the load pull contours. Hence, high or maximum efficiency is achieved at power back-off.
- the dual-band offset line structure can be designed using structures and techniques known in the domain, including for example a T-structure line designed to include the electrical lengths 11 and 12 needed to ensure a maximum or, alternatively, desirable efficiency match, at power back-off, at both frequencies fl and £2 can be used.
- the purpose of the dual-band peak offset line 120B is to provide an open circuit at the Doherty output combining node, when the peak stage is OFF. As the open circuit needs to be provided at the dual-frequency bands of operation, a dual-band offset line circuit is desirable.
- the dual-band offset line circuit can be designed using structures and techniques known in the domain, including for example a T-structure line designed to include the electrical lengths 11 and 12 needed to ensure desirable open circuits, at power back-off, at both fl and f2 can be used.
- the output impedance of the main amplifier 1 1 OA is a modulated impedance, R M , which is modulated as a result of the variation of the current of the peak amplifier 1 10B in conjunction with the dual-band Doherty combiner 140.
- the dual- band Doherty combiner 140 receives the first signal from the dual-band main offset line 120A, and receives the second signal from the dual-band peak offset line 120B.
- the dual-band Doherty combiner 140 serves as an impedance inverter and, in accordance with known methods, is configured to act as a dual-band impedance inverter that that ensures an impedance transformations that include -90 degrees phase shifts at the dual-band frequencies fl and £2 at which the dual-band Doherty amplifier 100 is configured to operate.
- the dual-band Doherty combiner is implemented using the known microstrip line "pi" structure.
- other known structures for impedance inverters capable of handling multiple frequencies can be used to implement the dual-band Doherty combiner 140, as well.
- the dual-band Doherty combiner 140 is connected to an output of the dual- band Doherty amplifier 100 via the dual-band impedance transformer 150.
- the dual-band impedance transformer is configured to transform the output load Zo of the dual-band Doherty amplifier 100 to the combining node load RL at the output of the dual-band Doherty combiner 140.
- each of the main amplifier 1 1 OA and the peak amplifier 1 1 OB include a hybrid packaged power device 1 14A and 1 14B.
- the hybrid packaged power device 1 14A of the main amplifier 1 1 OA includes two separate dies MD 1 and MD2 respectively configured and designed for two different frequencies fl and £2.
- the hybrid packaged power device 1 14B of the peak amplifier 1 10B includes two separate dies PD 1 and PD2 also respectively configured and designed for the two different frequencies fl and £2.
- the Doherty amplifier is capable of achieving high levels of performance, for example in terms of efficiency, over the two different frequencies fl and f2 which may be significantly far apart from one another.
- GaN Gallium Nitride
- some broadband technologies like Gallium Nitride (GaN) may use a single die power transistor to implement a dual-band Doherty amplifier.
- GaN power transistors because the Doherty power amplifier is inherently narrow band, using GaN power transistors will not allow for high performance over the two frequency bands fl and £2 of operation, mainly, when the these two frequencies are far apart.
- GaN power transistors are broadband at saturated power operation, the load contour variation over frequency generally presents a narrow band characteristic, at power-back-off (on the 2: 1 constant voltage standing wave ratio (VSWR) circle).
- the resulting GaN based Doherty amplifier may not be capable of achieving high levels of efficiency over multiple frequencies, mainly, when the frequencies are significantly separated from one another, for example a first frequency of 700MHz and a second frequency of 2100MHz or 2600MHz.
- GaN power transistors are expensive.
- less expensive alternative power transistor technologies like laterally diffused metal oxide semiconductor (LDMOS), have bandwidths which are generally even more narrow that GaN power transistors, and thus, are generally less capable than GaN technology of use in dual-band Doherty amplifiers.
- LDMOS laterally diffused metal oxide semiconductor
- the hybrid packaged power devices used in a Doherty amplifier use separate dies, each of which includes a power transistor designed or, for example, optimized for a different frequency (e.g, two dies designed for frequencies fl and f2, respectively).
- the use of multiple dies designed, respectively, for different frequencies allows a Doherty amplifier according to example embodiments to operate at high or maximum performance for multiple frequencies which are significantly separated from one another using, for example, low cost LDMOS power transistors. Consequently, the hybrid packaged power devices used in the dual-band Doherty amplifier 100 allow the Doherty amplifier to operate at higher overall efficiency while also maintaining lower production costs when compared to conventional GaN dual-band Doherty amplifiers. Additionally, in accordance with at least one example embodiment, hybrid packaged power devices used in the Doherty amplifier 100 may also include other types of dies, for example GaN dies, instead of, or in addition to, LDMOS dies.
- types of transistors the hybrid packaged power devices may include one or more of GaN power transistors, High Heterojunction Bipolar Transistors (HBT), Galium Arsenide power transistors (GaAs), and pseudomorphic heterojunction pHEMT power transistors.
- HBT High Heterojunction Bipolar Transistors
- GaAs Galium Arsenide power transistors
- pseudomorphic heterojunction pHEMT power transistors pseudomorphic heterojunction pHEMT power transistors.
- FIG. 2 illustrates a hybrid packaged power device 200 in accordance with at least one example embodiment.
- the hybrid packaged power device 200 includes a first transistor die, die l, and a second transistor die, die2 which are designed to operate at two frequencies fl and f2, respectively.
- FIG. 3 illustrates a circuit diagram of a portion of hybrid packaged power device 200 that corresponds to the first transistor die, die 1.
- FIG. 4 illustrates a circuit diagram of a portion of hybrid packaged power device 200 that corresponds to the second transistor die, die 2.
- One or both of the main and peak hybrid packaged power devices 1 14A and 1 14B may have the same structure and operation as the hybrid power packaged device 200.
- the hybrid power packaged device 200 implements the main hybrid packaged power device 1 14A
- the first transistor die diel illustrated in FIG. 2 may implement the first main die MD l
- the second transistor die die2 illustrated in FIG. 2 may implement the second main die MD2 illustrated in FIG. 1.
- the hybrid power packaged device 200 implements the peak hybrid packaged power device 1 14B
- the first transistor die diel illustrated in FIG. 2 may implement the first peak die PD 1
- the second transistor die die die2 illustrated in FIG. 2 may implement the second peak die PD2 illustrated in FIG. 1.
- Each of the transistor dies diel and die2 is connected to an input internal matching network and an output internal matching network.
- the respective input internal matching networks of transistor dies die 1 and die2 transform the low input impedances of transistor dies diel and die2 to levels that are more desirable for a power amplifier designer.
- the input internal matching networks of die 1 is designed or, for example, optimized for high or maximum performance at frequency fl while the input matching network of die2 is designed or, for example, optimized for high or maximum performance at frequency f2.
- the respective output internal matching networks of transistor dies diel and die2 transform the low output impedances of transistor dies die 1 and die2 to levels that are more desirable for a power amplifier designer.
- the output internal matching networks of die 1 is designed or, for example, optimized for high or maximum performance at frequency fl while the output matching network of die2 is designed or, for example, optimized for high or maximum performance at frequency f2.
- the input and output internal matching networks of transistor dies die 1 and die2 include an array of small diameter bonding wires and shunt metal oxide silicon (MOS) capacitors.
- MOS metal oxide silicon
- the input internal matching network of the first transistor die die 1 includes first inner input bonding wires Lgl connecting die l to a first input shunt capacitor Cinl which is connected to a first gate lead Gatel via first outer input bonding wires Linl ; and the output internal matching network of the first transistor die diel includes first inner output bonding wires Ldl connecting diel to a first output shunt capacitor Coutl which is connected to a first drain lead Drain 1 via first outer output bonding wires Loutl .
- the input internal matching network of the second transistor die die2 includes second inner input bonding wires Lg2 connecting die2 to a second input shunt capacitor Cin2 which is connected to a second gate lead Gate2 via second outer input bonding wires Lin2; and the output internal matching network of the second transistor die die2 includes second inner output bonding wires Ld2 connecting die2 to a second output shunt capacitor Cout2 which is connected to a second drain lead Drain2 via second outer output bonding wires Lout2.
- transistor dies diel and die2 may be designed to operate at two different frequencies fl and f2, respectively.
- the input and output internal matching networks of first transistor die diel may be designed in order to achieve optimal, or alternatively, desirable performance for a first frequency fl .
- the input and output internal matching networks of second transistor die die2 e.g., one or more of second capacitors Cin2, Cout2, and second bonding wires Lin2, Lg2, Ld2 and Lout2
- second transistor die die2 may be designed in order to achieve optimal, or alternatively, desirable performance for a second frequency f2.
- the internal matching networks can include up to 100 or 200 or more bonding wires and several MOS capacitors densely packaged into a package cavity of the hybrid packaged power device 200.
- a package type of the hybrid packaged power device 200 may be, for example, ceramic type or plastic type.
- the internal matching networks of the hybrid packaged power device 200 may be based on, for example, one or more of on-chip spiral inductors, capacitors and transmission lines.
- the internal matching networks of the hybrid packaged power device 200 may introduce very high- Q resonances that allow an impedance transformation function.
- Asymmetric dies can be used in the hybrid packaged power device 200.
- the asymmetry used can be reflected by one or more of the size of the dies and to the technology used to design the dies.
- the first main die MD 1 operating at f 1 and the second main die MD2 die operating at f2 can have half of the size of the first peak die PD 1 operating at fl and the second peak die PD2 operating at f2.
- the difference in size is directly related to the peak to average ratio (PAR) of the signal that is being amplified, which may vary based on the product or application for which the signal is being used.
- PAR peak to average ratio
- FIG. 5 illustrates a hybrid packaged power device 500 which includes asymmetric dies.
- the hybrid packaged power device 500 is the same as the hybrid packaged power device 200 with the exception that the second transistor die die2 is larger than the first transistor die diel .
- one or both of the main and peak hybrid packaged power devices 1 14A and 1 14B may have the same structure and operation as the hybrid power packaged device 500.
- the asymmetry in the dies within the main hybrid packaged device 1 14A can be reflected in the difference of the technology used for the MD 1 die operating at fl and the MD2 die operating at f2.
- MD 1 die operating at fl can be designed using LDMOS technology while MD2 die operating at £2 can use GaN technology.
- This technology asymmetry can allow the use of low cost technology (LDMOS) at low frequency of fl where LDMOS excels and have similar performance, in efficiency, than high cost technology like GaN which provide better performance at higher frequency f2 where LDMOS cannot compete.
- LDMOS low cost technology
- the asymmetry in the dies within the peak hybrid packaged device 1 14B can be reflected in the difference of the technology used for the PD 1 die operating at fl and the PD2 die operating at f2.
- PD1 die operating at fl can be designed using LDMOS technology while PD2 die operating at f2 can use GaN technology.
- This technology asymmetry can allow the use of low cost LDMOS technology at the low frequency of fl where LDMOS excels and has performance similar to that of GaN technology in terms efficiency, while also allowing the use of high cost technology like GaN at the higher f2 frequency where GaN technology excels and LDMOS technology may, under some circumstances, show some limitations.
- the asymmetry described above can be applied for both the main and peak hybrid packaged power devices 1 14A and 1 14B, simultaneously, or only for the main hybrid package device 1 14A, or only for the peak hybrid package device 1 14B.
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Abstract
An amplifying structure includes a main amplifier configured to amplify a first signal; and a peak amplifier configured to amplify a second signal, each of the main amplifier and the peak amplifier including, respectively, a hybrid power device, the hybrid power device including, a first power transistor die configured to amplify signals of a first frequency, and a second power transistor die configured to amplify signals of a second frequency different than the first frequency.
Description
DUAL-BAND HIGH EFFICIENCY DOHERTY AMPLIFIERS WITH HYBRID
PACKAGED POWER DEVICES
BACKGROUND
Wireless Communication Standards are changing rapidly in order to respond to the never decreasing thirst of the consumers who continuously seek the ability to exchange of high data volume at higher data rate, and at lower cost. Network operators may find it challenging to handle the cost associated with continuously trying to adapt their already deployed sites with the new standards in order to satisfy the desires of the consumers. Base station vendors face similar challenges as their wireless product strategy is affected by the continuous standard changes. Multi- standard and multi-band radio Base stations represent one solution that may reduce the cost of these products as well as the cost of the future wireless network infrastructures. The software defined radio appears to be the leading technology that will drive the future multi- standard base stations. Another enabling component for these converged products is the Multi-band transceiver. More specifically, a power amplifier included a Multi-band transceiver may be required to operate in a multitude of frequency bands. In addition, in order to keep the base station operating expenses (OPEX) low, the broadband/multiband Power Amplifiers should be highly efficient. This requirement for high efficiency represents another challenge for network operators and base station vendors.
SUMMARY
According to at least one example embodiment, an amplifying structure includes a main amplifier configured to amplify a first signal; and a peak amplifier configured to amplify a second signal, each of the main amplifier and the peak amplifier including, respectively, a hybrid power device, each of the hybrid power devices including, respectively, a first power transistor die configured to amplify signals of a first frequency, and a second power
transistor die configured to amplify signals of a second frequency different than the first frequency.
The amplifying structure may be a Doherty amplifier.
Sizes of the first and second power transistor dies of the main amplifier may be the same as sizes of the first and second power transistor dies of the peak amplifier, respectively. Sizes of the first and second power transistor dies of the main amplifier may be smaller than sizes of the first and second power transistor dies of the peak amplifier, respectively.
The first and second power transistor dies of the main amplifier and the first and second power transistor dies of the peak amplifier may each include a laterally diffused metal oxide semiconductor (LDMOS) structure.
The first and second power transistor dies of the main amplifier and the first and second power transistor dies of the peak amplifier may each include a Gallium Nitride (GaN) structure.
The first and second power transistor dies of the main amplifier and the first and second power transistor dies of the peak amplifier may each include one or more high heterojunction bipolar transistors (HBT).
The first and second power transistor dies of the main amplifier and the first and second power transistor dies of the peak amplifier may each include one or more pseudomorphic heterojunction pHEMT power transistors. The second frequency may be higher than the first frequency, the first power transistor dies of the main amplifier and the peak amplifier may each include a laterally diffused metal oxide semiconductor (LDMOS) structure,
and the second power transistor dies of the main amplifier and the peak amplifier may each include a Gallium Nitride (GaN) structure.
A difference between the first frequency and the second frequency may be in between 200MHz and 1000MHz.
A difference between the first frequency and the second frequency may be more than 1000MHz. The hybrid power device of the main amplifier may include a first input internal matching network configured to operate at the first frequency, where the first input internal matching network includes a first capacitor and being configured to transform an input impedance of the first power transistor die of the hybrid device of the main amplifier, and the hybrid power device of the main amplifier may include a second input internal matching network configured to operate at the second frequency, where the second input internal matching network includes a second capacitor and being configured to transform an input impedance of the second power transistor die of the hybrid device of the main amplifier.
The first input internal matching network may include a first plurality of inner bonding wires connecting the first capacitor to the first power transistor die of the hybrid device of the main amplifier and a first plurality of outer bonding wires connecting the first capacitor to a first gate lead, and the second input internal matching network may include a second plurality of inner bonding wires connecting the second capacitor to the second power transistor die of the hybrid device of the main amplifier and a second plurality of outer bonding wires connecting the second capacitor to a second gate lead.
The hybrid power device of the main amplifier may include a first output internal matching network configured to operate at the first frequency,
where the first output internal matching network includes a first capacitor and being configured to transform an output impedance of the first power transistor die of the hybrid device of the main amplifier, and the hybrid power device of the main amplifier may include a second output internal matching network configured to operate at the second frequency, where the second output internal matching network includes a second capacitor and being configured to transform an output impedance of the second power transistor die of the hybrid device of the main amplifier. The first output internal matching network may include a first plurality of inner bonding wires connecting the first capacitor to the first power transistor die of the hybrid device of the main amplifier and a first plurality of outer bonding wires connecting the first capacitor to a first drain lead, and the second output internal matching network may include a second plurality of inner bonding wires connecting the second capacitor to the second power transistor die of the hybrid device of the main amplifier and a second plurality of outer bonding wires connecting the second capacitor to a second drain lead. The hybrid power device of the peak amplifier may include a first input internal matching network configured to operate at the first frequency, where the first input internal matching network includes a first capacitor and being configured to transform an input impedance of the first power transistor die of the hybrid device of the peak amplifier, and the hybrid power device of the peak amplifier may include a second input internal matching network configured to operate at the second frequency, where the second input internal matching network includes a second capacitor and being configured to transform an input impedance of the second power transistor die of the hybrid device of the peak amplifier.
The first input internal matching network may include a first plurality of inner bonding wires connecting the first capacitor to the first power
transistor die of the hybrid device of the peak amplifier and a first plurality of outer bonding wires connecting the first capacitor to a first gate lead, and the second input internal matching network may include a second plurality of inner bonding wires connecting the second capacitor to the second power transistor die of the hybrid device of the peak amplifier and a second plurality of outer bonding wires connecting the second capacitor to a second gate lead.
The hybrid power device of the peak amplifier may include a first output internal matching network configured to operate at the first frequency, where the first output internal matching network includes a first capacitor and being configured to transform an output impedance of the first power transistor die of the hybrid device of the peak amplifier, and the hybrid power device of the peak amplifier may include a second output internal matching network configured to operate at the second frequency, where the second output internal matching network includes a second capacitor and being configured to transform an output impedance of the second power transistor die of the hybrid device of the peak amplifier. The first output internal matching network may include a first plurality of inner bonding wires connecting the first capacitor to the first power transistor die of the hybrid device of the peak amplifier and a first plurality of outer bonding wires connecting the first capacitor to a first drain lead, and the second output internal matching network may include a second plurality of inner bonding wires connecting the second capacitor to the second power transistor die of the hybrid device of the peak amplifier and a second plurality of outer bonding wires connecting the second capacitor to a second drain lead. One or more of the hybrid device of the main amplifier and the hybrid device of the peak amplifier may include one or more low-temperature co-fired creaming (LTCC) integrated circuits for implementing integrated input and
output matching networks with both or either of the main and the peak hybrid power devices.
BRIEF DESCRIPTION OF THE DRAWINGS
Example embodiments will become more fully understood from the detailed description given herein below and the accompanying drawings, wherein like elements are represented by like reference numerals, which are given by way of illustration only and thus are not limiting of the present invention, and wherein:
FIG. 1A illustrates a Doherty amplifier structure according to at least one example embodiment.
FIG. IB illustrated a Doherty amplifier structure including a digital signal processor (DSP) according to at least one example embodiment.
FIG. 2 illustrates a hybrid packaged power device structure of a Doherty amplifier according to at least one example embodiment. FIG. 3 illustrates a circuit diagram of a portion of the hybrid packaged power device of FIG. 2 that corresponds to a first transistor die.
FIG. 4 illustrates a circuit diagram of a portion of the hybrid packaged power device of FIG. 2 that corresponds to a second transistor die.
FIG. 5 illustrates an asymmetric variation of the hybrid packaged power device of FIG. 2 according to at least one example embodiment.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
Various example embodiments will now be described more fully with reference to the accompanying drawings. Like elements on the drawings are labeled by like reference numerals.
As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising,", "includes" and/ or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and/ or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/ or groups thereof.
Example embodiment will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as not to obscure the present invention with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain example embodiments. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification that directly and unequivocally provides the special definition for the term or phrase. Embodiments of the present invention overcome deficiencies of the conventional Doherty amplifiers when used in multi-band applications by providing a hybrid packaged power device. The hybrid packaged power devices according to example embodiments are configured to perform amplification over two different frequencies, which may be substantially separated from one another, while still allowing the Doherty amplifier to exhibit Doherty behavior. As will be discussed in greater detail below, both the main and peak power amplifiers of a Doherty amplifier may be
implemented by the hybrid packaged power devices according to example embodiments.
The Doherty amplifiers of the present invention may be embodied in a base station in a wireless communication system that provides wireless connectivity to a number of end uses. The Doherty amplifiers may amplify signals to be transmitted to the end uses. Further, the Doherty amplifiers of the present invention may be embodied in other types of devices such as W- CDMA, UMTS, LTE or WiMAX base stations, base transceiver stations, base station routers, WiFi access points, or any other device that provides the radio baseband functions for data and/ or voice connectivity between a network and one or more end users. The end users may include but are not limited to end user (EU) equipment, fixed or mobile subscriber units, receivers, cellular telephones, personal digital assistants (PDA), personal computers, or any other type of user device capable of operating in a wireless environment.
A Doherty amplifier according to example embodiments is a multi-band power amplifier including a hybrid package power device capable of operating with respect to at least two different frequencies, simultaneously. These embodiments are discussed with reference to FIGS. 1 -4 of the present application.
FIG. 1A illustrates a structure of a Doherty amplifier 100 according to at least one example embodiment.
The Doherty amplifier 100 includes a dual-band input splitter 105 configured to split an input signal into a first signal and a second signal, a main amplifier 1 1 OA for amplifying the first signal, a peak amplifier 1 1 OB for selectively amplifying the second signal, a dual-band phase compensator 130 for shifting a phase of the second signal, a dual-band Doherty combiner 140 for combining the output of the main amplifier 1 1 OA and the peak
amplifier 1 1 OB, and a dual-band impedance transformer 150 configured to perform the impedance transformation of the combining node load RL impedance to output load impedance of the Doherty ¾. The dual-band input splitter 105 generally divides the input signal into first and second signals and is capable of operating at two different frequencies. The dual-band input splitter 105 may have the structure of any known dual- band Doherty power splitter. The dual-band input splitter 105 may receive an input signal. The dual- band input splitter 105 may provide the first signal through a connection to an input of the main amplifier 1 1 OA, and provide the second signal though a connection to an input of the peak amplifier 1 10B via the phase compensator 130.
The phase compensator 130 is connected between the dual band input splitter 105 and the input of the peak amplifier 1 10B. The phase compensator 130 is configured to compensate for the phase change introduced by the dual-band Doherty combiner 140. The phase compensator 130 may be based, for example, on a three transmission line arrangement in a "pi" structure as is illustrated in FIG. 1A. Though FIG. 1A illustrates an example in which the phase compensator 130 may have the "pi" structure, the dual -band phase compensator 130 may have the structure of any known dual-band Doherty phase compensator.
Further, in embodiments where dual-band digital Doherty is used, the phase compensator 130 may be omitted. For example, FIG. IB shows the Doherty amplifier 100 including a digital signal processor (DSP) 170 for implementing dual-band digital Doherty. As is illustrated in FIG. IB, when the DSP 170 is used, the phase compensator 130 may be omitted.
After the input signal is split into the first and second signals and the second signal passes through the phase compensator 130, the first and second signals are then amplified, respectively, by the main amplifier 1 1 OA, or the combination of the main amplifier 1 10A and the peak amplifier 1 10B, as discussed below.
For instance, the peak amplifier 1 1 OB is selectively operable to operate at selected times in combination with the main amplifier 1 1 OA. That is, the peak amplifier 1 1 OB may be kept off until power requirements call for a higher power output from the whole Doherty power amplifier 100, at which time the peak amplifier 1 1 OB is turned on and operates to contribute to the output power increase of the Doherty power amplifier 100. In other words, the peak amplifier 1 10B amplifies the second signal at higher peak envelopes where the signal strength of the second signal is above a threshold level. The term "selectively operable" indicates the amplifier operational state changes in response to the input signal. Otherwise, if the signal strength of the second signal is below the threshold level, the peak amplifier 1 1 OB is turned OFF and only the main amplifier 1 1 OA operates to amplify the first signal.
The main amplifier 1 10A includes a dual band main input matching network (IMN) 1 12A, a main hybrid packaged power device 1 14A and a dual band main output matching network (OMN) 1 16A. Signals are input to the main amplifier 1 1 OA through the dual band main input matching network (IMN) 1 12 A, and output from the main amplifier 1 1 OA through the output matching network (OMN) 1 16A. As will be discussed in greater detail below, the main hybrid packaged power device 1 14A includes two dies, a first main die MD l and a second main die MD2. The first and second main dies MD l and MD2 include power transistors configured to operate at different frequencies, respectively. A first output of the dual-band main IMN 1 12A is connected to an input of the first main die MD 1 , and an output of the first main die MD l is connected to a first input of the dual-band main OMN 1 16A.
A second output of the dual-band main IMN 1 12 A is connected to an input of the second main die MD2, and an output of the second main die MD2 is connected to a second input of the dual-band main OMN 1 16A. The dual- band main input matching network IMN 1 12A transforms the 2 complex input impedances ¾mi= aimi±jbimi and Zim2 = aim2±/bim2 presented by the dies MD l and MD2, respectively, to an intermediate real impedance Ro. The real impedance Ro can be 50 Ω or any intermediary value that eases the design of the dual-band matching network IMN 1 12 A. The dual band main OMN 1 16A transforms the 2 complex output impedances Zomi= aomi±/b0mi and Zom2 = a0m2±/bom2 presented by the dies MD l and MD2, respectively, to a real impedance 2xRm at power back-off (peak stage is off) and to a real impedance Rm at peak power (peak running at full power). The real impedance Rm can be 50Ω or any intermediary value that ease the design of the Dual-band output matching network OMN 1 16A.
As used herein, a variable using the format 'Zx' denotes an impedance x, 'ax' denotes a resistance component of a corresponding impedance Zx, ¾x' denotes a reactance component of a corresponding impedance Zx, and 'j' is the imaginary unit.
In another embodiment, the main dies MD l and MD2 use integrated circuit technology including, for example, low-temperature co-fired ceramic (LTCC) or other similar technologies to allow highly integrated matching networks topologies that allow the design of internal matching circuitry that provide real input and output device impedances. In this case, the dual-band main input matching network IMN 1 12A transforms the 2 real input impedances Rimi and Rim2 presented by the dies MD l and MD2, respectively, to an intermediate real impedance Ro. The real impedance Ro can be, for example, 50 Ω or any intermediary value that eases the design of the Dual-band matching network IMN 1 12A. The dual band OMN 1 16A transforms the 2 real output impedances Romi and Rom2 presented by the dies MD l and MD2, respectively, to a real impedance 2xRm at power back-off (peak stage is off)
and to a real impedance Rm at peak power (peak running at full power) . The real impedance Rm can be, for example, 50Ω or any intermediary value that ease the design of the Dual-band output matching network OMN 1 16A. The peak amplifier 1 1 OB includes a structure similar to that discussed above with respect to the main amplifier 1 1 OA. The peak amplifier 1 1 OB includes a dual band peak input matching network (IMN) 1 12B, a peak hybrid packaged power device 1 14B and a dual band main output matching network (OMN) 1 16B. Signals are input to the peak amplifier 1 10B through the dual band peak input matching network (IMN) 1 12B, and output from the peak amplifier H OB through the output matching network (OMN) 1 16B. As will be discussed in greater detail below, the peak hybrid packaged power device 1 14B includes two dies, a first peak die PD 1 and a second peak die PD2. The first and second peak dies PD 1 and PD2 include power transistors configured to operate at different frequencies, respectively. A first output of the dual-band peak IMN 1 12B is connected to an input of the first peak die PD 1 , and an output of the first peak die PD 1 is connected to a first input of the dual-band peak OMN 1 16B. A second output of the dual-band peak IMN 1 12B is connected to an input of the second peak die PD2, and an output of the second peak die PD2 is connected to a second input of the dual-band peak OMN 1 16B. The dual-band peak IMN 1 12B transforms the 2 complex input impedances ZiPi= aiPi±/biPi and ZiP2 = aiP2±/biP2 presented by the dies PD 1 and PD2, respectively, to an intermediate real impedance Ro. The real impedance Ro can be, for example, 50 Ω or any intermediary value that eases the design of the Dual-band matching network IMN 1 12B. The dual band peak OMN 1 16B transforms the 2 complex output impedances Zopi= aopi±/bopi and Zop2 = aoP2±/bop2 presented by the dies PD 1 and PD2, respectively, to an intermediate real impedance Ro. The real impedance Ro can be, for example, 50 Ω or any intermediary value that ease the design of the Dual-band matching network OMN 1 16B.
In another embodiment, the peak dies PD l and PD2 uses integrated circuit technology like LTCC or other similar technologies to allow highly integrated matching network topologies that allow the design of internal matching circuitry that provide real input and output device impedances. In this case, the dual-band peak input matching network IMN 1 12B transforms the 2 real input impedances RiPi and RiP2 presented by the dies PD l and PD2, respectively, to an intermediate real impedance Ro. The real impedance Ro can be, for example, 50 Ω or any intermediary value that eases the design of the dual-band matching network IMN 1 12B. The dual band peak OMN 1 16B transforms the 2 real output impedances Ropi and Rop2 presented by the dies PD l and PD2, respectively, to an intermediate real impedance Ro. The real impedance Ro can be, for example, 50 Ω or any intermediary value that ease the design of the Dual-band matching network OMN 1 16B. The outputs of the main amplifier 1 1 OA and the peak amplifier 1 1 OB are respectively connected to the dual-band main offset line 120A and the dual- band peak offset line 120B. The dual-band main offset line 120A receives the first signal and the dual-band peak offset line 120B receives the second signal.
The purpose of the dual-band main offset line 120A is to ensure that the main stage load impedance at power back-off 2xRm is located in a high or peak efficiency area on the load pull contours. Hence, high or maximum efficiency is achieved at power back-off. As this condition should be verified at the dual-band frequencies, the dual-band offset line structure can be designed using structures and techniques known in the domain, including for example a T-structure line designed to include the electrical lengths 11 and 12 needed to ensure a maximum or, alternatively, desirable efficiency match, at power back-off, at both frequencies fl and £2 can be used.
The purpose of the dual-band peak offset line 120B is to provide an open circuit at the Doherty output combining node, when the peak stage is OFF.
As the open circuit needs to be provided at the dual-frequency bands of operation, a dual-band offset line circuit is desirable. The dual-band offset line circuit can be designed using structures and techniques known in the domain, including for example a T-structure line designed to include the electrical lengths 11 and 12 needed to ensure desirable open circuits, at power back-off, at both fl and f2 can be used.
In accordance with the known Doherty operating principle, the output impedance of the main amplifier 1 1 OA is a modulated impedance, RM, which is modulated as a result of the variation of the current of the peak amplifier 1 10B in conjunction with the dual-band Doherty combiner 140. The dual- band Doherty combiner 140 receives the first signal from the dual-band main offset line 120A, and receives the second signal from the dual-band peak offset line 120B. The dual-band Doherty combiner 140 serves as an impedance inverter and, in accordance with known methods, is configured to act as a dual-band impedance inverter that that ensures an impedance transformations that include -90 degrees phase shifts at the dual-band frequencies fl and £2 at which the dual-band Doherty amplifier 100 is configured to operate. In the example illustrated in FIG. 1A, the dual-band Doherty combiner is implemented using the known microstrip line "pi" structure. However, according to at least some embodiments, other known structures for impedance inverters capable of handling multiple frequencies can be used to implement the dual-band Doherty combiner 140, as well. The dual-band Doherty combiner 140 is connected to an output of the dual- band Doherty amplifier 100 via the dual-band impedance transformer 150. In accordance with known methods, the dual-band impedance transformer is configured to transform the output load Zo of the dual-band Doherty amplifier 100 to the combining node load RL at the output of the dual-band Doherty combiner 140.
As is discussed above, in the dual-band Doherty amplifier 100, each of the main amplifier 1 1 OA and the peak amplifier 1 1 OB include a hybrid packaged power device 1 14A and 1 14B. The hybrid packaged power device 1 14A of the main amplifier 1 1 OA includes two separate dies MD 1 and MD2 respectively configured and designed for two different frequencies fl and £2. Likewise, the hybrid packaged power device 1 14B of the peak amplifier 1 10B includes two separate dies PD 1 and PD2 also respectively configured and designed for the two different frequencies fl and £2. By using a hybrid package including two dies optimized or, alternatively, designed for two different frequencies fl and f2 for implementing both the main and peak amplifiers 1 10A and 1 10B of the Doherty amplifier 100, the Doherty amplifier is capable of achieving high levels of performance, for example in terms of efficiency, over the two different frequencies fl and f2 which may be significantly far apart from one another.
In comparison, some broadband technologies like Gallium Nitride (GaN) may use a single die power transistor to implement a dual-band Doherty amplifier. However, because the Doherty power amplifier is inherently narrow band, using GaN power transistors will not allow for high performance over the two frequency bands fl and £2 of operation, mainly, when the these two frequencies are far apart. In fact, although GaN power transistors are broadband at saturated power operation, the load contour variation over frequency generally presents a narrow band characteristic, at power-back-off (on the 2: 1 constant voltage standing wave ratio (VSWR) circle). Hence the resulting GaN based Doherty amplifier may not be capable of achieving high levels of efficiency over multiple frequencies, mainly, when the frequencies are significantly separated from one another, for example a first frequency of 700MHz and a second frequency of 2100MHz or 2600MHz. Further, GaN power transistors are expensive. Additionally, less expensive alternative power transistor technologies, like laterally diffused metal oxide semiconductor (LDMOS), have bandwidths which are generally even more
narrow that GaN power transistors, and thus, are generally less capable than GaN technology of use in dual-band Doherty amplifiers.
To the contrary, the hybrid packaged power devices used in a Doherty amplifier according to example embodiments use separate dies, each of which includes a power transistor designed or, for example, optimized for a different frequency (e.g, two dies designed for frequencies fl and f2, respectively). The use of multiple dies designed, respectively, for different frequencies allows a Doherty amplifier according to example embodiments to operate at high or maximum performance for multiple frequencies which are significantly separated from one another using, for example, low cost LDMOS power transistors. Consequently, the hybrid packaged power devices used in the dual-band Doherty amplifier 100 allow the Doherty amplifier to operate at higher overall efficiency while also maintaining lower production costs when compared to conventional GaN dual-band Doherty amplifiers. Additionally, in accordance with at least one example embodiment, hybrid packaged power devices used in the Doherty amplifier 100 may also include other types of dies, for example GaN dies, instead of, or in addition to, LDMOS dies.
For example, types of transistors the hybrid packaged power devices according to example embodiments may include one or more of GaN power transistors, High Heterojunction Bipolar Transistors (HBT), Galium Arsenide power transistors (GaAs), and pseudomorphic heterojunction pHEMT power transistors.
The structures of the hybrid packaged power devices 1 14A and 1 14B will now be discussed in greater detail below with reference to FIGS. 2-4. FIG. 2 illustrates a hybrid packaged power device 200 in accordance with at least one example embodiment. As is illustrated in FIG.2, the hybrid packaged power device 200 includes a first transistor die, die l, and a second
transistor die, die2 which are designed to operate at two frequencies fl and f2, respectively. FIG. 3 illustrates a circuit diagram of a portion of hybrid packaged power device 200 that corresponds to the first transistor die, die 1. FIG. 4 illustrates a circuit diagram of a portion of hybrid packaged power device 200 that corresponds to the second transistor die, die 2.
One or both of the main and peak hybrid packaged power devices 1 14A and 1 14B may have the same structure and operation as the hybrid power packaged device 200. For example, when the hybrid power packaged device 200 implements the main hybrid packaged power device 1 14A, the first transistor die diel illustrated in FIG. 2 may implement the first main die MD l and the second transistor die die2 illustrated in FIG. 2 may implement the second main die MD2 illustrated in FIG. 1. Similarly, when the hybrid power packaged device 200 implements the peak hybrid packaged power device 1 14B, the first transistor die diel illustrated in FIG. 2 may implement the first peak die PD 1 and the second transistor die die2 illustrated in FIG. 2 may implement the second peak die PD2 illustrated in FIG. 1.
Each of the transistor dies diel and die2 is connected to an input internal matching network and an output internal matching network. The respective input internal matching networks of transistor dies die 1 and die2 transform the low input impedances of transistor dies diel and die2 to levels that are more desirable for a power amplifier designer. Moreover, the input internal matching networks of die 1 is designed or, for example, optimized for high or maximum performance at frequency fl while the input matching network of die2 is designed or, for example, optimized for high or maximum performance at frequency f2. Similarly, the respective output internal matching networks of transistor dies diel and die2 transform the low output impedances of transistor dies die 1 and die2 to levels that are more desirable for a power amplifier designer. Moreover, the output internal matching networks of die 1 is designed or, for example, optimized for high or maximum performance at frequency fl while the output matching network of die2 is
designed or, for example, optimized for high or maximum performance at frequency f2.
The input and output internal matching networks of transistor dies die 1 and die2 will now be discussed in greater detail below with reference to FIGS.
As is illustrated in FIGS. 2-4, the input and output internal matching networks of transistor dies die 1 and die2 include an array of small diameter bonding wires and shunt metal oxide silicon (MOS) capacitors.
In the example illustrated in FIGS. 2 and 3, the input internal matching network of the first transistor die die 1 includes first inner input bonding wires Lgl connecting die l to a first input shunt capacitor Cinl which is connected to a first gate lead Gatel via first outer input bonding wires Linl ; and the output internal matching network of the first transistor die diel includes first inner output bonding wires Ldl connecting diel to a first output shunt capacitor Coutl which is connected to a first drain lead Drain 1 via first outer output bonding wires Loutl . Similarly, in the example illustrated in FIGS. 2 and 4, the input internal matching network of the second transistor die die2 includes second inner input bonding wires Lg2 connecting die2 to a second input shunt capacitor Cin2 which is connected to a second gate lead Gate2 via second outer input bonding wires Lin2; and the output internal matching network of the second transistor die die2 includes second inner output bonding wires Ld2 connecting die2 to a second output shunt capacitor Cout2 which is connected to a second drain lead Drain2 via second outer output bonding wires Lout2. As is discussed above, transistor dies diel and die2 may be designed to operate at two different frequencies fl and f2, respectively. In accordance with known techniques, the input and output internal matching networks of
first transistor die diel (e.g., one or more of first capacitors Cinl , Coutl , and first bonding wires Linl , Lgl , Ldl and Loutl) may be designed in order to achieve optimal, or alternatively, desirable performance for a first frequency fl . Similarly, the input and output internal matching networks of second transistor die die2 (e.g., one or more of second capacitors Cin2, Cout2, and second bonding wires Lin2, Lg2, Ld2 and Lout2) may be designed in order to achieve optimal, or alternatively, desirable performance for a second frequency f2. According to some example embodiments, for large transistor devices, the internal matching networks can include up to 100 or 200 or more bonding wires and several MOS capacitors densely packaged into a package cavity of the hybrid packaged power device 200. A package type of the hybrid packaged power device 200 may be, for example, ceramic type or plastic type. For high power radio frequency (RF) integrated circuit (IC) product implementations, the internal matching networks of the hybrid packaged power device 200 may be based on, for example, one or more of on-chip spiral inductors, capacitors and transmission lines. The internal matching networks of the hybrid packaged power device 200 may introduce very high- Q resonances that allow an impedance transformation function.
Asymmetric dies can be used in the hybrid packaged power device 200. The asymmetry used can be reflected by one or more of the size of the dies and to the technology used to design the dies.
In the case of asymmetric versions of main and peak hybrid packaged devices 1 14A and 1 14B, the first main die MD 1 operating at f 1 and the second main die MD2 die operating at f2 can have half of the size of the first peak die PD 1 operating at fl and the second peak die PD2 operating at f2. The difference in size is directly related to the peak to average ratio (PAR) of the signal that is being amplified, which may vary based on the product or application for which the signal is being used. Hence, for a PAR of 8-9dB, it
may be preferable for the peak efficiency to occur at 8-9dB back-off from peak power. Thus, it may be desirable for the sizes of first and second peak dies PD 1 and PD2 to be double the sizes of first and second main dies MD 1 and MD2. For example, FIG. 5 illustrates a hybrid packaged power device 500 which includes asymmetric dies. The hybrid packaged power device 500 is the same as the hybrid packaged power device 200 with the exception that the second transistor die die2 is larger than the first transistor die diel . In the same manner discussed above with reference to hybrid packaged power device 200, one or both of the main and peak hybrid packaged power devices 1 14A and 1 14B may have the same structure and operation as the hybrid power packaged device 500.
In another embodiment, the asymmetry in the dies within the main hybrid packaged device 1 14A can be reflected in the difference of the technology used for the MD 1 die operating at fl and the MD2 die operating at f2. As example, MD 1 die operating at fl can be designed using LDMOS technology while MD2 die operating at £2 can use GaN technology. This technology asymmetry can allow the use of low cost technology (LDMOS) at low frequency of fl where LDMOS excels and have similar performance, in efficiency, than high cost technology like GaN which provide better performance at higher frequency f2 where LDMOS cannot compete.
In another embodiment, the asymmetry in the dies within the peak hybrid packaged device 1 14B can be reflected in the difference of the technology used for the PD 1 die operating at fl and the PD2 die operating at f2. As an example, PD1 die operating at fl can be designed using LDMOS technology while PD2 die operating at f2 can use GaN technology. This technology asymmetry can allow the use of low cost LDMOS technology at the low frequency of fl where LDMOS excels and has performance similar to that of GaN technology in terms efficiency, while also allowing the use of high cost technology like GaN at the higher f2 frequency where GaN technology excels
and LDMOS technology may, under some circumstances, show some limitations.
The asymmetry described above can be applied for both the main and peak hybrid packaged power devices 1 14A and 1 14B, simultaneously, or only for the main hybrid package device 1 14A, or only for the peak hybrid package device 1 14B.
All the power transistor technologies mentioned above (LDMOS, GaN, GaAs FET, HBT, pHEMT) can use the hybrid package device dies and can follow the different configurations and asymmetries described above.
Variations of the example embodiments of the present invention are not to be regarded as a departure from the spirit and scope of the example embodiments of the invention, and all such variations as would be apparent to one skilled in the art are intended to be included within the scope of this invention.
Claims
1. An amplifying structure ( 100), comprising:
a main amplifier (1 10A) configured to amplify a first signal; and a peak amplifier ( 1 1 OB) configured to amplify a second signal, each of the main amplifier (1 14A) and the peak amplifier (1 14B) including, respectively, a hybrid power device, each of the hybrid power devices including, respectively,
a first power transistor die (MD 1 , PD 1) configured to amplify signals of a first frequency (fl), and
a second power transistor die (MD2, PD2) configured to amplify signals of a second frequency (f2) different than the first frequency.
2. The amplifying structure of claim 1 , wherein the amplifying structure is a Doherty amplifier.
3. The amplifying structure of claim 1 , wherein sizes of the first and second power transistor dies of the main amplifier are the same as sizes of the first and second power transistor dies of the peak amplifier, respectively.
4. The amplifying structure of claim 1 , wherein sizes of the first and second power transistor dies of the main amplifier are smaller than sizes of the first and second power transistor dies of the peak amplifier, respectively.
5. The amplifying structure of claim 1 , wherein the first and second power transistor dies of the main amplifier and the first and second power transistor dies of the peak amplifier each include a laterally diffused metal oxide semiconductor (LDMOS) structure, or the first and second power transistor dies of the main amplifier and the first and second power transistor dies of the peak amplifier each include a Gallium Nitride (GaN) structure.
6. The amplifying structure of claim 1 , wherein the first and second power transistor dies of the main amplifier and the first and second power transistor dies of the peak amplifier each include one or more high heterojunction bipolar transistors (HBT), or the first and second power transistor dies of the main amplifier and the first and second power transistor dies of the peak amplifier each include one or more pseudomorphic heterojunction pHEMT power transistors.
7. The amplifying structure of claim 1 , wherein the second frequency is higher than the first frequency, the first power transistor dies of the main amplifier and the peak amplifier each include a laterally diffused metal oxide semiconductor (LDMOS) structure, and the second power transistor dies of the main amplifier and the peak amplifier each include a Gallium Nitride (GaN) structure.
8. The amplifying structure of claim 1 , wherein a difference between the first frequency and the second frequency is in between 200MHz and 1000MHz.
9. The amplifying structure of claim 1 , wherein a difference between the first frequency and the second frequency is more than 1000MHz.
10. The amplifying structure of claim 1 wherein,
the hybrid power device of the main amplifier includes a first input internal matching network (Gate Lead Transistor 1 , Linl , Cinl , Lgl) configured to operate at the first frequency, the first input internal matching network including a first capacitor (Cinl) and being configured to transform an input impedance of the first power transistor die of the hybrid device of the main amplifier, and
the hybrid power device of the main amplifier includes a second input internal matching network (Gate Lead Transistor 2, Lin2, Cin2, Lg2)
configured to operate at the second frequency, the second input internal matching network including a second capacitor (Cin2) and being configured to transform an input impedance of the second power transistor die of the hybrid device of the main amplifier, wherein,
the first input internal matching network includes a first plurality of inner bonding wires (Lgl) connecting the first capacitor to the first power transistor die (Diel , MDl) of the hybrid device of the main amplifier and a first plurality of outer bonding wires (Linl) connecting the first capacitor to a first gate lead (Gate Lead Transitorl), and
the second input internal matching network includes a second plurality of inner bonding wires (Lg2) connecting the second capacitor (Cin2) to the second power transistor die (Die2, MD2) of the hybrid device of the main amplifier and a second plurality of outer bonding wires (Lin2) connecting the second capacitor (Cin2) to a second gate lead (Gate Lead Transitor2) .
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JP2016526382A JP6280645B2 (en) | 2013-07-19 | 2014-07-10 | Dual-band high-efficiency Doherty amplifier using hybrid packaged power devices |
EP14827057.2A EP3022839B1 (en) | 2013-07-19 | 2014-07-10 | Dual-band high efficiency doherty amplifiers with hybrid packaged power devices |
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US13/946,369 | 2013-07-19 | ||
US13/946,369 US9030260B2 (en) | 2013-07-19 | 2013-07-19 | Dual-band high efficiency Doherty amplifiers with hybrid packaged power devices |
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WO2015006866A1 true WO2015006866A1 (en) | 2015-01-22 |
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PCT/CA2014/050655 WO2015006866A1 (en) | 2013-07-19 | 2014-07-10 | Dual-band high efficiency doherty amplifiers with hybrid packaged power devices |
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EP (1) | EP3022839B1 (en) |
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US9565642B2 (en) * | 2014-04-11 | 2017-02-07 | Cree, Inc. | GaN amplifier for WiFi applications |
US9973155B2 (en) * | 2015-07-09 | 2018-05-15 | Tdk Corporation | Apparatus and methods for tunable power amplifiers |
US20180254747A1 (en) * | 2017-03-01 | 2018-09-06 | Sumitomo Electric Device Innovations, Inc. | Doherty amplifier |
CN116455334A (en) * | 2023-03-15 | 2023-07-18 | 华南理工大学 | Continuous hybrid regulation and control Doherty power amplifier, device and method |
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Also Published As
Publication number | Publication date |
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EP3022839A1 (en) | 2016-05-25 |
JP6280645B2 (en) | 2018-02-14 |
EP3022839A4 (en) | 2016-06-22 |
US9030260B2 (en) | 2015-05-12 |
JP2016525835A (en) | 2016-08-25 |
US20150022270A1 (en) | 2015-01-22 |
EP3022839B1 (en) | 2018-10-03 |
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