Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/44—Arrangements for executing specific programs
  • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
  • G06F9/45533—Hypervisors; Virtual machine monitors
  • G06F9/45558—Hypervisor-specific management and integration aspects
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/46—Multiprogramming arrangements
  • G06F9/48—Program initiating; Program switching, e.g. by interrupt
  • G06F9/4806—Task transfer initiation or dispatching
  • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
  • G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution
  • G06F9/4856—Task life-cycle, e.g. stopping, restarting, resuming execution resumption being on a different machine, e.g. task migration, virtual machine migration
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/44—Arrangements for executing specific programs
  • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
  • G06F9/45533—Hypervisors; Virtual machine monitors
  • G06F9/45558—Hypervisor-specific management and integration aspects
  • G06F2009/4557—Distribution of virtual machine instances; Migration and load balancing
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/44—Arrangements for executing specific programs
  • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
  • G06F9/45533—Hypervisors; Virtual machine monitors
  • G06F9/45558—Hypervisor-specific management and integration aspects
  • G06F2009/45583—Memory management, e.g. access or allocation

Definitions

• multiple processor cores may be included in a single integrated circuit die or on multiple integrated circuit dies that are arranged in a single chip package.
• a cache may be used to store data for access by one or more of the processor cores.
• An accelerator may be a special purpose processor focused on one or more applications.
• the methods may include detecting a trigger.
• the trigger may indicate a command has been sent to a processor to switch from execution of a first virtual machine to a second virtual machine.
• the methods may include, in response to detecting the trigger, selecting a programmable circuit and a program for the programmable circuit, where the programmable circuit is associated with the second virtual machine.
• the methods may further include generating a write command to write the program to the programmable circuit.
• the devices may include a memory, a switch detector, and a second processor.
• the switch detector may be effective to detect a trigger.
• the trigger may indicate that a command has been sent to a first processor to switch from execution of a first virtual machine to a second virtual machine.
• the second processor may be configured to be in communication with the memory and the switch detector.
• the second processor may be effective to detect the trigger.
• the second processor may be effective to identify an accelerator and accelerator map for the programmable circuit associated with the second virtual machine.
• the second processor may be effective to generate a write command to write the accelerator map to the accelerator.
• the systems may include a first processor, a virtual machine manager, a programmable circuit, and a reconfiguration device.
• the virtual machine manager may be effective to send a command to the first processor to switch from execution of a first virtual machine to a second virtual machine.
• the virtual machine manager may further be effective to generate a trigger in response to the command.
• the reconfiguration device may include a memory, a switch detector, and a second processor.
• the second processor may be effective to detect the trigger.
• the second processor may be effective to identify the programmable circuit and a map associated with the second virtual machine.
• the second processor may be effective to generate a write command to write the map to the programmable circuit.
• Fig. 1 illustrates an example system that can be utilized to implement reconfiguration with virtual machine switching
• Fig. 2 illustrates an example system that can be utilized to implement reconfiguration with virtual machine switching
• Fig. 3 illustrates an example system that can be utilized to implement reconfiguration with virtual machine switching
• Fig. 4 illustrates an example system that can be utilized to implement reconfiguration with virtual machine switching
• Fig. 5 illustrates an example system that can be utilized to implement reconfiguration with virtual machine switching
• Fig. 6 depicts a flow diagram for an example process for implementing reconfiguration with virtual machine switching
• Fig. 7 illustrates a computer program product that can be utilized to implement reconfiguration with virtual machine switching
• Fig. 8 is a block diagram illustrating an example computing device that is arranged to implement reconfiguration with virtual machine switching
• This disclosure is generally drawn, inter alia, to methods, apparatus, systems, devices, and computer program products related to reconfiguration with virtual machine switching.
• An accelerator reconfiguration device may detect a trigger.
• the trigger may indicate that a command has been sent to a processor to switch from execution of a first virtual machine to a second virtual machine.
• the reconfiguration device may identify a programmable circuit and a program for the programmable circuit associated with the second virtual machine.
• the reconfiguration device may further generate a write command to write the program to the programmable circuit.
• FIG. 1 illustrates an example system that can be utilized to implement reconfiguration with virtual machine switching arranged in accordance with at least some embodiments described herein.
• An example system 100 may include a processor core 108, a programmable circuit such as an accelerator 102, a
• programmable circuit such as an accelerator 104, a programmer such as an accelerator programmer 112, a virtual machine manager 120 and/or an accelerator reconfiguration device 116 all arranged in communication with one another.
• Accelerator programmer 112 may be a dedicated unit or a general purpose processor.
• Processor core 108 may include a memory 106 effective to store information that may be used by processor core 108 during operation. Accelerators 102 or 104 may be configured or reconfigured by a map 114 to be operable to execute a particular application or code.
• processor core 108, reconfigurable accelerators 102, 104, accelerator programmer 112, virtual machine manager 120 and/or an accelerator reconfiguration device 116 may be located on the same die 110.
• one or more of processor core 108, reconfigurable accelerators 102, 104, accelerator programmer 112, virtual machine manager 120 and/or an accelerator reconfiguration device 116 may be located on different dies.
• Accelerator reconfiguration device 116 may be implemented as software, hardware, or a combination of software and hardware. Accelerator reconfiguration device 116 may be part of virtual machine manager 120. Processor core 108 may be configured to use one or more of reconfigurable accelerator 102, 104 to perform operations or tasks..
• Accelerator programmer 112 may include accelerator maps 114.
• Accelerator maps 114 may correspond to one or more programs for reconfigurable accelerators 102, 104. Accelerator maps 114 may include binary data that may be streamed into gates of reconfigurable accelerators. Accelerator programmer 112 may be configured to program reconfigurable accelerators 102, 104 based on accelerator maps 114.
• Accelerator programmer 112 may be configured to program
• accelerator maps 114 may be effective to define states of gates or switches in an FPGA (field programmable gate array), EEPROM (electrically erasable
• processor core 108 may control accelerator programmer 112 to load a requested accelerator map 114 into reconfigurable accelerator 102, 104 based on an execution queue.
• virtual machine manager 120 may send a command to processor core 108 to implement a first virtual machine. After a period of time, virtual machine manager 120 may send a switch command 142 to processor core 108 to implement a second virtual machine.
• Virtual machine manager 120 may be, for example, a hypervisor.
• switch command 142 may be effective to implement a context switch in processor core 120 or a world switch in processor core 120.
• processor core 108 may stop processing instructions that correspond to the first virtual machine and may start processing instructions that correspond to the second virtual machine.
• a state of processor core 108 may remain unaltered.
• the state of processor core 108 may correspond to the state registers, buffers, caches etc. of processor core 108.
• Context switching may be used in situations where resources are shared between operations and those resources modify user memory but not low level system state.
• Virtual machine manager 120 may be used to implement a world switch in situations where a virtual machine being implemented by processor core 108 requests access to low level system states. In world switching, processing states may be captured and saved and then replaced with a saved state of another virtual machine or "world”.
• virtual machine manager 120 may be configured to send switch command 142 to processor core 108.
• Switch command 142 may be a command to processor core 108 to switch from a first virtual machine to a second virtual machine.
• Switch command 142 may be, for example, a world switch command or a context switch command
• information in registers and queues of processor core 108, and information regarding states, and other processor core information may be saved by virtual machine manager 120 and stored in VMM memory 118. Prior information relating to the second virtual machine may be transferred from VMM memory 118 to processor core 108 by virtual machine manager 120.
• Accelerator reconfiguration device 116 may be configured to detect switch command 142.
• Accelerator reconfiguration device 116 may further be configured to reconfigure one or more of reconfigurable accelerators 102, 104 in response detecting switch command 142.
• FIG. 2 illustrates an example system that can be utilized to implement reconfiguration with virtual machine switching arranged in accordance with at least some embodiments described herein. Those components in Fig. 2 that are labeled identically to components of Fig. 1 will not be described again for the purposes of clarity.
• accelerator programmer 112 may load map 224 to reconfigurable accelerator 102. Accelerator programmer 112 may also load map 226 to
• reconfigurable accelerator 104 When accelerator programmer 112 loads maps 224, 226 to reconfigurable accelerators 102, 104, a map copy 228, that includes a copy of map 224 and/or 226, may be sent to accelerator reconfiguration device 116.
• virtual machine manager 120 may also send a trigger 222 to accelerator reconfiguration device 116.
• Trigger 222 may indicate that virtual machine manager 120 has sent switch command 142 to processor core 108.
• accelerator reconfiguration device 116 may send a write command 238 to an appropriate reconfigurable accelerator 102, 104.
• Write command 238 may be a command to write the map in map copy 228 to an applicable reconfigurable accelerator 102, 104.
• Reconfiguration memory 336 may be adapted to store active accelerator maps 330 and/or virtual machine to accelerator relationships data 332.
• accelerator reconfiguration device 116 receives map copy 228, copies of maps for reconfigurable accelerators 102, 104 may be stored in active accelerator maps 330.
• Processor 340 may determine an active virtual machine at a time when maps 224, 226 are sent to reconfigurable accelerators 102, 104.
• a program executing within a virtual machine may recognize accelerator maps that are active.
• Processor 340 may store an association between the active virtual machine and active accelerator maps 224, 226 in virtual machine to accelerator relationships data 332.
• Virtual machine to accelerator relationships data 332 may include a table identifying relationships between virtual machines, accelerators, and accelerator maps.
• Virtual machine switch detector 334 may be configured to detect switch command 142 such as by detecting trigger 222.
• processor 340 may identify the particular virtual machine identified in switch command 142.
• trigger 222 may be a signal sent from virtual machine manager 120 and may identify the particular virtual machine in switch command 142.
• Processor 340 may then analyze virtual machine to accelerator relationships data 332 to identify a particular reconfigurable accelerator associated with the particular virtual machine.
• Processor 340 may also identify the particular accelerator map from active accelerator maps 330 associated with the particular virtual machine.
• Processor 340 may generate write command 238 to write the particular accelerator map to the particular reconfigurable accelerator.
• processor 340 may identify which virtual machine is under execution by processor core 108. For example, processor 340 may communicate with virtual machine manager 120 and/or processor core 108 to identify the virtual machine under execution. Alternatively, virtual machine manager 120 may send a signal, such as trigger 222, to accelerator reconfiguration device 116 indicating what virtual machine is under execution. Processor 340 may then update virtual machine to accelerator relationships data 332 to associate the virtual machine under execution with the corresponding accelerator and map.
• a direct memory access environment may be used to wall off location ranges in memory 106 so that those ranges belong to particular virtual machines and are inaccessible to other virtual machines.
• Virtual machine to accelerator relationship data 332 may store associations between virtual machines and memory location ranges.
• Processor 340 may then analyze virtual machine to accelerator relationship data 332 and detect that processor core 108 has switched to executing a different virtual machine based upon memory locations being accessed. For example, a first virtual machine may be associated memory locations 1 through 5 of memory 106.
• a second virtual machine may be associated with memory locations 6 through 10 in memory 106.
• Virtual machine to accelerator relationship data 332 may be configured to store indications of a virtual machine, an associated accelerator, a map, and a range of memory locations in memory 106.
• Fig. 4 illustrates an example system that can be utilized to implement accelerator reconfiguration with virtual machine switching arranged in accordance with at least some embodiments described herein. Those components in Fig. 4 that are labeled identically to components of Figs. 1, 2 and 3 will not be described again for the purposes of clarity.
• a system in accordance with the disclosure may be able to allow virtual machines to effectively work with relevant reconfigurable accelerators.
• Virtual machines may be prevented from working with accelerators associated with, or configured for, other virtual machines.
• Security may be improved in that a virtual machine may avoid working with a processor with an accelerator used by a prior virtual machine.
• processor 804 may be of any type including but not limited to a microprocessor ( ⁇ ), a microcontroller ( ⁇ ), a digital signal processor (DSP), or any combination thereof.
• Processor 804 may include one more levels of caching, such as a level one cache 810 and a level two cache 812, a processor core 814, and registers 816.
• An example processor core 814 may include an arithmetic logic unit (ALU), a floating point unit (FPU), a digital signal processing core (DSP Core), or any combination thereof.
• Processor 804 may include a programmable circuit 817 such as reconfigurable accelerators 102 and/or 104.
• An example memory controller 818 may also be used with processor 804, or in implementations memory controller 818 may be an internal part of processor
• the network communication link may be one example of a

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• 2013
  • 2013-06-25 WO PCT/US2013/047650 patent/WO2014209286A1/en active Application Filing
  • 2013-06-25 CN CN201380077736.2A patent/CN105393218B/zh not_active Expired - Fee Related
  • 2013-06-25 US US14/233,848 patent/US9619265B2/en not_active Expired - Fee Related

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