WO2014209285A1 - Cmos-compatible polycide fuse structure and method of fabricating same - Google Patents

Cmos-compatible polycide fuse structure and method of fabricating same Download PDF

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Publication number
WO2014209285A1
WO2014209285A1 PCT/US2013/047626 US2013047626W WO2014209285A1 WO 2014209285 A1 WO2014209285 A1 WO 2014209285A1 US 2013047626 W US2013047626 W US 2013047626W WO 2014209285 A1 WO2014209285 A1 WO 2014209285A1
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Prior art keywords
semiconductor
metal
polycide fuse
layer
fuse structure
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Ceased
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PCT/US2013/047626
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French (fr)
Inventor
Jeng-Ya D. YEH
Chia-Hong Jan
Walid M. Hafez
Joodong Park
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Intel Corp
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Intel Corp
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Application filed by Intel Corp filed Critical Intel Corp
Priority to CN201380076882.3A priority Critical patent/CN105283961B/en
Priority to DE112013007051.0T priority patent/DE112013007051B4/en
Priority to US14/780,222 priority patent/US9881927B2/en
Priority to KR1020157031743A priority patent/KR102101763B1/en
Priority to KR1020207008983A priority patent/KR102241180B1/en
Priority to PCT/US2013/047626 priority patent/WO2014209285A1/en
Priority to GB1520616.2A priority patent/GB2529955B/en
Priority to TW103120699A priority patent/TWI567940B/en
Publication of WO2014209285A1 publication Critical patent/WO2014209285A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/853—Complementary IGFETs, e.g. CMOS comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H10W20/493—Fuses, i.e. interconnections changeable from conductive to non-conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

Definitions

  • Embodiments of the invention are in the field of semiconductor devices and processing and, in particular, CMOS-compatible polycide fuse structures and methods of fabricating CMOS-compatible polycide fuse structures.
  • tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable a less complicated tri-gate fabrication process. In other instances, silicon-on- insulator substrates are preferred because of the improved short-channel behavior of tri-gate transistors.
  • microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on including passive features among active devices have increased, e.g., for system-on-chip (SoC) based architectures.
  • SoC system-on-chip
  • Figure 1A illustrates a cross-sectional view of a MOS-FET transistor having a metal gate/high-k material stack, in accordance with an embodiment of the present invention.
  • Figure IB illustrates a cross-sectional view of a CMOS-compatible polycide fuse structure, in accordance with an embodiment of the present invention.
  • Figures 2A-2I illustrate cross-sectional views representing various operations in a method of fabricating a polycide fuse structure, in accordance with an embodiment of the present invention.
  • Figure 3A illustrates a top angled view and a cross-sectional view of a polycide fuse structure for a non-planar semiconductor device architecture, in accordance with an embodiment of the present invention.
  • Figure 3B illustrates a cross-sectional view of a polycide fuse structure for a non-planar semiconductor device architecture, in accordance with another embodiment of the present invention.
  • Figures 4A-4K illustrate cross-sectional views representing various operations in a method of fabricating a polycide fuse structure for a non-planar semiconductor device architecture, in accordance with an embodiment of the present invention.
  • Figures 5A-5K illustrate cross-sectional views representing various operations in another method of fabricating a polycide fuse structure for a non- planar semiconductor device architecture, in accordance with an embodiment of the present invention.
  • Figures 6A-6L illustrate cross-sectional views representing various operations in another method of fabricating a polycide fuse structure for a non- planar semiconductor device architecture, in accordance with an embodiment of the present invention.
  • Figure 7 illustrates a computing device in accordance with one implementation of the invention.
  • CMOS -compatible polycide fuse structures and methods of fabricating CMOS-compatible polycide fuse structures are described.
  • numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure
  • One or more embodiments described herein are directed to polycide fuse structures and manufacturing methods for high-K metal gate technology.
  • CMOS complementary metal oxide semiconductor
  • OTP one time programmable
  • polysilicide polycide fuse structures and process technology
  • programmable fuses CMOS devices, high-K gate dielectric and/or metal gate processing schemes, one time programmable (OTP) fuses, polysilicide (polycide) fuse structures and process technology, and programmable fuses.
  • approaches described herein involve process integration schemes that enable fabrication of a polycide fuse element and high-k/metal gate CMOS technology integration. More specifically, in an embodiment, a lithography and etch patterning process is used to recess a dummy polysilicon structure prior to replacement gate processing in order to effectively bury a polysilicon gate underneath an inter-layer dielectric oxide film. The preserved polysilicon gate is then silicided and used as a one time programmable fuse structure. Embodiments described herein may enable an alternative of fuse element architecture for future technology nodes. Furthermore, embodiments described herein provide options beyond standard metal fusing that can be directly integratable with high-k and metal gate based CMOS transistors. [0017] To provide context, gate electrodes were initially formed from metal
  • MOSFET Metal- Oxide- Semiconductor Field Effect Transistor
  • gate-first process sequence was universally practiced so as to permit blanket deposition of the polysilicon, plasma etch-defined gate lengths, lightly-doped tip regions, dielectric sidewall spacers, and self-aligned source/drain (i.e., to the gate electrode).
  • gate electrodes are typically no longer formed strictly from aluminum.
  • the gate electrodes are now usually formed from a transition metal, an alloy of transition metals, or a transition metal nitride.
  • adoption of the metal gate also provided advantages to an alternative so- called “gate-last” process.
  • One implementation of the gate-last process involved a so-called “replacement gate” process which allowed use of different metals for the N-FET and P-FET in the circuit.
  • BEOL back end of line
  • metal fuses became the standard fuse structures. Due to technology scaling and back-end resistance increase, however, metal fuses are proving to be difficult for maintaining the resistance differential between the fuse element and parasitic routing resistance.
  • a polycide fuse is on the same level of the program transistor and typically does not suffer from the low resistance differential issue, potentially providing an improved fuse technology.
  • embodiments described herein may be compatible with planar type devices and architectures, but may also be compatible with non-planar architectures.
  • polycide fuse structure formation methods on non-planar high-k/metal gate technologies are also described.
  • one or more embodiments described herein are directed to process integration schemes that enable polysilicon preservation in certain regions during high-k and metal gate CMOS technology fabrication.
  • the polysilicon is preserved for later fabrication of a fuse element, e.g., which is patterned during a poly patterning process.
  • Lithography processing may be performed to enable the polysilicon preservation portion of the integration scheme.
  • a poly line for ultimate application as a polycide fuse element is exposed while the other poly gate regions are covered by photoresist. Dry etch processing can subsequently be performed, during which the poly fuse element is etched and recessed.
  • a differential poly thickness between the fuse element and the surrounding standard poly gate structures is achieved in the etch and recess process.
  • a polysilicon silicidation process may be performed in order to fabricate the polycide fuse element.
  • a dummy gate and gate replacement process may then be used to fabricate high-K and metal gate based transistors in the standard gate regions.
  • contact formation may be performed to provide contact landing on the polycide fuse element.
  • Figure 1 A illustrates a cross-sectional view of a MOS-FET transistor having a metal gate/high-k material stack, in accordance with an embodiment of the present invention.
  • Figure IB illustrates a cross-sectional view of a CMOS -compatible polycide fuse structure, in accordance with an embodiment of the present invention. It is to be understood that the structures of Figures 1 A and IB may be fabricated on a common substrate and, thus, the polycide fuse structure of Figure IB is compatible with the CMOS high-k metal gate based device of Figure 1 A.
  • a MOS-FET transistor 100A is formed in and above a substrate 102, such as a bulk single crystalline substrate.
  • a gate stack includes a metal gate (MG) electrode 104 and high-k gate dielectric layer 106 disposed above the substrate 102.
  • Spacers 108 are formed on the sidewalls of the gate stack, and an inter-layer dielectric layer 110 is formed on either side of the spacers 108.
  • Source and drain regions 112 are disposed in the substrate 102, on either side of the gate stack.
  • a polycide fuse structure 100B is formed above an isolation region 103 of the substrate 102.
  • the polycide fuse structure 100B includes polysilicon "gate" material 154, which may be disposed above a dielectric layer 156.
  • a metal silicide layer 170 is disposed on the polysilicon material 154. Spacers 158 may also be included, as depicted in Figure IB.
  • Figures 2A-2I illustrate cross-sectional views representing various operations in a method of fabricating a polycide fuse structure, in accordance with an embodiment of the present invention.
  • polycrystalline silicon lines 202 are patterned above a substrate 200, such as a single crystalline silicon substrate.
  • the polycrystalline silicon lines 202 may include a hardmask (HM) 204 and/or spacers 206, as depicted in Figure 2A.
  • HM hardmask
  • an insulating layer may be disposed between the substrate 202 and the polycrystalline silicon lines 202.
  • One or more of the lines may be fabricated on an isolation region 208.
  • Such a region can be formed with deposited oxide films such as by chemical vapor deposition (CVD), high density plasma deposition (HDP), or spin on dielectrics.
  • CVD chemical vapor deposition
  • HDP high density plasma deposition
  • An anti-reflective coating layer 210 and patterned photoresist layer 212 is then formed (which may involve a resist freeze operation) on the structure of Figure 1 A, as depicted in Figure 2B.
  • a polycrystalline silicon line intended for polycide fuse formation is exposed by the patterned photoresist layer 212.
  • the anti-reflective coating layer 210 is recessed, e.g., by an etch process, to expose the polycrystalline silicon line 214 through the anti-reflective coating layer 210.
  • the hardmask layer and upper spacer portions are then removed to expose the polysilicon of the polycrystalline silicon line 214, as depicted in Figure 2D.
  • a metal deposition/anneal or metal implant/anneal process is performed on the polysilicon of the polycrystalline silicon line 214 to provide a metal silicide layer 216.
  • the resulting structure is a polycide fuse structure 218.
  • resist and anti-reflective coating layers may also be removed.
  • An inter- layer dielectric layer 220 formed in a similar method as 208 (CVD, HDP, spin on dielectrics) is then formed above the resulting structures, as depicted in Figure 2F.
  • the inter-layer dielectric layer 220 to expose hardmasks of the remaining polycrystalline silicon lines, which may ultimately be removed, as depicted in Figure 2F.
  • the polycide fuse structure 218 is protected from the exposing process since it is recessed lower than the adjacent polycrystalline silicon structures.
  • polycrystalline silicon lines are removed in a replacement gate process to provide trenches 222.
  • a high-k gate dielectric layer 224 and metal gate electrode 226 is formed in trenches 222 to form transistor structures 228, as depicted in Figure 2H.
  • contacts 230 are made to the polycide fuse structure 218, e.g., through a dielectric layer 232.
  • a material stack for a polycide fuse structure fabricated in parallel with CMOS transistor devices is composed of a lower polycrystalline silicon layer and an upper metal silicide layer formed from the reaction of, e.g., Cobalt (Co) or Nickel (Ni) with the polycrystalline silicon layer.
  • the material stack for a polycide fuse structure is not blown, and never is, leaving a polycrystalline silicon layer and upper metal silicide layer to remain.
  • the material stack for a polycide fuse structure is ultimately blown (e.g., form a current resulting from applying a voltage to the structure), leaving a mixture of silicon and metal to remain. That is, the blown fuse may not have a discernible polycrystalline silicon layer and upper metal silicide layer.
  • the polycrystalline silicon has a grain size of approximately 20 nanometers.
  • a gate dielectric layer for the CMOS transistor devices fabricated in parallel with a polycide fuse structure is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy- nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.
  • a portion of gate dielectric layer may include a layer of native oxide formed from the top few layers of the substrate.
  • the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitride.
  • a gate dielectric layer for the CMOS transistor devices fabricated in parallel with a polycide fuse structure is composed of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides.
  • the gate electrode is composed of a non- workfunction-setting fill material formed above a metal workfunction- setting layer.
  • a non-planar polycide fuse structure may be included as an embedded polycide fuse structure with a non-planar architecture.
  • reference to a non-planar polycide fuse structure is used herein to describe a polycide fuse structure having a polysilicon/silicide layer formed over one or more fins protruding from a substrate.
  • Figure 3A illustrates a top angled view and a cross-sectional view of a polycide fuse structure for a non-planar semiconductor device architecture, in accordance with an embodiment of the present invention.
  • a semiconductor structure 300 includes a substrate 302 (only partially shown) having a non-planar device 304 and a non-planar polycide fuse structure 306 formed on an isolation layer 303.
  • Non- planar device 304 includes a gate stack 308, e.g., a metal gate/high-k gate dielectric gate stack. The gate stack 308 is formed over a first plurality of fins 310.
  • Non- planar polycide fuse structure 306 includes a non-planar polysilicon layer 312, which includes a silicide layer 349 as shown in the cross-sectional view, formed over a second plurality of fins 311. Both devices include spacers 314 and contacts 316.
  • the polysilicon layer 312 and overlying silicide layer 349 are formed conformal with the plurality of fins 311.
  • a dielectric layer isolates the polysilicon layer 312 from the plurality of fins 311.
  • the first and second pluralities of fins 310 and 311 are formed from a bulk substrate 302, as depicted in Figure 3A.
  • bulk substrate 302 and, hence, the pluralities of fins 310 and 311 may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate.
  • bulk substrate 302 is composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron or a combination thereof.
  • the concentration of silicon atoms in bulk substrate 302 is greater than 97%.
  • bulk substrate 302 is composed of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a boron-doped bulk silicon mono-crystalline substrate.
  • Bulk substrate 302 may alternatively be composed of a group III-V material.
  • bulk substrate 302 is composed of a ⁇ -V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof.
  • bulk substrate 302 is composed of a III-V material and the charge-carrier dopant impurity atoms are ones such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.
  • the pluralities of fins 310 and 311 is undoped or only lightly doped. In an embodiment, at least a portion of the pluralities of fins 310 and 311 is strained.
  • the substrate 302 includes an upper epitaxial layer and a lower bulk portion, either of which may be composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon- germanium or a ⁇ -V compound semiconductor material.
  • An intervening insulator layer composed of a material which may include, but is not limited to, silicon dioxide, silicon nitride or silicon oxy-nitride may be disposed between the upper epitaxial layer and the lower bulk portion.
  • Isolation layer 303 may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, a permanent gate structure from an underlying bulk substrate.
  • the isolation dielectric layer 303 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. It is to be understood that a global layer may be formed and then recessed to ultimately expose the active portions of the pluralities of fins 310 and 311.
  • the non-planar device 304 is a non-planar device such as, but not limited to, a fin-FET or a tri-gate device.
  • a semiconducting channel region of the non-planar device 304 is composed of or is formed in a three-dimensional body.
  • the gate stack 308 surrounds at least a top surface and a pair of sidewalls of the three-dimensional body, as depicted in Figure 3A.
  • at least the channel region is made to be a discrete three-dimensional body, such as in a gate-all-around device.
  • the gate electrode stack 308 completely surrounds the channel region.
  • the semiconductor devices are identical to each other. [0035] as mentioned above, in an embodiment, the semiconductor devices
  • gate stack 308 includes a gate dielectric layer and a gate electrode layer (not shown individually).
  • the gate electrode of gate stack 308 is composed of a metal gate and the gate dielectric layer is composed of a high-K material.
  • the spacers 314 are composed of an insulative dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride or silicon nitride.
  • contacts 316 are fabricated from a metal species.
  • the metal species may be a pure metal, such as tungsten, nickel or cobalt, or may be an alloy such as a metal-metal alloy or a metal- semiconductor alloy (e.g., such as a silicide material).
  • a planar polycide fuse structure may be included with a non-planar architecture.
  • reference to a planar polycide fuse structure is used herein to describe a polycide fuse structure having a polysilicon/silicide layer formed adjacent to, but not over, one or more fins protruding from a substrate.
  • Figure 3B illustrates a cross-sectional view of a polycide fuse structure for a non-planar semiconductor device architecture, in accordance with another embodiment of the present invention.
  • a semiconductor structure 350 includes a substrate 302 (only partially shown) having a non-planar device 304 and a planar polycide fuse structure 356 formed on an isolation layer 303.
  • Non-planar device 304 includes a gate stack 108, e.g., a metal gate/high-k gate dielectric gate stack.
  • the gate stack 308 is formed over a plurality of fins 310.
  • Planar polycide fuse structure 356 includes a planar polysilicon layer 362 formed over isolation layer 303.
  • the planar polysilicon layer 362 includes an upper silicide layer (not shown). Both devices include spacers 114 and contacts 116.
  • the other features of Figure 3B may be composed of materials similar to those described for Figure 3A.
  • the plurality of fins 310 is, in one embodiment, formed from a bulk substrate 302, as depicted in Figure 3B.
  • Figures 4A-4K illustrate cross-sectional views representing various operations in a method of fabricating a polycide fuse structure for a non-planar semiconductor device architecture, in accordance with an embodiment of the present invention.
  • an isolation layer 402 is formed on a patterned bulk substrate 404 and recessed to leave a plurality of fins 406 exposed.
  • a first layer of polysilicon 408 and a silicon nitride hardmask 410 is then formed conformal with the plurality of fins 406, as depicted in Figure 4B.
  • an insulating layer may first be formed on fins 406 to ultimately insulate polysilicon layer 408 from the fin material.
  • a patterning process e.g., a lithography and etch process, of the first layer of polysilicon 408 and the silicon nitride hardmask 410 is performed to provide a polycide fuse precursor structure 412.
  • a second layer of polysilicon 414 is then formed above the polycide fuse precursor structure 412.
  • the second layer of polysilicon 414 is planarized, e.g., by a chemical mechanical polishing process, and a second hardmask layer 416 is formed thereon, as depicted in Figure 4D.
  • a patterning process e.g., a lithography and etch process, of the second layer of polysilicon 414 and the second hardmask 416 is performed to provide dummy gate structures 418, which may include spacers 420.
  • the dummy gate structure 418 may then be masked by mask 422, and hardmask 410 is removed from the polycide fuse precursor structure 412.
  • a metal deposition/anneal or metal implant/anneal process is performed on the hardmask- free polycide fuse precursor structure 412 to provide a metal silicide layer 424.
  • the resulting structure is a polycide fuse structure 413, as depicted in Figure 4F.
  • inter-layer dielectric layer 426 e.g., silicon oxide
  • the inter-layer dielectric layer 426 is planarized to expose the polysilicon of the dummy gate structure 418, but to retain polycide fuse structure 413 as un-exposed.
  • the polysilicon of the dummy gate structures 418 is then removed, but the polycide fuse structure 413 is retained, as depicted in Figure 4H.
  • permanent gate electrodes 428 e.g., metal gate electrodes (with, possibly, high-k gate dielectric layers), are formed.
  • Additional inter-layer dielectric material 450 is formed and contact openings 430 are then formed to expose both the permanent gate electrodes 428 and the polycide fuse structure 413 for electrical connection, as depicted in Figure 4 J.
  • contacts 432 are formed, e.g., by tungsten metal fill and polishing.
  • the permanent gate structures 428 may be gate structures for a tri-gate device, while the structure 413 is a polycide fuse structure.
  • the above approach may be referred to as a dual polysilicon deposition approach.
  • Figures 5A-5K illustrate cross-sectional views representing various operations in another method of fabricating a polycide fuse structure for a non-planar semiconductor device architecture, in accordance with an embodiment of the present invention.
  • an isolation layer 502 is formed on a patterned bulk substrate 504 and recessed to leave a plurality of fins 506 exposed.
  • a first layer of polysilicon 508 and a silicon nitride hardmask 510 is then formed conformal with the plurality of fins 506, as depicted in Figure 5B.
  • an insulating layer may first be formed on fins 506 to ultimately insulate polysilicon layer 508 from the fin material.
  • a patterning process e.g., a lithography and etch process, of the silicon nitride hardmask 510 is performed to provide a polycide fuse mask 511.
  • a second layer of polysilicon 514 is then formed above the polycide fuse mask 511.
  • the second layer of polysilicon 514 is planarized, e.g., by a chemical mechanical polishing process, and a second hardmask layer 516 is formed thereon, as depicted in Figure 5D.
  • a patterning process e.g., a lithography and etch process, of the first layer of polysilicon 508, the second layer of polysilicon 514, and the second hardmask 516 is performed to provide dummy gate structures 518, which may include spacers 520, and to provide polycide fuse precursor structure 512.
  • the dummy gate structure 518 may then be masked by a mask 522, and hardmask 511 is removed from the polycide fuse precursor structure 512.
  • a metal deposition/anneal or metal implant/anneal process is performed on the hardmask- free polycide fuse precursor structure 512 to provide a metal silicide layer 524.
  • the resulting structure is a polycide fuse structure 513, as depicted in Figure 5F.
  • mask 522 is removed and an inter- layer dielectric layer 526 (e.g., silicon oxide) is formed over the dummy gate structures 518 and the polycide fuse structure 513.
  • the inter-layer dielectric layer 526 is planarized to expose the polysilicon of the dummy gate structure 518, but to retain polycide fuse structure 513 as un-exposed.
  • the polysilicon of the dummy gate structures 518 is then removed, but the polycide fuse structure 513 is retained, as depicted in Figure 5H.
  • permanent gate electrodes 528 e.g., metal gate electrodes (with, possibly, high-k gate dielectric layers), are formed. Additional inter-layer dielectric material 550 is formed and contact openings 530 are then formed to expose both the permanent gate electrodes 528 and the polycide fuse structure 513 for electrical connection, as depicted in Figure 5 J.
  • contacts 532 are formed, e.g., by tungsten metal fill and polishing.
  • the permanent gate structures 528 may be gate structures for a tri-gate device, while the structure 513 is a polycide fuse structure. The above approach may be referred to as a buried hardmask stacked polysilicon polycide fuse approach.
  • Figures 6A-6L illustrate cross-sectional views representing various operations in another method of fabricating a polycide fuse structure for a non-planar semiconductor device architecture, in accordance with an embodiment of the present invention.
  • an isolation layer 602 is formed on a patterned bulk substrate 604 and recessed to leave a plurality of fins 606 exposed.
  • a layer of polysilicon 608 is then formed above the fins 606, as depicted in Figure 6B.
  • an insulating layer may first be formed on fins 606 to ultimately insulate polysilicon layer 608 from the fin material.
  • the layer of polysilicon 608 is planarized, e.g., by a chemical mechanical planarization process, and a silicon nitride hardmask 610 is then formed.
  • a patterning process e.g., a lithography and etch process, of the silicon nitride hardmask 610 and the layer of polysilicon 608 is then performed to provide dummy gate structures 618 and a polycide fuse precursor structure 612, which may include spacers 620, as depicted in Figure 6D.
  • the dummy gate structure 618 may then be masked by mask 622.
  • the exposed polycide fuse precursor structure 612 is then recessed, e.g., by an etch process.
  • the recessing 623 involves removal of the hardmask as well as a portion of the polysilicon layer to provide modified polycide fuse precursor structure 612'. Subsequently, a metal deposition/anneal or metal implant/anneal process is performed on the modified polycide fuse precursor structure 612' to provide a metal silicide layer 624. The resulting structure is a polycide fuse structure 613, as depicted in Figure 6F. Referring to Figure 6G, mask 622 is removed and an inter-layer dielectric layer 626 (e.g., silicon oxide) is formed over the dummy gate structures 618 and the polycide fuse structure 613.
  • an inter-layer dielectric layer 626 e.g., silicon oxide
  • the inter- layer dielectric layer 626 is planarized to expose the polysilicon of the dummy gate structure 618, but to retain polycide fuse structure 613 as un-exposed.
  • the polysilicon of the dummy gate structures 618 is then removed, but the polycide fuse structure 613 is retained, as depicted in Figure 6H.
  • permanent gate electrodes 628 e.g., metal gate electrodes (with, possibly, high-k gate dielectric layers)
  • Additional inter-layer dielectric material 650 is then formed, as depicted in Figure 6J.
  • contact openings 630 are then formed to expose both the permanent gate electrodes 628 and the polycide fuse structure 613 for electrical connection.
  • the permanent gate structures 628 may be gate structures for a tri-gate device, while the structure 613 may be a polycide fuse structure.
  • the above approach may be referred to as a recessed polysilicon polycide fuse approach.
  • a polycide fuse structure described herein is compatible with current and future process technologies, e.g., the polycide fuse structure structures detailed are compatible with a trigate and/or high-k/metal gate process flow where polysilicon of active devices is sacrificial and replaced with a metal gate architecture on a non- planar trigate process.
  • an exposed plurality of dummy gates may ultimately be replaced in a replacement gate process scheme.
  • dummy gate material such as polysilicon may be removed and replaced with permanent gate electrode material.
  • a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing.
  • structures reserved for polycide fuses are blocked from removal of the polysilicon which is preserved for silicide formation.
  • the plurality of dummy gates is removed by a dry etch or wet etch process.
  • the plurality of dummy gates is composed of polycrystalline silicon or amorphous silicon and is removed with a dry etch process comprising SF 6 .
  • the plurality of dummy gates is composed of polycrystalline silicon or amorphous silicon and is removed with a wet etch process comprising aqueous NH 4 OH or tetramethylammonium hydroxide.
  • the plurality of dummy gates is composed of silicon nitride and is removed with a wet etch comprising aqueous phosphoric acid.
  • one or more embodiments of the present invention may also be directed to a gate aligned contact process.
  • a process may be implemented to form contact structures for semiconductor structure fabrication, e.g., for integrated circuit fabrication.
  • a contact pattern is formed as aligned to an existing gate pattern.
  • conventional approaches typically involve an additional lithography process with tight registration of a lithographic contact pattern to an existing gate pattern in combination with selective contact etches.
  • a conventional process may include patterning of a poly (gate) grid with separately patterning of contacts and contact plugs.
  • FIG. 7 illustrates a computing device 700 in accordance with one implementation of the invention.
  • the computing device 700 houses a board 702.
  • the board 702 may include a number of components, including but not limited to a processor 704 and at least one communication chip 706.
  • the processor 704 is physically and electrically coupled to the board 702.
  • the at least one communication chip 706 is also physically and electrically coupled to the board 702.
  • the communication chip 706 is part of the processor 704.
  • computing device 700 may include other components that may or may not be physically and electrically coupled to the board 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a
  • the communication chip 706 enables wireless communications for the transfer of data to and from the computing device 700.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi- Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 700 may include a plurality of communication chips 706. For instance, a first communication chip 706 may be dedicated to shorter range wireless
  • the processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704.
  • the integrated circuit die of the processor includes one or more passive devices, such as polycide fuse structures built in accordance with implementations of the invention.
  • the term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 706 also includes an integrated circuit die packaged within the communication chip 706.
  • the integrated circuit die of the communication chip includes one or more passive devices, such as polycide fuse structures built in accordance with implementations of the invention.
  • another component housed within the computing device 700 may contain an integrated circuit die that includes one or more passive devices, such as polycide fuse structures built in accordance with implementations of the invention.
  • the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 700 may be any other electronic device that processes data.
  • embodiments of the present invention include CMOS- compatible polycide fuse structures and methods of fabricating CMOS-compatible polycide fuse structures.
  • a semiconductor structure includes a substrate.
  • a polycide fuse structure is disposed above the substrate and includes silicon and a metal.
  • a metal oxide semiconductor (MOS) transistor structure is disposed above the substrate and includes a metal gate electrode.
  • the polycide fuse structure is not programmed and is composed of a layer of metal silicide on a layer of polysilicon.
  • the polycide fuse structure is programmed and is composed of a mixture of the silicon and the metal.
  • the MOS transistor structure further includes a high-k gate dielectric layer.
  • the high-k gate dielectric layer is disposed between the metal gate electrode and the substrate, and along sidewalls of the metal gate electrode.
  • the metal of the polycide fuse structure is nickel or cobalt.
  • the substrate is a bulk single crystalline silicon substrate
  • the MOS transistor structure is disposed on the bulk single crystalline silicon substrate
  • the polycide fuse structure is disposed on an isolation region disposed in the bulk single crystalline silicon substrate.
  • a semiconductor structure includes first and second semiconductor fins disposed above a substrate.
  • a polycide fuse structure is disposed above the first semiconductor fin but not above the second semiconductor fin.
  • the polycide fuse structure includes silicon and a metal.
  • a metal oxide semiconductor (MOS) transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin.
  • the MOS transistor structure includes a metal gate electrode.
  • the polycide fuse structure is not programmed and is composed of a layer of metal silicide on a layer of polysilicon.
  • the polycide fuse structure is programmed and is composed of a mixture of the silicon and the metal.
  • the MOS transistor structure further includes a high-k gate dielectric layer.
  • the high-k gate dielectric layer is disposed between the metal gate electrode and the second semiconductor fin, and along sidewalls of the metal gate electrode.
  • the metal of the polycide fuse structure is nickel or cobalt.
  • the polycide fuse structure is disposed on an electrically insulating layer disposed on the first semiconductor fin.
  • the first semiconductor fin is of a first plurality of semiconductor fins and the second semiconductor fin is of a second plurality of semiconductor fins.
  • the polycide fuse structure is disposed above the first plurality of semiconductor fins but not above the second plurality of semiconductor fins.
  • the MOS transistor structure is formed from the second plurality of semiconductor fins but not from the first plurality of semiconductor fins.
  • the first and second pluralities of semiconductor fins are electrically coupled to an underlying bulk semiconductor substrate.
  • the polycide fuse structure is a non-planar polycide fuse structure.
  • a semiconductor structure includes first and second semiconductor fins disposed above a substrate.
  • An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins.
  • a polycide fuse structure is disposed above the isolation region but not above the first and second semiconductor fins.
  • the polycide fuse structure includes silicon and a metal.
  • First and second metal oxide semiconductor (MOS) transistor structures are formed from the first and second semiconductor fins, respectively.
  • the MOS transistor structures each include a metal gate electrode.
  • the polycide fuse structure is not programmed and is composed of a layer of metal silicide on a layer of polysilicon.
  • the polycide fuse structure is programmed and is composed of a mixture of the silicon and the metal.
  • each of the first and second the MOS transistor structures further include a high-k gate dielectric layer, and the high-k gate dielectric layer is disposed between the metal gate electrode and the respective first or second semiconductor fin, and along sidewalls of the metal gate electrode.
  • the metal of the polycide fuse structure is nickel or cobalt.
  • the first semiconductor fin is of a first plurality of semiconductor fins and the second semiconductor fin is of a second plurality of semiconductor fins.
  • the first MOS transistor structure is formed from the first plurality of semiconductor fins and the second MOS transistor structure is formed from the second plurality of semiconductor fins.
  • the first and second pluralities of semiconductor fins are electrically coupled to an underlying bulk semiconductor substrate.
  • the polycide fuse structure is a planar polycide fuse structure.
  • the polycide fuse structure has an uppermost surface at a height less than the heights of the first and second semiconductor fins.

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Abstract

CMOS-compatible polycide fuse structures and methods of fabricating CMOS-compatible polycide fuse structures are described. In an example, a semiconductor structure includes a substrate. A polycide fuse structure is disposed above the substrate and includes silicon and a metal. A metal oxide semiconductor (MOS) transistor structure is disposed above the substrate and includes a metal gate electrode.

Description

CMOS-COMPATIBLE POLYCIDE FUSE STRUCTURE AND METHOD OF
FABRICATING SAME
TECHNICAL FIELD
[0001] Embodiments of the invention are in the field of semiconductor devices and processing and, in particular, CMOS-compatible polycide fuse structures and methods of fabricating CMOS-compatible polycide fuse structures.
BACKGROUND
[0002] For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
[0003] In the manufacture of integrated circuit devices, high-k and metal gate processing has been introduced into front end of line (FEOL) processing schemes to enable further scaling. Additionally, multi-gate transistors, such as frigate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable a less complicated tri-gate fabrication process. In other instances, silicon-on- insulator substrates are preferred because of the improved short-channel behavior of tri-gate transistors.
[0004] Scaling multi-gate transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of
microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on including passive features among active devices have increased, e.g., for system-on-chip (SoC) based architectures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] Figure 1A illustrates a cross-sectional view of a MOS-FET transistor having a metal gate/high-k material stack, in accordance with an embodiment of the present invention.
[0006] Figure IB illustrates a cross-sectional view of a CMOS-compatible polycide fuse structure, in accordance with an embodiment of the present invention.
[0007] Figures 2A-2I illustrate cross-sectional views representing various operations in a method of fabricating a polycide fuse structure, in accordance with an embodiment of the present invention.
[0008] Figure 3A illustrates a top angled view and a cross-sectional view of a polycide fuse structure for a non-planar semiconductor device architecture, in accordance with an embodiment of the present invention.
[0009] Figure 3B illustrates a cross-sectional view of a polycide fuse structure for a non-planar semiconductor device architecture, in accordance with another embodiment of the present invention.
[0010] Figures 4A-4K illustrate cross-sectional views representing various operations in a method of fabricating a polycide fuse structure for a non-planar semiconductor device architecture, in accordance with an embodiment of the present invention.
[0011] Figures 5A-5K illustrate cross-sectional views representing various operations in another method of fabricating a polycide fuse structure for a non- planar semiconductor device architecture, in accordance with an embodiment of the present invention.
[0012] Figures 6A-6L illustrate cross-sectional views representing various operations in another method of fabricating a polycide fuse structure for a non- planar semiconductor device architecture, in accordance with an embodiment of the present invention. [0013] Figure 7 illustrates a computing device in accordance with one implementation of the invention.
DESCRIPTION OF THE EMBODIMENTS
[0014] CMOS -compatible polycide fuse structures and methods of fabricating CMOS-compatible polycide fuse structures are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure
embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.
[0015] One or more embodiments described herein are directed to polycide fuse structures and manufacturing methods for high-K metal gate technology.
Embodiments may include one or more of complimentary metal oxide
semiconductor (CMOS) devices, high-K gate dielectric and/or metal gate processing schemes, one time programmable (OTP) fuses, polysilicide (polycide) fuse structures and process technology, and programmable fuses.
[0016] Generally, approaches described herein involve process integration schemes that enable fabrication of a polycide fuse element and high-k/metal gate CMOS technology integration. More specifically, in an embodiment, a lithography and etch patterning process is used to recess a dummy polysilicon structure prior to replacement gate processing in order to effectively bury a polysilicon gate underneath an inter-layer dielectric oxide film. The preserved polysilicon gate is then silicided and used as a one time programmable fuse structure. Embodiments described herein may enable an alternative of fuse element architecture for future technology nodes. Furthermore, embodiments described herein provide options beyond standard metal fusing that can be directly integratable with high-k and metal gate based CMOS transistors. [0017] To provide context, gate electrodes were initially formed from metal
(e.g., aluminum). However, for many technology nodes, a Metal- Oxide- Semiconductor Field Effect Transistor (MOSFET) had included a gate electrode that was fabricated from polysilicon so as to permit ion implantation (e.g., to customize doping to N- or P-type in the same circuit) and silicidation (to reduce contact resistance). Consequently, a fuse associated with the MOSFET in a circuit was also fabricated with silicided polysilicon. A so-called "gate-first" process sequence was universally practiced so as to permit blanket deposition of the polysilicon, plasma etch-defined gate lengths, lightly-doped tip regions, dielectric sidewall spacers, and self-aligned source/drain (i.e., to the gate electrode).
[0018] As dimensions of the MOSFET continued to be scaled down in recent technology nodes, polysilicon depletion became an increasingly severe problem. As a result, gate electrodes are now being formed from metal again.
However, gate electrodes are typically no longer formed strictly from aluminum. In order to achieve desired work functions, the gate electrodes are now usually formed from a transition metal, an alloy of transition metals, or a transition metal nitride. However, adoption of the metal gate also provided advantages to an alternative so- called "gate-last" process. One implementation of the gate-last process involved a so-called "replacement gate" process which allowed use of different metals for the N-FET and P-FET in the circuit. When the material in the gate electrode was changed from polysilicon back to metal, back end of line (BEOL) metal fuses became the standard fuse structures. Due to technology scaling and back-end resistance increase, however, metal fuses are proving to be difficult for maintaining the resistance differential between the fuse element and parasitic routing resistance. On the other hand, a polycide fuse is on the same level of the program transistor and typically does not suffer from the low resistance differential issue, potentially providing an improved fuse technology.
[0019] Furthermore, embodiments described herein may be compatible with planar type devices and architectures, but may also be compatible with non-planar architectures. Thus, in accordance with one or more embodiments of the present invention, polycide fuse structure formation methods on non-planar high-k/metal gate technologies are also described. [0020] As described in greater detail below in association the Figures, one or more embodiments described herein are directed to process integration schemes that enable polysilicon preservation in certain regions during high-k and metal gate CMOS technology fabrication. The polysilicon is preserved for later fabrication of a fuse element, e.g., which is patterned during a poly patterning process. Lithography processing may be performed to enable the polysilicon preservation portion of the integration scheme. In one such embodiment, a poly line for ultimate application as a polycide fuse element is exposed while the other poly gate regions are covered by photoresist. Dry etch processing can subsequently be performed, during which the poly fuse element is etched and recessed. In one such embodiment, a differential poly thickness between the fuse element and the surrounding standard poly gate structures is achieved in the etch and recess process. Following the patterning process, a polysilicon silicidation process may be performed in order to fabricate the polycide fuse element. A dummy gate and gate replacement process may then be used to fabricate high-K and metal gate based transistors in the standard gate regions. Then, following a metal gate fill and polish process, contact formation may be performed to provide contact landing on the polycide fuse element. The above described processes are integratable with the CMOS technology, with eth addition of a poly gate recess in fuse regions of the substrate.
[0021] As an example, of a CMOS-compatible polycide fuse structure,
Figure 1 A illustrates a cross-sectional view of a MOS-FET transistor having a metal gate/high-k material stack, in accordance with an embodiment of the present invention. Figure IB illustrates a cross-sectional view of a CMOS -compatible polycide fuse structure, in accordance with an embodiment of the present invention. It is to be understood that the structures of Figures 1 A and IB may be fabricated on a common substrate and, thus, the polycide fuse structure of Figure IB is compatible with the CMOS high-k metal gate based device of Figure 1 A.
[0022] Referring to Figure 1A, a MOS-FET transistor 100A is formed in and above a substrate 102, such as a bulk single crystalline substrate. A gate stack includes a metal gate (MG) electrode 104 and high-k gate dielectric layer 106 disposed above the substrate 102. Spacers 108 are formed on the sidewalls of the gate stack, and an inter-layer dielectric layer 110 is formed on either side of the spacers 108. Source and drain regions 112 are disposed in the substrate 102, on either side of the gate stack.
[0023] Referring to Figure IB, a polycide fuse structure 100B is formed above an isolation region 103 of the substrate 102. The polycide fuse structure 100B includes polysilicon "gate" material 154, which may be disposed above a dielectric layer 156. A metal silicide layer 170 is disposed on the polysilicon material 154. Spacers 158 may also be included, as depicted in Figure IB.
[0024] Figures 2A-2I illustrate cross-sectional views representing various operations in a method of fabricating a polycide fuse structure, in accordance with an embodiment of the present invention.
[0025] Referring to Figure 2A, polycrystalline silicon lines 202 are patterned above a substrate 200, such as a single crystalline silicon substrate. The polycrystalline silicon lines 202 may include a hardmask (HM) 204 and/or spacers 206, as depicted in Figure 2A. Although not shown, an insulating layer may be disposed between the substrate 202 and the polycrystalline silicon lines 202. One or more of the lines may be fabricated on an isolation region 208. Such a region can be formed with deposited oxide films such as by chemical vapor deposition (CVD), high density plasma deposition (HDP), or spin on dielectrics. An anti-reflective coating layer 210 and patterned photoresist layer 212 is then formed (which may involve a resist freeze operation) on the structure of Figure 1 A, as depicted in Figure 2B. A polycrystalline silicon line intended for polycide fuse formation is exposed by the patterned photoresist layer 212. Referring to Figure 2C, the anti-reflective coating layer 210 is recessed, e.g., by an etch process, to expose the polycrystalline silicon line 214 through the anti-reflective coating layer 210. The hardmask layer and upper spacer portions are then removed to expose the polysilicon of the polycrystalline silicon line 214, as depicted in Figure 2D. Referring to Figure 2E, a metal deposition/anneal or metal implant/anneal process is performed on the polysilicon of the polycrystalline silicon line 214 to provide a metal silicide layer 216. The resulting structure is a polycide fuse structure 218. As is also depicted in Figure 2E, resist and anti-reflective coating layers may also be removed. An inter- layer dielectric layer 220, formed in a similar method as 208 (CVD, HDP, spin on dielectrics) is then formed above the resulting structures, as depicted in Figure 2F. The inter-layer dielectric layer 220 to expose hardmasks of the remaining polycrystalline silicon lines, which may ultimately be removed, as depicted in Figure 2F. However, the polycide fuse structure 218 is protected from the exposing process since it is recessed lower than the adjacent polycrystalline silicon structures.
Referring to Figure 2G, polycrystalline silicon lines are removed in a replacement gate process to provide trenches 222. Subsequently, a high-k gate dielectric layer 224 and metal gate electrode 226 is formed in trenches 222 to form transistor structures 228, as depicted in Figure 2H. Referring to Figure 21, contacts 230 are made to the polycide fuse structure 218, e.g., through a dielectric layer 232.
[0026] As described throughout, in an embodiment, a material stack for a polycide fuse structure fabricated in parallel with CMOS transistor devices is composed of a lower polycrystalline silicon layer and an upper metal silicide layer formed from the reaction of, e.g., Cobalt (Co) or Nickel (Ni) with the polycrystalline silicon layer. In one embodiment, the material stack for a polycide fuse structure is not blown, and never is, leaving a polycrystalline silicon layer and upper metal silicide layer to remain. In another embodiment, the material stack for a polycide fuse structure is ultimately blown (e.g., form a current resulting from applying a voltage to the structure), leaving a mixture of silicon and metal to remain. That is, the blown fuse may not have a discernible polycrystalline silicon layer and upper metal silicide layer. In an embodiment, the polycrystalline silicon has a grain size of approximately 20 nanometers.
[0027] As described throughout, in an embodiment, a gate dielectric layer for the CMOS transistor devices fabricated in parallel with a polycide fuse structure is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy- nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of gate dielectric layer may include a layer of native oxide formed from the top few layers of the substrate. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitride.
[0028] As described throughout, in an embodiment, a gate dielectric layer for the CMOS transistor devices fabricated in parallel with a polycide fuse structure is composed of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides. In a specific embodiment, the gate electrode is composed of a non- workfunction-setting fill material formed above a metal workfunction- setting layer.
[0029] In another aspect, a non-planar polycide fuse structure may be included as an embedded polycide fuse structure with a non-planar architecture. In an embodiment, reference to a non-planar polycide fuse structure is used herein to describe a polycide fuse structure having a polysilicon/silicide layer formed over one or more fins protruding from a substrate. As an example, Figure 3A illustrates a top angled view and a cross-sectional view of a polycide fuse structure for a non-planar semiconductor device architecture, in accordance with an embodiment of the present invention.
[0030] Referring to both views of Figure 3A, a semiconductor structure 300 includes a substrate 302 (only partially shown) having a non-planar device 304 and a non-planar polycide fuse structure 306 formed on an isolation layer 303. Non- planar device 304 includes a gate stack 308, e.g., a metal gate/high-k gate dielectric gate stack. The gate stack 308 is formed over a first plurality of fins 310. Non- planar polycide fuse structure 306 includes a non-planar polysilicon layer 312, which includes a silicide layer 349 as shown in the cross-sectional view, formed over a second plurality of fins 311. Both devices include spacers 314 and contacts 316. In an embodiment, the polysilicon layer 312 and overlying silicide layer 349 are formed conformal with the plurality of fins 311. In one such embodiment, a dielectric layer (not shown) isolates the polysilicon layer 312 from the plurality of fins 311.
[0031] In an embodiment, the first and second pluralities of fins 310 and 311 are formed from a bulk substrate 302, as depicted in Figure 3A. In one such example, bulk substrate 302 and, hence, the pluralities of fins 310 and 311 may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In an embodiment, bulk substrate 302 is composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron or a combination thereof. In one embodiment, the concentration of silicon atoms in bulk substrate 302 is greater than 97%. In another embodiment, bulk substrate 302 is composed of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a boron-doped bulk silicon mono-crystalline substrate. Bulk substrate 302 may alternatively be composed of a group III-V material. In an embodiment, bulk substrate 302 is composed of a ΠΙ-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, bulk substrate 302 is composed of a III-V material and the charge-carrier dopant impurity atoms are ones such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium. In an embodiment, bulk substrate 302 and, hence, the pluralities of fins 310 and 311 is undoped or only lightly doped. In an embodiment, at least a portion of the pluralities of fins 310 and 311 is strained.
[0032] Alternatively, the substrate 302 includes an upper epitaxial layer and a lower bulk portion, either of which may be composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon- germanium or a ΠΙ-V compound semiconductor material. An intervening insulator layer composed of a material which may include, but is not limited to, silicon dioxide, silicon nitride or silicon oxy-nitride may be disposed between the upper epitaxial layer and the lower bulk portion.
[0033] Isolation layer 303 may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, a permanent gate structure from an underlying bulk substrate. For example, in one embodiment, the isolation dielectric layer 303 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. It is to be understood that a global layer may be formed and then recessed to ultimately expose the active portions of the pluralities of fins 310 and 311.
[0034] In an embodiment, the non-planar device 304 is a non-planar device such as, but not limited to, a fin-FET or a tri-gate device. In such an embodiment, a semiconducting channel region of the non-planar device 304 is composed of or is formed in a three-dimensional body. In one such embodiment, the gate stack 308 surrounds at least a top surface and a pair of sidewalls of the three-dimensional body, as depicted in Figure 3A. In another embodiment, at least the channel region is made to be a discrete three-dimensional body, such as in a gate-all-around device. In one such embodiment, the gate electrode stack 308 completely surrounds the channel region.
[0035] As mentioned above, in an embodiment, the semiconductor devices
304 includes a gate stack 308 at least partially surrounding a portion of the non- planar device 304. In one such embodiment, gate stack 308 includes a gate dielectric layer and a gate electrode layer (not shown individually). In an embodiment, the gate electrode of gate stack 308 is composed of a metal gate and the gate dielectric layer is composed of a high-K material.
[0036] In an embodiment, the spacers 314 are composed of an insulative dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride or silicon nitride. In an embodiment, contacts 316 are fabricated from a metal species. The metal species may be a pure metal, such as tungsten, nickel or cobalt, or may be an alloy such as a metal-metal alloy or a metal- semiconductor alloy (e.g., such as a silicide material).
[0037] In another aspect, a planar polycide fuse structure may be included with a non-planar architecture. In an embodiment, reference to a planar polycide fuse structure is used herein to describe a polycide fuse structure having a polysilicon/silicide layer formed adjacent to, but not over, one or more fins protruding from a substrate. As an example, Figure 3B illustrates a cross-sectional view of a polycide fuse structure for a non-planar semiconductor device architecture, in accordance with another embodiment of the present invention.
[0038] Referring to Figure 3B, a semiconductor structure 350 includes a substrate 302 (only partially shown) having a non-planar device 304 and a planar polycide fuse structure 356 formed on an isolation layer 303. Non-planar device 304 includes a gate stack 108, e.g., a metal gate/high-k gate dielectric gate stack. The gate stack 308 is formed over a plurality of fins 310. Planar polycide fuse structure 356 includes a planar polysilicon layer 362 formed over isolation layer 303. The planar polysilicon layer 362 includes an upper silicide layer (not shown). Both devices include spacers 114 and contacts 116. The other features of Figure 3B may be composed of materials similar to those described for Figure 3A. For example, the plurality of fins 310 is, in one embodiment, formed from a bulk substrate 302, as depicted in Figure 3B.
[0039] In a first non-planar fabrication approach, Figures 4A-4K illustrate cross-sectional views representing various operations in a method of fabricating a polycide fuse structure for a non-planar semiconductor device architecture, in accordance with an embodiment of the present invention. Referring to Figure 4A, an isolation layer 402 is formed on a patterned bulk substrate 404 and recessed to leave a plurality of fins 406 exposed. A first layer of polysilicon 408 and a silicon nitride hardmask 410 is then formed conformal with the plurality of fins 406, as depicted in Figure 4B. Although not depicted, an insulating layer may first be formed on fins 406 to ultimately insulate polysilicon layer 408 from the fin material. Referring to Figure 4C, a patterning process, e.g., a lithography and etch process, of the first layer of polysilicon 408 and the silicon nitride hardmask 410 is performed to provide a polycide fuse precursor structure 412. A second layer of polysilicon 414 is then formed above the polycide fuse precursor structure 412. The second layer of polysilicon 414 is planarized, e.g., by a chemical mechanical polishing process, and a second hardmask layer 416 is formed thereon, as depicted in Figure 4D. Referring to Figure 4E, a patterning process, e.g., a lithography and etch process, of the second layer of polysilicon 414 and the second hardmask 416 is performed to provide dummy gate structures 418, which may include spacers 420. The dummy gate structure 418 may then be masked by mask 422, and hardmask 410 is removed from the polycide fuse precursor structure 412. Subsequently, a metal deposition/anneal or metal implant/anneal process is performed on the hardmask- free polycide fuse precursor structure 412 to provide a metal silicide layer 424. The resulting structure is a polycide fuse structure 413, as depicted in Figure 4F. Referring to Figure 4G, mask 422 is removed and an inter-layer dielectric layer 426 (e.g., silicon oxide) is formed over the dummy gate structures 418 and the polycide fuse structure 413. The inter-layer dielectric layer 426 is planarized to expose the polysilicon of the dummy gate structure 418, but to retain polycide fuse structure 413 as un-exposed. The polysilicon of the dummy gate structures 418 is then removed, but the polycide fuse structure 413 is retained, as depicted in Figure 4H. Referring to Figure 41, permanent gate electrodes 428, e.g., metal gate electrodes (with, possibly, high-k gate dielectric layers), are formed. Additional inter-layer dielectric material 450 is formed and contact openings 430 are then formed to expose both the permanent gate electrodes 428 and the polycide fuse structure 413 for electrical connection, as depicted in Figure 4 J. Referring to Figure 4K, contacts 432 are formed, e.g., by tungsten metal fill and polishing. The permanent gate structures 428 may be gate structures for a tri-gate device, while the structure 413 is a polycide fuse structure. The above approach may be referred to as a dual polysilicon deposition approach.
[0040] In a second non-planar fabrication approach, Figures 5A-5K illustrate cross-sectional views representing various operations in another method of fabricating a polycide fuse structure for a non-planar semiconductor device architecture, in accordance with an embodiment of the present invention. Referring to Figure 5A, an isolation layer 502 is formed on a patterned bulk substrate 504 and recessed to leave a plurality of fins 506 exposed. A first layer of polysilicon 508 and a silicon nitride hardmask 510 is then formed conformal with the plurality of fins 506, as depicted in Figure 5B. Although not depicted, an insulating layer may first be formed on fins 506 to ultimately insulate polysilicon layer 508 from the fin material. Referring to Figure 5C, a patterning process, e.g., a lithography and etch process, of the silicon nitride hardmask 510 is performed to provide a polycide fuse mask 511. A second layer of polysilicon 514 is then formed above the polycide fuse mask 511. The second layer of polysilicon 514 is planarized, e.g., by a chemical mechanical polishing process, and a second hardmask layer 516 is formed thereon, as depicted in Figure 5D. Referring to Figure 5E, a patterning process, e.g., a lithography and etch process, of the first layer of polysilicon 508, the second layer of polysilicon 514, and the second hardmask 516 is performed to provide dummy gate structures 518, which may include spacers 520, and to provide polycide fuse precursor structure 512. The dummy gate structure 518 may then be masked by a mask 522, and hardmask 511 is removed from the polycide fuse precursor structure 512. Subsequently, a metal deposition/anneal or metal implant/anneal process is performed on the hardmask- free polycide fuse precursor structure 512 to provide a metal silicide layer 524. The resulting structure is a polycide fuse structure 513, as depicted in Figure 5F. Referring to Figure 5G, mask 522 is removed and an inter- layer dielectric layer 526 (e.g., silicon oxide) is formed over the dummy gate structures 518 and the polycide fuse structure 513. The inter-layer dielectric layer 526 is planarized to expose the polysilicon of the dummy gate structure 518, but to retain polycide fuse structure 513 as un-exposed. The polysilicon of the dummy gate structures 518 is then removed, but the polycide fuse structure 513 is retained, as depicted in Figure 5H. Referring to Figure 51, permanent gate electrodes 528, e.g., metal gate electrodes (with, possibly, high-k gate dielectric layers), are formed. Additional inter-layer dielectric material 550 is formed and contact openings 530 are then formed to expose both the permanent gate electrodes 528 and the polycide fuse structure 513 for electrical connection, as depicted in Figure 5 J. Referring to Figure 5K, contacts 532 are formed, e.g., by tungsten metal fill and polishing. The permanent gate structures 528 may be gate structures for a tri-gate device, while the structure 513 is a polycide fuse structure. The above approach may be referred to as a buried hardmask stacked polysilicon polycide fuse approach.
[0041] In a third non-planar fabrication approach, Figures 6A-6L illustrate cross-sectional views representing various operations in another method of fabricating a polycide fuse structure for a non-planar semiconductor device architecture, in accordance with an embodiment of the present invention. Referring to Figure 6A, an isolation layer 602 is formed on a patterned bulk substrate 604 and recessed to leave a plurality of fins 606 exposed. A layer of polysilicon 608 is then formed above the fins 606, as depicted in Figure 6B. Although not depicted, an insulating layer may first be formed on fins 606 to ultimately insulate polysilicon layer 608 from the fin material. Referring to Figure 6C, the layer of polysilicon 608 is planarized, e.g., by a chemical mechanical planarization process, and a silicon nitride hardmask 610 is then formed. A patterning process, e.g., a lithography and etch process, of the silicon nitride hardmask 610 and the layer of polysilicon 608 is then performed to provide dummy gate structures 618 and a polycide fuse precursor structure 612, which may include spacers 620, as depicted in Figure 6D. Referring to Figure 6E, the dummy gate structure 618 may then be masked by mask 622. The exposed polycide fuse precursor structure 612 is then recessed, e.g., by an etch process. The recessing 623, in one embodiment, involves removal of the hardmask as well as a portion of the polysilicon layer to provide modified polycide fuse precursor structure 612'. Subsequently, a metal deposition/anneal or metal implant/anneal process is performed on the modified polycide fuse precursor structure 612' to provide a metal silicide layer 624. The resulting structure is a polycide fuse structure 613, as depicted in Figure 6F. Referring to Figure 6G, mask 622 is removed and an inter-layer dielectric layer 626 (e.g., silicon oxide) is formed over the dummy gate structures 618 and the polycide fuse structure 613. The inter- layer dielectric layer 626 is planarized to expose the polysilicon of the dummy gate structure 618, but to retain polycide fuse structure 613 as un-exposed. The polysilicon of the dummy gate structures 618 is then removed, but the polycide fuse structure 613 is retained, as depicted in Figure 6H. Referring to Figure 61, permanent gate electrodes 628, e.g., metal gate electrodes (with, possibly, high-k gate dielectric layers), are formed. Additional inter-layer dielectric material 650 is then formed, as depicted in Figure 6J. Referring to 6K, contact openings 630 are then formed to expose both the permanent gate electrodes 628 and the polycide fuse structure 613 for electrical connection. Contacts 632 are then formed, e.g., by tungsten metal fill and polishing, as depicted in Figure 6L. The permanent gate structures 628 may be gate structures for a tri-gate device, while the structure 613 may be a polycide fuse structure. The above approach may be referred to as a recessed polysilicon polycide fuse approach.
[0042] Thus, one or more embodiments of the present invention address suitable properties of a polycide fuse structure. For example, in an embodiment, a polycide fuse structure described herein is compatible with current and future process technologies, e.g., the polycide fuse structure structures detailed are compatible with a trigate and/or high-k/metal gate process flow where polysilicon of active devices is sacrificial and replaced with a metal gate architecture on a non- planar trigate process.
[0043] In the above described approaches, an exposed plurality of dummy gates may ultimately be replaced in a replacement gate process scheme. In such a scheme, dummy gate material such as polysilicon may be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing. In one embodiment, as described above, structures reserved for polycide fuses are blocked from removal of the polysilicon which is preserved for silicide formation.
[0044] In an embodiment, the plurality of dummy gates is removed by a dry etch or wet etch process. In one embodiment, the plurality of dummy gates is composed of polycrystalline silicon or amorphous silicon and is removed with a dry etch process comprising SF6. In another embodiment, the plurality of dummy gates is composed of polycrystalline silicon or amorphous silicon and is removed with a wet etch process comprising aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the plurality of dummy gates is composed of silicon nitride and is removed with a wet etch comprising aqueous phosphoric acid.
[0045] Perhaps more generally, one or more embodiments of the present invention may also be directed to a gate aligned contact process. Such a process may be implemented to form contact structures for semiconductor structure fabrication, e.g., for integrated circuit fabrication. In an embodiment, a contact pattern is formed as aligned to an existing gate pattern. By contrast, conventional approaches typically involve an additional lithography process with tight registration of a lithographic contact pattern to an existing gate pattern in combination with selective contact etches. For example, a conventional process may include patterning of a poly (gate) grid with separately patterning of contacts and contact plugs.
[0046] Figure 7 illustrates a computing device 700 in accordance with one implementation of the invention. The computing device 700 houses a board 702. The board 702 may include a number of components, including but not limited to a processor 704 and at least one communication chip 706. The processor 704 is physically and electrically coupled to the board 702. In some implementations the at least one communication chip 706 is also physically and electrically coupled to the board 702. In further implementations, the communication chip 706 is part of the processor 704.
[0047] Depending on its applications, computing device 700 may include other components that may or may not be physically and electrically coupled to the board 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
[0048] The communication chip 706 enables wireless communications for the transfer of data to and from the computing device 700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi- Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 700 may include a plurality of communication chips 706. For instance, a first communication chip 706 may be dedicated to shorter range wireless
communications such as Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. [0049] The processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704. In some implementations of the invention, the integrated circuit die of the processor includes one or more passive devices, such as polycide fuse structures built in accordance with implementations of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
[0050] The communication chip 706 also includes an integrated circuit die packaged within the communication chip 706. In accordance with another implementation of the invention, the integrated circuit die of the communication chip includes one or more passive devices, such as polycide fuse structures built in accordance with implementations of the invention.
[0051] In further implementations, another component housed within the computing device 700 may contain an integrated circuit die that includes one or more passive devices, such as polycide fuse structures built in accordance with implementations of the invention.
[0052] In various implementations, the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 700 may be any other electronic device that processes data.
[0053] Thus, embodiments of the present invention include CMOS- compatible polycide fuse structures and methods of fabricating CMOS-compatible polycide fuse structures.
[0054] In an embodiment, a semiconductor structure includes a substrate. A polycide fuse structure is disposed above the substrate and includes silicon and a metal. A metal oxide semiconductor (MOS) transistor structure is disposed above the substrate and includes a metal gate electrode. [0055] In one embodiment, the polycide fuse structure is not programmed and is composed of a layer of metal silicide on a layer of polysilicon.
[0056] In one embodiment, the polycide fuse structure is programmed and is composed of a mixture of the silicon and the metal.
[0057] In one embodiment, the MOS transistor structure further includes a high-k gate dielectric layer.
[0058] In one embodiment, the high-k gate dielectric layer is disposed between the metal gate electrode and the substrate, and along sidewalls of the metal gate electrode.
[0059] In one embodiment, the metal of the polycide fuse structure is nickel or cobalt.
[0060] In one embodiment, the substrate is a bulk single crystalline silicon substrate, the MOS transistor structure is disposed on the bulk single crystalline silicon substrate, and the polycide fuse structure is disposed on an isolation region disposed in the bulk single crystalline silicon substrate.
[0061] In an embodiment, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A polycide fuse structure is disposed above the first semiconductor fin but not above the second semiconductor fin. The polycide fuse structure includes silicon and a metal. A metal oxide semiconductor (MOS) transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. The MOS transistor structure includes a metal gate electrode.
[0062] In one embodiment, the polycide fuse structure is not programmed and is composed of a layer of metal silicide on a layer of polysilicon.
[0063] In one embodiment, the polycide fuse structure is programmed and is composed of a mixture of the silicon and the metal.
[0064] In one embodiment, the MOS transistor structure further includes a high-k gate dielectric layer.
[0065] In one embodiment, the high-k gate dielectric layer is disposed between the metal gate electrode and the second semiconductor fin, and along sidewalls of the metal gate electrode. [0066] In one embodiment, the metal of the polycide fuse structure is nickel or cobalt.
[0067] In one embodiment, the polycide fuse structure is disposed on an electrically insulating layer disposed on the first semiconductor fin.
[0068] In one embodiment, the first semiconductor fin is of a first plurality of semiconductor fins and the second semiconductor fin is of a second plurality of semiconductor fins. The polycide fuse structure is disposed above the first plurality of semiconductor fins but not above the second plurality of semiconductor fins. The MOS transistor structure is formed from the second plurality of semiconductor fins but not from the first plurality of semiconductor fins.
[0069] In one embodiment, the first and second pluralities of semiconductor fins are electrically coupled to an underlying bulk semiconductor substrate.
[0070] In one embodiment, the polycide fuse structure is a non-planar polycide fuse structure.
[0071] In an embodiment, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A polycide fuse structure is disposed above the isolation region but not above the first and second semiconductor fins. The polycide fuse structure includes silicon and a metal. First and second metal oxide semiconductor (MOS) transistor structures are formed from the first and second semiconductor fins, respectively. The MOS transistor structures each include a metal gate electrode.
[0072] In one embodiment, the polycide fuse structure is not programmed and is composed of a layer of metal silicide on a layer of polysilicon.
[0073] In one embodiment, the polycide fuse structure is programmed and is composed of a mixture of the silicon and the metal.
[0074] In one embodiment, each of the first and second the MOS transistor structures further include a high-k gate dielectric layer, and the high-k gate dielectric layer is disposed between the metal gate electrode and the respective first or second semiconductor fin, and along sidewalls of the metal gate electrode. [0075] In one embodiment, the metal of the polycide fuse structure is nickel or cobalt.
[0076] In one embodiment, the first semiconductor fin is of a first plurality of semiconductor fins and the second semiconductor fin is of a second plurality of semiconductor fins. The first MOS transistor structure is formed from the first plurality of semiconductor fins and the second MOS transistor structure is formed from the second plurality of semiconductor fins. The first and second pluralities of semiconductor fins are electrically coupled to an underlying bulk semiconductor substrate.
[0077] In one embodiment, the polycide fuse structure is a planar polycide fuse structure.
[0078] In one embodiment, the polycide fuse structure has an uppermost surface at a height less than the heights of the first and second semiconductor fins.

Claims

CLAIMS What is claimed is:
1. A semiconductor structure, comprising:
a substrate;
a polycide fuse structure disposed above the substrate and comprising silicon and a metal; and
a metal oxide semiconductor (MOS) transistor structure disposed above the substrate, the MOS transistor structure comprising a metal gate electrode.
2. The semiconductor structure of claim 1, wherein the polycide fuse structure is not programmed and comprises a layer of metal silicide on a layer of polysilicon.
3. The semiconductor structure of claim 1, wherein the polycide fuse structure is programmed and comprises a mixture of the silicon and the metal.
4. The semiconductor structure of claim 1, wherein the MOS transistor structure further comprises a high-k gate dielectric layer.
5. The semiconductor structure of claim 4, wherein the high-k gate dielectric layer is disposed between the metal gate electrode and the substrate, and along sidewalls of the metal gate electrode.
6. The semiconductor structure of claim 1, wherein the metal of the polycide fuse structure is nickel or cobalt.
7. The semiconductor structure of claim 1, wherein the substrate is a bulk single crystalline silicon substrate, the MOS transistor structure is disposed on the bulk single crystalline silicon substrate, and the polycide fuse structure is disposed on an isolation region disposed in the bulk single crystalline silicon substrate.
8. A semiconductor structure, comprising: first and second semiconductor fins disposed above a substrate;
a polycide fuse structure disposed above the first semiconductor fin but not above the second semiconductor fin, the polycide fuse structure comprising silicon and a metal; and
a metal oxide semiconductor (MOS) transistor structure formed from the second semiconductor fin but not from the first semiconductor fin, the MOS transistor structure comprising a metal gate electrode.
9. The semiconductor structure of claim 8, wherein the polycide fuse structure is not programmed and comprises a layer of metal silicide on a layer of polysilicon.
10. The semiconductor structure of claim 8, wherein the polycide fuse structure is programmed and comprises a mixture of the silicon and the metal.
11. The semiconductor structure of claim 8, wherein the MOS transistor structure further comprises a high-k gate dielectric layer.
12. The semiconductor structure of claim 11 , wherein the high-k gate dielectric layer is disposed between the metal gate electrode and the second semiconductor fin, and along sidewalls of the metal gate electrode.
13. The semiconductor structure of claim 8, wherein the metal of the polycide fuse structure is nickel or cobalt.
14. The semiconductor structure of claim 8, wherein the polycide fuse structure is disposed on an electrically insulating layer disposed on the first semiconductor fin.
15. The semiconductor structure of claim 8, wherein the first semiconductor fin is of a first plurality of semiconductor fins and the second semiconductor fin is of a second plurality of semiconductor fins, wherein the polycide fuse structure is disposed above the first plurality of semiconductor fins but not above the second plurality of semiconductor fins, and wherein the MOS transistor structure is formed from the second plurality of semiconductor fins but not from the first plurality of semiconductor fins.
16. The semiconductor structure of claim 15, wherein the first and second pluralities of semiconductor fins are electrically coupled to an underlying bulk semiconductor substrate.
17. The semiconductor structure of claim 8, wherein the polycide fuse structure is a non-planar polycide fuse structure.
18. A semiconductor structure, comprising:
first and second semiconductor fins disposed above a substrate;
an isolation region disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins;
a polycide fuse structure disposed above the isolation region but not above the first and second semiconductor fins, the polycide fuse structure comprising silicon and a metal; and
first and second metal oxide semiconductor (MOS) transistor structures formed from the first and second semiconductor fins, respectively, the MOS transistor structures each comprising a metal gate electrode.
19. The semiconductor structure of claim 18, wherein the polycide fuse structure is not programmed and comprises a layer of metal silicide on a layer of polysilicon.
20. The semiconductor structure of claim 18, wherein the polycide fuse structure is programmed and comprises a mixture of the silicon and the metal.
21. The semiconductor structure of claim 18, wherein each of the first and second the MOS transistor structures further comprises a high-k gate dielectric layer, and wherein the high-k gate dielectric layer is disposed between the metal gate electrode and the respective first or second semiconductor fin, and along sidewalls of the metal gate electrode.
22. The semiconductor structure of claim 18, wherein the metal of the polycide fuse structure is nickel or cobalt.
23. The semiconductor structure of claim 18, wherein the first semiconductor fin is of a first plurality of semiconductor fins and the second semiconductor fin is of a second plurality of semiconductor fins, wherein the first MOS transistor structure is formed from the first plurality of semiconductor fins and the second MOS transistor structure is formed from the second plurality of semiconductor fins, and wherein the first and second pluralities of semiconductor fins are electrically coupled to an underlying bulk semiconductor substrate.
24. The semiconductor structure of claim 18, wherein the polycide fuse structure is a planar polycide fuse structure.
25. The semiconductor structure of claim 18, wherein the polycide fuse structure has an uppermost surface at a height less than the heights of the first and second semiconductor fins.
PCT/US2013/047626 2013-06-25 2013-06-25 Cmos-compatible polycide fuse structure and method of fabricating same Ceased WO2014209285A1 (en)

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CN201380076882.3A CN105283961B (en) 2013-06-25 2013-06-25 The compatible polycrystalline silicon fuse-wires structure of CMOS and its manufacturing method
DE112013007051.0T DE112013007051B4 (en) 2013-06-25 2013-06-25 CMOS-compatible polycide fuse bridge structure
US14/780,222 US9881927B2 (en) 2013-06-25 2013-06-25 CMOS-compatible polycide fuse structure and method of fabricating same
KR1020157031743A KR102101763B1 (en) 2013-06-25 2013-06-25 Cmos-compatible polycide fuse structure and method of fabricating same
KR1020207008983A KR102241180B1 (en) 2013-06-25 2013-06-25 Semiconductor structure with cmos-compatible polycide fuse structure
PCT/US2013/047626 WO2014209285A1 (en) 2013-06-25 2013-06-25 Cmos-compatible polycide fuse structure and method of fabricating same
GB1520616.2A GB2529955B (en) 2013-06-25 2013-06-25 CMOS-compatible polycide fuse structure and method of fabricating same
TW103120699A TWI567940B (en) 2013-06-25 2014-06-16 CMOS compatible multi-layer germanide fuse structure and manufacturing method thereof

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