WO2014205390A1

WO2014205390A1 - Transition rate controlled bus driver circuit with reduced load sensitivity

Info

Publication number: WO2014205390A1
Application number: PCT/US2014/043481
Authority: WO
Inventors: Vinay Agarwal; Joel Martin HALBERT
Original assignee: Texas Instruments Japan Ltd; Texas Instruments Inc
Current assignee: Texas Instruments Japan Ltd; Texas Instruments Inc
Priority date: 2013-06-20
Filing date: 2014-06-20
Publication date: 2014-12-24
Anticipated expiration: 2015-12-20
Also published as: US20140380065A1; US9507409B2

Abstract

In described examples, a circuit includes a signal lead of a bus (200) and a reference terminal. A first transistor (MNO) has a first control terminal and has a first current path coupled to the reference terminal. A second transistor (MNl) has a second control terminal coupled to the first control terminal and has a second current path coupled between the signal lead and the reference terminal. A third transistor (MPO) is arranged to provide a first current through the first current path when the signal lead is in a first logic state. A fourth transistor (MP1) is arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state.

Description

TRANSITION RATE CONTROLLED BUS DRIVER

CIRCUIT WITH REDUCED LOAD SENSITIVITY

[0001] This relates in general to electronic circuitry, and in particular to a transition rate controlled bus driver circuit with reduced load capacitance sensitivity.

BACKGROUND

[0002] In wired digital communication systems with variable connection lengths and bus termination impedances, challenging design limitations are related to rise and fall time, power dissipation, and low and high output voltage levels. These limitations are further complicated by signal overshoot and inductive ringing, which may cause interference between adjacent bus leads and communication errors. Often, bus circuit drive strength is balanced to control signal rise and fall times and to establish reliable logic levels after signal transitions. Some implementations may simply employ large n-channel and p-channel drive transistors with passive filter circuits, but those implementations are effective for only a limited range of bus loading. Other implementations may employ active current sources to achieve a controlled transition rate of a bus signal, but those implementations may be limited by power constraints.

[0003] FIG. 1 is a simplified circuit diagram of a conventional bus pull down circuit. The circuit includes bus 100 and n-channel pull down transistor M_PD 104. Feedback capacitor C_PD 102 is coupled between the gate and drain of transistor M_PD. In operation, the gate of M_PD is driven high by current source 106 to pull bus lead 100 low while current source 108 is off. Alternatively, the gate of M_PD is driven low by current source 108 when bus lead 100 is to remain high while current source 106 is off. Although this circuit provides a controlled pull down rate of bus lead 100, switching time is limited by current source 106 and threshold voltage and process variation of transistor M_PD 104. SUMMARY

[0004] In described examples, a circuit includes a signal lead of a bus and a reference terminal. A first transistor has a first control terminal and has a first current path coupled to the reference terminal. A second transistor has a second control terminal coupled to the first control terminal and has a second current path coupled between the signal lead and the reference terminal. A third transistor is arranged to provide a first current through the first current path when the signal lead is in a first logic state. A fourth transistor is arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIG. 1 is a circuit diagram of a conventional bus pull down circuit.

[0006] FIG. 2 is a circuit diagram of a bus driver circuit of the example embodiments.

[0007] FIG. 3 A is a circuit diagram showing operation of the bus driver circuit of FIG. 2 when a bus lead is driven to a high logic level.

[0008] FIG. 3B is a circuit diagram showing operation of the bus driver circuit of FIG. 2 when the bus lead is driven to a low logic level.

[0009] FIG. 4 is a timing diagram showing operation of the bus driver circuit of FIG. 2.

[0010] FIG. 5A is a circuit diagram showing operation of an alternative embodiment of the bus driver circuit when the bus lead is driven to a high logic level.

[0011] FIG. 5B is a circuit diagram showing operation of the alternative embodiment of the bus driver circuit when the bus lead is driven to a low logic level.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0012] FIG. 2 shows a bus driver circuit that is useful for driving bus leads or other loads having a wide range of capacitance and inductance. The bus 200 is shown as a single signal lead for the purpose of explanation. However, many bus drive circuits and signal leads may be required on an integrated circuit to drive internal or external address, data, and control bus signals. The bus driver circuit of FIG. 2 is preferably operated by a processor 210, which generates control, address, and data signals. Control signals from processor 210 determine whether the bus driver circuit is to drive signals on bus 200 or whether another device may have control of the bus. Address and data signals determine the logic state of individual bus leads. Address and data signals transmitted on the bus driver circuit are received by remote bus receiver circuit 206, which may be a Schmidt trigger or buffer circuit enabled by receive signal RXE H or other suitable receive circuit.

[0013] Transistor sizes of FIG. 2 are shown by way of example in the format X(W/L), where W is the width of a single transistor, L is the length of the transistor, and X is the number of parallel repetitions of the single transistor. In the example of FIG. 2, transistor names beginning with MP are p-channel metal oxide semiconductor (MOS) transistors. Transistors beginning with MN are n-channel MOS transistors. However, bipolar transistors may be used instead of MOS transistors. Finally, short horizontal lines at the source of p-channel transistors represent a positive supply voltage terminal (Vdd). Correspondingly, triangles at the source of n-channel transistors represent a reference voltage, such as Vss or ground.

[0014] The bus driver circuit of FIG. 2 includes a p-channel current mirror circuit formed by transistors MPO, MPl, MP3 and MP4. These transistors are normally operated in saturation with a same gate to source voltage, so their drain currents are relatively constant and proportional to their respective widths. The common gate of the p-channel current mirror circuit is connected to the common drain terminal of transistors MP7 and MN8. Transistors MP7 and MN8 have a common gate terminal, which is coupled to receive enable signal TXE H. When enable signal TXE H is low, MP7 is on, and MN8 is off. In this state, the common gate terminal of the p-channel current mirror circuit is coupled to Vdd, and the p-channel transistors of the current mirror circuit are off. Alternatively, when enable signal TXE_H is high, MP7 is off, and MN8 is on. In this state, the common gate terminal of the p-channel current mirror circuit is coupled to Vss through current source 204. Current source 204 provides a small current of approximately 32 μΑ to achieve a bias voltage of the common gate terminal so that the p-channel transistors of the current mirror circuit operate in saturation.

[0015] The bus driver circuit of FIG. 2 also includes an n-channel current mirror circuit formed by transistors MN0 and MN1. These transistors are also operated in saturation with a same gate to source voltage, so their drain currents are relatively constant and proportional to their respective widths. The common gate of the n-channel current mirror circuit is connected to the drain terminal of transistor MN6. Transistor MN6 is coupled to receive enable signal TXE L. When enable signal TXE L is high, MN6 is on. In this state, the common gate terminal of the n-channel current mirror circuit is coupled to Vss, and the n-channel transistors of the current mirror circuit are off. Alternatively, when enable signal TXE L is low, MN6 is off. In this state, the common gate terminal of the n-channel current mirror circuit is coupled to the drain of MPO, which provides a small current to achieve a bias voltage of the common gate terminal so that the n-channel transistors of the current mirror circuit operate in saturation.

[0016] When the bus driver circuit is enabled, data signal TX H is applied to the gates of MP2 and MN3. When TX_H is high, MP2 is off, and MN3 is on. In this state, the gate and drain of MN0 are connected to the drain of MPO in a diode configuration. Accordingly, the gate on the n-channel current mirror is held at approximately an n-channel transistor threshold voltage (V™) above Vss. Alternatively, when TX H goes low to pull bus lead 200 low, MP2 is on, and MN3 is off. In this state, the gate of MNO is connected to the drain of MPO and MP1, and the drain of MNO is open. The common gate terminal of the n-channel current mirror is coupled to bus lead 200 by capacitor CpD. Data signal TX_L is also applied to the gate of MN2. When TX_L is low, MN2 is off, and the drain of MNl is open. When TX L goes high, MN2 turns on to couple bus lead 200 to the drain of MNl. The series connection of MNl and MN2 is designed to sink more current than MP4 can source. Accordingly, bus lead 200 is pulled low through MNl and MN2 when TX_L goes high.

[0017] FIG. 3A shows operation of the bus driver circuit of FIG. 2 when bus lead 200 is driven high to a first logic state. Data signals TX H and TX L are high and low, respectively, when bus lead 200 is driven high. In this state, MP2 is off, and MN3 is on. MNO is configured as an MOS diode with gate and drain connected to lead 202. MPO provides a small current of approximately 2 μΑ to keep the common gate of MNO and MNl at approximately an n-channel threshold voltage V_TN above Vss. MN2 is off, so no current flows through MNl. MP4 is on and holds bus lead 200 at Vdd. This configuration is advantageous for several reasons. First, the circuit conducts only 2 μΑ through MPO in steady state operation when bus lead 200 remains high. Second, MP4 holds bus lead 200 high without any steady state power dissipation. Third, the gate of MNl is held at approximately V_T , SO any increase in gate voltage immediately begins a high to low transition of bus lead 200 without the time required for the control gate to reach V_TN.

[0018] FIG. 3B shows operation of the bus driver circuit of FIG. 2 when bus lead 200 is driven low to a second logic state. Referring also to the timing diagram of FIG. 4, at time tl, data signals TX L and TX H go high and low, respectively. The high level of TX L turns on MN2, thereby connecting pull down transistor MNl to bus lead 200. The low level of TX H turns off MN3 and turns on MP2. In this state, the drain of MNO is open, so that MNO conducts no current. MP2 is on, and the sum of current through MPO (2 μΑ) and MP1 (28 μΑ) or I_PD (30 μΑ) is applied to lead 202. This produces a slight increase in MNl gate voltage to an equilibrium value. MNl immediately begins to conduct current from MP4 and discharge bus lead 200. From time tl to time t2, bus lead 200 discharges at a rate of - I_PD/C_PD- Accordingly, the transition rate of bus lead 200 is controlled by IpD and C_PD and is substantially linear. This is because MNl operates in saturation, and the gate of MNl remains at an equilibrium voltage, so the current I_PD through C_PD is equal to Cp_D-dV200/(t2-tl). Accordingly, -I_PD/C_pd is equal to dV200/(t2-tl). At time t2, bus lead 200 achieves an output low value and is received by bus receiver 206. Subsequently, V202 increases linearly from time t2 to time t3 as current I_PD charges C_PD. As the gate voltage of MNl reaches Vdd, bus lead 200 reaches a minimum output low value (VO_L). From time t3 to time t4, MN1 operates in the linear region to hold bus lead 200 at VO_L- At time t4, data signals TX L and TX H go low and high, respectively. The low level of TX L turns off MN2, and current through MP4 charges bus lead 200 linearly to Vdd at time t5. The high level of TX H turns MN3 on and MP2 off. MN0 is once again configured as an MOS diode and operates in saturation to discharge lead 202 linearly to V™ at time t5.

[0019] Several advantages are apparent from the foregoing discussion. First, the control gate of pull down transistor MN1 begins at V_T - Accordingly, the high to low transition of bus lead 200 begins immediately with the transition of data signals TX L and TX H. Second, all transitions of bus lead 200 are linear and are driven by a relatively constant current from either the p-channel current mirror (MP4) or the n-channel current mirror (MN1). This greatly reduces inductive ringing and overshoot during bus transitions, because the ringing is equal to a product of bus inductance and a rate of change of current with time (L_Bus'di/dt). Because transition current is approximately constant, ringing and overshoot are small. Third, the transition rate of bus lead 200 is controlled by the selection of MP0 and MP1 (I_PD) and C_PD and is, accordingly, substantially independent of load capacitance for a wide range of values. Fourth, the bus drive circuit dissipates little (if any) steady state power. Moreover, power dissipation during signal transitions occurs for only a brief time until remote bus receiver 206 receives the data on bus lead 200.

[0020] FIGS. 5A and 5B show operation of an alternative embodiment of the bus driver circuit, where p-channel transistor MP4 is divided into two p-channel transistors or current sources 500 and 502. P-channel transistor 504 is added in series with transistor 500 and is controlled by data signal TX L. As previously described, when bus lead 200 remains high, data signal TX L remains low. The low level of TX L turns off MN2 and turns on p-channel transistor 504. Accordingly, p-channel transistors 500 and 502 provide current to drive bus lead 200 from a second logic state (low) to a first logic state (high). This is equivalent to the previously described embodiment of FIG. 3 A. A low to high transition of data signal TX L (FIG. 5B) subsequently turns on MN2 and turns off p-channel transistor 504. In this state, pull down transistor MNl must sink current from only p-channel transistor 502 and discharge bus lead 200. Accordingly, power dissipation is further reduced during high to low signal transitions of bus lead 200.

[0021] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims. For example, in the circuit of FIG. 3A, the control gate of n-channel transistor MNl is biased at approximately a threshold voltage V_TN above Vss. In an alternative embodiment, the control gate of n-channel transistor MNl may be biased slightly below the threshold voltage V_TN by making the channel length of n-channel transistor MNO less than the channel length of MNl. The short channel effect of MNO provides a bias voltage slightly less than V_TN, SO that n-channel transistor MNl remains off while control signal TX H is high. In this embodiment, n-channel transistor MN2 and control signal TX L may be eliminated, and the drain of n-channel transistor MNl may be directly connected to the drain of p-channel transistor MP4. Moreover, although individual transistors are used as switching devices, transmission gates or other suitable switching devices may also be used.

Claims

CLAIMS What is claimed is:

1. A circuit, comprising:

a signal lead;

a reference terminal;

a first transistor having a first control terminal and having a first current path coupled to the reference terminal;

a second transistor having a second control terminal coupled to the first control terminal and having a second current path coupled between the signal lead and the reference terminal;

a third transistor arranged to provide a first current through the first current path when the signal lead is in a first logic state; and

a fourth transistor arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state.

2. The circuit of claim 1, wherein the first transistor is configured as a diode when the signal lead is in the first logic state.

3. The circuit of claim 1, comprising a capacitor coupled between the signal lead and the second control terminal.

4. The circuit of claim 3, wherein the third and fourth transistors supply respective currents through the capacitor during a transition of the signal lead between the first and second logic states.

5. The circuit of claim 1, wherein the third and fourth transistors are connected as current mirrors when the signal lead is in the second logic state.

6. The circuit of claim 1, comprising a fifth transistor arranged to apply a voltage to the signal lead when the signal lead is in the first logic state and to apply a current to the signal lead during a transition from the second logic state to the first logic state.

7. The circuit of claim 1, wherein the second control terminal receives a voltage less than a threshold voltage when the signal lead is in the first logic state, and wherein the second control terminal receives a voltage greater than a threshold voltage when the signal lead is in the second logic state

8. The circuit of claim 1, comprising: a fifth transistor arranged to apply a current to the signal lead during a transition between the first and second logic states; and a sixth transistor arranged to apply a current to the signal lead only in the first logic state or during a transition from the second logic state to the first logic state.

9. The circuit of claim 8, wherein the fifth and sixth transistors are connected as current mirrors during a transition from the second logic state to the first logic state.

10. A circuit, comprising:

a signal lead;

a reference terminal;

a third transistor arranged to provide a first current to the signal lead when the signal lead is in a first logic state or a second logic state; and

a fourth transistor arranged to provide a second current to the signal lead only when the signal lead is in the first logic state or during a transition from the second logic state to the first logic state.

11. The circuit of claim 10, wherein the first transistor is configured as a diode when the signal lead is in the first logic state.

12. The circuit of claim 10, comprising a capacitor coupled between the signal lead and the second control terminal.

13. The circuit of claim 10, comprising: a fifth transistor arranged to provide a third current through the first current path when the signal lead is in the first logic state; and a sixth transistor arranged to apply a voltage to the second control terminal when the signal lead is in the second logic state.

14. The circuit of claim 13, wherein the fifth and sixth transistors are connected as current mirrors when the signal lead is in the second logic state.

15. The circuit of claim 10, wherein the first current is less than the second current.

16. A computer system, comprising :

a processor arranged to generate a data signal;

a signal lead;

a reference terminal;

a third transistor arranged to provide a first current through the first current path when the data signal is in a first logic state; and

a fourth transistor arranged to apply a voltage to the second control terminal when the data signal is in a second logic state.

17. The computer system of claim 16, wherein the first transistor is configured as a diode when the data signal is in the first logic state.

18. The computer system of claim 16, comprising a capacitor coupled between the signal lead and the second control terminal.

19. The computer system of claim 18, wherein the third and fourth transistors supply respective currents through the capacitor during a transition of the data signal between the first and second logic states.

20. The computer system of claim 16, comprising: a fifth transistor arranged to apply a current to the signal lead in response to the first or second logic states of the data signal; and a sixth transistor arranged to apply a current to the signal lead only in a first logic state of the data signal or during a transition from the second logic state to the first logic state of the data signal.