WO2014193592A3 - High performance system topology for nand memory systems - Google Patents

High performance system topology for nand memory systems Download PDF

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Publication number
WO2014193592A3
WO2014193592A3 PCT/US2014/036327 US2014036327W WO2014193592A3 WO 2014193592 A3 WO2014193592 A3 WO 2014193592A3 US 2014036327 W US2014036327 W US 2014036327W WO 2014193592 A3 WO2014193592 A3 WO 2014193592A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
active
modes
data
circuit
Prior art date
Application number
PCT/US2014/036327
Other languages
French (fr)
Other versions
WO2014193592A2 (en
Inventor
Eugene Jinglun Tam
Original Assignee
Sandisk Technologies Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/904,759 external-priority patent/US9324389B2/en
Priority claimed from US13/904,770 external-priority patent/US9728526B2/en
Application filed by Sandisk Technologies Inc. filed Critical Sandisk Technologies Inc.
Priority to CN201480021399.XA priority Critical patent/CN105122227B/en
Publication of WO2014193592A2 publication Critical patent/WO2014193592A2/en
Publication of WO2014193592A3 publication Critical patent/WO2014193592A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1003—Interface circuits for daisy chain or ring bus memory arrangements

Landscapes

  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used. The pads of the memory chip can be configurable to swap input and output pads to more efficiently form the memory chips into a package.
PCT/US2014/036327 2013-05-29 2014-05-01 High performance system topology for nand memory systems WO2014193592A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201480021399.XA CN105122227B (en) 2013-05-29 2014-05-01 High performance system for nand memory system opens up benefit

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US13/904,770 2013-05-29
US13/904,759 US9324389B2 (en) 2013-05-29 2013-05-29 High performance system topology for NAND memory systems
US13/904,770 US9728526B2 (en) 2013-05-29 2013-05-29 Packaging of high performance system topology for NAND memory systems
US13/904,759 2013-05-29

Publications (2)

Publication Number Publication Date
WO2014193592A2 WO2014193592A2 (en) 2014-12-04
WO2014193592A3 true WO2014193592A3 (en) 2015-01-22

Family

ID=50842381

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2014/036327 WO2014193592A2 (en) 2013-05-29 2014-05-01 High performance system topology for nand memory systems

Country Status (2)

Country Link
CN (1) CN105122227B (en)
WO (1) WO2014193592A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018032141A (en) * 2016-08-23 2018-03-01 東芝メモリ株式会社 Semiconductor device
US10811057B1 (en) * 2019-03-26 2020-10-20 Micron Technology, Inc. Centralized placement of command and address in memory devices

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040243769A1 (en) * 2003-05-30 2004-12-02 Frame David W. Tree based memory structure
WO2006115896A2 (en) * 2005-04-21 2006-11-02 Violin Memory, Inc. Interconnection system
US20090006772A1 (en) * 2007-06-27 2009-01-01 Gerald Keith Bartley Memory Chip for High Capacity Memory Subsystem Supporting Replication of Command Data
US20090070612A1 (en) * 2005-04-21 2009-03-12 Maxim Adelman Memory power management

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0169267B1 (en) 1993-09-21 1999-02-01 사토 후미오 Nonvolatile semiconductor memory device
US5903495A (en) 1996-03-18 1999-05-11 Kabushiki Kaisha Toshiba Semiconductor device and memory system
US6891753B2 (en) * 2002-09-24 2005-05-10 Sandisk Corporation Highly compact non-volatile memory and method therefor with internal serial buses
US6940753B2 (en) * 2002-09-24 2005-09-06 Sandisk Corporation Highly compact non-volatile memory and method therefor with space-efficient data registers
CN110047528A (en) * 2005-09-30 2019-07-23 考文森智财管理公司 Multiple independent serial link memories
US7489548B2 (en) 2006-12-29 2009-02-10 Sandisk Corporation NAND flash memory cell array with adaptive memory state partitioning
US7818512B2 (en) * 2007-06-27 2010-10-19 International Business Machines Corporation High capacity memory subsystem architecture employing hierarchical tree configuration of memory modules
US7934052B2 (en) 2007-12-27 2011-04-26 Pliant Technology, Inc. System and method for performing host initiated mass storage commands using a hierarchy of data structures

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040243769A1 (en) * 2003-05-30 2004-12-02 Frame David W. Tree based memory structure
WO2006115896A2 (en) * 2005-04-21 2006-11-02 Violin Memory, Inc. Interconnection system
US20090070612A1 (en) * 2005-04-21 2009-03-12 Maxim Adelman Memory power management
US20090006772A1 (en) * 2007-06-27 2009-01-01 Gerald Keith Bartley Memory Chip for High Capacity Memory Subsystem Supporting Replication of Command Data

Also Published As

Publication number Publication date
WO2014193592A2 (en) 2014-12-04
CN105122227B (en) 2018-10-23
CN105122227A (en) 2015-12-02

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