WO2014173631A1

WO2014173631A1 - A method and a system for reducing power consumption in a processing device

Info

Publication number: WO2014173631A1
Application number: PCT/EP2014/056388
Authority: WO
Inventors: Subash G S; Vishnu SWAMINATHAN
Original assignee: Siemens Aktiengesellschaft
Priority date: 2013-04-26
Filing date: 2014-03-31
Publication date: 2014-10-30

Abstract

A method and a system (15) for determining the operational parameters for a processing device (10) for reducing the power consumption in a processing device (10) are elucidated in the present invention. The method involves the determination of the optimum operating voltage (V_DD1 215,V_DD2 225,V_DD3235) and the optimum clock frequency (f1max, f2max, f3max) for the processing device (10) based on the deadline (86,91- 93) of the work (300,310,320,330) executed by the processing device (10), and variation of the operating voltage (V_DD) and the clock frequency (f) for controlling the active state time period (84,111) and the idle state time periods (85,150) such that the power consumed by the processing device (10) is reduced.

Description

A method and a system for reducing power consumption in a processing device

The present invention relates to the field of processing devices, and particularly to a method and a system for reducing power consumption in the processing device. A processing device, such as a General Purpose Processor, a Microcontroller, an Application Specific Integrated Circuit (ASIC) , a Field Programmable Gate Array (FPGA) , a Digital Signal Processor, is widely used for a plethora of

applications. The power consumed by the processing device is of paramount importance, especially if the processing device is used for applications which mandate stringent power consumption requirements. The processing device can be powered by a battery in such applications, wherein the battery may not be easily rechargeable due to lack of charging points for recharging the battery, or due to the inaccessibility of the charging points. Such applications can include remote embedded applications such as remote

communication devices, remote sensor networks, fetal heart rate systems, satellite systems, et cetera. In the

aforementioned applications, the power available to the processing device is a premium and the available power is to be used in an optimal and ingenious manner such that the operational life of the battery is maximized thereby ensuring the operational fidelity of the system that comprises the processing device.

Every processing device operates at a certain operating voltage and a certain operating clock frequency for the execution of the one or more tasks by the processing device. This means that a fixed number of clock cycles are required for the execution of the tasks during the active state of the processing device. The processing device may drift into an idle state after the execution of the aforementioned tasks. Power is dissipated by the processor during its idle state too. Furthermore, modern processing devices are based on Complementary Metal Oxide Semiconductor Field Effect

Transistor (CMOS) technologies, wherein active state leakage currents and idle state leakage currents are involved during the active state and idle state of the processing device. The active state leakage currents and the idle state leakage currents are potential contributors to gross wastage of power .

Currently, the reduction in power consumption is achieved by using a Dynamic Voltage and Frequency Scaling based CMOS processing device for the aforementioned applications, wherein the processing device includes the provision to dynamically (i.e. in real-time) scale up and scale down both the operating voltage and the operating clock frequency for the execution of the task. In order to reduce the power consumption of the processing device, the operating voltage and the operating clock frequency of the processing device are randomly varied.

However, the aforementioned technique is not optimal and further reduction in power consumption and enhancement of the operational life of the battery is achievable by ingenious operation of the processing device.

It is an object of the present invention to propose a method and a system to further reduce the power consumed in a processing device.

The object is achieved by a method for reducing power consumption in a processing device according to claim 1 and a system thereof according to claim 9. The underlying object of the present invention is to reduce the power consumption in a processing device. This is achieved according to a method for determining the

operational parameters for reducing the power consumed in the processing device. The operational parameters comprise operating voltage and clock frequency for the processing device. The processing device is capable of operating at a maximum operating voltage and at a maximum clock frequency for executing a work in a time interval . An active state and an idle state are included in the time interval . The

processing device executes the work during the active state, and the processing device is idle during the idle state. A deadline for the work defines a time instance by which the work is to be executed by the processing device. Herein, an operating voltage and a clock frequency for the processing device is determined, such that a time instance of execution of the work by the processing device configured to operate at the determined operating voltage and at the determined clock frequency is less than the time instance of the deadline.

Furthermore, the power dissipated by the processing device configured to operate at the determined operating voltage and the determined clock frequency is less than the power

dissipated by the processing device configured to operate at the maximum operating voltage and the maximum clock

frequency. The determined operating voltage is lesser than the maximum operating voltage. The determined clock frequency is lesser than the maximum clock frequency, and greater than the lowest clock frequency permitted by the determined operating voltage for operating the processing device.

Herewith, a reduction in the power consumed by the processing device can be achieved when the processing device is

configured to operate at the determined operating voltage and the determined clock frequency.

In accordance with an embodiment of the present invention, the determined clock frequency is the highest clock frequency permitted by the determined operating voltage for operating the processing device at the determined operating voltage. Therewith, both the completion of the task prior to the deadline and a reduction in the power consumed by the

processing device are achieved. In accordance with another embodiment of the present

invention, an intermediate clock frequency for operating the processing device is determined. The intermediate frequency is such that if the processing device is configured to operate at the determined intermediate clock frequency, the time instance of execution of the work coincides with the time instance of the deadline for the work. In accordance with yet another embodiment of the present invention, for the intermediate clock frequency, the

determined operating voltage is the lowest permitted

operating voltage for operating the processing device at the intermediate clock frequency.

By determining the lowest permitted operating voltage, and by increasing the clock frequency to the highest clock frequency permitted by the lowest permitted operating voltage, a higher reduction in the power consumed by the processing device is achieved.

In accordance with yet another embodiment of the present invention, in the step of determining the operating voltage and the clock frequency, the clock frequency is determined as the highest permitted clock frequency for operating the processing device at the determined operating voltage.

This results in an even more effective power consumption since both the operating volatage and the operating frequency are optimized.

In accordance with yet another embodiment of the present invention, a number of tasks in the work to be executed in the time interval is determined and, if the work comprises a plurality of tasks, respective deadlines of the plurality of the tasks are obtained. Herewith, the determination of the operational parameters for the processing device for executing a plurality of tasks in a certain time interval is facilitated. Then, the determined intermediate clock frequency is

determined such that if the processing device is configured to operate at the intermediate clock frequency, then the time instance of execution of the work coincides with the time instance of the earliest of the deadlines. Therewith, the determined operating voltage and the determined clock

frequency correspond to a set of optimum operational

parameters for executing the plurality of tasks. Furthermore, the determined operational parameters are such that each of the tasks is completed not only prior to the respective deadline, but also at a reduced operating voltage, thereby reducing the power consumed by the processing device.

In accordance with yet another embodiment of the present invention, also a number of tasks in the work to be executed in the time interval is determined and, if the work comprises a plurality of tasks, respective slacks for the plurality of tasks are determined. Therein, a slack is the time difference between the time instance of the deadline for the task and the time instance of execution for the task.

Then, the determined intermediate clock frequency is such that if the processing device is configured to operate at the intermediate clock frequency, then the time instance of execution of the work coincides with the time instance of the task with the least slack. Therewith, the determined

operating voltage and the determined clock frequency

correspond to another set of optimum operational parameters for executing the plurality of tasks. Furthermore, the determined operational parameters are such that each of the tasks is completed not only prior to the respective deadline, but also at a reduced operating voltage, thereby reducing the power consumed by the processing device. In accordance with yet another embodiment of the present invention, the processing device is configured to operate at the determined clock frequency and the determined operating voltage for executing the work during the active state. Thus, the processing device can be readied for operating at the determined operating voltage and the determined clock

frequency for reducing the power consumed by the processing device . A system for executing the aforementioned method for reducing the power consumption in the processing device is disclosed herein. The system comprises a first module, a second module, a third module, and a fourth module. Each of the modules is operably coupled to the processing device. An operating voltage and a clock frequency of the processing device are controlled by the first module. The work executed by the processing device is managed by the second module.

Information related to the deadline of the work is received by the third module. A clock frequency for the processing device based on the information related to the deadline is determined by the fourth module. Herewith, the system

facilitates the processing device to be configured to operate at the determined operating voltage and the determined clock frequency to achieve a reduction in the power consumed by the processing device.

In accordance with an embodiment of the present invention, the fourth module is operably coupled to the first module for providing the determined clock frequency to the first module for controlling the clock frequency of the processing device. Therewith, the time required for configuring the processing device to operate at any particular operating voltage and any particular clock frequency is reduced. In accordance with another embodiment of the present

invention, at least one of the modules is located internal to the processing device. Therewith, it simplifies the

manufacturing of the processing device comprising the system, because the processing device comprising the system can now be manufactured as a single unit, such as an ASIC. Thus, a reduction in the number of components is achieved. Preferably, the system is adapted to configure the processing device to operate at the determined clock frequency and the determined operating voltage as determined by the method according to any of the above embodiments. Therewith, a reduction in the power consumed by the processing device and the system, respectively, is achieved.

The aforementioned and other embodiments of the invention related to a method and a system for reducing power

consumption in a processing device will now be addressed with reference to the accompanying drawings of the present

invention. The illustrated embodiments are intended to illustrate, but not to limit the invention. The accompanying drawings contain the following figures, in which like numbers refer to like parts, throughout the description and drawings. The figures illustrate in a schematic manner further examples of the embodiments of the invention, in which:

FIG 1 depicts an exemplary CMOS based processing device operably coupled to a system for reducing power consumption in the processing device,

FIG 2 depicts an exemplary method for reducing powe

consumption in the processing device referred in FIG 1 based on DVFS,

FIG 3 depicts a graph comprising operating voltages and the corresponding range of clock frequencies for the processing device of FIG 1,

FIG 4-6 depicts an exemplary time interval and the

variation of the operating voltage and clock frequency of the processing device referred FIG 1 based on an embodiment of the method referred to in FIG 2,

FIG 7-9 depicts another exemplary time interval and the variation of the operating voltage and clock frequency of the processing device referred to in FIG 1 based on another embodiment of the method referred to in FIG 2, and

FIG 10-11 depicts another exemplary time interval and the variation of the operating voltage and clock frequency of the processing device referred to in FIG 1 based on yet another embodiment of the method referred to in FIG 2.

An exemplary processing device 10 for elucidating the present invention is depicted in FIG 1.

For the purpose of elucidation of the present invention, the processing device 10 of FIG 1 is considered to be a CMOS based processor comprising a plurality of CMOS gates 20. The processor 10 comprises at least a first terminal 30 and a second terminal 40 whereby the processor 10 derives the power required for its operation. Herein, the first terminal 30 provides the DC operating voltage V_DD, and the second

terminal 40 is the ground terminal GND .

The processor 10 of FIG 1 is a DVFS-based processor, wherein the operating voltage V_DD and the clock frequency 'f are capable of being scaled up or scaled down in real-time by providing appropriate instructions to a first module 21. The first module 21 is operably coupled to the processor 10, and the first module 21 controls the operating voltage V_DD and the clock frequency f of the processor 10. Under normal operating conditions, the processor 10 operates at a designated operating voltage V_DD and a designated clock frequency f, which are specific to the processor 10. Herein, the operational parameters for the processor 10 comprise the operating voltage V_DD and the clock frequency f of the processor 10. The designated operating voltage V_DD and the designated clock frequency f are specified by the

manufacturer of the processor 10, and usually configured as the maximum operating voltage V_DDmax and maximum clock

frequency f_max under normal operating conditions. However, the operating voltage V_DD and the clock frequency f are

changeable in real-time based on the type of the task, power consumption constraints, et cetera, and this is achieved by appropriate instructions to the first module 21 in real-time.

Herein, it may be noted that the operations of the processor 10 include the execution of work in an interval of time. The work comprises the execution of one or more tasks that are to be executed in the aforementioned interval of time. Herein, a task is to be construed as one or more instructions that are to be executed. Furthermore, it is to be construed that every work has a deadline. The processor 10 is in the active state during execution of the tasks. During the active state, the active state power consumed by the processor 10 is equal to the sum of active state switching power and the active state leakage power. The active state switching power is directly proportional to the square of the operating voltage V_DD, and the active state leakage power is directly proportional to the product of the operating voltage V_DD and the active state leakage current.

The processor 10 is in the idle state after the execution of the tasks and before the arrival of the next set of tasks. During the idle state, the idle state power consumed by the processor 10 is the idle state leakage power, which is equal to the product of the operating voltage V_DD and the idle state leakage current.

The total power consumed by the processor 10 is equal to the sum of active state power and idle state power. Whereas, the power dissipated by the processor 10 is equal to the sum of the active state leakage power and the idle state leakage power. I.e., the active state leakage power and the idle state leakage power contribute to the power wasted by the processor 10.

The focus of the present invention is on reducing the power dissipated by the processor 10, i.e. reducing the active state leakage power and the idle state leakage power of the processor 10. This is achieved by ingenious selection of operating voltages V_DD and clock frequencies f based on the one or more tasks to be executed by the processor 10.

A second module 22 is provided to manage the execution of the tasks by the processor 10. The second module 22 can be a task manager according to an exemplary aspect of the present invention. The second module 22 can queue the tasks to be executed, and the same can be realised by means of any appropriate data structure. The second module 22 is operably coupled to the processor 10, and the second module 22 can be queried by the processor 10 to fetch information concerning the aforementioned tasks.

Furthermore, it may be noted herein that each task to be executed by the processor 10 is designated with a certain deadline, wherein the deadline indicates the latest time instance at which the task is to be executed by the processor 10. Normally a third module 25 is provided to receive

information related to the deadline for the aforementioned task. The third module 25 can be a scheduling agent according to an exemplary aspect of the present invention. The third module 25 is operably coupled to the processor 10, and the third module 25 can be queried by the processor 10 to fetch information concerning the deadline for the tasks, the statuses of execution of the aforementioned tasks, et cetera. The clock frequency f of the processor 10 is used to

determine the time instance of execution t_e of the task. A fourth module 27 is provided for determining the time

instance of execution of the task. Time instance of execution t_e is determined based on the operating voltage V_DD, the operating clock frequency f of the processor, the size of the task (for example the number of instructions comprised in the task) et cetera. Herein, it may be noted that according to one aspect, the fourth module 27 can be provided with an operating voltage V_DD, the operating clock frequency f, the size of the task, et cetera as input data, and therewith the time instance of execution t_e for the task can be determined. In a further improvement, i.e. according to another aspect of the fourth module 27, the fourth module 27 can be provided with the time instance of execution t_e, operating voltage V_DD, the size of the task as inputs, et cetera as input data, and therewith an appropriate clock frequency f for the processor 10 can be determined. Thus, in one aspect the fourth module 27 can be used for the determination of the time instance of execution t_e for a task based on a certain operating clock frequency f, and according to another aspect the fourth module 27 can be used for the determination of the operating clock frequency f based on a certain time instance of

execution t_e .

It may be observed herein that the time instance of execution t_e can precede the deadline t_d depending on the clock

frequency f of the processor 10. If the time instance of execution t_e precedes the deadline t_d, then the processor 10 enters into an idle state after the execution of the task until the arrival of the next task. Thus, the processor 10 is in the active state during the execution of the task thereby resulting in power dissipation due to active state leakage power, and the processor 10 is in the idle state after the execution of the task thereby resulting in power dissipation due to idle state leakage power.

Herein, a system 15 for reducing the power consumption, in accordance with an exemplary embodiment of the present invention, comprises the aforementioned modules 21,22,25,27. All the modules 21,22,25,27 of the system 15 are located internal to the processor 10 as depicted in FIG 1. However, without loss of generality, some or all of the modules

21,22,25,27 of the system 15 can be located either internal or external to the processor 10, but the modules 21,22,25,27 of the system 15 are always operably coupled to the processor 10, i.e. the system 15 is operably coupled to the processor 10. Furthermore, the individual modules 21,22,25,27 of the system 15 can be realised either as hardware modules or as software modules or combinations thereof. According to an exemplary aspect of the present invention, the active state leakage power can be reduced by reducing the operating voltage V_DD, because the active state leakage power is directly proportional to the operating voltage V_DD .

However, the operating clock frequency f gets reduced if the operating voltage V_DD is reduced thereby leading to a longer execution time, i.e. the processor 10 is required to be active for a longer period of time for the completion of the task. On the other hand, if the operating voltage V_DD and the operating clock frequency f are increased, the processor 10 is required to be active for a shorter period of time for the completion of the task. However this results in an increased idle state for the processor 10, thereby leading to an increased idle state leakage power. Therefore, the operating voltage V_DD, the operating clock frequency f, the active period, and the idle period are to be ingeniously varied for achieving reduced power consumption in the processor 10.

The succeeding passages will focus on different techniques proposed in the present invention for reducing the power consumed in the processor 10, wherein certain ingenious DVFS techniques are proposed, which can be implemented on the processor 10 for task execution.

A flowchart of a method for reducing the power consumption in the processor 10 is depicted in FIG 2.

It is to be noted herein that the method depicted in FIG 2 for reducing the power consumed in the processor 10 of FIG 1 will be elucidated with cross-references to FIGS 3 to 11. Furthermore, the focus of the method is to determine the operational parameters (operating voltage and the clock frequency) for the processor 10 for reducing the power consumed by the processor 10.

The method for reducing the power consumption commences with step 410, wherein the processor 10 is initially configured to operate at the maximum operating voltage V_DDmax and the maximum clock frequency f_max . This can be achieved by

providing appropriate instructions to the first module 21, wherein the instructions are related to the operating voltage DDmax and the maximum clock frequency f_max . Thus, if the processor 10 is configured to work at the maximum clock frequency f_max, the third module 25 can compute and allocate the appropriate deadline t_d for the execution of any

particular task based on the clock frequency f_max .

Reference is now made to FIG 3, wherein diagrams 50 depict exemplary operating voltages V_DD 61-63, and a range of clock frequencies f 71-73 for the corresponding operating voltages V_DD 61-63 for the processor 10. The horizontal axis 70 of the lower diagram 50 denotes clock frequency f and the vertical axis 60 of the graph 50 denotes operating voltage V_DD . The diagram 50 give overviews about permitted combinations of clock frequencies f 71-73 and operating voltages V_DD 61-63 which would allow a reliable operation of the processor 10. Typically, such diagrams 50 is available for every DVFS based processor 10.

In particular, the upper diagram shows permitted clock frequencies for selected operating voltages. Correspondingly, the lower diagram shows permitted operating voltages for selected clock frequencies.

The clock frequency f corresponding to the reference sign 73 is to be construed as the maximum clock frequency f_max, and the operating voltage V_DD corresponding to the reference sign 63 is to be construed as the maximum operating voltage V_DDmax . Similarly, the clock frequency f corresponding to the

reference sign 71 is to be construed as the minimum clock frequency f_mi_n, and the operating voltage V_DD corresponding to the reference sign 61 is to be construed as the minimum operating voltage V_DDmi_n.

The diagrams 50 in FIG 3 can be interpreted such that for each of the operating voltages V_DD 61-63, a certain range of clock frequencies f 71-73 are permitted for reliably

operating the processing device 10 at the respective

operating voltage V_DDi 61-63, as indicated in the upper diagram. Correspondingly, for each of the clock frequencies f 71-73, a certain range of operating voltages V_DD 61-63 are permitted for reliably operating the processing device 10 at the respective clock frequencies f 71-73, as indicated in the lower diagram.

It is to be noted herein that there is a range of clock frequencies f for every operating voltage V_DD . Furthermore, it may be noted herein that the operating voltages V_DD and the clock frequencies f for the processor 10 are changeable only in discrete values, because the processor 10 comprises CMOS gates 20 which are digital electronic components. I.e. for any particular operating voltage V_DD, the clock frequency f can be varied only in discrete steps, and vice versa. For any particular operating voltage V_DD, there is a range of operating clock frequencies f, and if the clock frequency f is to be increased beyond the specified range, then the processor 10 is required to be configured to operate at the next higher operating voltage V_DD, which specifies the next range of operating clock frequencies f applicable for that higher operating voltage V_DD . For example, in the upper diagram, if the operating voltage V_DD is fixed at the operating voltage V_DD indicated by the reference sign 61, then the processor 10 can operate reliably at any clock frequency f that lies in the range specified between the clock frequencies f indicated by the reference signs 71 and 72. In other words, for the operating voltage V_DD 61, clock frequencies 71 and 72 are permitted. Whereas, if the operating voltage V_DD is fixed at the operating voltage V_DD indicated by the reference sign 62, then the processor 10 can operate reliably at any clock frequency f that lies in the range specified between the clock

frequencies f indicated by the reference signs 71 and 73. In other words, for the operating voltage V_DD 62, clock

frequencies 71 and 73 are permitted.

Correspondingly, as shown in the lower diagram of FIG 3, if the clock frequency f is fixed at the frequency indicated by the reference sign 71, then the processor 10 can operate reliably at any operating voltage indicated by the reference signs 61 and 62. In other words, for the clock frequency f

71, operating voltages 61 and 62 are permitted. Whereas, if the clock frequency is fixed at the frequency indicated by the reference sign 72, then the processor 10 can operate reliably at any operating voltage indicated by the reference signs 61, 62, and 63. In other words, for the clock frequency

72, operating voltages 61, 62, and 63 are permitted.

Thus, by step 410, the processor 10 is configured to operate at the maximum operating voltage V_DDmax 63 and maximum clock frequency f_max 73.

In step 420, the number of tasks to be executed by the processor 10 for any particular time interval is determined. The number of tasks to be executed in the aforementioned time interval can be one or more than one, and the number of tasks is dependent on the application wherefore the processor 10 is used. The information concerning the number of tasks can be obtained by querying the second module 22 of the processor 10.

Herein, further steps of the method will be elucidated based on the determined number of tasks to be executed by the processor 10 in any time interval. If there is only a single task to be executed in the aforementioned time interval, then according to an exemplary embodiment of the present

invention, the method steps subsequent to step 420 can comprise steps 430,440,450 and 460. However, if there are multiple tasks to be executed in the time interval, then the method steps subsequent to step 420 can comprise steps

470,480,490 and 500 according to another embodiment, or the method steps subsequent to step 420 can comprise steps

470,510,520 and 530 according to yet another embodiment of the present invention.

Furthermore, cross-reference will be made to FIGS 4 to 11 for elucidating the different method steps subsequent to step 420. The FIGS 4 to 11 depict exemplary time intervals 80,110 for depicting the execution of a single task 300 or multiple tasks 310,320,330, and different instances of time thereof, wherein the different instances of time indicate time

instances of execution t_e, time instances of deadlines t_d, et cetera. Herein the respective horizontal axes 250 of the respective FIGURES represent time t, and the respective vertical axes 270 of the respective FIGURES represent

operating voltages V_DD of the processor 10 in the respective time intervals 80,110 corresponding to different stages of task execution in accordance with the method.

Herein, a first situation is considered, wherein only a single task 300 is to be executed in an exemplary time interval 80. Reference is herein made to FIG 4, FIG 5 and FIG 6 for explaining the method steps 430, 440, 450 and 460 respectively according to the exemplary embodiment of the present invention.

Reference is now made to FIG 4, wherein the time interval 80 depicts the exemplary task 300 to be executed and the various time instances 81,82 thereof. In step 430, a deadline 86 for the completion of the task 300 is obtained. The time instance t<j 82 denotes the deadline 86. The deadline 86 for the task 300 is dependent on the

application wherefore the processor 10 is utilised. The deadline 86 for the task 300 is normally determined by the third module 25, and the deadline 86 can be obtained by the processor 10 by querying the third module 25.

Initially, the operating voltage V_DD and the clock frequency f for the processor are fixed at maximum operating voltage DDmax 63 and maximum clock frequency f_max 73 respectively. The fourth module 27 can be used to determine the time instance t_e 81 of execution of the task 300 based on the maximum operating voltage V_DDmax 63 and maximum clock frequency f_max 73. Accordingly, the time instance t_e that denotes the time instance of execution t_e 81 for the task 300 based on maximum operating voltage V_DDmax 63 and maximum clock frequency f_max 73 is determined. The exemplary deadline 86 is assigned to the task 300, and the exemplary deadline 86 corresponds to the time instance t<j 82.

It may be noted herein that the processor 10 is in the active state during a time period 84, i.e. until the time instance t_e, and the processor 10 is in the idle state during a time period 85, i.e. between the time instance t_e and the time instance t_d. Herein, the active state leakage power

dissipated by the processor 10 corresponds to time period 84, and the idle state leakage power dissipated by the processor 10 corresponds to time period 85. Since the processor 10 is configured to operate at maximum operating voltage V_DDmax 63 and maximum clock frequency f_max 73, the active state leakage power and the idle state leakage power are functions of maximum operating voltage V_DDmax 63. In step 440, a first intermediate clock frequency f_± for the processor 10 is determined such that a new time instance of execution t_ei for the task 300 coincides with the time instance t_d 82 of the deadline 86 for the task 300. This is achieved by providing the time instance t_<j 82 of the deadline 86 to the fourth module 27 for determining the first

intermediate clock frequency f_± for the processor 10.

Furthermore, an exemplary lowest operating voltage V_DDi 215 that can ensure the reliable operation of the processor 10 operating at the first intermediate clock frequency f_± is therewith determined by referring to the Voltage-Frequency graph 50 of FIG 3. The lowest such operating voltage V_DDi 215 is termed as a first operating voltage V_DDi 215.

Now that the new time instance t_ei of execution is same as the time instance t_<j 82 of deadline 86, the first

intermediate clock frequency f_± is lower than the maximum clock frequency f_max 73, because the time period of execution 87 is increased from the previous time period of execution 84. Since the first intermediate clock frequency f_± is less than the maximum clock frequency f_max 73, the processor 10 can now be operated at the first operating voltage V_DDi 215, and it can be ascertained that operating voltage V_DDi 215 is less than the maximum operating voltage V_DDmax 63.

Reference is now made to FIG 5, wherein the time interval 80 now depicts a scenario of how the task 300 being executed by the processor 10 may appear, if the processor 10 were to be configured with the first operating voltage V_DDi 215 and the first intermediate clock frequency f_± .

It may be observed that now the new time instance t_ei of execution for the task 300 coincides with the time instance td 82 of deadline 86 for the task 300. Herein, the first operating voltage V_DDi 215 is less than the maximum operating voltage V_DDmax 63, and the first intermediate clock frequency fi is less than the maximum clock frequency f_max 73.

Furthermore, the processor 10 is in the active state during a time period 87, and the completion of the time period 87 coincides with the time instance td 82 of deadline 86 of the task 300. Therefore, the processor 10 is not in the in the idle state at all, and therewith the power dissipated by the processor 10 corresponds to the active state leakage power only, i.e. the power dissipated by the processor 10 in the time period 87. Thus, if required, in accordance with an optional step 450, the processor 10 can be configured to operate at the first operating voltage V_DDi 215 and the first intermediate clock frequency f_±, such that the task 300 is executed at the time instance t_d 82 of deadline 86.

In step 460, for the first operating voltage V_DDi 215, the highest clock frequency fi_max that permits the reliable operation of the processor 10 at the first operating voltage V_DD i 215 is determined by referring to the Voltage-Frequency graph 50 of FIG 3. Herein, the highest clock frequency fi_max is also termed as a first clock frequency fi_max.

Thereafter, the processor 10 is configured to operate with the first operating voltage V_DDi 215 and the first clock frequency f_{± max}, by configuring the processor 10 with V_DDi 215 and fimax, i.e. by scaling the operating voltage V_DD and the clock frequency f accordingly. This can be achieved by providing the appropriate instructions to the first module 21, wherein the instructions correspond to V_{DD ±} 215 and fi_max.

Reference is now made to FIG 6, wherein the time interval 80 now depicts the task 300 being executed by the processor 10 configured with the first operating voltage V_{DD ±} 215 and the first clock frequency fi_max.

It may be observed that now the final new instance t_e 83 of execution for the task 300 lies between the actual time instance t_e 81 of execution and the time instance td 82 of the deadline 83 for the task 300. Herein, it may be observed that the first operating voltage V_{DD ±} 215 is less than the maximum operating voltage V_DDmax 63; and the first clock frequency fi_max is less than the maximum clock frequency f_max 73 but greater than the first intermediate clock frequency _{2 Q}

fi . Thus, the task 300 is executed before the deadline 86, and the first operating voltage V_DDi 215 of the processor 10 is also configured to be lower than the maximum operating voltage V_DDmax 63.

It may be noted herein that the processor 10 is in the active state only during the time period 88, i.e. until the time instance 83, which is greater than the time period 84 and lesser than the time period 87. Also, the first operating voltage V_{DD ±} 215 during the time period 88 is less than the maximum operating voltage V_DDmax 63. Therefore, though the time period 88 is greater than the time period 84, due to the reduced first operating voltage V_DDi 215, the active state leakage power is reduced. Furthermore, the idle state time period 89, i.e. between the time instance 83 and the time instance 82, is lesser than the idle state time period 85, i.e. the idle state is achieved earlier, thereby resulting in reduced idle state leakage power.

Therefore, it may be noted that not only is the task 300 completed prior to the time instance t_d 82 of deadline 86, but also a reduction in the power consumption is achieved. The reduction in the power consumption is achieved due to a reduced first operating voltage V_{DD ±} 215 during the active state, and also due to a reduced idle state time period 89. Thus the active state leakage power is reduced during the active state time period 88, and the idle state leakage power is also reduced during the idle state time period 89.

Therewith, overall reduction in the power consumption is achieved .

Now, a second situation is considered, wherein multiple tasks 310,320,330 are to be executed by the processor 10 according to another exemplary time interval 110. Reference is made to FIG 7, wherein three exemplary tasks 310,320,330, which are to be executed in the time interval 110, are considered for elucidation. The three tasks 310,320,330 are chronologically contiguous and consecutive. The tasks 310,320,330 have respective deadlines 91-93, and the respective deadlines 91- 93 are denoted by respective individual instances of time 134-136 for completion. Furthermore, the tasks 310,320,330 have respective time instances 131-133 of execution based on maximum operating voltage V_DDmax 63, and maximum clock

frequency f_max 73 of the processor 10. It may be noted herein that the processor 10 is in active state during the time period 111, thereby contributing to active state leakage power, and the processor 10 is in idle state during the time period 137 thereby contributing to idle state leakage power.

Herein, two different embodiments are elucidated for

achieving reduction in power consumed by the processor 10 for executing multiple tasks 310,320,330 in the time interval 110. An embodiment focuses on 'earliest of the deadlines 91- 93' based approach, and this approach will be explained with reference to method steps 470,480,490 and 500, of FIG 2 and with reference to FIG 8 and FIG 9. Another embodiment focuses on 'least of the slacks and the idle time' based approach, and this approach will be explained with reference to method steps 470,510,520 and 530, of FIG 2 and with reference to FIG 10 and FIG 11.

Herein the term "slack" is introduced to denote the time difference between a time instance denoting a deadline for a certain task and a time instance denoting a time of execution of the task. For example, slack for the task 310 will be the time difference between the time instances denoted by

reference signs 135 and 131, which is denoted by the time period 130. Slack for the task 320 will be the time

difference between the time instances denoted by reference signs 134 and 132, which is denoted by the time period 140. Similarly, slack for the task 330 will be the time difference between the time instances denoted by reference signs 136 and 133, which is denoted by the time period 150. Furthermore, the idle time for entire set of tasks 310,320,330 is the time difference between time instance denoted by 190 (beginning of next task (say 340) and time instance 133, which is the end of task 330. In this case, the least amongst the different slacks and the idle time is considered for determining the operational voltage and the clock frequency for operating the processor 10.

With reference to the 'earliest of the deadlines 91-93' approach, in step 470, the time instances 134-136 for the individual deadlines 91-93 for the completion of the

individual tasks 310,320,330 are obtained. Since the

deadlines 91-93 for the tasks 310,320,330 are normally determined by the third module 25, the time instances 134-136 for the individual deadlines 91-93 can be obtained by

querying the third module 25.

Reference is now made to FIG 7. According to an embodiment based on 'earliest of the deadlines 91-93', in a subsequent step 480, the earliest deadline 91 of the deadlines 91-93 is determined, i.e. the earliest time instance 134 of the time instances 134-136 of corresponding to the completion of the various tasks is determined 310,320,330. Furthermore, the earliest of the time instance 134 of completion is considered to be a common deadline for all the tasks 310,320,330. In a subsequent step 490, the time instance 134 of the earliest deadline 91 is provided to the fourth module 27 for

determining a second intermediate clock frequency f₂ such that the time instances 131-133 of execution of the tasks 310,320,330 coincide with the time instance 134 of the earliest deadline 91. Furthermore, the lowest operating voltage V_DD2 225, that is required to be provided to the processor 10 for reliably operating at the second

intermediate clock frequency f₂ is determined by referring to the Voltage-Frequency graph 50 of FIG 3. Herein, the minimum operating voltage V_{DD 2} 225 is termed as a second operating voltage V_DD2 225. Reference is now made to FIG 8, wherein the time interval 110 now depicts a scenario of how the multiple tasks 310,320,330 being executed by the processor may appear, if the processor 10 were to be configured with the second operating voltage V_DD2 225 and the second intermediate clock frequency f₂.

It may be observed that now the new time instances 141-143 of execution for the tasks 310,320,330 have changed, and the new time instance 143 of execution for the latest task 330 coincides with the time instance 134 of the earliest deadline 91 for the tasks 310,320,330. Herein, it may be noted that the second operating voltage V_DD2 225 is less than the maximum operating voltage V_DDmax 63 and the second intermediate clock frequency f₂ is less than the maximum clock frequency f_max 73. Furthermore, the processor 10 is in the active state during a time period 160, i.e. until the time instance 134, thereby resulting in the active state leakage power only during the time period 160, and the processor 10 is in the idle state during a time period 165, i.e. between the time instance 134 and time instance 136, thereby resulting in the idle state leakage power only during the time period 165. The completion of the time period 160 coincides with the time instance 134 of the earliest of the deadlines 91-93 of the tasks

310,320,330.

Thus, if required, the step 490 can also include configuring the processor 10 to operate at the second operating voltage V_DD2 225 and the second intermediate clock frequency f₂, such that the multiple tasks 310,320,330 are executed at the new time instances 141-143. This may be performed by providing the appropriate instructions to the first module 21, wherein the appropriate instructions may correspond to the second operating voltage V_DD2 225 and the second intermediate clock frequency f₂.

In step 500, for the second operating voltage V_DD2 225, the highest clock frequency f_2max that permits the reliable operation of the processor 10 at the second operating voltage V_DD2 225 is determined by referring to the Voltage-Frequency graph 50 of FIG 3. The highest clock frequency f_2max is termed as a second clock frequency f_2max. Thereafter, the processor 10 is configured to operate with the second operating voltage V_DD2 225 and the second clock frequency f_2max , by configuring the processor 10 with V_DD2 225 and f_2max , i.e. by scaling the operating voltage V_DD and the clock frequency f accordingly. This can be achieved by providing the appropriate

instructions to the first module 21, wherein the instructions correspond to V_DD2 225 and f_2max .

Reference is now made to FIG 9, wherein the time interval 110 now depicts the tasks 310,320,330 being executed by the processor 10 configured with the second operating voltage V_DD2 225 and the second clock frequency f_2max .

It may be observed that the new time instance 151-153 of execution for any of the tasks 310,320,330 lies between the actual time instance 131-133 of execution and the actual time instance 134-136 of the respective deadlines 91-93 for the respective tasks 310,320,330. Herein, it may be observed that the second operating voltage V_DD2 225 is less than the maximum operating voltage V_DDmax 63; and the second clock frequency f2max is less than the maximum clock frequency f_max 73 but greater than the second intermediate clock frequency f₂.

Thus, the tasks 310,320,330 are executed before the actual time instances 134-136 of the respective deadlines 91-93, and the second operating voltage V_DD2 225 of the processor is also configured to be lower than the maximum operating voltage

VDDmax 63.

It may be noted herein that the processor 10 is in the active state during the time period 170, which is greater than the time period 111 and lesser than the time period 160. However, the second operating voltage V_DD2 225 during the time period 170 is less than the maximum operating voltage V_DDm_ax 63, though the time period 170 is greater than the time period 160. Therefore, the active state leakage power is reduced. Furthermore, the idle state time period 175 is lesser than the previous idle state time period 137, i.e. a reduction in the idle state is achieved, thereby resulting in reduced idle state leakage power.

Therefore, it may be noted that not only are the tasks

310,320,330 completed prior to the individual time instances 134-136 of deadlines 91-93, but also a reduction in the power consumption is achieved. The reduction in the power

consumption is achieved due to a reduced second operating voltage V_DD2 225 during the active state, and also due to a reduced idle state time period 175. Thus the active state leakage power is reduced during the active state, and the idle state leakage power is also reduced during the idle state . Reference is now made to FIG 7. According to an embodiment based on 'least of the slacks and the idle time', in a subsequent step 510, the minimum value of the individual time periods 140,150,160 corresponding to the slack of the tasks 310,320,330 is determined. Herein, the step 510 involves the determination of the slacks for the individual slacks also.

The minimum value between the idle time and the time instance 136 of the deadline 93 of the task 330 with the least slack is considered to be a common deadline for the execution of all the tasks 310,320,330. In a subsequent step 520, the time instance 136 of the deadline 93 of the task 330 with the least slack is provided to the fourth module 27 for

determining a third intermediate clock frequency f₃ such that the time instances 131-133 of execution of the tasks coincide with the minimum value between the idle time and the time instance 136 of the deadline 93 of the task 330 with the least slack. Furthermore, the minimum operating voltage V_DD3 235, that is required to be provided to the processor 10 for reliably operating at the third intermediate clock frequency f₃ is determined. Herein, the minimum operating voltage V_DD3 235 is termed as a third operating voltage V_DD3 235.

Reference is now made to FIG 10, wherein a time interval 110 now depicts a scenario of how the tasks 310,320,330 being executed by the processor 10 may appear, if the processor 10 were to be configured with the third operating voltage V_{DD 3} 235 and the third intermediate clock frequency f₃. It may be observed that now the new time instances 162-164 of execution for the tasks 310,320,330 have changed, and the new time instance 164 of execution for the latest task 330 coincides with the minimum value between the idle time and the time instance 136 of the task 330 with the least slack, i.e. with the time instance 136 of the deadline 93. Herein, the third operating voltage V_{DD 3} 235 is less than the maximum operating voltage V_DDmax 63, and the third intermediate clock frequency f₃ is less than the maximum clock frequency f_max 73.

Furthermore, the processor 10 is in the active state during the time period 161 thereby resulting in the active state leakage power during the time period 161, and the processor is not in the idle state at all.

Thus, if required, the step 520 can also include configuring the processor 10 to operate at the third operating voltage V_{DD 3} 235 and the third intermediate clock frequency f₃, such that all the tasks 310,320,330 are executed by the time instance 136 of the deadline 93 of the latest task 330. This may be performed by providing the appropriate instructions to the first module 21, wherein the appropriate instructions may correspond to the third operating voltage V_{DD 3} 235 and the third intermediate clock frequency f₃.

In step 530, for the third operating voltage V_{DD 3} 235, the highest clock frequency f_3max that permits the reliable operation of the processor 10 at the operating voltage V_DD3

235 is determined. The highest clock frequency f_3max is termed as a third clock frequency f_3max. Thereafter, the processor 10 is configured to operate with the third operating voltage V_DD ₃ 235 and the third clock frequency f_3max by configuring the processor 10 with V_DD3 235 and f_3max, i.e. by scaling the operating voltage V_DD and the clock frequency f accordingly. This can be achieved by providing the appropriate instructions to the first module 21, wherein the instructions correspond to V_DD3 235 and f_3max.

Reference is now made to FIG 11, wherein the time interval 110 now depicts the tasks 310,320,330 being executed by the processor 10 configured with the third operating voltage V_DD3 235 and the third clock frequency f_3max.

It may be observed that the new time instance 172-174 of execution for any task 310,320,330 lies between the actual time instance 131-133 of execution and the actual time instance 134-136 of the respective deadline 91-93 for the respective task 310,320,330. Herein, it may be observed that the third operating voltage V_DD3 235 is less than the maximum operating voltage V_DDmax 63; and the third clock frequency f3max is less than the maximum clock frequency f_max 73 but greater than the third intermediate clock frequency f₃. Thus, the tasks 310,320,330 are executed before the time instances 134-136 of the respective deadlines 91-93, and the third operating voltage V_{DD 3} 235 of the processor 10 is also configured to be lower than the maximum operating voltage

VDDmax 63.

It may be noted herein that the processor 10 is in the active state during the time period 166, which is greater than the time period 111 and lesser than the time period 161. However, the third operating voltage V_DD3 235 during the time period 166 is less than the maximum operating voltage V_DDmax 63, though the time period 166 is greater than the time period 111. Therefore, the active state leakage power is reduced. Furthermore, the idle state time period 175 is lesser than the previous idle state time period 137, i.e. a reduction in the idle state is achieved, thereby resulting in reduced idle state leakage power. Therefore, it may be noted that not only are the tasks

310,320,330 completed prior to the individual time instances 134-136 of deadlines 91-93, but also a reduction in the power consumption is achieved. The reduction in the power consumption in the processor 10 is achieved due to a reduced operating voltage V_DD3 235 during the active state, and also due to a reduced idle state time period 167. Thus the active state leakage power is reduced during the active state, and the idle state leakage power is also reduced during the idle state .

Though the invention has been described herein with reference to specific embodiments, this description is not meant to be construed in a limiting sense. Various examples of the disclosed embodiments, as well as alternate embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that such modifications can be made without departing from the scope of the present invention.

Claims

Patent claims:

1. A method for determining operational parameters for a processing device (10) for reducing the power consumption in the processing device (10) during operation of the processing device (10) ,

wherein the processing device (10) is capable of operating at a maximum operating voltage V_DDmax (63) and at a maximum clock frequency f_max (73) for executing a work (300,310,320,330) in a time interval (80,110), wherein the time interval (80,110) comprises an active state (84,111) and an idle state

(85,137), wherein the processing device (10) executes the work (300,310,320,330) during the active state (84,111) and the processing device (10) is idle during the idle state (85, 137) , and

wherein a deadline (86,91-93) for the work (300,310,320,330) defines a time instance (82,134-136) by which the work

(300,310,320,330) is to be executed by the processing device (10) ,

the method comprising:

- a step of determining an operating voltage (V_DDi 215,V_DD2 225,V_DD3235) and a clock frequency (fi_max, f₂max, f3max) for the processing device (10), such that a time instance (83,151- 153,172-174) of execution of the work (300,310,320,330) by the processing device (10) configured to operate at the determined operating voltage (V_DDi 215,V_DD2225,V_DD3235) and at the determined clock frequency (fi_max, f_2max, f3max) is less than the time instance (82,134-136) of the deadline (86,91-93), and such that the power dissipated by the processing device (10) configured to operate at the determined operating voltage (V_DDi 215,V_DD2225,V_DD3235) and the determined clock frequency (fi_max, f_2max, f_3max) is less than the power dissipated by the processing device (10) configured to operate at the maximum operating voltage V_DDmax (63) and the maximum clock frequency f_max (73) ,

wherein

- the determined operating voltage (V_DDi 215,V_DD2225,V_DD3235) is lesser than the maximum operating voltage V_DDmax (63) , - the determined clock frequency (fi_max, f_2max, f3max) is lesser than the maximum clock frequency f_max (73), and

- the determined clock frequency (fi_max, f_2max, f3max) is greater than the lowest clock frequency (fi_mi_n, f_2min, f3min) permitted by the determined operating voltage (V_DDi 215,V_DD2225,V_DD3235) for operating the processing device (10) .

2. The method according to claim 1, wherein the determined clock frequency (fi_max, f_2max, f3max) is the highest clock

frequency permitted by the determined operating voltage (V_DDi 215,V_DD2225,V_DD3235) for operating the processing device (10) at the determined operating voltage (V_DDi 215, V_DD2225, V_DD3235) .

3. The method according to claim 1 or 2 , wherein the step of determining the operating voltage (V_DDi 215,V_DD2225,V_DD3235) and the clock frequency (fi_max, f_2max, f_3max) comprises:

- a step of determining an intermediate clock frequency

(fi,f₂,f₃) for operating the processing device (10), such that if the processing device (10) is configured to operate at the determined intermediate clock frequency (fi,f₂,f₃), the time instance (83,151-153,172-174) of execution of the work

(300,310,320,330) coincides with the time instance (82,134- 136) of the deadline (86,91-93) for the work

(300,310,320,330) ,

wherein the step of determining the intermediate clock frequency (fi,f₂,f₃) precedes the step of determining the operating voltage (V_DDi 215,V_DD2225,V_DD3235) and the clock frequency (fi_max, f_2max, f_3max) for the processing device (10).

4. The method according to claim 3, wherein in the step of determining the operating voltage (V_DDi 215,V_DD2225,V_DD3235) and the clock frequency (fi_max, f_2max, f_3max) , the operating voltage (V_DDi 215,V_DD2225,V_DD3235) is determined as the lowest permitted operating voltage (V_DD) for operating the

processing device (10) at the determined intermediate clock frequency ( fi , f₂ , f₃) .

5. The method according to claim 4, wherein in the step of determining the operating voltage (V_DDi 215,V_DD2225,V_DD3235) and the clock frequency (fi_max, f_2max, f3max) , the clock frequency (fimax, f2max, f3max) is determined as the highest permitted clock frequency for operating the processing device (10) at the determined operating voltage (V_DDi 215, V_DD2225, V_DD3235) .

6. The method according to claim 5, further comprising a step of determining a number of tasks in the work

(300,310,320,330) to be executed in the time interval

(80,110), wherein the step of determining the number of tasks precedes the step of determining the operating voltage (V_DDi 215,V_DD2225,V_DD3235) and the clock frequency (fi_max, f_2max, f3max) for the processing device (10) ,

wherein

- if the work (300,310,320,330) comprises a plurality of tasks, then the method further comprises a step of obtaining respective deadlines (86,91-93) of each of the plurality of the tasks, wherein each of the respective deadlines (86,91- 93) defines a time instance (82,134-136) by which the

respective task is to be executed by the processing device (10) , wherein the step of obtaining respective deadlines (86,91-93) precedes the step of determining the intermediate clock frequency (fi,f₂,f₃), and

- in the step of determining the intermediate clock frequency (fi,f₂,f₃), the determined intermediate clock frequency

(fi,f₂,f₃) is such that if the processing device (10) is configured to operate at the intermediate clock frequency (fi,f₂,f₃), then the time instance (81,131-133) of execution of the work (300,310,320,330) coincides with the time

instance (134) of the earliest of the deadlines (91) .

7. The method according to claim 5, further comprising a step of determining a number of tasks in the work

(300,310,320,330) to be executed in the time interval

wherein

- if the work (300,310,320,330) comprises a plurality of tasks, then the method further comprises a step of

determining respective slacks for the plurality of tasks, wherein each of the slacks defines the time difference between the time instance (82,134-136) of the deadline

(86,91-93) for the respective task and the time instance (81,131-133) of execution for the respective task, wherein the step of determining the respective slacks for the

plurality of tasks precedes the step of determining the intermediate clock frequency (fi,f₂, f3) , and

- in the step of determining the intermediate clock frequency (fi,f₂, f3) , the determined intermediate clock frequency

instance (93) of the task with the least slack.

8. The method according to any of the claims 5 to 7 , further comprising :

- a step of configuring the processing device (10) to operate at the determined clock frequency (fi_max, f_2max, f3max) and the determined operating voltage (V_DDi 215,V_DD2225,V_DD3235), wherein the step of configuring the processing device (10) succeeds the step of determining the intermediate clock frequency (fi,f₂,f₃), such that the processing device (10) operates at the determined clock frequency (fi_max, f_2max, f3max) and the determined operating voltage (V_DDi 215,V_DD2225,V_DD3235) for executing the work (300,310,320,330) during the active state (88, 170, 166) .

9. A system (15) for executing the method according to any of the claims 1 to 8 for reducing the power consumption in the processing device (10) ,

the system (15) comprising: - a first module (21) for controlling an operating voltage (V_DD) and a clock frequency (f) of the processing device (10) , wherein the first module (21) is operably coupled to the processing device (10) ,

- a second module (22) for managing the execution of the work by the processing device (10) , wherein the second module (22) is operably coupled to the processing device (10) ,

- a third module (25) for receiving information related to the deadline (86,91-93), wherein the third module (25) is operably coupled to the processing device (10) , and

- a fourth module (27) for determining a clock frequency (f) for the processing device (10) based on the information related to the deadline (86,91-93), wherein the fourth module (27) is operably coupled to the processing device (10) .

10. The system (15) according to claim 9, wherein the fourth module (27) is operably coupled to the first module (21) for providing the determined clock frequency (fi_max, f_2max, f3max) to the first module (21) for controlling the clock frequency (f) of the processing device (10) .

11. The system (15) according to claim 9 or claim 10, wherein at least one of the first module (21) , the second module (22), the third module (25), and the fourth module (27) is located internal to the processing device (10) .

12. A system (15) according to any of the claims 9 to 11, wherein the system is adapted to configure the processing device (10) to operate at the determined clock frequency (fimax, f₂max, f3max) and the determined operating voltage (V_DDi

215,V_DD2225,V_DD3235) as determined by the method according to any of the claims 1 to 8.

13. A Complementary Metal Oxide Semiconductor Field Effect Transistor based processor comprising the system (15)

according to any of the claims 9 to 12.

14. The Complementary Metal Oxide Semiconductor Field Effect Transistor based processor according to claim 13, wherein the operating voltage (V_DD) and the clock frequency (f) of the processor is changeable in real-time.