WO2014169388A1 - Modular multilevel dc/dc converter for hvdc networks - Google Patents

Abstract

The apparatus comprises one or more strings, each string: comprising two pairs of arms, each pair of arms being defined by an inner arm and an outer arm, series-stacked around an associated node, each arm being defined by a plurality of cascaded submodules; and in use, being connected to one of the networks such that the arms are arranged in symmetric relation about an associated midpoint, with the inner arms flanked by the outer arms. The nodes, in use, are coupled to the other of the networks, for transfer of DC power between the networks. Means for providing paths for circulating AC currents are provided along with means to achieve power balance of submodules notwithstanding the DC power transfer.

Description

MODULAR MULTILEVEL DC/DC CONVERTER FOR HVDC NETWORKS

Field of the Invention

The invention relates to the field of high- voltage DC networks. Background

For high-voltage direct current (HVDC) transmission applications, it is known to provide for bidirectional single-stage DC/DC conversion using a modular structure based on the cascaded connection of half-bridge submodules, with power balance for each submodule capacitor achieved via circulating AC currents. Full-bridge submodules are also known, as are submodules that can function as full-bridge submodules in certain situations, such as the clamp-double-submodule described in R. Marquardt, "Modular multilevel converter: An universal concept for HVDC-networks and extended DC-bus-applications," in International Power Electronics Conference, Jun. 2010, pp. 502-507, incorporated herein by reference. Throughout this document, the terms "full-bridge submodules" and "full-bridge function submodules" are used interchangeably, and should be understood to encompass conventional full-bridge submodules and submodules that have full-bridge functionality and other enhancements.

Summary of the Invention

Forming one aspect of the invention is apparatus for coupling a pair of HVDC networks to one another for power transfer. This apparatus comprises one or more strings and reactive circuit means. Each string comprises two pairs of arms. Each pair of arms is defined by an inner arm and an outer arm, series-stacked around an associated node. Each arm is defined by a plurality of cascaded submodules. Each string, in use, is connected to one of the networks such that the arms are arranged in symmetric relation about an associated midpoint, with the inner arms flanked by the outer arms. The nodes, in use, are coupled to the other of the networks , for transfer of DC power between the networks. The reactive circuit means is for providing paths for AC current flow such that: each arm forms part of at least one path; each outer arm forms part of a path that is coextending at least in part to a path in respect of which the adjacent inner arm forms part; reactive components are incorporated such that each arm is in a path that includes a reactive element and such that near loss-less power exchange occurs between each outer arm and the adjacent inner arm to achieve power balance of submodules notwithstanding the DC power transfer.

According to another aspect of the invention, a choke can be provided in each arm.

According to another aspect of the invention, the apparatus can further comprise a capacitor and inductor, connected in series to one another and connected in parallel with the outer or inner arms, to define a low pass filter to ensure that the differential DC output voltage remains at a near constant potential. According to another aspect, the inductor can be a coupled inductor.

According to another aspect of the invention, the one or more strings can consist of one string and the reactive circuit means comprises a capacitor for each pair of arms and connected in parallel therewith.

According to another aspect of the invention, the one or more strings can consist of two or more strings and the reactive circuit means in respect of one of the two or more strings can includes another of the two or more strings.

According to another aspect of the invention, the reactive circuit means can be defined in part by a reactive structure linking the string midpoints together.

According to another aspect of the invention, the reactive structure linking the string midpoints together can be an inductive reactive structure.

According to another aspect of the invention, the reactive circuit means can include an inductor in each arm. According to another aspect of the invention, the apparatus can further comprise, for each of one or more of the strings, additional arms deployed in parallel relation to the arms of said each string.

According to another aspect of the invention, full-bridge function submodules can define the cascaded submodules in respect of a plural portion of the cascaded submodules in the outer arms and the apparatus can be capable of both step-up and step-down operation.

According to another aspect of the invention, the apparatus can be used to couple two HVDC networks of substantially similar voltages.

According to another aspect of the invention, the apparatus can be used to suppress fault currents, by controlling the submodules in the outer arms to impose the appropriate polarity of voltage during fault events.

According to other aspect of the invention, the cascaded submodules in respect of the outer arms can be defined by full-bridge function submodules. According to another aspect of the invention, this apparatus can be used to suppress fault currents, by controlling the full-bridge function submodules in the outer arms to impose the appropriate polarity of voltage during fault events. According to another aspect of the invention, this apparatus can be used to couple two HVDC networks of substantially similar voltages.

Forming yet another aspect of the invention is apparatus for coupling a pair of unipolar HVDC networks to one another for power transfer. This apparatus comprises one or more strings and reactive circuit means. Each string comprises a pair of arms, series-stacked around an associated node, each arm being defined by a plurality of cascaded submodules. Each string, in use, is connected to one of the networks; the other of the networks is coupled to the node of each string, for transfer of DC power between the pair of networks. The reactive circuit means is for providing paths for AC current flow such that: each arm forms part of at least one path; each outer arm forms part of a path that is coextending at least in part to a path in respect of which the adjacent inner arm forms part; reactive components are incorporated such that each arm is in a path that includes a reactive element and such that near loss-less power exchange occurs between each outer arm and the adjacent inner arm to achieve power balance of submodules notwithstanding the DC power transfer. Full-bridge function submodules define the cascaded submodules in respect of at least a plural portion of the cascaded submodules in the outer arms and the apparatus is capable of both step-up and step-down operation.

According to another aspect of the invention, this apparatus can further comprise a capacitor and inductor, connected in series to one another and connected in parallel with the outer or inner arm, to define a low pass filter to ensure that the differential DC output voltage remains at a near constant potential.

According to another aspect of the invention, in this apparatus, full-bridge function submodules can define the cascaded submodules in respect of the plurality of the cascaded submodules in the outer arms.

According to another aspect of the invention, the apparatus can be used to suppress fault currents, by controlling the submodules in the outer arms to impose the appropriate polarity of voltage during fault events.

According to another aspect of the invention, the midpoints of each string can be linked together without the interposition of a reactive structure.

According to another aspect of the invention, the one or more strings comprises two or more strings and the reactive circuit means in respect of one of the strings of a pair of the strings can include the other of the pair.

It will be evident from the foregoing, and from a review of the detailed description that follows, that the DC/DC conversion architecture embodied within the apparatus is of significant advantage, in that, inter alia, it:

• is modular and scalable

• can serve a function similar to a circuit breaker, for bidirectional interruption of DC fault currents

• is capable of both step-up and step-down voltage level conversion

• has relatively low rating and operating losses for the inductive elements linking each string

• can be used to connect bipolar HVDC networks together

• can be used to connect HVDC networks of substantially similar voltage Other advantages and features associated with the architecture will become evident upon a review of the following detailed description and the appended drawings, the latter being briefly described hereinafter.

Brief Description of the Drawings

Figure 1 shows the architecture of a single-string modular multi-level DC/DC converter

(DC-MMC) according to a first exemplary embodiment of the invention;

Figure 2(a) shows the half-bridge submodule (HB/SM) switching cell configuration (variant #1) for j submodule of the architecture of Figure 1;

Figure 2(b) shows the half-bridge submodule (HB/SM) switching cell configuration (variant #2) for f submodule of the architecture of Figure 1;

Figure 2(c) shows the full-bridge submodule (FB/SM) switching cell configuration for f^h submodule of the architecture of Figure 1;

Figure 3 shows the architecture of a DC-MMC according to a second exemplary embodiment of the invention;

Figure 4 shows the architecture of a DC-MMC according to a third exemplary embodiment of the invention;

Figure 5 is a simplified model for string #1 of DC-MMC, with ideal output filtering and AC filter currents neglected;

Figure 6 is a phasor diagram of fundamental frequency AC voltages and currents for single-string

DC-MMC architecture in Figure 1, with AC output filter currents neglected, for (i) step-down operation with DC power flow from input to output and (ii) step-up operation with DC power flow from output to input; is a phasor diagram of fundamental frequency AC voltages and currents for single-string DC-MMC architecture in Figure 1, with AC output filter currents neglected, for (i) step-down operation with DC power flow from output to input and (ii) step-up operation with DC power flow from input to output; is an AC circuit diagram for the top leg of the single-string DC-MMC architecture of Figure 1; shows the architecture of an interleaved two-string DC-MMC according to a fourth exemplary embodiment of the invention; is a phasor diagram of fundamental frequency AC voltages and currents for interleaved two-string DC-MMC architecture in Figure 9, with AC output filter currents neglected, for (i) step-down operation with DC power flow from input to output and (ii) step-up operation with DC power flow from output to input; is a phasor diagram of fundamental frequency AC voltages and currents for interleaved two-string DC-MMC architecture in Figure 9, with AC output filter currents neglected, for (i) step-down operation with DC power flow from output to input and (ii) step-up operation with DC power flow from input to output; is a phasor diagram of fundamental frequency AC voltages and currents imposing unity power factor operation on outer arms of interleaved two-string DC-MMC architecture in Figure 9, with AC output filter currents neglected, for (i) step-down operation with DC power flow from input to output and (ii) step-up operation with DC power flow from output to input; is a phasor diagram of fundamental frequency AC voltages and currents imposing unity power factor operation on outer arms of interleaved two-string DC-MMC architecture in Figure 9, with AC output filter currents neglected, for (i) step-down operation with DC power flow from output to input and (ii) step-up operation with DC power flow from input to output; shows the architecture of an interleaved three-string DC-MMC according to a fifth exemplary embodiment of the invention; shows the interconnection of two different bipolar HVDC networks using two-string DC-MMC architecture in Figure 9, showing a sixth exemplary embodiment of the invention; shows interleaved two-string DC-MMC architecture in Figure 9 with two cascaded sets of SMs connected in parallel for each inner arm, showing a seventh exemplary embodiment of the invention; shows steady-state voltage and current waveforms for two-string bidirectional DC-MMC architecture in Figure 9 with D=0.6 (step-down) and power flow from input to output: (a) DC input and output voltages, (b) DC input and output currents, (c) filter inductor currents and (d) filter capacitor currents; shows steady-state voltage and current waveforms for two-string bidirectional DC-MMC architecture in Figure 9 with D=0.6 (step-down) and power flow from input to output: (a) arm voltages for string no. 1 (b) arm voltages for string no. 2 (c) arm currents for string no. 1 and (d) arm currents for string no. 2; shows steady-state voltage and current waveforms for two-string bidirectional DC-MMC architecture in Figure 9 with D=0.9 (step-down) and power flow from output to input: (a) DC input and output voltages, (b) DC input and output currents, (c) filter inductor currents and (d) filter capacitor currents; shows steady-state voltage and current waveforms for two-string bidirectional DC-MMC architecture in Figure 9 with D=0.9 (step-down) and power flow from output to input: (a) arm voltages for string no. 1 (b) arm voltages for string no. 2 (c) arm currents for string no. 1 and (d) arm currents for string no. 2; shows steady-state voltage and current waveforms for two-string bidirectional DC-MMC architecture in Figure 9 with D=\ .05 (step-up) and power flow from input to output: (a) DC input and output voltages, (b) DC input and output currents, (c) filter inductor currents and (d) filter capacitor currents; shows steady-state voltage and current waveforms for two-string bidirectional DC-MMC architecture in Figure 9 with D=\ .05 (step-up) and power flow from input to output: (a) arm voltages for string no. 1 (b) arm voltages for string no. 2 (c) arm currents for string no. 1 and (d) arm currents for string no. 2; shows steady-state voltage and current waveforms for two-string bidirectional DC-MMC architecture in Figure 9 with D=\ .15 (step-up) and power flow from output to input: (a) DC input and output voltages, (b) DC input and output currents, (c) filter inductor currents and (d) filter capacitor currents; shows steady-state voltage and current waveforms for two-string bidirectional DC-MMC architecture in Figure 9 with D=\ . \5 (step-up) and power flow from output to input: (a) arm voltages for string no. 1 (b) arm voltages for string no. 2 (c) arm currents for string no. 1 and (d) arm currents for string no. 2; shows the architecture of an interleaved two-string DC-MMC according to an eighth exemplary embodiment of the invention; shows a three-string DC-MMC architecture with input and output filtering; shows a two-string DC-MMC architecture with input and output filtering; illustrates the principle of operation for two-string DC-MMC architecture: DC current (solid lines) and circulating AC current (dotted lines) paths are shown. Average AC power exchange between arms (P_ac) for SM capacitor charge balancing is indicated by the bold arrows; Figure 29 Phasor diagrams illustrating adjustment to fundamental frequency component of vi_k in Figure 35 to eliminate undesired ripple in ¾;

Figure 30 Fundamental frequency AC rms phasor diagrams that illustrate the power transfer mechanism used to achieve power balance of SM capacitors in two-string DC-MMC, with AC output filter currents neglected, valid for: (a) D < 1, i_m > 0 and D > 1, i_m < 0; (b) D < 1, i_m < 0 and /J > 1, i_m > 0;

Figure 31 Fundamental frequency AC rms phasor diagrams depicting modulation strategy to ensure power balance of SM capacitors in two-string DC-MMC while imposing unity power factor on outer arms and near unity power factor operation on inner arms, with AC output filter currents neglected, valid for: (a) D < 1, i_m > 0 and/J > 1, i_m < 0; (b) Z⁾ <1, i_m < 0 and D > \, /i„ > 0;

Figure 32 Circulating AC current control for each string (i.e. x E { 1, 2}) enabling open loop voltage control of the two-string DC-MMC;

Figure 33 shows simulation results for two-string DC-MMC in Figure 27 with D = 0.5 and i_m > 0; V

= 3.5 kV_pk, V_c = 2.2 kV, L_s = 0 mH, C_s = 0 ^F;

Figure 34 shows simulation results for two-string DC-MMC in Figure 27 with D = IA and i_m > 0; V

= 1.2 kV_pk, V_c = 2.9 kV, L_s = 0.5 mH, C_s = 40 ^F;

Figure 35 shows a single-string implementation of DC-MMCs with k = m = 1 as basis for 4 kW laboratory prototype: (a) circuit diagram (b) experimental layout;

Figure 36 shows the single-string architecture in Figure 35 operating in step-down mode with v_m =

478 V, v_out = 240 V, Ρ_ονΛ = 4.0 kW; waveforms recorded using Linux -based data acquisition software with _sampi_e = 2 _sw; Figure 37 shows the single-string architecture in Figure 35 operating in step-down mode with v_m = 478 V, v_out = 240 V, R₀ut = 4.0 kW; voltage channel gains are 140 V/div due to external sensor gain of 1.4 V/V: (a) positive pole currents (b) input and output DC quantities;

Figure 38 shows the single-string architecture in Figure 35 operating in step-up mode with v_m = 478

V, v_out = 500 V, Pout = 4.2 kW; waveforms recorded using Linux-based data acquisition software with _sample = 2/_sw;

Figure 39 shows the single-string architecture in Figure 35 operating in step-up mode with v_m = 478

V, v_out = 500 V, Out = 4.2 kW; voltage channel gains are 280 V/div due to external sensor gain of 1.4 V/V;

Figure 40 shows experimental results corresponding to Figure 37(b) where 50 Hz ripple in i_m exists prior to its elimination via proposed compensation scheme.

Detailed Description

Reference is now made to Figures 1 and 2, which show a modular multi-level DC/DC converter (DC-MMC) that has been augmented with input and output filters. The DC-MMC will be seen in Figure 1 to be bipolar and symmetric about the string midpoint ol and to utilize two series-stacked legs, each consisting of k + m cascaded submodules (SMs). Each of the cascaded sets of k and m SMs should be understood to define a respective arm. In general, the DC-MMC can employ any combination of half-bridge SMs (HB/SMs) and full-bridge SMs (FB/SMs), but as shown in Figure 1, each of the outer arms and inner arms of the string are comprised of k FB/SMs and m HB/SMs, respectively. It will be understood and seen that each outer arm is series stacked to an adjacent inner arm about an associated node, nl, pi . Arms voltages Vik, Vi_m and v'i_m,v'ik have both DC and AC components. Each arm contains a choke J_a to accommodate the switching action of the SMs. Connected in parallel with each leg is a capacitor, C_r / 2. In addition to DC biasing, an important role of these capacitors is to provide circulating AC currents. Thus, the capacitors are low impedance to the chosen AC operating frequency. The circulating currents set up by the capacitors enable relatively low loss exchange of average AC power between the arms of each leg. The input filter for each pole consists of a series inductor L_s. The arrangement of Jf and f constitute low-pass output filters. The ground reference for the single-string architecture is established by the grounded midpoint of the input and output DC networks. The ground is not directly coupled to the string midpoint ol in Figure 1 as v_ol contains an AC component. If required, a ground reference can be added at the input or output by installing two series-connected capacitors between the DC poles and grounding their midpoint, similar to the bipolar grounding scheme that is commonly adopted for voltage- sourced converter based HVDC systems.

Operation

The single-string DC-MMC architecture in Figure 1 can either step-up or step-down the input voltages v_m+ and Vin- to produce v_out+ and v_out-, respectively. The voltage conversion ratio, D, is defined as j Δ_ ' \ mt— ' ^'i nit -

"i + ^'' 'i n - (1)

The complement of the voltage conversion ratio, D' , is defined as

U - I U )

From (1) and (2) the operating modes of the DC-MMC are summarized

• Step-down operation: 0<D< \ and thus 0<D' < 1

• Step-up operation: D> \ and thus D' <0.

Step-up operation (D> \) is made possible by exploiting the additional switching state provided by the FB/SMs, i.e. v_smj ^■= -v_CJ.

For step-down operation (D< 1) where the voltage at node pi (and nl) relative to ground always remains below Vin+ (and remains above -v_m-), however, each of the FB/SMs in Figure 1 need only function as a HB/SM. The range of permissible step-up and step-down voltage conversion ratios depends primarily on the SM ratio k to m and the maximum allowable SM capacitor voltage. The single-string DC-MMC architecture can therefore generate v_out+ and v_out- within a certain range of step-up and step-down ratios, without the use of an AC transformer. Step-up capability for the DC-MMC is in practice most beneficial for values of D near unity. Designing for larger values of D, e.g. D = 1.5, is not cost effective as the input and output terminals of the DC-MMC could in this case simply be "swapped" and the voltage conversion ratio changed accordingly, e.g. D = 1/1.5. However, by designing for a small step-up range around unity, for example 0.9 < D < 1. 1, the DC-MMC can accommodate both networks fluctuating around their nominal values. This would otherwise be difficult or impossible to achieve using only HB/SMs. The DC-MMC's ability to interconnect HDVC networks of similar voltage levels is a significant operational advantage, as future HVDC grids will likely be formed in part by meshing together smaller pre-existing DC grid segments - some of which will assuredly be at similar voltage levels.

The input network sets the DC voltage across each leg, i.e. v_m+ and v_m.. These voltages, however, can be unevenly split between the arms. For example, the DC components of v^v^ can take on unequal values that sum to v_m+. The division of v_m+ (and v_in-) between the arms of the top (and bottom) leg is achieved by controlling the number and polarity of SM capacitors inserted in each arm via switching action.

To achieve single-stage DC/DC conversion the AC components of vik, vi_m and v'_lm,v'ik act to ensure charge balance of the SM capacitors. That is, the AC components of the arm voltages are synthesized such that net average power is exchanged between the arms of each leg. Circulating AC currents established by the capacitors C_r/ 2 and arm chokes J_a enable this power exchange in a near lossless manner. DC power flow can be reversed by simply changing the polarity of i_m. Bidirectional power flow is a result of employing the SMs in Figure 2, which inherently permit bidirectional current flow.

To perform voltage balancing of the SM capacitors in Figure 1, voltage balancing control schemes developed for the DC/AC modular multilevel converter (MMC) can be adapted, including but not limited to those shown in the following references, incorporated herein by reference: (1) L. Angquist, A. Antonopoulos, D. Siemaszko, K. Hves, M. Vasiladiotis, and H.-P. Nee, "Open-loop control of modular multilevel converters using estimation of stored energy," IEEE Trans. Ind. Appl., vol. 47, no. 6, pp. 2516-2524, Nov.-Dec. 2011; (2) M. Hagiwara and H. Akagi, "Control and experiment of pulsewidth-modulated modular multilevel converters," IEEE Trans. Power Electron., vol. 24, no. 7, pp. 1737-1746, Jul. 2009; (3) A. Antonopoulos, L. Angquist, and H.-P. Nee, "On dynamics and voltage control of the modular multilevel converter," in 13th European Conference on Power Electronics and Applications, Sep. 2009, pp. 1-10; and (4) S. Rohner, S. Bernet, M. Hiller, and R. Sommer, "Modulation, losses, and semiconductor requirements of modular multilevel converters," IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2633-2642, Aug. 2010.

Theory of Operation

In the following passages, the operation of the single-string bidirectional DC-MMC architecture is detailed. The analysis begins under the assumption of negligible filter currents. This assumption is subsequently relaxed and the impact of output filter currents is discussed. Unless otherwise indicated, the following assumptions are used:

• each arm has a large number of SMs such that ideal sinusoidal AC voltages are synthesized

• AC voltages and currents are represented by their steady-state fundamental frequency components

• output AC filtering is ideal, i.e. Jf and CV constitute ideal low-pass filters

DC/DC Conversion Process

The DC components of v^v^ and v'_lm,v'i_k are varied by controlling the number of SM capacitors inserted in each arm. Moreover, the use of FB/SMs in the outer arms enables negative valued DC components for vi_k and v'i_k by inverting the polarity of v_smy as needed. The single-string DC-MMC architecture can thus achieve a prescribed range for D, i.e. D ≡ [D_min , D_max . This range is determined primarily by the SM ratio k to m and the maximum allowable SM capacitor voltage v_cy (see Figure 2) in each arm. However, conduction losses increase significantly for low values of D (as will be shown shortly) and thus Z)_min has a practical lower limit. Moreover, a practical upper limit for Z)_max comes into play as large values of D (i.e. values of D significantly greater than unity) drive up the total number of SMs, or equivalently the voltage rating of individual SMs. Therefore, the DC-MMC architectures become more cost effective as the value of D approaches unity. In Figure 1 the AC components of arms voltages ik, i_m and v'_lm,v'ik are synthesized by appropriate switching of the SMs. Each arm can therefore be viewed as a controllable AC voltage source with a variable DC component. The fundamental frequency of the arms voltages, however, is not constrained to 50/60 Hz. This freedom in choosing the modulating frequency comes from the fact the AC voltages and currents do not directly impact D. These AC quantities remain internal to the DC-MMC and act only to ensure charge balance of the SM capacitors. Therefore, modulating frequencies higher than 50/60 Hz can be exploited to reduce the size of the input and output filters, as well as the size of the SM storage capacitors.

In Figure 1 the output filter currents are designed to be relatively small in comparison to the AC component of the arms currents

\k\ < < I ' it I

In (3) and (4), i denotes the fundamental frequency component of ¾, i.e. i = I cos(a>_mt + 0,).

To illustrate the ideal single-stage DC/DC conversion process in Figure 1, a simplified model for string #1 of the DC-MMC is provided in Figure 5. This model captures all of the power transfer mechanisms involved in the energy conversion process of the DC-MMC. The cascaded SMs within each arm are modeled using ideal voltage sources, which is common practice in DC/ AC MMC analysis. These sources model both the DC and fundamental frequency AC components of the arms voltages. Note the impact of filter currents is neglected as warranted by (3) and (4). All currents are separated into their DC and AC parts with positive integer n denoting the number of interleaved strings, e.g. n = 1 for Figure 1. The inclusion of variable allows for application of the string model in Figure 5 to multi-string DC-MMC architectures, which will be introduced in latter sections.

From Figure 5 the DC/DC conversion process can be visualized. The DC current through the inner arms increases as D becomes smaller. For D <0.5, the inner arms carry a DC current greater than \i_m/n\. This operating region thus incites increased conduction losses, and may necessitate additional inner arms installed in parallel to avoid derating of power transfer between networks. The ability to parallel multiple arms is enabled by the inclusion of L_a in each arm. Restructuring of arm chokes in Figure 1 to eliminate individual chokes is possible, provided the basic requirement of an inductance in every voltage loop is not violated.

The string of cascaded SMs in Figure 1 follows the DC/DC conversion process illustrated in Figure 5. The outer arms and inner arms carry a DC current of \i_m/n\ and \(D'/D)i_in/n\, respectively. To ensure steady-state power balance of each SM capacitor in string #1, the following average power constraints must be met

D'P, dc

V_{l k} . Ii_k = -Z>'(t _hl+) ^ =

n 2n (5)

V_{l m} · I_im = D' (v _l I )—

n 2n (6)

D'P_{i lc}

V _m - l[_nl = D>(v,_u ) '

2n (7)

Vi„ - I'_{l k} = -£> ;„

n 2n (8)

Vik · Iik denotes the phasor dot product, i.e. Vik · Iik = (VI/2) cos(6>_v - 6>i). The notation Vik and Iik signifies the fundamental frequency AC rms phasors for ⁱ lk and ' Ik, respectively. That is, Vi_k = (V/V2)z6>_v and I_ik = (/Λ/2) 6>_;. P_dc is the total DC power transfer between networks, as shown in Figure 5, where Pdc > 0 corresponds to i_m > 0.

Power balance constraints (5) through (8) reveal an average AC power equal to \DP_dc/2n\ must be exchanged between each outer arm and the adjacent inner arm. The direction of power exchange depends on the polarities of D' (step-up/step-down) and Pdc (DC power transfer direction). For example, Figure 5 shows the outer arms must deliver average AC power to the inner arms for: 1) D' > 0, P_ic > 0 and 2) D' < 0, .P_dc < 0. Based on the preceding discussion, the single-string DC-MMC in Figure 1 internally circulates a total average AC power of

Note interconnecting two HVDC networks of similar voltage levels requires only a small amount of AC power to be circulated. In contrast, for D = 0.5 the DC-MMC must internally circulate 50% of the total DC power transfer in terms of AC power. To ensure a net AC voltage is not impressed across the input or output DC terminals, requirements are imposed on the synthesized arms voltages

To satisfy (5) through (10) for all operating conditions, there are an infinite number of possible combinations of AC arms voltages (and resulting AC arms currents). Figures 6 and 7 illustrate two AC phasor diagrams providing such example combinations of arms voltages and currents for the single-string DC-MMC. In these diagrams the arms voltages are of equal magnitude and positive values of Φ correspond to V_lm leading Vi_k (e.g., Φ = -90° in Figure 6). The average AC power exchanged between arms is adjusted by changing Φ and/or the voltage magnitudes. The circulating AC currents are established by voltages AYi and AY impressed across a net capacitive impedance. Note the only change between Figure 6 and Figure 7 is the arms voltages have been reflected about the imaginary axis.

The phasor diagrams in Figure 6 and Figure 7 neglect the impact of the output filter currents based on (3) and (4). This is a reasonable approximation that simplifies the phasor analysis and aids in clearly illustrating key aspects of the DC/DC conversion process. Therefore, this approximation is adopted in all subsequent phasor diagrams introduced for the multi-string DC-MMC architectures. However, it should be noted the AC output filter currents are necessarily accounted for in all simulations and experiments.

Input and Output Filtering

In Figure 1 there is no net AC voltage impressed across the DC output terminals (i.e. from v_out+ to v_out-). However, the existence of AC voltages at nodes pi and nl with respect to ground is an undesirable but innate consequence of the SM based structure. Unless removed, the DC output poles will be excited with an AC component. Thus, low-pass filters are needed to ensure the output DC poles remain at a near constant potential, i.e. ideally Dv_m+ and Dv_m. relative to ground. The use of passive elements L_f and _f is one example of how to achieve the required voltage attenuation. This is a low cost alternative to the use of active filtering. The use of an input filter for the single-string DC-MMC architecture is optional. Inductor L_s is a simple series filter that provides additional attenuation of AC currents. As highlighted previously, the AC modulating frequency can be increased to minimize the overall size and thus cost of the filters.

Note, sizing of Lf and _f is based on achieving an acceptable AC voltage attenuation at the fundamental operating frequency.

Impact of Filter Currents on DC/DC Conversion Process

Up until this point the filter currents and ^ have been neglected based on (3) and (4). This approximation is now relaxed to explain the impact of the filter currents on the DC/DC conversion process. The assumption of ideal output AC filtering is still enforced.

Figure 8 shows the equivalent AC circuit diagram for the top leg of the single-string DC-MMC architecture. Due to symmetry only one leg need be analysed. Each source generates an average AC power

The dot product Vu,^■ If i_s always equal to zero as I_f is phase shifted 90 degrees from Vi_k. Therefore, both sources still exchange equal average power even though they do not share a common AC current. However, it should be noted the flow of filter currents impacts the amount of AC power exchange between arms.

Second and Third Exemplary Embodiments

Figure 3 shows a variant of the architecture in Figure 1 where all FB/SMs have been replaced with HB/SMs. This variant is limited to step-down operation, but otherwise operates in a manner substantially similar to that of the structure of Figure 1 and thus is not described in detail.

The same applies with respect to Figure 4, which shows the third embodiment, wherein all HB/SMs of Figurel have been replaced with FB/SMs, and thus remains capable of step-up and step-down operation. Multiple-String Architectures for the DC-MMC

A two-string bidirectional DC-MMC architecture forming a fourth embodiment of the invention is depicted in Figure 9. In this configuration the biasing capacitors in Figure 1 are replaced with a second string of cascaded HB/SMs and FB/SMs. The maximum output power of the two-string architecture is therefore twice that of the single-string. To set up the circulating AC currents necessary for the DC/DC conversion process, two inductors of value L_r are connected at the midpoints of each string as shown. Inductors L_r together with arm chokes J_a form the composite net inductance seen by the circulating AC current. As such, a degree of design freedom exists in selecting the relative sizes of L_r and J_a. For example, choice of L_r equal to zero is viable, however, a more cost-effective solution will result by incorporating a non-zero L_r since this inductance carries no DC current component. Inductors L_r can be utilized as no net DC voltage exists between the string midpoints. In contrast, the single-string architecture is constrained to use capacitors (C_r / 2) due to DC biasing requirements. Similar to the single-string architecture, each of the strings in Figure 9 can employ HB/SMs (as in Figure 3), FB/SMs (as in Figure 4) or any combination thereof.

In Figure 9 the differential AC voltage across the two string midpoints (i.e. v_ol = -v_o2) permits an optional ground reference to be established as shown. The operational benefits empowered by this local ground connection in terms of insulation coordination offer significant benefit. The ability to locally ground the structure in Figure 9 is thus a key advantage over the single-string architecture. It should be noted it is also possible to use series-connected capacitors as opposed to inductors. Both elements will set up the AC currents needed for the DC/DC conversion process. However, in the case of using capacitors, the DC-MMC structure becomes high-impedance (capacitively) grounded. Therefore, although any reactive element can be used, inductors are utilized in Figure 9 to establish a low impedance or zero impedance DC ground reference.

The DC output nodes of the two strings are paralleled as shown in Figure 9. The interleaving of strings permits each to carry one-half of the total power transfer while sharing common output voltages v_out+ and Vout- Interleaving also significantly improves the low-pass filtering of AC voltages present at the output DC poles. This benefit is a direct result of the cancellation of AC filter currents as ^?1 (and ' ¹ ) and (and ¾ ) are of opposite phase relative to one another. As a result, ^?f and ⁷f ideally carry no fundamental frequency AC current. The output voltages v_out+ and v_out- are therefore effectively free of AC stimuli. In practice, C_f will carry a small amount of high frequency current introduced by the switching of the SMs.

In comparison to the single-string architecture, the sizing requirements of C_f for the two-string architecture is greatly reduced. In the former, C_f carries fundamental frequency current and must be sized accordingly. The cancellation of filter currents enabled by output interleaving is thus another key advantage of the two-string DC-MMC architecture.

The use of coupled inductors as shown in Figure 9 is suitable to provide the large value of inductance needed for attenuation of the AC filter currents. The magnetizing inductance of the coupled inductors,

J_f, imposes a large AC impedance to ¹ and '2 (and ¹ and ¾) while eliminating DC flux in the core.

Each string of cascaded SMs in Figure 9 follows the DC/DC conversion process previously outlined for the single-string architecture. However, the circulating AC currents are now enabled by inductors L_r. To satisfy charge balance of the SM capacitors within each string, there are infinitely many possible combinations of arm voltages (and resulting arm currents). The AC phasor diagrams in Figure 10 and Figure 11 shows two example combinations accommodating all possible operating modes of the two-string DC-MMC. Keeping with prior convention, the arms voltages are of equal magnitude and positive Φ corresponds to Vi_m leading Vi_k. The average AC power exchanged between arms is adjusted by changing Φ and/or the voltage magnitudes.

It should be stressed that Figures 6 and 7 (single-string architecture) and Figures 10 and 11 (two-string architecture) illustrate only one possible strategy for controlling the AC arms voltages of the DC-MMC. For example, it is also possible to modulate the AC arms voltages such that the outer arms of each string operate at unity power factor. For a given magnitude of AC arm voltages, V, this unity power factor control scheme can minimize the circulating AC currents needed to satisfy steady-state power balance of the SM capacitors when operating with larger values of D (e.g. D > 0.6). Phasor diagrams imposing unity power factor for the outer arms of each string in Figure 9 are given in Figure 12 and Figure 13. From inspection of the two-string architecture in Figure 9 it becomes evident the DC-MMC can be extended to a generalized w-string interleaved architecture, where n is a positive integer.

For example, a three-string architecture (n = 3) can be realized as shown in Figure 14. Similar to the two-string architecture, the three-string DC-MMC architecture employs coupled inductors at the output for AC filtering purposes. The use of coupled inductors as shown in Figure 14 is suitable to provide the large value of inductance needed for attenuation of the AC filter currents, while eliminating DC flux in the core of each set of coupled inductors. The magnetizing inductance of each set of coupled inductors is denoted by L_f.

Operating voltages on the order of hundreds of kilovolts can be achieved by stacking the appropriate number of SMs in each string. Power transfers on the order of hundreds of megawatts or even gigawatts can be achieved by interleaving the necessary number of strings.

For multi-string architectures («>1), the phase shift required between AC modulating waveforms of each string is

360 /« (13)

For example, n = 2 gives a phase shift of 180°. This result aligns with Figure 10 through Figure 13 for the two-string DC-MMC architecture.

Analysis of Multiple-String DC-MMC Architectures

This section provides aditional analysis of the multi-string DC-MMC architectures, focusing on internal power transfer mechanisms and steady-state power balance requirements of the SM capacitors. Basic power flow equations are also derived and discussed.

The principle of operation of the two-string DC-MMC architecture is conceptualized in Figure 28. As the two-string and three-string architectures have the same operating principle, the former is chosen here for simplicity. DC current paths are shown with solid lines while circulating AC current paths are represented using dotted lines. Ρ_Άα signifies the average AC power exchanged between each pair of arms for SM capacitor power balancing. Note, Ρ_Ά0 is visually represented in Figure 5 by the arrows between each outer arm and the adj acent inner arm. A non-zero DC power transfer (i.e. i_m≠ 0) necessitates a non-zero Ρ_Ά0 to keep the SM capacitor voltages balanced. The polarity of AC power exchange between arms depends on the DC-MMC operating mode, as indicated in Figure 5. The requisite Pac in Figure 28 is achieved through the interaction of the circulating AC currents and AC components of the arms voltages. The shuttling of average AC power between arms is done in a near lossless manner as the circuit impedance consists of reactive elements. This power transfer mechanism, a well-known concept in traditional AC power systems for transferring average power between networks, is an enabling mechanism by which single-stage DC/DC conversion for series-cascaded SMs is realized.

An important characteristic of the two-string topology in Figure 28, which also applies for the three-string DC-MMC architecture (and, in general, any multi-string architecture), is the inherent symmetry in AC current paths about the converter midpoint. This symmetry, enabled by the physical linking of string midpoints, is exploited to achieve natural cancellation of AC voltages across the input and output DC terminals.

Figure 30 gives two example AC phasor diagrams that illustrate the fundamental power transfer mechanism employed to achieve steady-state power balance of each SM capacitor in Figure 9, for all possible operating modes of the DC-MMC. These phasor diagrams are similar to those shown in Figure 10 and Figure 1 1, however, in Figure 30 the peak magnitude of the AC arms voltages is explicitly denoted by V. Keeping with prior convention, Φ is the phase shift between AC voltages of each outer arm and the adjacent inner arm, with positive values of Φ defined for the inner arm voltage leading the outer arm voltage. For example, positive values of Φ for string #1 correspond to Vi_m leading Vi_k and V'i_m leading V'i_k- Note the modulating waveforms of each string are displaced by 180^°.

It is easy to visualize via phasor dot products that each pair of inner and outer arms in Figure 30 exchange equal average AC power as dictated by (5) through (8). However, adopting such a strategy constrains each pair of arms to equally share the reactive power requirements of the composite load formed by L_r and J_a. This implies each arm operates at an equal AC power factor (in Figure 30 the example case of power factor equal to 0.707 is shown where Φ = ±90°). As will be discussed shortly, an advantageous strategy is to impose unity power factor on the outer arms while realizing near unity power factor operation for the inner arms as shown in Figure 31. Here, by chosen convention, Mis the ratio of inner arm to outer arm AC voltage magnitudes, e.g. M =

For a fixed Ϋ, this modulation scheme minimizes the circulating AC currents needed for the DC/DC conversion process. Moreover, it significantly reduces the circuit reactance required to establish the circulating AC currents. This is based on the principle that, for larger/⁾ (e.g. D » 0.5), the outer arms will likely have less available voltage headroom (as \D'\ « 0.5) and therefore their AC voltage should be maximized. Note, phasor diagrams in Figure 31 are a generalized version of those shown in Figure 12 and Figure 13, i.e. Figures 12 and 13 are drawn for a fixed and Φ. Based on Figure 5 and Figure 31, the average power exchanged between each outer arm and the adjacent inner arm is

where

X_r — )_m(L_r + L_a) (15)

Positive values of Pw_m denote average AC power delivered from each outer arm to the adjacent inner arm of the same string. In general,

is adjusted by changing any combination of M, V or Φ. Converters designed with smaller X_r offer reduced circuit var requirements and result in values of |Φ| approaching 180°

Equation (15) reveals the DC-MMC can in fact be operated with L_r equal to zero. That is, the midpoints of each string in Figure 9 (and similarly Figure 14) can be connected together and, possibly, or, if desired, solidly grounded. In this case the arm chokes solely provide the reactance needed to setup the circulating AC currents. However, it must be stressed midpoint inductors L_r need only carry AC currents while arm chokes J_a must carry both DC and AC currents. Allocation of circuit inductance to L_r versus J_a is the outcome of a converter design optimization, which therefore enables cost reduction.

Equating (14) with the required average power exchange as dictated by (5) through (8) gives

MV² . D'P_dc

——— an Φ =—

X_T 2n (16) Power balance criteria (16) is a primary design equation quantifying the amount of average AC power that must be exchanged between arms in steady-state, as a function of the voltage conversion ratio and DC power transfer between HVDC networks. Furthermore, (16) provides additional insight into DC-MMC operation as it relates AC and DC power transfer mechanisms. Substituting n = 2 reveals each pair of arms in Figure 9 exchange

of average AC power via circulating AC currents. This result aligns with the string model in Figure 5.

Bidirectional Fault Blocking for the DC-MMC

In addition to enabling step-up operation and the interconnection of HVDC networks with similar voltage levels, the FB/SMs in Figure 1, Figure 9 and Figure 14 (and also the 2k FB/SMs in Figure 4) can be used to provide bidirectional fault blocking for the DC-MMC. That is, the DC-MMC can interrupt fault currents initiated by DC faults in either the input or output side networks similar to a DC circuit breaker. This is accomplished by controlling the FB/SMs (and possibly also HB/SMs) in the outer arms to impose the appropriate polarity of voltage during fault events, thereby blocking the flow of fault currents, using a strategy similar to the fault blocking scheme described for the MMC in R. Marquardt, "Modular multilevel converter: An universal concept for HVDC-networks and extended DC-bus-applications," in International Power Electronics Conference, Jun. 2010, pp. 502-507, incorporated herein by reference. The inner arms of the DC-MMC need only employ HB/SMs as no benefit is realized with bipolar voltage injection. In general, to ensure bidirectional fault blocking the 2k outer arm SMs within each string must collectively provide enough blocking voltage to counteract the larger of v_in+ + v_in- and v_out+ + v_out-.

Table 1 summarizes the fault blocking capability of the DC-MMC.

Table 1 : DC-MMC Bidirectional Fault Blocking Capability: Outer Arms SM Blocking Voltage

Requirements

Outer Arms SM Blocking Voltage Requirements (Normalized Relative to t¾_n+ + !'i_n- )

Fault Condition Step-Down Operation (D < 1) Step-Up Operation (D > 1)

Input Side Network Fault D [p.u.] (FB/SMs) D [p.u.] (FB/SMs)

(Block Output Network Voltage) (Inject Negative Voltage) (Inject Negative Voltage)

Output Side Network Fault 1.0 [p.u.] (HB/SMs) 1.0 [p.u.] (HB/SMs)

(Block Input Network Voltage) (Inject Positive Voltage) (Inject Positive Voltage)

Bidirectional Fault D [p.u.] (FB/SMs) + D' [p.u.] (HB/SMs) D [p.u.] (FB/SMs)

Blocking Capability (Inject Pos./Ncg. Voltages) (Inject Pos./Ncg Voltages)

Example Scenario Step-Down Operation (D < 1 ) Step-Up Operation (D > 1)

D = 0.5 0.5 [p.u.] (FB/SMs) + 0.5 [p.u.] (HB/SMs) = 1.0 [p.u.]

D = 0.8 0.8 [p.u.] (FB/SMs) + 0.2 [p.u.] (HB/SMs) = 1.0 [p.u.]

D = 1.1 1.1 [p.u.] (FB/SMs)

The blocking voltages required for the outer arm are provided in p.u. (normalized relative to input side DC network voltage) and are partitioned into individual HB/SM and FB/SM requirements. For example, a value of "0.6 p.u. (FB/SMs)" signifies that the outer arms of each string must have enough FB/SMs to support 60% of the input network voltage. Table 1 illustrates that faults located in the input side network require the outer arms to inject a negative voltage to counteract the output side network. This necessitates the use of FB/SMs. The amount of p.u. negative voltage to be injected is equal to the voltage conversion ratio D, and is the same for both step-down and step-up modes. In the case of faults located in the output side network, the outer arms must inject a positive voltage to counteract the input side network. HB/SMs are sufficient to provide the 1.0 p.u. positive voltage injection for both step-down and step-up modes. To achieve bidirectional fault blocking for step-down operation, only D p.u. of FB/SMs are needed (where D < 1) to block both input and output side faults. To minimize the total semiconductor cost FIB/SMs are used for the remaining D' p.u. of blocking voltage (i.e. D + D' = 1.0). During step-up operation, D p.u. of FB/SMs are necessary (where D > 1).

Observe from Table 1 that, to enable bidirectional fault blocking for the DC-MMC, the outer arms may consist of any combination of FB/SMs and FIB/SMs as determined by the operating range for D.

Open Loop Voltage Control

Open loop control techniques for balancing of SM capacitor voltages within the DC/AC MMC have been discussed in several papers including: (1) D.C. Ludois and G. Venkataramanan, "Simplified terminal behavioral model for a modular multilevel converter," IEEE Trans. Power Electron., vol. 29, no. 4, pp. 1622-1631, Apr. 2014; (2) A. Antonopoulos, L. Angquist, L. Harnefors, K. lives and H.-P. Nee, "Global asymptotic stability of modular multilevel converters," IEEE Trans. Ind. Electron., vol. 61, no. 2, pp. 603-612, Feb. 2014; (3) L. Angquist, A. Antonopoulos, D. Siemaszko, K. lives, M. Vasiladiotis and H.-P. Nee, "Open-loop control of modular multilevel converters using estimation of stored energy," IEEE Trans. Ind. Appl, vol. 47, no. 6, pp. 2516-2524, Nov. 2011; (4) A. Haider, N. Ahmed, L. Angquist and H.-P. Nee, "Open-loop approach for control of multi-terminal DC systems based on modular multilevel converters," in Proceedings of the 14th European Conference on Power Electronics and Applications, 2011, pp. 1-9; and (5) R.F. Lizana, M.A. Perez and J. Rodriguez, "DC voltage balance control in a modular multilevel cascaded converter," in IEEE International Symposium on Industrial Electronics, May 2012, pp. 1973-1978.

One of the simplest forms of open loop control, direct modulation, as described in A. Antonopoulos, L. Angquist, and H.-P. Nee, "On dynamics and voltage control of the modular multilevel converter," in 13th European Conference on Power Electronics and Applications, Sep. 2009, pp. 1-10, incorporated herein by reference, adopts fixed sinusoidal modulating signals for the MMC arms. Balancing of SM capacitor voltages is achieved by a sort and selection algorithm that arranges capacitors based on their voltage measurements, and inserts the appropriate one(s) at each switching instant based arm current measurements. However, such a modulation approach alone is insufficient to ensure voltage balancing of SM capacitors for the DC-MMC. This is because the DC-MMC employs a fundamentally different power transfer mechanism: the direct exchange of average AC power between arms (see Figure 5). Any slight imbalance in this power exchange, for example, such as that caused by a sudden change in P^ in Figure 5, will cause the SM capacitor voltages to diverge from their desired nominal values. Consequently, some form of regulation is required.

Circulating AC Current Control

Figure 32 shows a proposed circulating AC current control scheme that enables open loop voltage control of the two-string DC-MMC; in this scheme, the SM capacitor voltages are balanced by regulating the average AC power exchanged between inner and outer arms.. The control structure is partitioned into four blocks for each string; inner and outer arm logic for the positive and negative poles. To maintain power balance of the SM capacitors, closed loop control of the circulating AC currents is adopted according to the modulation strategy in Figure 31. As previously described the outer arms are imposed to operate at unity power factor while the inner arms operate at near unity power factor. However, the inner arms can alternatively operate at unity power factor by simply mirroring the inner/outer arms logic in Figure 32. In general, the proposed control can be modified to split the vars generation between arms as desired.

In Figure 32 the AC component of the outer arms modulating signals are fixed for each string. In contrast, the AC component of the inner arms modulating signals are the outcome of closed-loop control action. Proportional resonant (PR) compensators synthesize the inner arms AC voltages needed to drive the circulating AC currents in phase with the outer arms. AC current references for the outer arms are generated by proportional-integral (PI) compensators acting on the error between the sum of inner arm minus outer arm SM capacitor voltages. When this error deviates from zero, which signifies an imbalance in the AC power exchange between arms, the PI compensators adjust the magnitude of circulating AC currents to re-establish SM capacitor power balance. High-pass filters used in the feed-back loop ensure the compensators act only on the AC component of the outer arms currents. Similar to the DC/ AC MMC, a sort algorithm, such as described in A. Hassanpoor, S. Norrga, H. Nee, and L. Angquist, "Evaluation of different carrier-based PWM methods for modular multilevel converters for HVDC application," in 38th Annual Conference on IEEE Industrial, Electronics Society, 2012, pp. 388-393, incorporated herein by reference, orders the SM capacitors in each arm from lowest to highest voltages. Using the reference voltage modulating signals for each arm, e.g. \ ^[v ^l*^{k ;} v* ^lm ' ν' ^l*^m ' v' ^l*^k 1^J for string #1, the SPWM blocks generate gating signals by selecting the appropriate SM capacitor(s) (via sort algorithm) to insert at each switching instant based on arm current direction and arm voltage polarity. The nominal voltage of each

SM capacitor is denoted by Note, use of measured currents i_xk and i_x' _k in Figure 32 for control feedback implicitly assumes output filtering keeps the circulating AC currents confined to the converter structure. Other strategies in which to obtain the circulating AC current measurements for control feedback purposes are also possible. For example, control feedback of circulating AC currents in Figure 32 could alternatively be implemented by replacing measured quantities i_xk and i_x' _k with (i_xk+t_Xm)/2 and (i_X' k+ix' _m)/2, respectively. In Figure 32 the DC components of the modulating signals are fixed for all arms based on the desired converter voltage conversion ratio D. This is sufficient for open loop voltage control of the DC-MMC. In practice, additional control loop(s) would be needed to regulate the DC output currents from each string to ensure proper current/power sharing between strings.

Deployment

Deployment of the two-string DC-MMC architecture in Figure 9 as an interface between two bipolar HVDC networks defines a sixth exemplary embodiment of the invention, shown in Figure 15. Due to the ability of the DC-MMC to achieve both step-up and step-down voltage conversion, the possible operating scenarios for Figure 15 include:

• Voltage of HVDC network #1 nominally greater than voltage of HVDC network #2

• Voltage of HVDC network #1 nominally less than voltage of HVDC network #2

• Voltage of HVDC network #1 nominally equal to voltage of HVDC network #2.

The two-string DC-MMC architecture can accommodate any one of the above three scenarios by operating in: 1) step-down 2) step-up or 3) combination of step-down/step-up modes of operation as needed. That is, the two-string DC-MMC architecture can interconnect HVDC networks of nominally different or equal voltage levels, and manage the power transfer between them. Moreover, it can act as a DC circuit breaker and suppress the flow of fault currents between the HVDC networks, regardless of fault location.

The seventh exemplary embodiment of the invention shown in Figure 16 shows an example case wherein two sets of cascaded SMs are connected in parallel for the inner arms of Figure 9. This example is of practical importance as it avoids de-rating of the DC-MMC's output power when operating at lower values of D.

The eighth exemplary embodiment of the invention shown in Figure 25 is a variant of Figure 9, wherein the midpoints of each string are linked together without the interposition of a reactive structure. In this case, the required circuit reactance is obtained from the inductor in each arm. Without intending to be bound by theory, the structure in Figure 25 is believed to have utility at least in the context wherein the net AC voltage generated by each outer arm and the adjacent inner arm is relatively low, such as can be obtained, for example, only, if the system were configured in accordance with the phasor diagrams of Figure 10 or Figure 11 with |Φ| approaching 180°.

PSCAD/EMTDC Simulation Results

Idealized voltage and current waveforms are simulated to demonstrate the steady-state operation of the two-string DC-MMC architecture in Figure 9. The two-string architecture is chosen for this case study as it illustrates the operational benefits enabled with interleaving.

The following four operating scenarios are considered:

• Two-string DC-MMC architecture with D= .6 (step-down operation) and power flow from input to output

• Two-string DC-MMC architecture with D=0.9 (step-down operation) and power flow from output to input

• Two-string DC-MMC architecture with Z⁾=1.05 (step-up operation) and power flow from input to output

• Two-string DC-MMC architecture with D=\. 15 (step-up operation) and power flow from output to input

All waveforms are generated using the software package PSCAD/EMTDC. The fundamental operating (i.e. modulating) frequency of the AC waveforms is selected as 400 Hz. In each scenario the DC power transfer is 960 MW. To ensure steady-state power balance for each SM capacitor, the AC arm voltages are controlled according to the scheme given in Figure 12 and Figure 13. AC output filter currents are accounted for in all simulations. Two-String DC-MMC Architecture: DC Power Flow from Input to Output with D= .6

Simulation results illustrating the steady-state operation of the two-string DC-MMC architecture in Figure 9 with D=0.6 and power flow from input to output are provided in Figure 17 and Figure 18. The AC components of the arms voltages and arms currents reflect the phasor diagram in Figure 12.

Two-String DC-MMC Architecture: DC Power Flow from Output to Input with D= .9

Figures 19 and 20 show simulation results for the steady-state operation of the two-string DC-MMC architecture in Figure 9 with D=0.9. Power flow is from output to input. The AC components of the arms voltages and arms currents conform with the phasor diagram in Figure 13.

Two-String DC-MMC Architecture: DC Power Flow from Input to Output with Z⁾=1.05

Simulation results illustrating the steady-state operation of the two-string DC-MMC architecture in Figure 9 with Z⁾=1.05 and power flow from input to output are provided in Figure 21 and Figure 22. The AC components of the arms voltages and arms currents reflect the phasor diagram in Figure 13.

Two-String DC-MMC Architecture: DC Power Flow from Output to Input with Z⁾=1.15

Figure 23 and Figure 24 show simulation results for the steady-state operation of the two-string DC-MMC architecture in Figure 9 with D=I A 5. Power flow is from output to input. The AC components of the arms voltages and arms currents conform with the phasor diagram in Figure 12.

PLECS Simulation Results

Reference is now made to Figure 26 and Figure 27, which shows the three-string DC-MMC and two-string DC-MMC, respectively, with input and output filtering. Input filtering is provided by inductors Js and capacitors C_s. The subsequent simulations results correspond to the two-string DC-MMC in Figure 27, for which a comprehensive switched converter model is developed in PLECS. This converter model includes detailed modeling of switch nodulation and capacitor cell sort algorithms, which was not represented in the prior idealized PSCAD/EMTDC simulations. Two operating scenarios for the two-string DC-MMC are simulated in PLECS to validate the open-loop voltage control strategy proposed in Figure 32. The scenarios include: 1) D = 0.5 (step-down) and 2) D = 1.1 (step-up). For each scenario the DC power transfer between networks, P_<i_c, is 14 MW. A full switched model of Figure 27 is implemented with four SMs per arm, i.e. k = m = 4; ideal switches are utilized. In both cases i_m > 0 (and thus Ρ&₀ > 0) such that Figure 31(a) and Figure 31(b) are utilized. To ensure power balance of SM capacitors the two-string DC-MMC must exchange D'P^/4 of average AC power between inner and outer arms (ref. Figure 5). The fundamental modulating frequency of the arms voltages is selected as 50 Hz. The APOD SPWM scheme as described in A. Hassanpoor, S. Norrga, H. Nee, and L. Angquist, "Evaluation of different carrier-based PWM methods for modular multilevel converters for HVDC application," in 38th Annual Conference on IEEE Industrial Electronics Society, 2012, pp. 388-393, incorporated herein by reference, is adopted, although alternative modulation schemes can be used. Simulation parameters are given in Table 2.

Table 2: PLECS Simulation Parameters for Figure 27 (k = m = 4)

In the subsequent discussions, the string model in Figure 5 and phasor diagrams in Figure 31 are heavily leveraged. PLECS Simulation: Step-Down Operation

Simulation results for D = 0.5 with DC power transfer from input to output are given in Figure 33. The DC input and output voltages are ±8.8 kV and ±4.4 kV, respectively. i_m and z_out have average values of 0.795 kA and 1.59 kA, respectively. For the two-string DC-MMC to facilitate the transfer of 14 MW, each outer arm delivers D'P^ = 1.75 MW of average AC power to the adjacent inner arm (i.e. Pw_m = +1.75 MW). This is achieved with an AC voltage for the outer arms of V = 3.5 kV_pk and circulating AC currents of 1.0 kA_pk.

Figure 33 shows the AC currents in the arms circulate in a symmetric fashion about the converter midpoint as dictated by Figure 5, e.g. ^{= i l iri = "} 'Ί™ ^{= _ i}'ik . All of the arms have the same DC current magnitude of 0.398 kA (/^' _1η/2) due to the fact D' = D = 0.5. However, outer arms currents z^'lk, i'l_k, h ,

have a positive average value (+0.398 kA) while inner arms currents z^'i_m, i _m, i_2m, have a negative average value (-0.398 kA). The opposing polarity of DC arms currents aligns with Figure 5 and is a result of the DC-MMC operating in step-down mode. As demonstrated by i i₂ and i , i'₂ waveforms, L_f imposes a large AC impedance and confines the circulating AC currents within the DC-MMC structure. This validates the prior assumption of negligible AC output inductor currents.

In Figure 33 the AC components of the arms modulating signals (i.e. scaled versions of AC arms voltages) and AC components of the arms currents align with the phasor diagram in Figure 31(a). Average AC power is delivered from each outer arm to the adjacent inner arm, with outer arms operating at unity power factor and inner arms supplying the necessary vars. For example, ⁱ ik and *ik in Figure 33 are phase-shifted 180° (outer arm delivering average AC power at unity power factor) while it *

m slightly lags ^'Ίι^η (inner arm receiving average AC power near unity power factor and supplying vars). To supply reactive power the inner arms have a slight larger AC voltage magnitude relative to the outer arms, as illustrated in Figure 31(a). SM capacitor voltage waveforms plotted for string #1 verify charge balance is achieved via the described power transfers. Similar waveforms exist for string #2. The balancing of SM capacitor voltages as shown validates the adopted closed loop AC current control strategy. As can be seen in Figure 33, i_m and z_out contain a small second harmonic (i.e. 100 Hz) ripple component. This open-loop operating characteristic of the DC-MMC is not captured in the prior analysis as it was restricted to fundamental frequency operation. The second harmonic current ripple can be mitigated by increasing the energy storage capacity of the SMs (i.e. increasing C_sm). Furthermore, it is likely that supplemental arm voltage control can be incorporated to suppress the generation of second harmonic voltages, similar to that implemented for the DC/ AC MMC described in K. lives, A. Antonopoulos, L. Harnefors, S. Norrga, L. Angquist and H.-P. Nee, "Capacitor voltage ripple shaping in modular multilevel converters allowing for operating region extension," in 37th Annual Conference on IEEE Industrial Electronics Society, 2011, pp. 4403-4408. For this case study, the SM capacitors are sized to achieve acceptable 100 Hz current ripple as well as tolerable capacitor voltage ripple.

PLECS Simulation: Step-Up Operation

Simulation results for D = 1.1 are provided in Figure 34. The input voltage of ±8.8 kV is now stepped up to ±9.68 kV. This scenario is chosen to demonstrate the DC-MMC's ability to interconnect DC networks of similar voltages by exploiting FB/SMs in the outer arms. The average value of i_m remains the same as for step-down mode (0.795 kA), however, z_out now has an average value of 0.723 kA due to the relation i_m = Di_oat. For the same P_&c = 14 MW, only 0.35 MW of average AC power is exchanged between arms in Figure 34 as opposed to the 1.75 MW needed for step-down operation with D = 0.5. This is because \D'\ has decreased from 0.5 to 0.1. However, as D' = -0. 1 but Rdc remains positive, the polarity of power exchange has reversed and is now from inner to outer arms (i.e. Pw_m = -0.35 MW). This is achieved with V = 1.2 kV_pk and circulating AC currents of 0.583 kA_pk.

The average value of outer arms currents z^' _lk, z'lk, z_2k, z^' _2k in Figure 34 remains unchanged from the simulated step-down scenario (+0.398 kA), which is consistent with Figure 5. The DC component of inner arms currents i\_m, i _m, z_2m, z _2m, however, is now +0.036 kA, i.e. flowing towards the neutral, as necessary for boost operation. Relative to the outer arms, the inner arms of the DC-MMC need only carry a small amount of DC current for values of D near unity. In Figure 34, the AC components of the arms modulating signals and the AC arms currents align with the phasor diagram in Figure 31(b). Average AC power exchange is now from each inner arm to the adjacent outer arm. The outer arms still operate at unity power factor while the inner arms supply vars. For example, lk and ?-i k in Figure 34 are in phase (outer arm receiving average AC power at unity power factor) while ^' 'im lags ^ i m by nearly 180° (inner arm delivering average AC power near unity power factor and supplying vars). The described waveforms demonstrate the DC-MMC's ability to meet power balance of each SM capacitor while performing step-up voltage level conversion.

To facilitate step-up operation the nominal voltage of each SM capacitor in Figure 34 has increased from 2.2 to 2.9 kV. This increase in ^caP, which for simplicity in this case study is imposed for all arms, permits the inner arms to achieve the DC output voltage required for step-up mode.

In comparison to Figure 33, the waveforms for step-up operation display significantly more switching ripple content. This stems from using a relatively low number of SMs in each arm (four) in order to reduce the simulation complexity and runtime. To compensate for the low number of SMs, the arm choke inductance and SPWM carrier frequency are selected to accommodate the added ripple during step-up. In addition, input filter elements L_s = 0.5 H and C_s = 40 μ¥ are utilized for the step-up scenario to reduce switching ripple for i_m. For the step-down scenario, an input filter is not required. This is affirmed by the very low switching ripple content in Figure 33. Note, in both Figure 33 and Figure 34 the DC-MMC can provide bidirectional fault blocking as the outer arms have sufficient voltage to withstand the larger of the input or output DC terminal voltages.

Experimental Validation of Single-Stage DC/DC Conversion Process

In this section, experimental results are presented for a 4 kW laboratory prototype based on the single-string DC-MMC shown in Figure 1. The single-string is the simplest realization of the bipolar DC-MMC and operates in a fundamentally similar manner to that described for the multi-string architectures. Although consisting of a single SM string, the prototype enables practical validation of the ability to satisfy power balance of SM capacitors via circulating AC currents - the key power transfer mechanism enabling single-stage DC/DC conversion for the studied multi-string architectures. The main objective of the experimental work is to support the DC-MMC PLECS simulations, by demonstrating successful field implementation of the proposed energy conversion concept; notably, the circulating AC currents remain confined to the converter structure despite typical load and parameter imbalances. Such non-ideal conditions are not represented in the simulations. The experiments include step-down and step-up scenarios similar to those previously described for the PLECS simulations.

Figure 35 shows the circuit diagram and experimental layout for the single-string DC-MMC. Power exchange equation (14) remains valid for the single-string DC-MMC, but with (15) now defined as

Xv = -((¾_{m r})^_1 + OmLa- (17)

Note (17) implies the net circuit reactance can be either capacitive (<0) or inductive (>0). The converter in Figure 35(b) is designed with X_r > 0 as J_a is selected sufficiently large to limit the switching ripple that results from using a low number of SMs.

The open-loop voltage control in Figure 32 is adopted. The control logic is implemented on a real-time Linux based PC controller with integrated FPGA. Circuit and control parameters are given in Table 3.

Table 3 : Experimental Parameters for Figure 35

Converter Parameters Value

DC input network voltage, v_ln 480 V

Arm choke, L_a 5 mH

Midpoint capacitor, C_r/2 5.3 niF

SM capacitor, C_sm 2.4 mF

Output filter rms winding voltage, (Vj^max)_rms 66.5 V

Output filter rms winding current, (/™^a )_rms 16.7 A

Output filter magnetizing inductance. L 2210 mH

Output filter capacitor, C_f 10 μΈ

Fundamental modulating frequency, /_m 50 Hz

Switching frequency, /_sw 5 kHz

Control Parameters Value

Proportional gain, 0.2 A/V

Proportional gain, K_D' 2 V/A

Integral gain, A 12 A/Vs

Resonant gain, K! 600 V/As

Resonant damping term, ζ 0.01

High-pass filter pole, a 15 rad/s Experimental Validation: Step-Down Operation

Figure 36 shows experimental results for step-down operation with v_m = 478 V, v_out = 240 V and P_out = 4.0 kW. This experiment supplements the step-down PLECS simulation in Figure 33. To account for converter losses and switch dead-time, D is adjusted to provide the desired input/output voltage ratio of 0.5 and nominal SM capacitor voltage of 260 V. The AC voltage,!?, is set to achieve outer arms voltages of 94 V_pk (uncompensated); further details on the definition of "uncompensated" will be provided shortly.

In Figure 36 the positive pole AC modulating signals ¾^■■ ^l~^Tim and positive pole AC arms currents ^'< ^! i m exhibit similar phase relationships to those discussed for Figure 33; namely, ^L'ik and ^? ik are phase-shifted 180° while ¾ slightly lags i im as shown by Figure 31(a). Positive pole SM capacitor voltages ' ' ^η "<·ϊ^η demonstrate the average AC power exchange from outer arm to inner arm ensures proper charge balancing. Negative pole SM capacitor voltages ^'^ i ^{1 ■}■ ¼- i confirm the requisite AC power exchange also occurs between negative pole arms.

Experimental waveforms for the positive pole currents and input/output DC quantities are given in Figure 37. Figure 37(a) shows the switching ripple content which cannot be seen in the waveforms of Figure 36.

Observe from Figure 37(b) that i_m is effectively free of 50 Hz ripple. This shows AC currents used for SM capacitor power balancing can be confined to circulate within the converter structure despite typical load and parameter imbalances. Such validation is largely important to demonstrate the practical feasibility of the proposed energy conversion concept for the DC-MMC.

Experimental Validation: Step-Up Operation

Figure 38 shows experimental results for step-up operation with v_m = 478 V, v_out = 500 V and P_out = 4.2 kW. This experiment supplements the step-up PLECS simulation in Figure 34, as both utilize voltage conversion ratios greater than unity. D is adjusted to achieve a voltage conversion ratio of 1.05 and nominal SM capacitor voltage of 325 V. The AC voltage, Ϋ, is set to achieve outer arms voltages of 35 V_pk (uncompensated). Similar to Figure 34, ^Lik and ^?-ik are in phase while ' lm lags ^'Um by nearly 180°. This reflects delivery of average AC power from inner arm to outer arm as dictated by Figure 3 1(b). Note the average component of i\_m is small relative to the average value of z^'ik, which is consistent with the simulated step-up scenario in Figure 34. ^v k illustrates the outer arm FB/SM injects the appropriate bipolar voltage as required for D > 1. The steady-state responses of ·Α' <A" > ^v<n verifies SM capacitor power balance can in practice be achieved for step-up operation using the open loop voltage control scheme in Figure 32. SM capacitor voltage ripple for the inner and outer arms is 19.6 and 1 .8 V_pk-_Pk, respectively. The relatively large capacitor voltage ripple for the inner arms relative to the outer arms is consistent with Figure 34.

DC input and output experimental waveforms are shown in Figure 39. Similar to Figure 37(b), these waveforms validate the practical feasibility of the proposed energy conversion concept as the circulating AC currents remain internal to the DC-MMC structure.

Practical Control Consideration: Pole Asymmetry

Due to practical aspects such as component variation, unequal device losses and pole loading imbalances, the experimental setup in Figure 35(b) initially exhibited a small degree of asymmetry between poles. This asymmetry manifested itself by inciting a 50 Hz ripple in i_m. That is, a small net fundamental frequency AC voltage component existed across the input DC rails of the converter, due to imperfect AC voltage cancellation along the string. Sources of imperfect cancellation include: unequal circulating AC currents between poles, component variations between each C 2, J_r, J_a, or load impedance imbalance. Such scenarios do not occur in simulation where ideal conditions are imposed. As an example, the impact of uncompensated pole asymmetry on the step-down experiment in Figure 37(b) is illustrated by Figure 40. Here an undesired 50 Hz ripple component of i_m is seen to be 1 .4 A_pk-_Pk- To address this practical issue, an un-utilized degree of control freedom was exploited.

To eliminate the 50 Hz ripple in z^' _in, such as that shown in Figure 40, a slight magnitude and phase adjustment was made to the 50 Hz component of Vik. This strategy, conceptualized in Figure 29, was implemented for Figures 36 through 39. The key concept is that a small change in the 50 Hz component of vik causes a corresponding change in the circulating AC current z^'i_a. By using the appropriate AV and Αφ, the AC voltage drop across the positive pole C/2 can be shifted to achieve zero net AC voltage along the entire string. Although implemented for the positive pole, this scheme is equally valid for the negative pole. Table 4 lists the magnitude and phase adjustments used for the step-down and step-up experiments. Note only relatively small adjustments were required. These parameters were determined experimentally and added as fixed offsets to the control logic in Figure 32. Although sufficient to demonstrate efficacy of this compensation method, in practice closed loop regulation can be readily developed based on the concept of AC voltage adjustment.

Table 4: Uncompensated versus compensated 50 Hz component of Vi_k in Figure 35 to

eliminate 50 Hz i_m ripple

50 Hz component of t'n,

Operati ng Mode Uncompensated Compensated

Step- down 94. I.H:os ( i<',„i) 91.4 c s(w,„i 1 5.3" )

Step- up Sfi.S cosi -1- 5. -^ri^c )

Variations

Whereas specific embodiments of the invention are shown herein, variations are possible.

For example, the passive filters shown in Figure 1 are merely examples of possible filter types. That is, the feasible configurations for the input and output filters are not limited to the ones adopted in Figure 1.

Other filter designs achieving the necessary high-frequency waveform attenuation may be used. This includes use of coupled inductors for output filtering purposes as shown in Figure 9 and Figure 14.

Further, whereas Figure 1 shows input and output filters, it will be understood that the use of input filtering is optional.

As well, whereas the benefits of the topology are immense in the context of bipolar networks, this is not essential. As well, whereas specific operating conditions and parameters are disclosed as part of the simulations and others, persons of ordinary skill will understand that these are included for illustration, only, and are not intended to be limiting.

Accordingly, the invention should be understood as limited only by the accompanying claims, purposively construed.

Claims

Apparatus for coupling a pair of HVDC networks to one another for power transfer, the apparatus comprising: one or more strings, each string comprising two pairs of arms, each pair of arms being defined by an inner arm and an outer arm, series-stacked around an associated node, each arm being defined by a plurality of cascaded submodules; and in use, being connected to one of the networks such that the arms are arranged in symmetric relation about an associated midpoint, with the inner arms flanked by the outer arms, the nodes, in use, being coupled to the other of the networks , for transfer of DC power between the networks; and reactive circuit means for providing paths for AC current flow such that: each arm forms part of at least one path; each outer arm forms part of a path that is coextending at least in part to a path in respect of which the adjacent inner arm forms part; reactive components are incorporated such that each arm is in a path that includes a reactive element and such that near loss-less power exchange occurs between each outer arm and the adjacent inner arm to achieve power balance of submodules notwithstanding the DC power transfer.

Apparatus according to claim 1, wherein a choke is provided in each arm.

Apparatus according to claim 1, further comprising a capacitor and inductor, connected in series to one another and connected in parallel with the outer or inner arms, to define a low pass filter to ensure that the differential DC output voltage remains at a near constant potential.

4. Apparatus according to any one of claims 1 to 3, wherein the one or more strings consists of one string and the reactive circuit means comprises a capacitor for each pair of arms and connected in parallel therewith.

5. Apparatus according to any one of claims 1 to 3, wherein the one or more strings consists of two or more strings and the reactive circuit means in respect of one of the two or more strings includes another of the two or more strings.

6. Apparatus according to claim 5, wherein the reactive circuit means is defined in part by a

reactive structure linking the string midpoints together.

7. Apparatus according to claim 6, wherein the reactive structure linking the string midpoints

together is an inductive reactive structure.

8. Apparatus according to any one of claims 4 to 7, wherein the reactive circuit means includes an inductor in each arm.

9. Apparatus according to any one of claims 1 to 8, further comprising, for each of one or more of the strings, one or more additional arms, each of said one or more additional arms being deployed in parallel relation to an arm of said each string.

10. Apparatus according to any one of claims 1 to 9, wherein full-bridge function submodules define the cascaded submodules in respect of a plural portion of the cascaded submodules in the outer arms and the apparatus is capable of both step-up and step-down operation.

11. Use of the apparatus of claim 10 to couple two HVDC networks of substantially similar voltages.

12. Use of the apparatus of claim 10 to suppress fault currents, by controlling the submodules in the outer arms to impose the appropriate polarity of voltage during fault events.

13. Apparatus according to any one of claims 1 to 9, wherein the cascaded submodules in respect of the outer arms are defined by full-bridge function submodules.

14. Use of the apparatus of claim 13 to suppress fault currents, by controlling the full-bridge function submodules in the outer arms to impose the appropriate polarity of voltage during fault events.

15. Use of the apparatus of claim 13 to couple two HVDC networks of substantially similar voltages.

16. Apparatus for coupling a pair of unipolar HVDC networks to one another for power transfer, the apparatus comprising: one or more strings, each string comprising a pair of arms, series-stacked around an associated node, each arm being defined by a plurality of cascaded submodules, each string, in use, being connected to one of the networks; the other of the networks being coupled to the node of each string, for transfer of DC power between the networks; and reactive circuit means for providing paths for AC current flow such that: each arm forms part of at least one path; each outer arm forms part of a path that is coextending at least in part to a path in respect of which the adjacent inner arm forms part; reactive components are incorporated such that each arm is in a path that includes a reactive element and such that near loss-less power exchange occurs between each outer arm and the adjacent inner arm to achieve power balance of submodules notwithstanding the DC power transfer, wherein full-bridge function submodules define the cascaded submodules in respect of a plural portion of the cascaded submodules in the outer arms and the apparatus is capable of both step-up and step-down operation.

17. Apparatus according to claim 16, further comprising a capacitor and inductor, connected in series to one another and connected in parallel with the outer or inner arm, to define a low pass filter to ensure that the differential DC output voltage remains at a near constant potential.

18. Use of the apparatus of claim 16 to suppress fault currents, by controlling the submodules in the outer arms to impose the appropriate polarity of voltage during fault events.

19. Apparatus according to claim 16, wherein full-bridge function submodules define the cascaded submodules in the outer arms.

20. Use of the apparatus of claim 19 to suppress fault currents, by controlling the full-bridge function submodules in the outer arms to impose the appropriate polarity of voltage during fault events.

21. Apparatus according to one of claim 5 and claim 8, wherein the midpoints of each string are linked together without the interposition of a reactive structure.

22. Apparatus according to any one of claims 1 to 3, wherein the one or more strings comprises two or more strings and the reactive circuit means in respect of one of the strings of a pair of the strings includes the other of the pair.

23. Apparatus for coupling a pair of HVDC networks to one another for power transfer, the

apparatus comprising: one or more strings, each string comprising two pairs of arms, each pair of arms being defined by an inner arm and an outer arm, series-stacked around an associated node, each arm being defined by a plurality of cascaded submodules; and in use, being connected to one of the networks such that the arms are arranged in symmetric relation about an associated midpoint, with the inner arms flanked by the outer arms, the nodes, in use, being coupled to the other of the networks , for transfer of DC power between the networks; and means for providing paths for circulating AC currents such that: each arm forms part of at least one path and each outer arm forms part of a path that is coextending at least in part to a path in respect of which the adjacent inner arm forms part; and control action means for adjusting the magnitude and/or phase of the circulating AC currents to regulate the power exchange between each outer arm and the adjacent inner arm.

Apparatus for coupling a pair of HVDC networks to one another for power transfer, the apparatus comprising: one or more strings, each string comprising two pairs of arms, each pair of arms being defined by an inner arm and an outer arm, series-stacked around an associated node, each arm being defined by a plurality of cascaded submodules; and in use, being connected to one of the networks such that the arms are arranged in symmetric relation about an associated midpoint, with the inner arms flanked by the outer arms, the nodes, in use, being coupled to the other of the networks , for transfer of DC power between the networks; and means for providing paths for circulating AC currents such that: each arm forms part of at least one path and each outer arm forms part of a path that is coextending at least in part to a path in respect of which the adjacent inner arm forms part; and control action means for adjusting the magnitude and/or phase of the AC voltages for each inner arm and/or each outer arm to ensure that no circulating AC current enters the input HVDC network.

Apparatus according to claim 3, wherein the inductor is a coupled inductor.