WO2014166090A1 - Procédés de vérification de disponibilité de prédiction résiduelle inter-vue - Google Patents

Procédés de vérification de disponibilité de prédiction résiduelle inter-vue Download PDF

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Publication number
WO2014166090A1
WO2014166090A1 PCT/CN2013/074084 CN2013074084W WO2014166090A1 WO 2014166090 A1 WO2014166090 A1 WO 2014166090A1 CN 2013074084 W CN2013074084 W CN 2013074084W WO 2014166090 A1 WO2014166090 A1 WO 2014166090A1
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WO
WIPO (PCT)
Prior art keywords
residual prediction
ivrp
reference block
availability
tus
Prior art date
Application number
PCT/CN2013/074084
Other languages
English (en)
Inventor
Jicheng An
Kai Zhang
Jian-Liang Lin
Original Assignee
Mediatek Singapore Pte. Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mediatek Singapore Pte. Ltd. filed Critical Mediatek Singapore Pte. Ltd.
Priority to PCT/CN2013/074084 priority Critical patent/WO2014166090A1/fr
Publication of WO2014166090A1 publication Critical patent/WO2014166090A1/fr

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/597Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding specially adapted for multi-view video sequence encoding
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N2013/0074Stereoscopic image analysis
    • H04N2013/0081Depth or disparity estimation from stereoscopic image signals

Definitions

  • the invention relates generally to Three-Dimensional (3D) video processing.
  • the present invention relates to methods for inter-view residual prediction in 3D video coding.
  • 3D video coding is developed for encoding or decoding video data of multiple views simultaneously captured by several cameras. Since all cameras capture the same scene from different viewpoints, multi-view video data contains a large amount of inter-view redundancy. To share the previously encoded residual information of reference views, an additional tool called inter-view residual prediction has been integrated to the current HEVC based 3D video coding.
  • the inter-view residual prediction is based on a disparity vector (DV) derivation for the current block.
  • a DV is firstly derived for a current prediction unit (PU) and then the residual block in the reference view that is referenced by the DV is used for predicting the residual of the current PU.
  • PU current prediction unit
  • a more detailed illustration of the concept for deriving a reference block location inside the reference view is given in Fig 2.
  • a DV is firstly determined for current PU. The DV is added to the location of the top-left sample of the current PU yielding the location of the top-left sample of the reference block. Then, similar as for motion compensation, the block of residual samples in a reference view that is located at the derived reference location is subtracted from the current residual and only the resulting difference signal is transform coded.
  • the IVRP can be disabled by checking the mode or coded block flag (CBF) information of the reference block in the reference view.
  • CBF coded block flag
  • the inefficient reference residual block which contains mainly the zero residual samples would be removed from the IVRP mode so that the computational complexity is reduced.
  • Fig.l is a diagram illustrating the basic concept for inter-view residual prediction
  • Fig. 2 is a diagram illustrating the derivation of the location of reference residual block.
  • a DV is firstly derived for current PU and then the reference block in the reference view that is located by the DV is used for check the availability of IVRP for current PU.
  • the DV can be derived by the well-known neighbouring block-based DV (NBDV) method, depth-oriented NBDV (DoNBDV) method as shown in current HTM6.0, or other DV derivation methods.
  • NBDV neighbouring block-based DV
  • DoNBDV depth-oriented NBDV
  • the DV is added to the location of the top-left sample of the current PU yielding the location of the top-left sample of the reference block which has the same size as current PU.
  • One or more transform units (TUs) covered or partially covered by the reference block are selected.
  • the TU could be in any position of the reference block.
  • a typical selection is to use one TU in the center of the reference position, or to use four TUs in the four corners of the reference block.
  • IVRP is disabled when the TUs contain no non-zero CBF values or the TUs are intra coded.
  • the inefficient reference residual block which contains mainly the zero residual samples would be removed from the IVRP mode so that the computational complexity is reduced.
  • inter-view residual prediction methods described above can be used in a video encoder as well as in a video decoder.
  • Embodiments of disparity vector derivation methods according to the present invention as described above may be implemented in various hardware, software codes, or a combination of both.
  • an embodiment of the present invention can be a circuit integrated into a video compression chip or program codes integrated into video compression software to perform the processing described herein.
  • An embodiment of the present invention may also be program codes to be executed on a Digital Signal Processor (DSP) to perform the processing described herein.
  • DSP Digital Signal Processor
  • the invention may also involve a number of functions to be performed by a computer processor, a digital signal processor, a microprocessor, or field programmable gate array (FPGA).
  • processors can be configured to perform particular tasks according to the invention, by executing machine-readable software code or firmware code that defines the particular methods embodied by the invention.
  • the software code or firmware codes may be developed in different programming languages and different format or style.
  • the software code may also be compiled for different target platform.
  • different code formats, styles and languages of software codes and other means of configuring code to perform the tasks in accordance with the invention will not depart from the spirit and scope of the invention.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

L'invention concerne des procédés de vérification de disponibilité de l'IVRP (prédiction résiduelle inter-vue) pour codage vidéo multi-vue et codage vidéo 3D. L'invention propose de désactiver l'IVRP en vérifiant les informations CBF (Drapeau de bloc codé) du bloc de référence. Dans le procédé de la présente invention, le bloc résiduel de référence inefficace qui contient principalement les échantillons résiduels zéro serait supprimé du mode IVRP pour réduire la complexité de calcul.
PCT/CN2013/074084 2013-04-11 2013-04-11 Procédés de vérification de disponibilité de prédiction résiduelle inter-vue WO2014166090A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2013/074084 WO2014166090A1 (fr) 2013-04-11 2013-04-11 Procédés de vérification de disponibilité de prédiction résiduelle inter-vue

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2013/074084 WO2014166090A1 (fr) 2013-04-11 2013-04-11 Procédés de vérification de disponibilité de prédiction résiduelle inter-vue

Publications (1)

Publication Number Publication Date
WO2014166090A1 true WO2014166090A1 (fr) 2014-10-16

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012171442A1 (fr) * 2011-06-15 2012-12-20 Mediatek Inc. Procédé et appareil de prédiction et de compensation de vecteurs de mouvement et de disparité pour codage vidéo 3d
EP2579592A1 (fr) * 2011-10-04 2013-04-10 Thomson Licensing Procédé et dispositif de codage prédictif inter-vues, dispositif de décodage et support de stockage lisible sur ordinateur supportant les données codées d'un affichage

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012171442A1 (fr) * 2011-06-15 2012-12-20 Mediatek Inc. Procédé et appareil de prédiction et de compensation de vecteurs de mouvement et de disparité pour codage vidéo 3d
EP2579592A1 (fr) * 2011-10-04 2013-04-10 Thomson Licensing Procédé et dispositif de codage prédictif inter-vues, dispositif de décodage et support de stockage lisible sur ordinateur supportant les données codées d'un affichage

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"ITU STUDY GROUP 16 Question 6. HEVC Extension for Multiview Video Coding and Multiview Video plus Depth Coding", VCEG 44ND MEETING., 17 April 2012 (2012-04-17), Retrieved from the Internet <URL:http://www.itu.int/md/T09-SG16-C-0946/en> [retrieved on 20131118] *

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