WO2014163183A1 - Semiconductor memory device - Google Patents

Abstract

The purpose of the present invention is to decrease the layout size of a sense amplifier and reduce the current consumption of bit lines in a semiconductor memory device that uses a memory cell that inverts the voltage supplied during writing and the voltage detected during reading. A semiconductor memory device comprises the memory cell that is connected between the bit lines and a power source node, and a word line that is connected to a control terminal of the memory cell. Moreover, the device comprises a sense amplifier having a retaining circuit that temporarily stores data read from the memory cell, and a read-write switch that is connected between the bit lines and a first node of the retaining circuit. Furthermore, the device comprises a counter that is provided to correspond to a word line, counts the number of times the word line is activated, and outputs a data inversion control signal indicating whether the count is odd or even, and an external output circuit that performs inversion/non-inversion of data on the basis of the data inversion control signal when data in the sense amplifier retaining circuit is externally input or output.

Description

Semiconductor memory device

(Description of related applications)
The present invention is based on the priority claim of Japanese Patent Application: Japanese Patent Application No. 2013-079775 (filed on April 5, 2013), the entire contents of which are incorporated herein by reference. Shall.
The present invention relates to a semiconductor memory device. In particular, the present invention relates to a thyristor memory or an FBC (Floating Body Cell) memory that accumulates charges in a floating body.

As the current large-capacity semiconductor memory device, DRAM is the most common and widely used in computer systems and the like. However, DRAM is said to reach the limit of miniaturization in the next few years. Therefore, research and development of various large-capacity semiconductor memory devices have been conducted for the purpose of replacing DRAM. Among them, the following prior art is disclosed for a floating body memory that accumulates electric charges in a floating body of a thyristor or a bipolar transistor. Like the DRAM, these floating body memories are also classified as volatile memories that require a refresh operation at regular intervals.

Patent Document 1 discloses a thyristor memory having a structure that does not require a MOS transistor. Generally, in the thyristor memory, since information is stored by accumulating charges in the gate capacitance between the gate of the MOS transistor and the body node FB, there is a problem that the cell leak current increases due to the GIDL current of the MOS transistor. According to the thyristor memory described in Patent Document 1, since it is not necessary to use a MOS transistor, cell leakage current is small and miniaturization is possible.

Further, Patent Document 1 discloses a semiconductor memory device in which a memory cell array is constituted by the thyristor memory. In the semiconductor memory device, the FB (floating body) of each thyristor memory is connected to a word line WL via a capacitor, and the anode of each thyristor memory is connected to a bit line BL. Patent Document 1 discloses a method of controlling the word line WL and the bit line BL in each operation of cell writing of the cell High, cell writing of the cell Low, and cell reading (cell writing is illustrated in FIG. For cell readout, see FIG. 8 of Patent Document 1).

Patent Document 2 discloses a semiconductor memory device in which a memory cell array is configured by an FBC memory. The semiconductor memory device includes a burst length counter that counts the number of accesses to the column in the burst mode, and the sense amplifier SA corresponding to the bit line BL when the burst length counter becomes equal to a preset burst length. The sense node is controlled to be electrically connected. As a result, current consumption during writing in the burst mode is reduced.

JP 2012-234940 A JP 2008-52876 A JP 2011-70727 A

The following analysis is given from the viewpoint of the present invention.

It should be noted that the disclosure of Patent Document 1 above is incorporated herein by reference.

A thyristor memory or FBC memory has a property that a voltage supplied to a bit line at the time of writing and a voltage detected by the bit line at the time of reading are inverted. Therefore, the sense amplifier of Patent Document 1 includes a first node (inverted sense amplifier bit line BLSAB in FIG. 15) in the sense amplifier and a read switch (transistors N22 and N22A in FIG. 15) that connects the bit line, and a second node. There are provided two types of switches: a non-inverted sense amplifier bit line BLSAT in FIG. 15 and a write switch (transistors N3 and N3A in FIG. 15) connecting the bit lines. Then, the voltage of the bit line is detected at the first node via the read switch at the time of reading, and writing is performed by supplying the voltage from the second node to the bit line via the write switch at the time of writing. This corresponds to the problem that the voltage of 1 is reversed between reading and writing.

However, in the above configuration, there is a problem that the layout size increases because it is necessary to provide a read switch and a write switch for each sense amplifier.

Also, when data is read from the thyristor memory or FBC memory and written back, it is necessary to charge and discharge the bit line as the voltage of the bit line is reversed when shifting from the read operation to the write back operation. At this time, current consumption increases. In particular, when a bit line has a coupling capacitance between adjacent bit lines and different data is handled between the bit line and the adjacent bit line, current consumption due to charging / discharging of the coupling capacity is extremely high. There is a problem of becoming larger.

Therefore, in a semiconductor memory device using a memory cell in which the voltage detected at the time of reading and the voltage supplied at the time of writing are inverted, such as a thyristor memory or an FBC memory, the layout size of the sense amplifier is reduced and the current consumption of the bit line is reduced. Reduction is desired.

The semiconductor memory device according to the first aspect of the present invention includes the following components. That is, the semiconductor memory device is connected between a bit line and a power supply node, and a memory cell in which stored data is inverted when data is written back without inverting the voltage detected at the time of reading, and the memory cell And a word line connected to the control terminal. Further, the semiconductor memory device includes a sense amplifier having a holding circuit that temporarily stores read data from the memory cell, and a read / write switch connected between the first node of the holding circuit and the bit line. Including. The semiconductor memory device includes a counter provided corresponding to the word line, counting the number of times the word line is activated, and outputting a data inversion control signal indicating whether the number is even or odd. . Further, the semiconductor memory device includes an external input / output circuit that performs inversion / non-inversion of data based on the data inversion control signal when data of the holding circuit of the sense amplifier is input / output externally.

According to the present invention, in the semiconductor memory device using the memory cell in which the voltage detected at the time of reading and the voltage supplied at the time of writing are inverted, the layout size of the sense amplifier is reduced and the current consumption of the bit line is reduced. It is possible to provide a semiconductor memory device that can contribute.

1 is a block diagram showing a configuration of a semiconductor memory device according to one embodiment. 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment. FIG. 3 is a circuit diagram showing a SWL counter circuit of the semiconductor memory device according to the first embodiment. 1 is a circuit diagram showing a memory cell of a semiconductor memory device according to a first embodiment. 1 is a circuit diagram of a sense amplifier of a semiconductor memory device according to a first embodiment. FIG. 6 is a waveform diagram showing an operation of the semiconductor memory device according to the first embodiment. FIG. 6 is a circuit diagram showing a memory cell of a semiconductor memory device according to Modification 1 of the first embodiment. FIG. 6 is a circuit diagram showing a memory cell of a semiconductor memory device according to a second modification of the first embodiment. FIG. 10 is a circuit diagram showing a memory cell of a semiconductor memory device according to Modification 3 of the first embodiment. It is a block diagram which shows the structure of the semiconductor memory device which concerns on 2nd Embodiment. FIG. 5 is a diagram illustrating a configuration of a counter cell and a counter amplifier for a counter cell of a semiconductor memory device according to a second embodiment. FIG. 6 is a circuit diagram of a buffer circuit of a semiconductor memory device according to a second embodiment. FIG. 6 is a waveform diagram showing an operation of the semiconductor memory device according to the second embodiment. It is a block diagram which shows the structure of the semiconductor memory device of a comparative example. It is a circuit diagram of the sense amplifier of the semiconductor memory device of a comparative example. It is a wave form diagram which shows operation | movement of the semiconductor memory device of a comparative example.

First, an outline of an embodiment of the present invention will be described. Note that the reference numerals of the drawings added in the description of the outline of the embodiment are merely examples for helping understanding, and are not intended to be limited to the illustrated modes.

As shown in FIG. 1, the semiconductor memory device 100 in one embodiment includes the following components. That is, the semiconductor memory device 100 is connected between the bit line (BL) 120 and the power supply node 102, and the memory cell in which the stored data is inverted when the voltage detected at the time of reading is written back without being inverted. 101 and a word line (WL) 122 connected to the control terminal 103 of the memory cell. The semiconductor memory device 100 includes a holding circuit 106 that temporarily stores read data from the memory cell 101, and a read / write switch connected between the first node 107 of the holding circuit 106 and the bit line (BL) 120. 105, and a sense amplifier 109. The semiconductor memory device 100 is provided corresponding to the word line (WL) 122, counts the number of times the word line (WL) 122 is activated, and indicates a data inversion control signal indicating whether the number is even or odd. 14 is included. The semiconductor memory device 100 further includes an external input / output circuit 108 that inverts / non-inverts data based on the data inversion control signal 14 when the data of the sense amplifier holding circuit 106 is externally input / output. .

In the above configuration, the node in the sense amplifier connected to the bit line (BL) 120 is not changed during reading and writing back (in either case, the node is connected to the first node). Therefore, the memory cell 101 on the activated word line (WL) 122 inverts the cell High / cell Low every time the word line (WL) 122 is activated. However, in accordance with the data inversion control signal 14, the logic of the data when externally output is inverted / non-inverted, so that the logic of the data output externally can be in a correct state. In addition, when data is externally input, data corresponding to the data inversion control signal 14 can be written into the holding circuit 106 by inverting / non-inverting the logic of the data in accordance with the data inversion control signal 14.

As described above, the logic of external data can be handled without changing the node in the sense amplifier connected to the bit line (BL) 120 during reading and writing back. Therefore, the switch connecting the bit line (BL) 120 and the node in the sense amplifier can be configured by one read / write switch 105, and the layout size of the sense amplifier can be reduced.

In addition, since it is not necessary to invert the voltage of the bit line (BL) 120 at the time of reading and writing back, the charge / discharge of the bit line (BL) 120 and the bit line are changed when shifting from the reading operation to the writing back operation. Charging / discharging of the coupling capacitance (111 in FIG. 1) between (BL) 120 and adjacent bit line (adjacent BL) 131 is reduced. In particular, when different data is handled in the bit line 120 and the adjacent bit line 131, the effect of reducing the charge / discharge of the coupling capacitance (111 in FIG. 1) is great. This reduces current consumption.

In the semiconductor memory device 100, at the time of reading, the read / write switch 105 is turned on to read data in the memory cell 101 to the first node 107 of the sense amplifier 109 via the bit line (BL) 120. The data is temporarily stored in the holding circuit 106, and at the time of writing back, the read / write switch 105 is turned on, and the voltage of the first node 107 of the sense amplifier 109 is supplied to the bit line (BL) 120 without being inverted. You may make it write back to.

As in the semiconductor memory device 21 shown in FIG. 2, the counter 104 may be constituted by a counter circuit (23 in FIG. 3) that counts up upon activation of the word line WL.

On the other hand, like the semiconductor memory device 22 shown in FIGS. 10 and 11, the counter 104 may be composed of a counter cell 16 a that is substantially the same as the memory cell 26. Here, the counter cell 16a corresponding to the word line (sub word line 7 in FIGS. 10 and 11) reads / writes simultaneously with the memory cell 26 connected to the word line (sub word line 7 in FIGS. 10 and 11). A write operation may be performed, and the data inversion control signal 14 may be generated based on the read data of the counter cell 16a.

In the semiconductor memory device 22, as shown in FIG. 11, the counter amplifier for the counter cell (49: CSA in FIG. 11) corresponds to the counter cell 16a and is substantially the same as the sense amplifier (19: SA in FIG. 5). ) May be further provided.

In the semiconductor memory device 22, as shown in FIG. 11, the first node (corresponding to BLSAB in the CSA) of the holding circuit of the counter cell sense amplifier CSA and the second node complementary to the first node (in the CSA) A buffer circuit 15 for generating a data inversion control signal 14 based on a signal of a counter IO line pair (corresponding to the CIOB line and the CIOT line in FIG. 11) electrically connected to the BLSAT). May be.

In the semiconductor memory device (21 in FIG. 2, 22 in FIG. 10, etc.), the memory cell 26 is a memory that stores data by accumulating charges in the floating body FB, as shown in FIGS. The floating body FB may be connected to the control terminal 103 of the memory cell via capacitors C1, C2, etc., including elements (thyristor 36 in FIG. 4, bipolar transistor 37 in FIG. 7, etc.).

In the semiconductor memory device (21 in FIG. 2, 22 in FIG. 10, etc.), the memory cell 26 may be the memory cell 26 of the thyristor memory shown in FIG. In this case, the memory element is the thyristor 36, the anode 221 of the thyristor is connected to the bit line BL, the cathode 222 of the thyristor is connected to the power supply node 102, and the gate 223 of the thyristor constitutes the floating body FB. May be.

In the semiconductor memory device (21 in FIG. 2, 22 in FIG. 10, etc.), the memory cell may be the memory cell 27 of the FBC memory shown in FIG. In that case, the memory element is the bipolar transistor 37, the collector of the bipolar transistor 37 is connected to the bit line BL, the emitter of the bipolar transistor 37 is connected to the power supply node 102, and the base of the bipolar transistor 37 is connected to the floating body FB. You may make it comprise.

The semiconductor memory device (21 in FIG. 2, 22 in FIG. 10 and the like) further includes a word line driver (sub word line driver 3 in FIG. 2) for controlling the voltage of the word line WL, and as shown in FIG. When the read operation is performed by activating the line WL, the word line driver 3 holds the voltage of the word line WL at the word line standby voltage VWSL, and the sense amplifier (19 in FIG. 5) sets the bit line BL to the first voltage. After the first control (T1 in FIG. 6) to precharge (VARY in FIG. 6) and the first control, the word line driver 3 sets the word line WL to the word line read voltage VWLR, and then the sense amplifier A second control (T2 to T4 in FIG. 6) for canceling the precharge of the bit line BL and reading out the data of the memory cell (26 in FIG. 5) from the bit line BL to the sense amplifier 19; It may be performed.

In the semiconductor memory device (21 in FIG. 2, 22 in FIG. 10, etc.), as shown in FIG. 6, the data read to the sense amplifier (19 in FIG. 5) is written into the memory cells (26 in FIG. 5). In the case of performing the returning operation, the third control (T5 in FIG. 6) for setting the data voltage read by the sense amplifier 19 to the bit line BL without inversion, and after the third control, the word line driver ( The sub-word line driver 3) in FIG. 2 sets the word line WL to the word line write voltage VWLW that is higher than the word line read voltage VWLR (T6 in FIG. 6), and after the fourth control, A fifth control (T7 in FIG. 6) in which the word line driver 3 sets the word line WL to the word line precharge voltage VWLP which is an intermediate voltage between the word line read voltage VWLR and the word line standby voltage VWLS; After the control 5, the sixth control (T 8 in FIG. 6) in which the sense amplifier 19 sets the bit line BL to the first power supply voltage VSS supplied to the power supply node (102 in FIG. 4), After the control, the word line driver 3 may perform a seventh control (T9 in FIG. 6) for returning the voltage of the word line WL to the word line standby voltage VWLS.

In the semiconductor memory device (21 in FIG. 2, 22 in FIG. 10, etc.), as shown in FIG. 2 or FIG. 7, a plurality of word lines WL wired in the first direction intersect with the first direction. A plurality of bit lines BL wired in the second direction and a plurality of memory cells provided corresponding to the intersections of the plurality of word lines WL and the plurality of bit lines BL (memory cells 26 included in the cell region 1) ), A plurality of sense amplifiers (sense amplifier 19 included in the sense amplifier region 2) respectively provided corresponding to the plurality of bit lines BL, and a plurality provided respectively corresponding to the plurality of word lines WL. Counter (the SWL counter circuit 23 included in the SWL counter area 13 of FIG. 2 or the counter cell 16a of FIG. 11).

In the semiconductor memory device (21 in FIG. 2, 22 in FIG. 10, etc.), the plurality of word lines WL have a hierarchical structure composed of main word lines and sub word lines SWL, and a plurality of counters (SWL counter area in FIG. 2). SWL counter circuit 23 and counter cell 16a in FIG. 11) may be provided corresponding to a plurality of sub word lines SWL.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

[First Embodiment]
(Configuration of the first embodiment)
The configuration of the first embodiment will be described in detail with reference to FIGS. FIG. 2 is a block diagram showing the configuration of the semiconductor memory device 21 according to the first embodiment, and mainly shows the configuration of the memory cell array and its peripheral portion. As shown in FIG. 2, the memory cell array of the semiconductor memory device 21 is divided into a plurality of cell regions 1 and arranged. The word lines are configured by a hierarchical structure of main word lines (not shown) and sub word lines 7, and a plurality of memory cells 26 in each cell region 1 are arranged at intersections of the plurality of sub word lines 7 and the plurality of bit lines 8. Is done.

As shown in FIG. 2, the plurality of sub word lines 7 in each cell region 1 are connected to two sub word line drivers 3 adjacent to both sides of each cell region 1 so as to be distributed evenly and oddly.

In addition, the plurality of bit lines 8 in each cell region 1 are distributed and connected to the sense amplifiers 19 (FIG. 5) in two sense amplifier regions 2 adjacent to both sides of each cell region 1, evenly and oddly. . The sense amplifier 19 (FIG. 5) detects the voltage of the bit line 8 at the time of reading, and supplies a voltage corresponding to the write data to the bit line 8 at the time of writing.

The address input to an address input circuit (not shown) is decomposed into a column address and a row address and supplied to the Y decoder 5 and the X decoder 4 respectively. Then, the sub word line 7 selected by the X decoder 4 is activated. Further, the sense amplifier 19 (FIG. 5) corresponding to the column selection signal (YS) 9 selected by the Y decoder 5 is selected.

Further, in the upper cell region 1 in FIG. 2, the connection between the sense amplifier region 2 and the data amplifier 6 is shown (the other sense amplifier regions 2 are not shown), but the same. As shown in FIG. 2, each sense amplifier 19 in the sense amplifier region 2 is connected to the data amplifier 6 via an inverted IO line IOB and non-inverted IO lines IOT (10a, 10b). For example, at the time of reading, the data amplifier 6 uses the inverted IO line IOB and the non-inverted IO line IOT (10a, 10b) for the data of the flip-flop (FF in FIG. 5) holding the signal detected by each sense amplifier 19. ) And amplifies the read data. The data amplifier 6 outputs the amplified data to the data input / output circuit 11. The data input / output circuit 11 further amplifies the signal and outputs it from the data input / output terminal 12 as external data. The data amplifier 6 and the data input / output circuit 11 in FIG. 2 correspond to the external input / output circuit 108 in FIG. 1 referred to in the outline description of the embodiment.

At the time of writing, when external data is input from the data input / output terminal 12, the flip-flop (FF in FIG. 5) of the sense amplifier 19 corresponding to the write address is passed through the data input / output circuit 11 and the data amplifier 6. Data is written to

Next, the data inversion control signal generation unit 32 (inside the one-dot chain line in FIG. 2) of FIG. 2 will be described. The data inversion control signal generation unit 32 includes a SWL counter area 13 provided corresponding to each sub word line 7 in the same direction as the X decoder 4, and a sub word line driver 3 that supplies the sub word line 7 to each SWL counter area 13. , Including.

Each SWL counter area 13 includes a SWL counter circuit 23 (FIG. 3) connected to each sub word line 7. Details of the SWL counter circuit 23 will be described later.

The data inversion control signal generation unit 32 inverts / non-inverts data when external input / external output is performed on data of the memory cell 26 connected to the sub word line 7 selected and activated by the X decoder 4. The function of generating the data inversion control signal 14 for controlling the above is fulfilled. The data inversion control signal generation unit 32 corresponds to the data inversion control signal generation unit 112 in FIG. 1 referred to in the outline description of the embodiment.

Next, the SWL counter circuit 23 arranged in the SWL counter area 13 will be described with reference to FIG. FIG. 3 is a circuit diagram showing the SWL counter circuit 23 of the semiconductor memory device 21. In the SWL counter area 13, a SWL counter circuit 23 is provided for each sub word line 7. FIG. 3 shows the SWL counter circuit 23 connected to the sub word lines SWL_i−1, SWLi, and SWL_i + 1. Of these, details of the SWL counter circuit 23 connected to the sub word line SWLi are shown.

As shown in FIG. 3, the SWL counter circuit 23 includes a latch circuit composed of inverter circuits INV2 and INV3, a latch circuit composed of inverter circuits INV4 and INV5, N-type transistors M1 and M2, and an inverter INV1. Constitutes one flip-flop circuit. In the flip-flop circuit, the voltage of the sub word line SWLi and the voltage complementary to SWLi are supplied to the gates of the N-type transistors M1 and M2, respectively, and the on / off of the NMOS transistors M1 and M2 is controlled exclusively. Then, the output of the flip-flop circuit (node NC3) is fed back to the input of the flip-flop circuit (one of the source and drain of the N-type transistor M1) via the inverter INV6 to constitute a 1-bit counter circuit. Yes.

The 1-bit counter circuit counts up at each falling edge timing of SWLi and operates to switch between 0 and 1 of the node NC1 of the output of the 1-bit counter circuit. In other words, the 1-bit counter circuit sets the node NC1 to 0 when the number of times that the falling edge of the sub word line SWLi is detected is an even number, and sets the number of times that the number of times that the falling edge of the sub word line SWLi is detected to be an odd number. Node NC1 is set to 1.

The N-type transistor M3 functions as a switch for selecting the SWL counter circuit 23 corresponding to the activated sub word line 7. For example, when SWLi is activated and is at a high level, the N-type transistor M3 of the SWL counter circuit 23 connected to SWLi is turned on, and the voltage of the node NC1 is output as the data inversion control signal 14. On the other hand, when none of the sub word lines 7 is activated, the data inversion control signal 14 is in a floating state.

Next, a memory cell used in the semiconductor memory device 21 will be described with reference to FIG. In the semiconductor memory device 21, the memory cell 26 of the thyristor memory described in Patent Document 1 is used as the memory cell 26. FIG. 4A corresponds to FIG. FIG. 4B shows a circuit diagram symbol of the thyristor 36.

In the memory cell 26 of the thyristor memory of FIG. 4A, the sub word line connection terminal 103a, the bit line connection terminal 110a, and the power supply node 102 are connected to the sub word line 7, the bit line 8, and the ground VSS, respectively. A capacitor C1 is provided between the floating body FB (thyristor gate 223) and the sub word line connection terminal 103a. The anode 221 of the thyristor and the cathode 222 of the thyristor are connected to the bit line connection terminal 110a and the power supply node 102, respectively.

The thyristor 36 has an emitter connected to the cathode 222, a base connected to the floating body FB, an NPN transistor Q1 connected to the node FN, an emitter connected to the anode 221, a base connected to the node FN, and a collector connected to the floating body FB. A connected PNP transistor Q2 is provided. As shown in FIG. 4A, the memory cell 26 is a memory cell of a thyristor memory having a structure not including a MOS transistor.

(Operation principle of memory cell of thyristor memory)
Next, the operation principle of the memory cell 26 of the thyristor memory will be described with reference to the circuit diagram of FIG. When the voltage of the FB node is increased from a low voltage through the capacitor C1, when the voltage between the FB node and the cathode (VSS) reaches near the voltage of the built-in potential VBI of the PN junction, the FB node Diode forward current begins to flow from to the cathode (VSS). This current is equivalent to the base-emitter current of the NPN transistor Q1.

If the voltage of the FB node is increased through the capacitance of the capacitor C1 when the bit line BL (anode) is sufficiently high, the NPN transistor Q1 is weakly turned on when the voltage VBI is reached and the node FN is turned on. It goes down to a low level, which turns on the PNP transistor Q2 to raise the FB node to a higher voltage. As a result, the NPN transistor Q1 is turned on more strongly, and the anode (BL) and the cathode VSS of the thyristor 36 become conductive.

Once the thyristor 36 is in a conductive state, as long as a sufficiently high voltage is applied to the bit line BL (anode), the conductive state is maintained even if a coupling voltage is applied to the FB node via the capacitance of the capacitor C1.

The non-conduction of the thyristor 36 is performed by setting the potential difference between the anode (BL) and the cathode (VSS) to a small potential difference equal to or lower than the voltage VBI. When the bit line BL is set to the voltage VBI or lower, the FB node is lowered to the voltage VBI or lower due to the leakage current of the PN junction. As a result, the NPN transistor Q1 is turned off, so that the anode (BL) and the cathode (VSS) of the thyristor 36 are turned off.

Next, the sense amplifier 19 will be described in detail with reference to FIG. FIG. 5 is a circuit diagram of the sense amplifier 19 of the semiconductor memory device 21 according to the first embodiment. A bit line (BL) 8 is connected to the sense amplifier 19 from the cell region, and a bit line (BLA) 8 is connected to another adjacent cell region A. In FIG. 5, the drain of the N-type transistor N1 is connected to the bit line (BL) 8, the gate of the N-type transistor N1 is connected to the control signal BLDIS, and the source is connected to the power supply VSS. Similar to the N-type transistor N1, the N-type transistor N1A is connected to the bit line (BLA) 8. The N-type transistors N1 and N1A fix the potential of the bit line (BL, BLA) 8 to the level of the power supply VSS when the bit line (BL, BLA) 8 is not selected (standby), respectively.

One of the source and drain of the N-type transistor N2 (read / write switch) is connected to the bit line (BL) 8, the inverted sense amplifier bit line BLSAB (first node) is connected to the other of the source and drain, and the gate is connected. A control signal TG is connected. The control signal TG is a signal that is activated and becomes a high level when the voltage of the bit line 8 is detected at the time of reading and when the voltage corresponding to the write data is supplied to the bit line 8 at the time of writing. When the control signal TG is at a high level, the bit line (BL) 8 and the inverted sense amplifier bit line BLSAB (first node) are electrically connected. Similarly, an N-type transistor N2A (read / write switch) is provided between the bit line (BLA) 8 and the inverted sense amplifier bit line BLSAB, and a control signal TGA is connected to the gate of the N-type transistor N2A.

A flip-flop F. between the inverting sense amplifier bit line BLSAB (first node) and the non-inverting sense amplifier bit line BLSAT (second node). F. Is provided to amplify the potential difference between the inverted sense amplifier bit line BLSAB and the non-inverted sense amplifier bit line BLSAT. Flip-flop F.F. F. Includes P-type transistors P5 and P6 and N-type transistors N4 and N5. Also, flip-flop F.F. F. Is connected to SAP as the power source of the P-type transistor and SAN as the power source of the N-type transistor. The power supplies SAP and SAN are flip-flops F. F. It is activated only when the operation is required. When activated, the power supply SAP has the same potential as the power supply VARY, and the power supply SAN has the same potential as the power supply VSS. The maximum amplitude of the bit line 8 is determined by the voltages of the power supplies SAP and SAN and the voltage of the power supply VARY. When inactive, the power supply SAP has the same potential as the power supply VSS, and the power supply SAN has the same potential as the power supply VARY. Note that the flip-flop F.F. F. Functions as a holding circuit for temporarily storing data read from the memory cell 26, and corresponds to the holding circuit 106 of FIG. 1 referred to in the outline description of the embodiment.

The N-type transistor N6 is a switch that connects the inverted sense amplifier bit line BLSAB and the inverted IO line IOB, and the N-type transistor N7 is a switch that connects the non-inverted sense amplifier bit line BLSAT and the non-inverted IO line IOT. is there. Both N-type transistors N6 and N7 are controlled to be conductive / non-conductive by a column selection signal YSi. Flip-flop F.F. F. When externally writing data to the flip-flop F. F. When the data held in the memory is read out, the inverted sense amplifier bit line BLSAB and the inverted IO line IOB, and the non-inverted sense amplifier bit line BLSAT and the non-inverted IO line IOT are connected via the N-type transistors N6 and N7. , Input and output data.

The P-type transistor P1 is connected between the inverted sense amplifier bit line BLSAB and the bit line activation power supply VARY. The P-type transistor P2 is connected between the non-inverting sense amplifier bit line BLSAT and the bit line determination reference power supply VBLREF. Control signals ACTB1 and ACTB2 are connected to the gates of the P-type transistors P1 and P2, respectively. The control signals ACTB1 and ACTB2 are activated and become low level during the read operation.

The P-type transistors P3 and P4 are connected in series between the inverted sense amplifier bit line BLSAB and the power supply VARY, and a control signal ACT2B and a constant current reference voltage VIREF are supplied to the gates of the P-type transistors P3 and P4, respectively. The P-type transistor P4 functions as a constant current source and is set to a constant current reference voltage VIREF = about VARY−VTP (where VTP is a threshold voltage of the P-type transistor P4). The P-type transistor P3 is turned on during the read period (T1 to T3 in FIG. 6).

(Operation of the first embodiment)
Next, the operation of the first embodiment will be described with reference to FIG. FIG. 6 shows operation waveforms when the semiconductor memory device 21 is operated in compliance with DRAM (Dynamic Random Access Memory) specifications. As basic operation specifications of a DRAM, there are an access operation for reading or writing data in a memory cell to the outside, and a refresh operation for refreshing cell data at regular intervals.

In the access operation, an ACT command is given from the outside, and in response to a designated row address and ACT command, a word line (main word line and sub word line 7) is selected and connected to the activated sub word line 7. Data is read from the memory cell 26 to the corresponding sense amplifier 19. Next, when a READ command is given, the data read to the sense amplifier 19 is output to the outside via the IO lines (IOB and IOT) based on the designated column address. When a WRITE command is given from the outside, the external data is supplied to the flip-flop F.F of the sense amplifier 19 corresponding to the designated column address. F. Write until.

Next, when the PRE (precharge) command is given, the flip-flop F.F. F. The write data stored in is actually written into the memory cell. At this time, in the sense amplifier 19 other than the sense amplifier corresponding to the column address specified by the WRITE command, the data of the memory cell 26 read by the ACT command is stored, and the stored data is stored in the memory cell 26. Written back.

In the refresh operation, a refresh command is given from the outside, an ACT command and a refresh word line address are issued inside the semiconductor memory device 21, and then a PRE command is issued to perform refresh. That is, the data of the memory cell 26 read by the ACT command is written back to the memory cell 26.

As described above, both the access operation and the refresh operation are performed in the order of the ACT command to the PRE command. Here, in the ACT command and the PRE command, all the memory cells 26 connected to the selected and activated sub word line 7 simultaneously perform the ACT operation and the PRE operation, respectively. FIG. 6 shows a refresh operation only for the ACT operation and the PRE operation. In the access operation, a READ command or a WRITE command (not shown) is executed between the ACT command and the PRE command.

The waveforms of the sub-word line 7 and the bit line 8 in FIG. 6 are as follows: the memory cell 26 connected to the sub-word line (7: SWLi) and the bit line (8: BL) in the cell region of FIG. ) And the memory cell 26n connected to the adjacent bit line (8n: adjacent BL).

Next, the contents of each waveform displayed in FIG. 6 will be described in order. BLDIS, TG, ACT1B, and ACT2B are control signals supplied to the sense amplifier 19. SAP and SAN are the flip-flops F. F. Power supply voltage supplied to the P-type transistors P5 and P6 and the N-type transistors N4 and N5. SWLi indicates the voltage of the activated sub word line 7 (voltage driven by the sub word line driver 3). BL and adjacent BL indicate the voltages of the bit line 8 and the adjacent bit line 8n. Further, the voltages of the inverted sense amplifier bit line BLSAB, the non-inverted sense amplifier bit line BLSAT, and the voltage of the FB of the memory cell 26 are displayed in an overlapping manner. NC1 is the voltage of the node NC1 of the SWL counter circuit 23 connected to the activated sub word line SWLi. Further, the voltage of the data inversion control signal 14 is shown.

Next, the operation at each timing of T1 to T9 in FIG. 6 will be described. First, it is in a standby state until timing T1. That is, at this time, the sub word line 7 is in a non-selected state. Further, the control signal BLDIS is at the high level and the control signal TG is at the low level, and the bit line 8 is disconnected from the inverted sense amplifier bit line BLSAB of the sense amplifier 19 and fixed at the low level (VSS). Further, the flip-flop F.F. F. The power supply SAP supplied to the power supply is low level and the power supply SAN is high level. F. Is inactive, and the non-inverted sense amplifier bit line BLSAT and the inverted sense amplifier bit line BLSAB are in a floating state.

Further, the control signals ACTB1 and ACTB2 are also inactive high level. In FIG. 6, it is assumed that the memory cell 26 stores the state of the cell Low and the FB node is the voltage VL.

Suppose that the node NC1 of the SWL counter circuit 23 (FIG. 3) is at a low level. In addition, any subword line SWL is inactive, the N-type transistor M3 of any SWL counter circuit 23 is in an off state, and the data inversion control signal 14 is in a floating state.

When an ACT command is given from the outside, at the timing T1, the control signal BLDIS is set to the low level, and the bit line 8 is released from the state fixed at the low level (VSS), and ACTB1, ACTB2 The signal becomes low level and activated, and the inverted sense amplifier bit line BLSAB is set to the voltage VARY, and the non-inverted sense amplifier bit line BLSAT is set to the voltage VBLREF. Further, the control signal TG is activated and the inverted sense amplifier bit line BLSAB and the bit line 8 are connected. Then, the bit line 8 is driven by the voltage VARY of the inverting sense amplifier bit line BLSAB, and the voltage of the bit line 8 also rises to the voltage VARY.

At timing T2, the sub word line driver 3 increases the voltage of the sub word line SWLi to the word line read voltage VWLR. When the voltage of the sub word line SWLi rises to the word line read voltage VWLR at timing T2, the voltage of the FB node is also raised through the capacitor C1 of the memory cell 26. Although the memory cell 26 is in the cell low state and the FB node rises from the voltage VL, it does not rise to the voltage VBI at which the memory element (thyristor 36) becomes conductive. Therefore, the memory element (thyristor 36) is non-conductive.

Further, at timing T2, the control signal ACTB1 is raised to a high level to be inactivated, the inverted sense amplifier bit line BLSAB is released from the state where it is strongly fixed to the voltage VARY, and the control signal ACTB2 is at the low level. Therefore, the voltage VARY is weakly supplied by the constant current source of the P-type transistor P4. The inverted sense amplifier bit line BLSAB is connected to the bit line 8 via an N-type transistor N2 (read / write switch). Here, since the memory element (thyristor 36) of the memory cell 26 is not conductive, there is no route for current to flow to VSS, and the voltages of the bit line 8 and the inverted sense amplifier bit line BLSAB hold the voltage VARY. Even if the bit line BL level is lowered due to the coupling capacitance of the adjacent BL described later, the voltage VARY is weakly supplied by the P-type transistor P4, so that it is returned to the voltage VARY. Further, the non-inverting sense amplifier bit line BLSAT maintains the voltage VBLREF according to the low level of the control signal ACTB2.

At timing T2, the N-type transistor M3 (FIG. 3) of the SWL counter circuit 23 connected to the activated sub word line SWLi is turned on, and the data inversion control signal 14 outputs a low level.

At the timing T3, since the memory element (thyristor 36) of the memory cell 26 is not conductive, the voltage of the inverted sense amplifier bit line BLSAB holds VARY, and the voltage of the inverted sense amplifier bit line BLSAB> non-inverted sense amplifier bit line. The relationship is the BLSAT voltage (VBLREF).

Further, at the timing T3, the control signal TG is set to the low level, and the connection between the bit line 8 and the inverted sense amplifier bit line BLSAB is disconnected. Further, by deactivating the control signal ACT2B to High level, the weak supply of the voltage VARY to the inverting sense amplifier bit line BLSAB is stopped, and the non-inverting sense amplifier bit line BLSAT is fixed to the voltage VBLREF. Open. Further, the power supply SAP is set to the high level (VARY), the power supply SAN is set to the low level (VSS), and the flip-flops F.F. F. And flip-flop F. F. Thus, amplification of the potential difference between the non-inverted sense amplifier bit line BLSAT and the inverted sense amplifier bit line BLSAB is started. In the periods T3 to T4, the flip-flops F.F. F. As a result, the non-inverted sense amplifier bit line BLSAT is amplified to the low level, and the inverted sense amplifier bit line BLSAB is amplified to the high level. This flip-flop F.F. F. This state corresponds to data “0”.

In the access operation, after timing T4, although not shown in FIG. 6, a READ command and / or a WRITE command are executed. In the READ command, the flip-flop F.F. F. The data “0” stored in the data is output from the data input / output terminal 12 via the data amplifier 6 and the data input / output circuit 11. In the above operation, the data amplifier 6 receives the data inversion control signal 14 and inverts / non-inverts data. In the periods T4 to T5, the data inversion control signal 14 is at the low level. This indicates that the data read by the ACT command is data that has been inverted an even number of times (including the case where the inversion is 0 times). If the read data is inverted even number of times, it means that the data is normal logic data, so the data amplifier 6 does not invert the data. As a result, correct logical data “0” can be output to the outside.

In the WRITE command, external data input from the data input / output terminal 12 is sent to the flip-flop F.F of the sense amplifier 19 via the data input / output circuit 11 and the data amplifier 6. F. Is written to. Also in the above operation, the data amplifier 6 receives the data inversion control signal 14 and inverts / non-inverts data. Since the data inversion control signal 14 is at the low level, the data amplifier 6 does not invert the data. As a result, when external data “0” is written, the flip-flop F.F of the sense amplifier 19 is passed through the inverted IO line IOB and the non-inverted IO line IOT. F. High is written to the inverted sense amplifier bit line BLSAB, and Low is written to the non-inverted sense amplifier bit line BLSAT (state of timing T5 in FIG. 6). When the external data “1” is written, Low is written to the inverted sense amplifier bit line BLSAB, and High is written to the non-inverted sense amplifier bit line BLSAT.

In the semiconductor memory device 21 shown in FIG. 2, the data amplifier 6 receives the data inversion control signal 14 and performs inversion / non-inversion of data by the READ command and the WRITE command. However, the present invention is not limited to this. The inversion / non-inversion of the data is performed by the flip-flop F. It can be executed at any point in the path between F and the data input / output terminal 12. For example, instead of the data amplifier 6, the data input / output circuit 11 may receive the data inversion control signal 14 and invert / non-invert data.

When a PRE command is given from the outside after the timing T4, the control signal TG is activated to a high level at the timing T5 in response thereto. In the semiconductor memory device 21 of the first embodiment, also in the PRE operation, the bit line 8 and the inverted sense amplifier bit line BLSAB of the sense amplifier 19 are connected as in the ACT operation (see Patent Document 1 and Patent Document 2). In the semiconductor memory device, in the PRE operation, the bit line 8 and the non-inverted sense amplifier bit line BLSAT of the sense amplifier 19 are connected, which will be described later in a comparative example). Accordingly, when the PRE operation is performed at the timing T5, the voltage supplied to the bit line 8 is not inverted from the voltage of the bit line 8 detected by the ACT operation. Specifically, the bit line 8 detects the High level during the ACT operation, and supplies the High level to the bit line 8 during the PRE operation.

At timing T6, the sub word line driver 3 increases the voltage of the sub word line SWLi to the word line write voltage VWLW. Accordingly, the voltage at the FB node of the memory cell 26 rises to the voltage VBI or higher via the capacitor C1. At this time, since the bit line 8 is driven to the high level (VARY), the thyristor 36 becomes conductive. When the thyristor 36 becomes conductive, the FB node is at the level of the voltage VON determined by the ratio of the ON resistance of the PNP transistor Q2 and the internal resistance of the PN junction diode between the FB node and VSS (cathode).

At timing T7, the sub word line driver 3 reduces the voltage of the bit line 8 to the word line precharge voltage VWLP between the word line write voltage VWLW and the word line standby voltage VWLS. Since the bit line 8 is driven to a high level (VARY) and the thyristor 36 is in a conductive state, the voltage at the FB node maintains the level of the voltage VON even when the voltage of the sub word line SWLi falls to the word line precharge voltage VWLP. And it doesn't change.

At timing T8, the control signal TG falls, the bit line 8 is disconnected from the inverted sense amplifier bit line BLSAB, and the control signal BLDIS rises, and the voltage of the bit line 8 is fixed to the low level (VSS). Further, the flip-flop F.F. F. The power supply SAP is set to the low level, the power supply SAN is set to the high level, and the flip-flop F. F. Is deactivated.

At timing T8, as the voltage of the bit line 8 decreases to VSS, the conduction state of the thyristor 36 ends, and the voltage at the FB node also decreases to the built-in potential VBI.

At timing T9, the voltage of the sub word line SWLi is lowered from the word line precharge voltage VWLP to the word line standby voltage VWLS. Since the thyristor 36 is in a non-conductive state, the FB node is lowered to the voltage VH via the capacitor C1.

At timing T9, in response to the fall of the sub word line SWLi from the word line precharge voltage VWLP to the word line standby voltage VWLS, the SWL counter circuit 23 connected to the sub word line SWLi counts up, and the SWL counter circuit 23 NC1 transitions from the Low level to the High level. At timing T9, the N-type transistor M3 of the SWL counter circuit 23 is turned off, so that the data inversion control signal 14 is in a floating state.

Here, the threshold voltage of the N-type transistor M1 of the SWL counter circuit 23 and the logic threshold voltage of the inverter INV1 are set to be between the word line precharge voltage VWLP and the word line standby voltage VWLS. Thereby, the count-up can be performed at the timing (T9) when the sub word line SWLi falls from the word line precharge voltage VWLP to the word line standby voltage VWLS.

In the SWL counter circuit 23 of FIG. 3, the falling of the sub word line SWLi at the timing T9 is detected. However, the present invention is not limited to this, and the change of the sub word line SWLi during the PRE operation period may be detected. For example, the SWL counter circuit 23 may be configured to detect the rise of the sub word line SWLi at the timing T6 or the fall of the sub word line SWLi at the timing T7.

In the PRE operation during the periods T5 to T9, since the high level voltage is supplied to the bit line 8 and written to the memory cell 26, the storage state of the memory cell 26 is inverted to the state of the cell High. In the SWL counter circuit 23, every time the sub word line SWLi is activated, the SWL counter circuit 23 connected to the sub word line SWLi is counted up, and the count value is held in the node NC1. When the node NC1 transitions to High as at the timing T9, the number of times that the sub word line SWLi is activated is an odd number and the data in the memory cell 26 connected to the sub word line SWLi is in an inverted state. Holding.

FIG. 6 shows the case where the sub word line SWLi is activated. In this case, the memory cells connected to the sub word lines 7 other than the sub word line SWLi (that is, inactive sub word lines) 7 The ACT operation and PRE operation are not performed. Also, the SWL counter circuit 23 connected to the inactive sub word line does not perform the count-up operation.

Next, the operation at timings T1 'to T9' in FIG. 6 will be described. In timings T1 'to T9', the same sub word line SWLi as in timings T1 to T9 is activated, and the ACT command → PRE command is executed again. In the operation at timings T1 'to T9', various control signals and the voltage of the sub-word line driver 3 are the same as those at the timings T1 to T9, and thus the description thereof is omitted.

First, immediately before entering T1 ', the storage state of the memory cell 26 is inverted to the cell high state, and the FB node is at the voltage VH. Further, the node NC1 of the SWL counter circuit 23 connected to the sub word line SWLi is at a high level.

Then, when an ACT command is given from the outside, the inverted sense amplifier bit line BLSAB is set to the voltage VARY and the non-inverted sense amplifier bit line BLSAT is set to the voltage VBLREF at the timing T1 '. Further, the inverted sense amplifier bit line BLSAB and the bit line 8 are connected. The bit line 8 is also driven by the voltage VARY of the inversion sense amplifier bit line BLSAB, and the voltage of the bit line 8 also rises to the voltage VARY.

At timing T2 ', the sub word line driver 3 raises the voltage of the sub word line 7 to the word line read voltage VWLR. When the voltage of the sub word line SWLi rises to the word line read voltage VWLR at timing T2 ', the voltage of the FB node is also raised through the capacitor C1 of the memory cell 26. The memory cell 26 is in the cell high state, the FB node rises from the voltage VH to the voltage VBI at which the memory element (thyristor 36) becomes conductive, and the memory element (thyristor 36) becomes conductive.

At timing T2 ', the inverted sense amplifier bit line BLSAB is released from the state where it is strongly fixed to the voltage VARY, and the voltage VARY is supplied weakly by the constant current source of the P-type transistor P4. Here, since the memory element (thyristor 36) of the memory cell 26 is conductive, a current flows from the bit line 8 through the thyristor 36. The current value of the constant current source of the P-type transistor P4 is set sufficiently smaller than the current value of the thyristor 36. As a result, the voltages of the bit line 8 and the inverted sense amplifier bit line BLSAB gradually decrease. On the other hand, the non-inverting sense amplifier bit line BLSAT maintains the voltage VBLREF.

At timing T2 ', the N-type transistor M3 (FIG. 3) of the SWL counter circuit 23 connected to the activated sub word line SWLi is turned on, and the data inversion control signal 14 outputs a high level.

At the timing T3 ′, since the memory element (thyristor 36) of the memory cell 26 is conductive, the voltage of the inverted sense amplifier bit line BLSAB gradually decreases, so that the voltage of the inverted sense amplifier bit line BLSAB <the non-inverted sense amplifier. The bit line BLSAT voltage (VBLREF) is established.

Here, at the timing T3 ', the flip-flop F.F. F. And flip-flop F. F. Thus, amplification of the potential difference between the non-inverted sense amplifier bit line BLSAT and the inverted sense amplifier bit line BLSAB is started. In the periods T3 'to T4', the flip-flops F.F. F. As a result, the non-inverted sense amplifier bit line BLSAT is amplified to High level, and the inverted sense amplifier bit line BLSAB is amplified to Low level. This flip-flop F.F. F. This state corresponds to data “1”.

In the access operation, after timing T4 ', a READ command and / or a WRITE command are executed, although not shown in FIG. In the periods T4 'to T5', the data inversion control signal 14 is at a high level. This indicates that the data “1” read by the ACT command is data that has been inverted an odd number of times. When the read data is inverted an odd number of times, it means that the logic is inverted. Therefore, the data amplifier 6 receives the high level of the data inversion control signal 14 and inverts the data. As a result, the data can be externally output after the correct logical data “0” is obtained.

In the WRITE command, external data “0” is set to flip-flop F. F. In the case of writing to, data is inverted upon receiving the high level of the data inversion control signal 14. As a result, Low is written to the inverted sense amplifier bit line BLSAB and High is written to the non-inverted sense amplifier bit line BLSAT (state of timing T5 'in FIG. 6). When external data “1” is written, High is written to the inverted sense amplifier bit line BLSAB and Low is written to the non-inverted sense amplifier bit line BLSAT.

Subsequently, when a PRE command is given from the outside after the timing T4 ', the control signal TG is activated to the high level at the timing T5' in response thereto. In the semiconductor memory device 21 of the first embodiment, also in the PRE operation, the bit line 8 and the inverted sense amplifier bit line BLSAB of the sense amplifier 19 are connected as in the ACT operation. As a result, the voltage VSS is supplied to the bit line 8, and the voltage of the bit line 8 drops to VSS. That is, when shifting to the PRE operation at timing T5 ', the voltage supplied to the bit line 8 is not inverted from the voltage of the bit line 8 detected by the ACT operation. Specifically, the bit line 8 is lowered to the low level during the ACT operation, and the low level is supplied to the bit line 8 during the PRE operation. Further, after the timing T5 ', since the bit line 8 is at the low level (VSS), the thyristor 36 is non-conductive.

At the timing T6 ', the sub word line driver 3 increases the voltage of the sub word line SWLi to the word line write voltage VWLW. Along with this, the FB node of the memory cell 26 temporarily rises to the voltage VBI or higher through the capacitor C1, but it reaches the voltage VBI level by the PN junction between the FB node (P-type region) and the cathode VSS (N-type region). Decrease at high speed.

At the timing T7 ', the sub word line driver 3 reduces the voltage of the bit line 8 to the word line precharge voltage VWLP. Since the thyristor 36 is in a non-conductive state, the voltage at the FB node decreases to a low voltage via the capacitor C1 as the voltage of the sub word line SWL decreases.

At timing T8 ', the bit line 8 is disconnected from the inversion sense amplifier bit line BLSAB, and the voltage of the bit line 8 is fixed to the low level (VSS). Further, the flip-flop F.F. F. The power supply SAP is set to the low level, the power supply SAN is set to the high level, and the flip-flop F. F. Is deactivated.

At timing T9 ', the voltage of the sub word line SWLi is lowered from the word line precharge voltage VWLP to the word line standby voltage VWLS. Since the thyristor 36 is in a non-conductive state, the FB node is lowered to the voltage VL via the capacitor C1.

At timing T9 ′, the SWL counter circuit 23 connected to the sub word line SWLi counts up in response to the sub word line SWLi falling from the word line precharge voltage VWLP to the word line standby voltage VWLS. NC1 of the circuit 23 transitions from the High level to the Low level. At timing T9 ', the N-type transistor M3 of the SWL counter circuit 23 is turned off, so that the data inversion control signal 14 is in a floating state.

In the PRE operation in the periods T5 ′ to T9 ′, since the low level voltage is supplied to the bit line 8 and written to the memory cell 26, the memory state of the memory cell 26 is inverted again to the cell low state, It returns to the normal logic data “0” at the timing T1. When the node NC1 transitions to low as at the timing T9 ′, the node NC1 has an even number of times that the sub word line SWLi has been activated, and the data in the memory cell 26 connected to the sub word line SWLi has been normally rotated. It holds information that it is stored in logic.

In FIG. 6, the voltage of the adjacent bit line 8n connected to the memory cell 26n is indicated by a broken line. At the timing T1, the memory cell 26n is different from the memory cell 26 and is in the state of the cell High. Therefore, the waveform of the adjacent bit line 8n at the timings T1 to T9 is the same as the waveform of the bit line 8 at the timings T1 'to T9'. The waveform of the adjacent bit line 8n at the timings T1 'to T9' is the same as the waveform of the bit line 8 at the timings T1 to T9 '.

Referring to the voltage waveforms of the bit line 8 and the adjacent bit line 8n in FIG. 6, the voltages of the bit line 8 and the adjacent bit line 8n rise from VSS to VARY at timings T1 and T1 ′. Since the same voltage is used for 8n, the current consumption due to charging / discharging of the coupling capacitor (31 in FIG. 5) at this time is small. Further, as described above, since the voltages of the bit line 8 and the adjacent bit line 8n are not inverted at the timings T5 and T5 ′ for shifting to the PRE operation, charging / discharging of the coupling capacitor (31 in FIG. 5) is performed. Current consumption can be greatly reduced. Details of this effect will be described later in comparison with a comparative example.

In the example of the waveform displayed in FIG. 6, the node NC1 of the SWL counter circuit 23 (FIG. 3) is at the low level at the timing T1, but the present disclosure is not particularly limited to the low level. The present disclosure is applied to a volatile memory. The volatile memory semiconductor memory device 21 stores information of external data input in the WRITE command in the access operation performed after power-on, and the data stored in the subsequent READ command. Is output externally. Therefore, data is inverted / non-inverted according to the logic of the node NC1 of the SWL counter circuit 23 (FIG. 3) when it is input by the WRITE command, and the data of the node NC1 when the data is output externally also by the subsequent READ command. If the data is inverted / non-inverted by logic, the number of times the sub word line is activated (even times or odd times) after the WRITE command and before the READ command is automatically set. Sometimes, the input logic (inverted / non-inverted) of the external data matches the logic (inverted / non-inverted) of the external output data. Therefore, there is no need to initialize the node NC1 of the SWL counter circuit 23 (FIG. 3) to a low level immediately after the power is turned on, and the initial logic of the node NC1 is composed of the inverter circuits INV2 and INV3 when the power is turned on. The logic may be determined by chance by the latch circuit.

(Comparative example)
Next, in order to show the effects of the first embodiment, a comparative example disclosed in Patent Document 1 will be described with reference to FIGS. In FIG. 14 to FIG. 16, the same reference numerals are assigned to components that function in substantially the same manner as in the first embodiment, and description thereof is omitted.

FIG. 14 is a block diagram showing a configuration of a semiconductor memory device 121 of a comparative example. The semiconductor memory device 121 of the comparative example is different from the semiconductor memory device 21 of the first embodiment in the following two points. First, the semiconductor memory device 121 of the comparative example is configured not to include the data inversion control signal generation unit 32 of the semiconductor memory device 21 of the first embodiment.

Second, the sense amplifier 59 of the semiconductor memory device 121 of the comparative example has a read switch (N-type transistors N22, N22A) and a write switch (N-type transistor N3) as switches that connect the bit line 8 and the node of the sense amplifier 59. , N3A). At the time of reading, the read switch N22 or N22A is turned on to connect the bit line 8 and the inverted sense amplifier bit line BLSAB (first node). On the other hand, at the time of writing, the write switch N3 or N3A is turned on to connect the bit line 8 and the non-inverted sense amplifier bit line BLSAT (second node). Control signals TGR and TGRA are control signals for controlling on / off of the reed switches N22 and N22A. Control signals TGW and TGWA are control signals for controlling on / off of the light switches N3 and N3A.

The comparative example corresponds to a memory cell in which the memory state is inverted when the voltage detected on the bit line 8 at the time of reading is written back without being inverted like a thyristor memory. The nodes of the sense amplifier 59 connected to the line 8 are switched to mutually complementary nodes. By connecting the bit line 8 and the sense amplifier 59 in this way, the storage state does not reverse every time a write operation is performed on the memory cell 26 by the PRE command as in the first embodiment. Therefore, since it is not necessary to invert / non-invert data by the READ command and the WRITE command, the data inversion control signal generation unit 32 of the first embodiment is not provided.

Next, the operation of the semiconductor memory device 121 of the comparative example will be described with reference to FIG. In FIG. 16, both the case where the memory cell 26 is the cell high and the case where the memory cell 26 is the cell low are displayed in the initial state. In FIG. 16, a waveform with “H” indicates a voltage waveform related to the memory cell of the cell High in the initial state, and a waveform with “L” relates to the memory cell of the cell Low in the initial state. The voltage waveform is shown. In the following description, the respective memory cells are referred to as “H” cells and “L” cells.

Among the various control signals in FIG. 16, the only difference from the control signal in FIG. 6 (first embodiment) is that TGR is activated during the ACT operation and TGW is activated during the PRE operation. In the following description, description of the control signal is omitted because it overlaps. FIG. 16 also shows a refresh operation only for the ACT operation and the PRE operation. In the access operation, a READ command or a WRITE command is executed between the ACT command and the PRE command.

Also, in FIG. 16, the operations of T1 to T4 of the “H” cell are the same as those of T1 ′ to T4 ′ of FIG. Further, the operations of T1 to T4 of the “L” cell are the same as those of T1 to T4 in FIG.

In the access operation, a READ command and / or a WRITE command are executed after timing T4.

Subsequently, when a PRE command is given from the outside, the control signal TGW is activated at timing T 5, and the bit line 8 is connected to the non-inverted sense amplifier bit line BLSAT of the sense amplifier 59. At this time, as indicated by a broken-line frame region R in FIG. 16, the voltage of the bit line 8 changes greatly. Specifically, in the case of the “H” cell, the voltage (BL “H”) of the bit line 8 is gradually decreased due to the thyristor 36 being in a conductive state during the ACT operation and flowing, but is not inverted at the timing T5. The voltage VARY (BLSAT “H”) is supplied from the sense amplifier bit line BLSAT, and rises to the voltage VARY. On the other hand, in the case of the “L” cell, the voltage (BL “L”) of the bit line 8 is the voltage VARY because the thyristor 36 is in a non-conductive state during ACT operation and no current flows through the thyristor 36. Is maintained. When the voltage VSS (BLSAT “L”) is supplied from the non-inverting sense amplifier bit line BLSAT at the timing T5, the voltage VSS falls.

As described above, in the case of the semiconductor memory device 121 of the comparative example, the voltage of the bit line 8 is inverted at the timing T5 immediately after the PRE command is started, as indicated by the broken line frame region R. The current consumption due to increases. In particular, when different data is handled between the bit line 8 and the adjacent bit line 8n (that is, in FIG. 16, one of the bit line 8 and the adjacent bit line 8n is an “H” cell, and the other is “L”. ”), The voltages are reversed at timing T5, so that the current consumption due to charging / discharging of the coupling capacitance (31 in FIG. 15) between the bit line 8 and the adjacent bit line 8n is very high. There is a problem that gets bigger.

Next, the operation waveforms at timings T6 to T9 in FIG. 16 are the same as the timings T6 to T9 in FIG. 6 (first embodiment) in the case of the “H” cell, except for the waveform of the FB node. In the case of the “L” cell, the operation is the same as that at the timings T6 ′ to T9 ′ in FIG. 6 (first embodiment). Therefore, the voltage at the FB node will be described below.

In the case of the “H” cell, the thyristor 36 is conductive after the voltage of the bit line 8 rises to VARY at the timing T5. When the thyristor 36 is conductive, the FB node is at the level of the voltage VON determined by the ratio between the ON resistance of the PNP transistor Q2 and the internal resistance of the PN junction diode between the FB node and VSS (cathode). Also at the timing T6, the FB node maintains the level of the voltage VON.

In the case of the “L” cell, the thyristor 36 becomes non-conductive after the voltage of the bit line BL falls to VSS at the timing T5. When the thyristor 36 is non-conductive, the voltage at the FB node once rises to VBI or higher through the capacitor C1 at timing T6, but the voltage is increased to the voltage VBI level by the PN junction between the voltage at the FB node and the cathode VSS. To drop.

Subsequently, in the case of the “H” cell, since the thyristor 36 is conductive until the timing T8, the FB node maintains the voltage VON. On the other hand, in the case of the “L” cell, at the timing T7, the voltage at the FB node decreases as the voltage of the sub word line SWLi decreases to the word line precharge voltage VWLP via the capacitor C1.

Next, in the case of the “H” cell, when the voltage of the bit line 8 decreases to VSS at the timing T8, the thyristor 36 becomes non-conductive and the FB node decreases to the voltage VBI. On the other hand, in the case of the “L” cell, since the thyristor 36 is non-conductive before the timing T8, the voltage at the FB node does not change.

Next, at timing 9, since the thyristor 36 is non-conductive in both the “H” cell and the “L” cell, the voltage of the sub-word line SWLi has decreased from VWLP to VWLS via the capacitor C 1. Along with this, the voltage decreases. As a result, in the case of the “H” cell, the FB node becomes the voltage VH, and in the case of the “L” cell, the FB node becomes the voltage VL.

Next, effects obtained in the first embodiment will be described by comparing the first embodiment with a comparative example.

First, in the sense amplifier 59 of the semiconductor memory device 121 of the comparative example, two types of switches, read switches N22 and N22A connected to the bit line 8 at the time of reading, and write switches N3 and N3A connected to the bit line 8 at the time of writing. It has. On the other hand, the sense amplifier 19 of the semiconductor memory device 21 according to the first embodiment is composed of only the read / write switches N2 and N2A that are shared during reading and writing. Thereby, in the first embodiment, the layout size of the sense amplifier 19 can be reduced.

Secondly, in the semiconductor memory device 121 of the comparative example, the voltage of the bit line 8 is inverted when shifting to the PRE operation after the ACT operation, so that the current consumption due to charging / discharging of the bit line 8 increases (FIG. 16 dashed frame regions R). In particular, when different data is handled between the bit line 8 and the adjacent bit line 8n, current consumption due to charging / discharging of the coupling capacitor (31 in FIG. 15) becomes very large. On the other hand, in the semiconductor memory device 21 of the first embodiment, the voltage of the bit line 8 is not inverted when the PRE operation is performed after the ACT operation. In addition, current consumption due to charging / discharging of the coupling capacitance (31 in FIG. 15) between the bit line 8 and the adjacent bit line 8n can be reduced.

In the first embodiment, the memory state of the memory cell 26 is inverted every time the PRE operation is performed. However, the data amplifier 6 inverts / non-inverts the data in accordance with the data inversion control signal 14, thereby external output. It is possible to make the data to be forward rotated logic. In addition, when data is externally input, the data amplifier 6 inverts / non-inverts the data in accordance with the data inversion control signal 14, so that the flip-flop F. F. The data to be written to can be set to a value corresponding to the data inversion control signal 14.

(Modification 1 of the first embodiment)
Next, Modification 1 of the first embodiment will be described with reference to FIG. FIG. 7 is a circuit diagram of the memory cell 27 of the FBC memory according to the first modification of the first embodiment. Although the memory element is the thyristor 36 in the first embodiment, the memory element of the first modification of the first embodiment is the bipolar transistor 37. However, the basic write and read operation waveforms and circuit configuration need not be changed from the first embodiment except that the structure and operation principle of the memory element are slightly different. Only differences from the first embodiment will be described below. In FIG. 7, compared with FIG. 4 of the first embodiment, in the first embodiment, the bit line (BL) 8 is connected to the anode of the thyristor, whereas the modification of the first embodiment. 1 is connected to the collector of the bipolar transistor 37. The emitter is connected to the power supply node 102, and the base is connected to the counter electrode of the sub word line SWL of the capacitor C2.

The operation principle of the memory cell of the FBC memory is described in detail in Patent Document 1, and the description is omitted.

Further, in the description of the first embodiment described above, if the location described as the memory cell 26 is read as the memory cell 27 and the location indicated as the thyristor 36 for the memory element is read as the bipolar transistor 37, The description of the first embodiment can be used as it is for the first modification of the first embodiment.

In the first modification of the first embodiment, the same effect as in the first embodiment can be obtained.

(Modification 2 of the first embodiment)
Next, Modification 2 of the first embodiment will be described with reference to FIG. FIG. 8 is a circuit diagram of a memory cell 28 of a general thyristor memory. There is an NMOS transistor NC whose substrate is an FB node. The PNP transistor Q4 and the parasitic NPN transistor Q3 constitute a thyristor 38. The emitter of the PNP transistor Q4 whose base is the N-type region of the node FN is connected to the bit line BL (anode), the gate of the NMOS transistor NC is connected to the sub word line SWL, and the source of the NMOS transistor NC is connected to the power supply node 102. Is done. When not selected, the FB node is floating, and a memory operation is performed by storing electric charge in the gate capacitance between the gate of the NMOS transistor NC and the FB node.

In the description of the first embodiment described above, if the location described as the memory cell 26 of the thyristor memory is replaced with the memory cell 28 of the thyristor memory, and the location described as the thyristor 36 is replaced with the thyristor 38, The description of the first embodiment can be used as it is for the modification 2 of the first embodiment.

In the second modification of the first embodiment, the same effect as in the first embodiment can be obtained.

(Modification 3 of the first embodiment)
Next, a third modification of the first embodiment will be described with reference to FIG. FIG. 9 is a circuit diagram of a memory cell 29 of a general FBC memory. There is an NMOS transistor NC having a node FB as a substrate, and a bipolar transistor 39 is formed. The drain of the NMOS transistor NC is connected to the bit line BL (drain), the gate of the NMOS transistor NC is connected to the sub word line SWL, and the source of the NMOS transistor NC is connected to the power supply node 102. When not selected, the FB node is floating, and a memory operation is performed by storing electric charge in the gate capacitance between the gate of the NMOS transistor NC and the FB node.

In the description of the first embodiment described above, the place where the memory cell 26 of the thyristor memory is read as the memory cell 29 of the FBC memory, and the place where the thyristor 36 is written is read as the bipolar transistor 39. The description of the first embodiment can be used as it is for the modification 3 of the first embodiment.

In the third modification of the first embodiment, the same effect as in the first embodiment can be obtained.

[Second Embodiment]
(Configuration of Second Embodiment)
Next, the configuration of the second embodiment will be described with reference to FIGS. In the second embodiment, the SWL counter circuit 23 of the first embodiment is replaced with a counter cell (16a in FIG. 11) substantially the same as the memory cell 26, and SWLi is reduced by the counter cell (16a in FIG. 11). The number of activations is counted. That is, the counter 104 in FIG. 1 referred to in the outline description of the embodiment is configured by a counter cell (16a in FIG. 11) in the second embodiment.

FIG. 10 is a block diagram showing a configuration of the semiconductor memory device 22 according to the second embodiment. As can be seen by comparing FIG. 10 with FIG. 2 (first embodiment), the semiconductor memory device 22 of FIG. 10 replaces the data inversion control signal generator 32 of FIG. 2 with the data inversion control signal generator 42 (in FIG. 10). It is a configuration that is replaced with (within the alternate long and short dash line). The other parts are the same as those in FIG. 2, and are given the same reference numerals and redundant description is omitted. Here, the data inversion control signal generation unit 42 includes the counter cell 16a (FIG. 11), and simultaneously with the read / write operation of the memory cell 26 connected to the sub word line SWLi, the counter cell 16a connected to the sub word line SWLi. The data inversion control signal 14 is generated based on the data read from the counter cell 16a.

In FIG. 10, the counter cell 16a (FIG. 11) is connected to a counter bit line (CBL) 8a which is a bit line closest to the X decoder 4 side. In FIG. 10, a cell region including the counter bit line 8a among the plurality of cell regions 1 is referred to as a cell region 1a with a counter cell. The counter bit line 8a is connected to a counter cell sense amplifier (49: CSA in FIG. 11) having the same configuration as that of the sense amplifier 19. In FIG. 10, a region including the counter cell sense amplifier (CSA) 49 is referred to as a counter cell sense amplifier-equipped sense amplifier region (SA region with CSA) 2a.

Furthermore, the data inversion control signal generation unit 42 in FIG. 10 includes a buffer circuit 15 and a CYS generation circuit 5a. Details of these will be described later.

Next, the configuration of the counter cell 16a and the counter cell sense amplifier (CSA) 49 will be described with reference to FIG. FIG. 11 shows two cell areas 1a with counter cells and an SA area 2a with CSA arranged between them. As shown in FIG. 11, a plurality of counter cells 16a are connected to a counter bit line (CBL) 8a corresponding to the plurality of sub-word lines 7.

The configuration of the counter cell sense amplifier (CSA) 49 connected to the counter bit line (CBL) 8a is the same as the configuration of the sense amplifier 19 (SA0, SA1, etc. in FIG. 11) connected to the bit line 8. is there. When a certain sub word line SWLi is activated after the power is turned on, the counter cell 16a connected to the sub word line SWLi performs a read operation at the time of an ACT command and a PRE command, respectively, similarly to the memory cell 26 connected to the sub word line SWLi. And write operation.

With the above configuration, each counter cell 16a counts up during the PRE command operation when the corresponding sub word line SWLi is activated, and holds the number of activations in the counter cell 16a. Specifically, during the PRE command operation, the cell Low and the cell High are inverted and written when the number of times of activation is even and odd, and the data is retained. Note that the correspondence between the cell low and the cell high when the number of times of activation is even or odd may be either. When the cell (the sub word line) is first activated after power-on, the flip-flop F.F of the counter cell sense amplifier (CSA) is activated. F. Is activated (the power supply SAP is set to High and the power supply SAN is set to Low), the logic High and Low of the non-inverted sense amplifier bit line BLSAT and the inverted sense amplifier bit line BLSAB are influenced by chance, and are determined. The even number and the odd number of times of activation with the determined logic may be associated with the cell low and cell high, and this correspondence is inherited as long as the power is turned on.

Flip-flop F. of the sense amplifier (CSA) 49 for counter cell. F. Inverted sense amplifier bit line BLSAB and non-inverted sense amplifier bit line BLSAT are connected to an inverted counter IO line (CIOB line) and a non-inverted counter IO line (CIOT line) through N-type transistors N6 and N7, respectively. The N-type transistors N6 and N7 in the counter cell sense amplifier (CSA) 49 are ON / OFF controlled by a counter column selection signal (CYS) 9a output from the CYS generation circuit 5a. That is, when the counter column selection signal (CYS) 9a is in the activated state, the inverted sense amplifier bit line BLSAB and the non-inverted sense amplifier bit line BLSAT of the counter cell sense amplifier (CSA) 49 are the CIOB line and the CIOT line, respectively. Connected.

Next, details of the buffer circuit 15 of FIG. 11 will be described with reference to FIG. FIG. 12 is a circuit diagram of the buffer circuit 15. The buffer circuit 15 includes a flip-flop F.F. of the counter cell sense amplifier (CSA) 49 read via the CIOB line and the CIOT line. F. Is a circuit that outputs the data inversion control signal 14. The buffer circuit 15 includes a P-type transistor P91 and an N-type transistor N91 that constitute a driver. The output terminals of the NAND circuit 91 and the NOR circuit 91 are connected to the gates of the P-type transistor P91 and the N-type transistor N91, respectively. Also, the CIOBT line is connected to one end of the NAND circuit 91 and the NOR circuit 91. The CIOB line is connected to the other ends of the NAND circuit 91 and the NOR circuit 91 through an inverter circuit INV91. A P-type transistor P92 is connected between the power supply VARY and the CIOB line. A P-type transistor P93 is connected between the power supply VARY and the CIOT line. Here, the gates of the P-type transistors P92 and P93 are both connected to the power supply SAP.

With the above configuration, when the power supply SAP is at the low level, the P-type transistors P92 and P93 are turned on, the drains of the P-type transistors P92 and P93 are at the voltage VARY, and both the P-type transistor P91 and the N-type transistor N91 are turned off. The data inversion control signal 14 is in a floating state.

When the power supply SAP is at a high level and the CIOB line is at a high level and the CIOT line is at a low level, the outputs of the NAND circuit 91 and the NOR circuit 91 are both at a high level, and the data inversion control signal 14 is low. Become a level. When the power supply SAP is at a high level and the CIOB line is at a low level and the CIOT line is at a high level, the outputs of the NAND circuit 91 and the NOR circuit 91 are both at a low level, and the data inversion control signal 14 is a voltage. It becomes VARY High level. That is, the buffer circuit 15 sets the level of the non-inverted sense amplifier bit line BLSAT of the counter cell sense amplifier (CSA) 49 to the data inversion control signal 14 when the power supply SAP is at a high level and the counter column selection signal (CYS) is active. Output.

(Operation of Second Embodiment)
Next, the operation of the second embodiment will be described with reference to FIG. In the semiconductor memory device 22 of the second embodiment, the part that is different from the operation of the semiconductor memory device 21 of the first embodiment is the operation of the data inversion control signal generation unit 42. The other parts are the same as those in FIG. 6 showing the operation of the semiconductor memory device 21 of the first embodiment, and thus the description thereof is omitted.

Therefore, in FIG. 13, only the counter column selection signal CYS and the data inversion control signal 14 of the one-dot chain line frame are described. The counter column selection signal CYS is generated by the CYS generation circuit 5a. The period during which the data inversion control signal 14 is required is when the READ command and the WRITE command are executed. Therefore, as shown in FIG. 13, the CYS generation circuit 5a activates the counter column selection signal CYS (High level) at the timing T4 when the ACT operation ends.

In addition, when the counter column selection signal CYS is activated (High level) and the power supply SAP is at the High level, the buffer circuit 15 as described above, the counter cell 16a connected to the activated sub word line SWLi. The data inversion control signal 14 is generated from the data read out via the CIOB line and the CIOT line.

The data inversion control signal 14 is supplied to the data amplifier 6 when the READ command and the WRITE command are executed. In the data amplifier 6, by performing the inversion / non-inversion of the data in accordance with the data inversion control signal 14, it is possible to output the normally inverted logic data when the data is output to the outside. When data is externally input, the flip-flop F.F. F. The data to be written to can be made to correspond to the data inversion control signal 14.

As described above, according to the semiconductor memory device 22 according to the second embodiment, as in the first embodiment, after the ACT operation, when the transition to the PRE operation is performed, the charge / discharge of the bit line 8 and the bit Current consumption due to charging / discharging of the coupling capacitance (31 in FIG. 5) between the line 8 and the adjacent bit line 8n is reduced. As a result, the effect of reducing the current consumption can be obtained as in the first embodiment. Furthermore, in the semiconductor device according to the second embodiment, the layout area can be made smaller than that of the first embodiment by replacing the SWL counter circuit 23 of the first embodiment with the counter cell 16a. It is done.

The present disclosure is effective when applied to a semiconductor memory device using a memory element in which the potential of the storage state of a memory cell is inverted when shifting from a read operation to a write back operation, such as a thyristor memory or an FBC memory. .

It should be noted that, within the scope of the entire disclosure (including claims and drawings) of the present invention, the embodiments can be changed and adjusted based on the basic technical concept. Various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) can be combined or selected within the framework of the entire disclosure of the present invention. That is, the present invention naturally includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea. In particular, with respect to the numerical ranges described in this document, any numerical value or small range included in the range should be construed as being specifically described even if there is no specific description.

1: Cell area 1a: Cell area with counter cell 2: Sense amplifier area (SA area)
2a: Sense amplifier area with sense amplifier for counter cell (SA area with CSA)
3: Sub-word line driver (word line driver)
4: X decoder 5: Y decoder 5a: CYS generation circuit 6: Data amplifier 7: Sub word line (SWL, SWLi)
8, 120: Bit lines (BL, BLA)
8a: Counter bit line (CBL)
8n, 131: Adjacent bit line (adjacent BL)
9: Column selection signal (YS, YSi)
9a: Counter column selection signal (CYS)
10a, 10b: Inverted IO line (IOB) and non-inverted IO line (IOT)
11: Data input / output circuit 12: Data input / output terminal 13: SWL counter area 14: Data inversion control signal 15: Buffer circuit 16a: Counter cell 19, 59: Sense amplifier (SA)
21, 22, 100, 121: Semiconductor memory device 23: SWL counter circuit (counter circuit)
26, 26n, 28: Memory cell 27 (of thyristor memory), 29: Memory cell 31 of FBC memory, 111: Coupling capacitance 32, 42, 112: Data inversion control signal generator 36, 38: Thyristor 37, 39: Bipolar transistor 49: Sense amplifier (CSA) for counter cell
101: Memory cell (MC)
102: Power supply node 103: Memory cell control terminals 103a to 103d: Sub-word line connection terminals (memory cell control terminals)
104: counter 105: read / write switch 106: holding circuit 107: first node 108: external input / output circuit 109: sense amplifier (SA, SAi)
110, 110a to d: Bit line connection terminal 122: Word line (WL)
221: Anode 222: Cathode 223: Gate C1, C2: Capacitor Q1, Q3: NPN transistor Q2, Q4: PNP transistors N1, N1A, N4-7, N91, M1-3: N-type transistor N2, N2A: Read / write switch (N-type transistor)
N22, N22A: Reed switch (N-type transistor)
N3, N3A: Light switch (N-type transistor)
P1-P6, P91-93: P-type transistor NC: MOS transistors INV1-6, INV91: Inverter circuit NAND91: NAND circuit NOR91: NOR circuit F.P. F. : Flip-flop NC1-3: Node FB: Floating body SAN, SAP: Power supply BLSAB: Inverted sense amplifier bit line (first node)
BLSAT: Non-inverting sense amplifier bit line (second node)
IOB: Inverted IO line IOT: Non-inverted IO line BLDIS, TG, TGR, TGRA, TGW, TGWA, ACT1B, ACT2B: Control signal VIREF: Constant current reference YS (YSi): Column selection signal VARY: Array power supply VBLREF: Bit line Determination reference power supply CIOB: inverted counter IO line CIOT: non-inverted counter IO line

Claims (13)

1. A memory cell connected between the bit line and the power supply node, and in which the stored data is inverted when writing back without inverting the voltage detected at the time of reading;
   A word line connected to a control terminal of the memory cell;
   A sense amplifier having a holding circuit for temporarily storing read data from the memory cell, and a read / write switch connected between the first node of the holding circuit and the bit line;
   A counter provided corresponding to the word line, counting the number of times the word line is activated, and outputting a data inversion control signal indicating whether the number is even or odd;
   An external input / output circuit that performs inversion / non-inversion of data based on the data inversion control signal when data of the holding circuit of the sense amplifier is externally input / output;
   A semiconductor memory device.
2. At the time of reading, the read / write switch is turned on, the data of the memory cell is read to the first node of the sense amplifier via the bit line, and temporarily stored in the holding circuit of the sense amplifier,
   2. The write-back to the memory cell according to claim 1, wherein at the time of writing back, the read / write switch is turned on to supply the bit line to the bit line without inverting the voltage of the first node of the sense amplifier. Semiconductor memory device.
3. 3. The semiconductor memory device according to claim 1, wherein the counter is a counter circuit that counts up upon activation of the word line.
4. The counter comprises a counter cell that is substantially the same as the memory cell;
   The counter cell corresponding to the word line is read / written simultaneously with the memory cell connected to the word line,
   The semiconductor memory device according to claim 1, wherein the data inversion control signal is generated based on read data of the counter cell.
5. 5. The semiconductor memory device according to claim 4, further comprising a counter cell sense amplifier corresponding to the counter cell and substantially the same as the sense amplifier.
6. A buffer for generating the data inversion control signal based on a signal of a counter IO line pair electrically connected to a first node of the holding circuit of the counter amplifier for the counter cell and a second node complementary to the first node The semiconductor memory device according to claim 5, further comprising a circuit.
7. The memory cell includes a memory element that stores data by accumulating charges in a floating body;
   7. The semiconductor memory device according to claim 1, wherein the floating body is connected to a control terminal of the memory cell via a capacitor.
8. The memory element is a thyristor;
   The anode of the thyristor is connected to the bit line;
   The cathode of the thyristor is connected to the power supply node;
   The semiconductor memory device according to claim 7, wherein a gate of the thyristor constitutes the floating body.
9. The memory element is a bipolar transistor;
   The collector of the bipolar transistor is connected to the bit line;
   An emitter of the bipolar transistor is connected to the power supply node;
   The semiconductor memory device according to claim 7, wherein a base of the bipolar transistor constitutes the floating body.
10. A word line driver for controlling the voltage of the word line;
    When the word line is activated and a read operation is performed,
    A first control in which the word line driver holds the voltage of the word line at a word line standby voltage, and the sense amplifier precharges the bit line to a first voltage;
    After the first control, the word line driver sets the word line to the word line read voltage, and then the sense amplifier releases the precharge of the bit line, and the memory is transferred from the bit line to the sense amplifier. A second control for reading cell data;
    The semiconductor memory device according to claim 1, wherein:
11. When performing the operation of writing back the data read to the sense amplifier to the memory cell,
    A third control in which the sense amplifier sets the bit line without inverting the voltage of the read data;
    After the third control, a fourth control in which the word line driver sets the word line to a word line write voltage that is higher than the word line read voltage;
    After the fourth control, a fifth control in which the word line driver sets the word line to a word line precharge voltage that is an intermediate voltage between the word line read voltage and the word line standby voltage;
    After the fifth control, a sixth control in which the sense amplifier sets the bit line to a first power supply voltage supplied to the power supply node;
    After the sixth control, a seventh control in which the word line driver returns the voltage of the word line to the word line standby voltage;
    The semiconductor memory device according to claim 10.
12. A plurality of the word lines wired in a first direction;
    A plurality of the bit lines wired in a second direction intersecting the first direction;
    A plurality of memory cells provided corresponding to intersections of the plurality of word lines and the plurality of bit lines;
    A plurality of the sense amplifiers respectively provided corresponding to the plurality of bit lines;
    A plurality of counters respectively provided corresponding to the plurality of word lines;
    A semiconductor memory device according to claim 1, comprising:
13. The plurality of word lines have a hierarchical structure including a main word line and a sub word line,
    The semiconductor memory device according to claim 12, wherein the plurality of counters are provided corresponding to the plurality of sub-word lines, respectively.

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