WO2014149775A1 - Architecture pour une centrale électrique comprenant des groupes de dispositifs de génération d'énergie électrique - Google Patents

Architecture pour une centrale électrique comprenant des groupes de dispositifs de génération d'énergie électrique Download PDF

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Publication number
WO2014149775A1
WO2014149775A1 PCT/US2014/020862 US2014020862W WO2014149775A1 WO 2014149775 A1 WO2014149775 A1 WO 2014149775A1 US 2014020862 W US2014020862 W US 2014020862W WO 2014149775 A1 WO2014149775 A1 WO 2014149775A1
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WIPO (PCT)
Prior art keywords
power
voltage
inverter
balancer
switch
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PCT/US2014/020862
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English (en)
Inventor
Eric B. Cummings
Original Assignee
Maxout Renewables, Inc.
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Priority claimed from US13/840,958 external-priority patent/US9136703B2/en
Application filed by Maxout Renewables, Inc. filed Critical Maxout Renewables, Inc.
Publication of WO2014149775A1 publication Critical patent/WO2014149775A1/fr

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
    • H02J7/35—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering with light sensitive cells
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00—Circuit arrangements for dc mains or dc distribution networks
    • H02J1/001—Hot plugging or unplugging of load or power modules to or from power distribution networks
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00—Circuit arrangements for dc mains or dc distribution networks
    • H02J1/10—Parallel operation of dc sources
    • H02J1/102—Parallel operation of dc sources being switching converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00—Circuit arrangements for dc mains or dc distribution networks
    • H02J1/10—Parallel operation of dc sources
    • H02J1/106—Parallel operation of dc sources for load balancing, symmetrisation, or sharing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

Definitions

  • photovoltaic cells generally produce a maximum power at a particu lar voltage and current that depends on the properties of the ceil and the amount of illumination. Away from this maximum power point, the conversion efficiency of the cell drops.
  • a utility-scale power plant may comprise such cells numbering in the thousands, deployed across square kilometers. Given this large scale configuration, it may be difficult to operate an entire plant at peak efficiency. [0006] In addition, the output from photovoltaic cells is typically processed to produce an alternating current to output onto the electrical power grid. This can be difficult to manage with such a large number of discrete PV cells.
  • a solar power plant must operate under a range of non-ideal conditions.
  • non-ideal conditions include a lack of full suniighi, and possible outages on an electrical power grid.
  • embodiments of the present invention relate to a cost- optimized architecture for a photovoltaic power plant that can operate at or near its maximum production efficiency. Embodiments of the present invention may continue to function under adverse conditions, such as grid outages and lack of full sunlight.
  • the series connection of various power sources, such as photovoltaic panels and cells, chemical batteries, fuel cells, thermo-electric devices, and the like is often desirable to increase output voltage. However, such arrangements often result in sub- optimal performance including lower power efficiency, lower lifetime, etc. because of differences between the characteristics of the various power sources, including efficiency, history, aging, temperature, temperature gradients, and illumination.
  • Embodiment of the present invetion generally relate to power converters. Some embodiments of the present invention are directed to economical solar-power optimizer circuits.
  • a power-plant power system architecture employs techniques to reduce the levelized cost of energy imposed by the power system, the elements of which may be unconventional, in one embodiment, a solar energy concentrator in the form of an inflated reflector, focuses light onto a high-concentration photovoltaic receiver.
  • a plurality of these concentrators are grouped into a series-connected cluster that shares control circuitry as well as support structure. Individual concentrators are maintained at their maximum power point via balance controllers that control the flow of current that shunts this series connection. DC current from clusters must transmit moderate distances, e.g., 300-1000 m to a centralized inverter.
  • the inductance of transmission lines is maximized using an air-spaced twisted pair, enhancing the performance of a boost-type three phase inverter.
  • the outputs of clusters are kept separate to individual inverters in a massively interleaved array co-located at a central location.
  • Step-up transformers convert from inverter voltages to grid voltages, and small transformers provide isolation and voltage step-up only on receiver-to-receiver imbalance currents, typically ⁇ 20% of the total current.
  • deficits in performance of power systems can be mitigated by the use of a 'balancer' that judiciously draws extra power, sources extra power, or both draws and sources power to individual power sources connected series to effect more optimal performance.
  • Figure 1A illustrates an arrangement of balancing circuitry according to an embodiment of the present invention,that supports a cluster of N receivers.
  • Figure I B shows a conventional cluster of series-connected receivers.
  • Figure 1C shows a conventional approach to handling power imbalances among clusters of receivers.
  • Figure I D shows a conventional cluster in which maximum-power-point tracking switchers are series connected.
  • Figure I E shows an alternate arrangement of balancer circuits which can pass current bi-directionally between each receiver without the need for a direct connection to each other or a connection to a power bus.
  • Figure 2A shows a balancer circuit arrangement in which the balancer circuit for each receiver is separate.
  • Figure 2AA shows a simplified schematic diagram of a bidirectional isolated flyback converter used for bi-directional power flow.
  • Figure 2AB shows a simplified schematic diagram of a half-bridge bidirectional converter used for bi-directional power flow.
  • Figure 2AC shows a simplified schematic diagram of a bi-directional Cuk converter used for bi-directional power flow.
  • Figure 2B shows an alternative arrangement or balancer circuitr '- in which a single multiple-tap transformer is employed.
  • Figure 2C shows a balancer circuit that employs a passive rectifier bridge.
  • Figure 2D shows a balancer circuit that employs a transformer that has isolated, coupled windings.
  • Figure 2EA shows a simplified schematic diagram of a unidirectional isolated flyback converter.
  • Figure 2EB shows a simplified schematic diagram of a unidirectional two- switch forward isolated converter.
  • Figure 2EC shows a simplified schematic diagram of a unidirectional isolated Cuk converter circuit.
  • Figure 3 shows an illustration according to the present invention, of an embodiment of a power plant layout.
  • Figure 3A shows a simplified view of a power plant according to an embodiment of the present invention.
  • Figures 3AA-3AE show arrangements of cluster voltages according to embodiments of the present invention.
  • Figure 4A shows a diagram of a pair of DC transmission lines.
  • Figure 4B shows a cross-sectional view of the spacing of an insulated twisted pair maintained by a polymer web.
  • Figure 4C shows a cross-sectional view of an alternative cross-section of an insulated twisted pair which minimizes polymer use.
  • Figure 5 A shows an embodiment of a physical layout of die on a receiver substrate
  • Figure 5B shows a schematic diagram of a electrical circuit in a receiver showing an assortment of design elements aimed at improving off-design performance.
  • Figure 6 shows such a cluster of collectors.
  • Figure 7 shows a schematic block diagram of an embodiment of a master/slave arrangement of balancers.
  • Figure 8 shows a schematic diagram of an embodiment of a balancer slave according to the present invention.
  • Figure 9 A shows a schematic diagram of an interleaved inverter system according to an embodiment of the present invention
  • Figure 9B shows an embodiment of an inverter system that provides for switch synchronization daisy-chaining via circuitry
  • Figure 1 OA shows a schematic diagram of an embodiment of an inverter slave according to an embodiment of the present invention.
  • Figure 10B shows a diagram of an embodiment of an inverter slave that uses a daisy chain of handshake signals to perform soft switching, reduced-stress switching, low-noise, switching, or other switching enhancements.
  • Figure 1 1A shows a UPS associated with inverters according to an embodiment of the present invention.
  • Figure 1 I B shows an electrical connection arrangement for reducing secondary damage from a failed switch.
  • Figure 11C shows an alternate circuit for reducing secondary damage resulting from an increase in negative common voltage substantially above the three- phase plant voltages.
  • Figure 12 A shows a schematic circuit diagram of a low-side switch module comprising a low side driver module and a switch module.
  • Figure 12B shows a schematic circuit diagram of an embodiment of a high- side switch module.
  • Figure 13 A shows an embodiment of a switch module.
  • Figure 13B shows the switch module illustrated in Figure 13 A with its cover removed.
  • Figure 13C shows a view of the base side of the switch module cover.
  • Figure 14A shows a simplified mechanical drawing of the assembly of switch modules, low-side modules, and high-side driver modules as would be placed into an inverter slave housing.
  • Figure 14B shows an arrangement of low-side and high-side driver modules and switch modules inserted into an inverter slave housing according to an embodiment.
  • FIG. 14C shows a simplified internal assembly of an embodiment of an inverter slave.
  • Figure 15 A shows a top view of an inverter slave according to an embodiment of the present inv ention.
  • Figure 15B shows a shows a back side view of an inverter slave according to an embodiment of the present invention.
  • Figures 16A and 16B respectively show isometric top front and back views of an embodiment of an inverter slave engaged with its active cooling module.
  • Figures 17A- 17D show components of an embodiment of a coolant module.
  • Figure 17E shows an alternate interface that mates the cooling module and cooled elements
  • Figure 17F is an expanded view of the cooling plate and cooled plate interface arrangements illustrated in Figure 17E.
  • Figure 17G shows an alternate interlocking interface between the cooling plate and cooled elements.
  • Figures 18A and 18B show the cold side of a splitter plate.
  • Figures 18C and 18D show the same patterns on the hot side of the splitter plate.
  • Figure 18E shows how the cooled components lie physically with respect to the patterns of jets in the splitter plate.
  • Figure 19 shows a ten-by-ten array of coolant modules assembled into an inverter heat exchanger.
  • Figures 20A-20D show an embodiment of an assembly of inverter slaves, cooling system, motherboard, and back panel, fitting together.
  • Figure 21 shows a mechanical drawing of a housing structure according to an embodiment of the present invention, that contains the assembly illustrated in Figures 20A-20D.
  • Figure 22 shows the assembly illustrated in Figures 20A-20D disposed in a housing without a front panel attached.
  • Figures 23A-23E respectively show a top-front isometric view, a front view, a back isometric view, a back view , and side view of the inverter assembly 2300 with front-panel attached,
  • Figure 24 shows an embodiment of the interleaved inverter containing a motorized traverse to programmatically operate arrays of mechanical switches.
  • Figure 25 shows a schematic diagram of a communications and control network according to an embodiment of the present invention.
  • Fig. 26A shows a schematic diagram of an arrangement of a string, load and balancer operating without boost according to the present invention
  • Fig. 26B shows a schematic diagram of an alternative arrangement of a string, load and balancer operating without boost according to the present invention.
  • Fig. 26C shows a schematic diagram of an arrangement of two s trings, two loads and balancer according to the present invention.
  • Fig, 27 A shows a schematic diagram of an arrangement of a string, load and balancer operating in boost mode according to the present invention.
  • Fig. 27B shows a schematic diagram of an aternative arrangement of a string, load and balancer operating in boost mode according to the present invention.
  • Fig, 28 shows a schematic diagram of an embodiment of a "mode switch" according to the present invention.
  • Fig. 29A shows an arrangement of string, load, and a modular
  • Fig. 29B shows an arrangement of two strings, two loads, and a modular decomposition of an alternative balancer having jumper settings to support this arrangement according to the present invention.
  • Fig. 29C shows an arrangement of strings, load, and balancer system configured as a single string, according to an embodiment of the present invention.
  • Fig. 30 show r s a schematic diagram of an embodiment of circuitry to support isolated power supplies and generate various voltages according to the present invention.
  • Fig. 31 shows a schematic diagram of an embodiment of circuitry used to produce various isolated voltages in balancer channels from waveforms produced by the apparatus diagrammed in Fig. 5.
  • Fig, 32A shows a schematic diagram of an isolated bidirectional communications bus-system according to an embodiment of the present invention.
  • FIG. 32B shows a schematic diagram of an embodiment of a bus that conveys power and communications signals between balancer channels and a master controller in accordance with the present invention.
  • Fig. 33 shows a schematic diagram of a balancer channel circuit embodiment in accordance with the present invention.
  • Fig. 34 shows a schematic diagram of a master circuit embodiment in accordance with the present invention.
  • Fig. 35 shows a schematic diagram of an embodiment of a multi-stage, multi-mode system power circuit that derives power for the balancer from a string in accordance with the present invention.
  • Fig. 36 shows a schematic diagram of an isolated controller according to an embodiment of the present invention that provides for sampling and control of a second string having an alternate ground reference potential.
  • Fig. 37A shows an end-on view of electronics within a balancer system according to the present invention.
  • 80 1 Fig. 37B shows a rotated view of electronics within a balancer system according to the present invention.
  • Fig, 37C shows an alternate rotated view of the electronics of a balancer system according to the present invention.
  • microcontroller refers to a digital system that can perform a programmed function, e.g., a standard microcontroller, FPOA, CPLD, microprocessor, computer, ASIC, system on a chip, or composite assemblies of parts that can perform a function.
  • a switch refers to something whose conductivity can be made to change, e.g., MOSFETs, IGBTs, fets, bipolar transistors, SCRs, mechanical switches, mechanical and solid state relays, contactors, an IGBT in parallel combination with a free-wheeling diode such as a fast-recovery diode, a series combination of a MOSFET and blocking diode oriented oppositely to the MOSFET body diode, a series combination of MOSFETs connected such that their body diodes are oppositely oriented, and the like.
  • Embodiments of the present invention relate to a concentrated photovoltaic- based power plant for utility-scale electricity generation.
  • An architecture of the plant is driven by at least the following two considerations. First, the plant is designed to be readily scalable to produce power levels relevant to global energy consumption.
  • the plant is designed to achieve the minimum possible levelized cost of energy.
  • This minimum cost includes various aspects of producing power, including but not limited to initial capital costs, installation costs, maintenance costs, and consumable costs, [8096]
  • power plants are designed that can be routinely upgraded by improved firmware and software, and managed obsolescence of rapidly evolving components. Certain cost savings are based on making maximal use of phenomena and materials that are economic externalities, for example the use of air and soil as structural elements. Other cost savings may be achieved by forming a rigid concave reflector shape of a thin film under air pressure.
  • the architecture of the power distribution system can utilize a similar cost-saving philosophy.
  • Particular embodiments of the present invention utilize inflated reflective films, or "balloons", to concentrate light onto photovoltaic receivers. Additional details describing various embodiments of inflatable solar concentrator balloon methods and apparatuses, which may be suited for use in accordance with the present invention, can be found in U.S. Patent Application No. 1 1/843,531, which is published as U.S. Patent Publication No. 2008/0047546 and U.S. Provisional Patent Application No. 61 /299124, which are both incorporated by reference in their entirety for all530poses. Additional details describing various embodiments of receiver structures, which may be suited for use in accordance with the present invention, can be found in U.S. Patent Application No.
  • Each mirror may reflect light from an approximate 2.25-3 m diameter area to a secondary optic roughly 200 mm in diameter. This secondary optic distributes and further concentrates light by a factor of approximately 2-3, onto a dense array of photovoltaic die, while providing passive optical compensation for pointing-angle errors. Additional details describing various embodiments of secondary optic structures and interconnection of die can be found in U.S. Patent Application No. 12/720,429, which is incorporated by reference in its entirety for all purposes.
  • dies may be series-connected in substrings. These substrings can be joined together in series and/or parallel combinations to provide passive electrical compensation for pointing-angle errors.
  • Figure 5A shows an embodiment (500) of a physical lay out of die (e.g., 502) on a receiver substrate (504). Some sequences of adjacent die may be series connected in strings, for example 506.
  • strings may be paralleled with others to provide substantially the same total power output when pointing is non-ideal.
  • string 506 could be paralleled with string 508, 510, or 512.
  • a region of die 514 are substantially series connected.
  • compensation may be provided near the center, for example via paralleling strings 516 and 518, 520, or 522.
  • FIG. 5B shows a schematic diagram 530 of a electrical circuit in a receiver sho wing an assortment of design elements aimed at improving off- design, e.g., mis- pointed, receiver performance.
  • Solar cell die e.g., 532
  • Element 538 may be a diode, typically a Sehottky diode because of its low forward voltage drop, that provides an alternate current conduction path when the string current is greater than that supported by the photocurrent produced by the die. Such a ease can arise when one or a plurality of die in a siring are under-illuminated.
  • a number of die in a string bypassed by a Sehottky diode may be judiciously chosen, and this number may vary from one string (e.g., 536) to another (e.g., 540). Considerations in this choice can include but are not limited to including the reverse breakdown voltage of the solar cells, the receiver-location-speciftc variation in illumination, and others.
  • a plurality of strings e.g., 542 and 544 may be paralleled, and the combination are protected by a diode 546 across the terminals of the strings 548.
  • individual die or a substring of die may be paralleled via connections 550 and bypass diode(s) inserted across the terminals of the strings 552.
  • bypass diodes e.g., 554, may be arranged to reduce the cumulativ e voltage drop of a plurality of bypass diodes if multiple diodes are forward biased.
  • the voltage between receiver terminals 556 and 558 is the receiver output voltage.
  • the size of capacitance can be chosen judiciously according to one or more considerations.
  • a smaller capacitor is typically less expensive than a bigger one, but isolates the receiver from current ripple arising from switching circuitry less. This current ripple may reduce efficiency by causing the receiver to depart periodically from its maximum-power-production region.
  • An excessively large capacitor may cause problems with high inrush currents in switching circuits, such currents being far larger than could be sustained by the receiver. This could thereby increase potential current stresses, and possibly requiring additional protection circuitry and snubbing.
  • One element of certain embodiments according to the present invention is the use of a capacitor that is small enough to obviate or mitigate source-side over-current protection.
  • An objective of the secondary optic/receiver design is to provide peak power output for the largest possible pointing errors. In some situations, it may be appropriate for a receiver to produce more than one voltage or current output. Such a configuration avoids excessively dividing the receiver voltage by paralleling to a common voltage that all substrings can support.
  • a target power for each receiver is O (600-1000 W) with a voltage of 0 (100 V). Using silicon solar cells, this corresponds to approximately 200-400 individual die, given some paralleling of strings.
  • O 600- 1000 W
  • 600W 600W to 1000W.
  • concentrators are grouped into a cluster, for example 8 balloons that share a common support and tracking structure and inflation controller. Additional details describing various embodiments of balloon support and/or tracking structures can be found in U.S. Patent Application No. 1 1 /844,877, which has been published as U.S. Patent Publication No. 2008/0168981 and U.S. Provisional Patent Application No.
  • FIG. 6 shows such a cluster 600 of collectors.
  • Elements 602 are concentrators
  • element 604 is a structure that supports the concentrators.
  • Elements 606 are receivers that convert light that fell on the mirrors of 602. [8114] in some embodiments, each cluster produces approximately between 6-8 kW. The output or outputs of individual concentrators are series connected.
  • the maximum power of each concentrator is expected to vary significantly (e.g., up to 30%) over the life-span of its reflector. This variance can depend on such factors as the model of the reflector, and variations in the receiver.
  • each concentrator In order to maximize the total power produced by the cluster, each concentrator can be operated near its maximum power point, which requires excess or deficit currents to be drawn or supplied individually to each concentrator by a balance circuit. Where the strings are series connected, this balance circuitry only needs to supply or draw imbalance currents (for example ⁇ 30% of the total load), thereby providing the dual advantage of requiring lower-rated circuitry and dramatically reducing the dependence of the overall efficiency on the efficiency of the balance circuitry.
  • the DC voltage from each cluster may be transmitted on high-inductance twisted pairs of aluminum wires having optimized cross-sectional area.
  • the length of these individual wires in a power plant may be between about 300- 1000 m, because of the relative diffuseness of the solar power resource. With a 0.5 cm air-spaced helix, it is practical to obtain inductances of several hundred micro-Henries over transmission lines of this distance, reducing the need for input filter inductors for properly chosen inverter architectures (and obviating them in some arrangements).
  • the DC power from each cluster goes to individual three-phase inverter circuits that are massively interleaved.
  • the DC power from clusters may not be combined in order to reduce the wire conductor count.
  • a cost of the small amount of extra insulator material to keep the lines separate is more than offset by the elimination of power-sharing concerns among the interleaved inverters.
  • a 1 M W plant can include approximately 200 clusters, thus O(200) interleaved inverters are combined to produce precision sinusoidal outputs with minimal filtering.
  • Inverters may be co-localized, simplifying maintenance and high- frequency coordinated interleaving. These inverters are preferably arranged in a factor pre-assembled and tested rack system in a standard shipping container.
  • the primary power path of these inverters is completely transformer-less. This is because transformers are expensive in up-front capital costs, produce significant parasitic electrical losses, and require ongoing maintenance.
  • the function of electrical system isolation may be served by the main power plant step-up transformer at the point of electrical interconnection with the grid.
  • this main plant transformer can comprise four single- phase transformers, with three normally in service and the fourth serving as a plant spare.
  • the transformers will also be co-located with the inverter (within -30 m).
  • Design of a power plant according to embodiments of the present invention may be guided by one or more of the following principles.
  • Efficiency may be pursued only as cost justified. This is due to the marginal cost of increased DC power production of a technology-specific cost per Watt, for example less than about $0.50-5.00 /W,
  • Chopper/switcher circuit architectures may be utilized ihai benefit from the inductance of the interconnect wires. An example is where the inductance of the interconnect wires replaces or is in series with, a discrete inductor.
  • DC currents from separate sources are not combined. Rather, the DC currents are run parallel to separate switching circuitry in order to avoid issues of power balancing.
  • Separate switching circuitry may be massively interleaved. This interleaving is finely timed in order to reduce switching stresses.
  • Separate switching circuits may be grouped to one location, and in some cases to one enclosure. Such grouping can minimize component duplication, facilitate interleaving and high- frequency communications and coordination, minimize enclosure cost, minimize maintenance costs, minimize enclosure and interconnection costs, etc.
  • Water cool switches, capacitors, and/or inductors can be used to save on heat sinks, and extend component life, reduce size, eliminate fans and openings to the environment.
  • Elements that tend to fail may be .grouped in minimum units, e.g., single IGBT or MQSFET-f driver, and these groupings are made easily and safely swappable in the field. These are consumable paiis, and should be minimized along with the cost of replacing them.
  • the system can also be designed to eliminate throwing good parts away with bad ones because of co-packaging, for example the case with IGBT "six- packs.”
  • Elements are packaged soundly to prevent secondary damage or contamination on failure.
  • An example of this is packaging to contain exploding electrolytics or burning IGBTs.
  • a hybrid of analog and digital control may be used for the best dynamic response and pseudo-static optimizations. This is referred to as managed one-cycle control (mOCC).
  • mOCC managed one-cycle control
  • the system may be designed to be able to oppose non-ideal grid waveforms, such as departure from smusoidaliry and to control production of imaginary power. This opposition could require the attention and intervention on a sub-cycle or cycle- to-cycle basis of a microcontroller. This behavior may be useful for solar power plants to become majority power producers.
  • the interleaved inverter may be designed to degrade gracefully when inverters fail or clusters are taken offline.
  • Essential communications can be performed using wired connections, preferably using RS485 physical layers or similarly mature and robust links. Wireless links may be used for non-essential control or monitoring or for sparse auxiliary equipment such as weather stations and video surveillance/monitoring/event troubleshooting. Barring new developments, optical links should be used only if necessary because of cost concerns.
  • Microcontroller firmware can be updated from a central location, for example via a plant-local RS485/Ethernet network.
  • Remote debugging and control may be implemented over a plant-focal network.
  • the plant network can comprise RS485/Ethernet and preferably via a non-local network such as the internet.
  • All elements of the power system can be designed to survive lightning strikes to the plant without damage, via lightning-rods, grounding, and appropriate transient suppression at entry and exit points of shielded enclosures.
  • the receiver may contain a ⁇ 20G-mm diameter, one-layer, high-heat- transfer, printed circuit board bearing a radial array of rectangular silicon solar cell die attached to printed circuit traces via eutectic solder and aluminum wire or ribbon bonds.
  • the individual die may be series connected into a number of strings.
  • the board is kept cool via impingement of numerous immersed jets of cool water on the back side of the printed circuit board that is electrically insulated from the front circuitry by a thin thermally conductive ceramic dielectric.
  • the power from strings is earned via multiple conductors from this primary printed circuit board to a nearby conventional printed circuit board, for combining in parallel and series arrangements to reduce the effect of concentrator mis-alignment on power output.
  • An example is shown in Figures 5A and B. It is possible that the final receiver supplies more than one voltage/current through separate outputs if it is impractical to achieve enough passive electrical alignment-error compensation otherwise.
  • This secondary board may also contain filter capacitors, bypass diodes, active switching circuitry, and sensing circuitry. Water cooling is available for this circuit board, if needed.
  • This board can be located at the interior of the concentrator at heights that make servicing difficult. Therefore it may not be an ideal location for components that require periodic replacement, such as electrolytics.
  • the target voltage for the receiver is 0(100 V @ 8 A). This voltage may be produced by a series and parallel combination of -200 to 400 silicon solar cell die illuminated at several hundred suns concentration. For minimal support stmcture stifmess requirements, the mass of the receiver should be kept at a practical minimum.
  • the physical receiver comprises an approximately 200-mm diameter one-layer die- mount board with conventional secondary PCB for string combining and / or active power circuitry and/or sensing circuitry.
  • the receiver employs passive electrical compensation coupled with passive optical compensation.
  • the receiver provides for active compensation of imbalance currents/voltages of substrings to approximate MPPT across in-homogeneously illuminated receiver.
  • the receiver includes high-frequency filter capacitors, preferably on a secondary, conventional, printed circuit board. * The mass of the receiver should be as low as practical.
  • a cluster comprises multiple concentrators in proximity, for example as shown in Fig. 6.
  • a cluster comprises 0(8) concentrators.
  • Clusters of concentrators share support structure, track together, and share control circuitry in an easily serviced enclosure, typically within about 8-10 m of wire distance of the furthest receivers.
  • the receivers may supply only O(100 V). These modules may be connected in series to obtain a voltage O(600- 1000 V) at -8 A for efficient plant-scale (e.g., 300-1000 m) DC-transmission to our inverter circuitry.
  • circuitry is needed to shunt currents to and/or from each receiver to ensure each receiver is individually power optimized. This circuitry is referred to as "balance circuitry.”
  • Figure 1A illustrates an arrangement 100 of balancing circuitry according to an embodiment of the present invention, that supports a cluster of N receivers 102.
  • the receivers are series connected via conductors 104 through which a common current z ' o flows.
  • An array of "Balancers" 106 either unidireetionally draws current 108, unidireetionally supplies current 1 10, or bidirectionally passes current 1 12 through shunt paths. This allows each receiver to supply a total current different from ig, such that each receiver independently operates at its maximum power point.
  • the output voltage 1 14 relative to the current return 1 16 is the sum of the receiver voltages.
  • the output current is the sum of the common current io and the individual Balancer currents t, which could be positive or negative depending on the design of the Balancers.
  • FIG. 1 The specific balancing arrangement shown in Fig. 1 . represents just one embodiment, and alternatives are possible. For example, other embodiments may employ parallel input connections and -imbalance-voltage balancing, drawing and supplying power to or from a separate DC or AC line, etc.
  • Fig. 1 A The Balancer system according to an embodiment of the present invention shown in Fig. 1 A, may be contrasted with conventional configurations.
  • Fig. IB shows a conventional cluster 130 of series-connected 134 receivers 132. In this approach, all receivers must pass the same current, producing the maximum possible power only if the receivers and their illumination is suitably matched.
  • Figure 1 C shows a conventional approach 150 to handling power imbalances among clusters of receivers 1 52.
  • Separate switching circuits 154 operate so as to draw the maximum power 156 from each receiver, producing a common output voltage Y b to paralleled outputs across 158 and 160.
  • Fig. ID shows a conventional cluster 170 in which maximum- power-point tracking switchers 172 are series connected, producing a common output current.
  • These switchers can be converters, producing a DC output or inverters, producing one or more phases of AC output.
  • the design 180 in Fig. IE shows an alternate arrangement of balancer circuits which can pass current 182. bi-directionally between each receiver without the need for a direct connection to each other or a connection to a power bus. Instead, balance currents are passed via at least one transformer 184 which inductively couples outputs of balancers 186.
  • the Balancers may be designed to support a maximum current imbalance that is considerably lower than the maximum expected series current in. In normal operation, it would be unlikely for receivers to exhibit more than a certain variation in output power relative to each other, for example between about 5-20%.
  • the Balancer may be designed for best efficiency in this normal range and / or a reduced efficiency up to a maximum power rating. This de-rating of the balance circuit can considerably reduce cost.
  • the required efficiency of the balance circuit is much lower than if it operated on the full power output of the recei v er. For example, if a Balancer has an efficiency of 80% while Balancing 20% of the receiver current, the overall power efficiency, assuming no series connection losses, is a respectable 96%. The reduced efficiency requirements translate to further cost savings.
  • the weakest-performing active receiver in a cluster could be shut down.
  • Balaneers that draw excess receiver current as in 108 must be coordinated (for example via communications or handshaking) because a maximum power condition at a Balancer associated with the top-performing receiver can prompt the shut-down of the bottom-performing receiver.
  • shutting down a weak-performing receiver may be prompted by a net reduction in output associated with inefficiencies in the Balance circuits.
  • the Balancer may 1) actively short-circuit its associated receiver (in the manner of a synchronous rectifier switch using mechanical relays or solid state switches), 2) passively bypass the associated receiver with a diode, or 3) perform no operation if its associated receiver has acceptable bypass elements. If the receiver uses synchronous rectification, it may be paralleled with passive bypass circuitry so the Balancer may periodically deactivate the bypass switch to cheek to see if the receiver performance has changed. It may be advantageous to choose a balance-circuit architecture that utilizes switches that can short-circuit the receiver when kept turned on.
  • the power used by a. balancer circuit can be supplied in whole or in part by the voltage V) from its associated receiver or by the voltage ⁇ V f from the cluster or from an alternate power source.
  • the power source for critical balancer circuitry (such as microcontrollers), must be designed and managed judiciously to ensure de vices do not "brown out” or enter indeterminate states, and to ensure that the system remains in control and responsive as needed, regardless of energy production from its associated receiver and to a lesser extent, its cluster.
  • Receivers may be routinely inoperative, for example during and awaiting concentrator maintenance. Mis-pointed clusters will also lose locally generated power. Careful consideration of the power source at least for critical elements of the balance circuitry is necessary. It may be advantageous to pow r er this critical circuitry via a separate non-volatile power source, or for the cluster voltage to be maintained at a minimum level that allows critical operations via a low-power centralized supply.
  • the power supplied to or harvested from the modules is locally provided at least substantially from the solar cells. Excess power harvested from a receiver may ⁇ be injected to the 600-800 V output of the array. For an 8-receiver cluster, this involves a voltage step up of ⁇ 8x from the receiver voltage. This voltage step up can be made efficient by utilizing an appropriate winding ratio in the isolation transformer that is needed to allow balance circuits to float relative to the cluster ouiput. Such large voltage adjustments are generally to be made only where a transformer is otherwise required, and a turns ratio is employed judiciously to maintain efficiency. [8174] Boost and buck or buck/boost circuitry could be used in such balance circuits.
  • the Balancers shown in Fig. 1A have inputs and outputs that are isolated. The voltage at the output is ⁇ N times that at the input, since it is the result of series connecting as many as N receivers, given that some receivers may be bypassed.
  • the balancer circuit may therefore use an isolation step-up transformer having an appropriate turns ratio to ensure efficient switching behavior.
  • the Balancers are able to de tect the maximum power point of the receiver. This generally requires the Balancer to have information about both the receiver output voltage and the total receiver output current.
  • the Balancers can readily measure the currents i, a and voltages V,, but cannot as easily measure the common current in. Measuring i 0 can be accomplished by having a "master" controller that senses the common current and reports it to slave controllers in each balance circuit. [8177] Because the data is common to all controllers, it can be transmitted as a broadcast to all slaves simultaneously. By dithering or some other such perturbation, each balance controller can then establish the maximum power point or the paih toward the maximum power point of its receiver.
  • digital communications may comprise conduction-based signaling such as differential voltage signaling (e.g., RS485, Ethernet, and others), single-ended voltage signaling (e.g., RS232), current loop signaling (including voltage, current or others), or RF signaling that is multiplexed on conductors (e.g., coaxial cables, twisted pairs, or power lines), inductively coupled signals, capac vely coupled signals, free-space RF signaling (e.g., WiFi, blue tooth, or others), microwave links, optical signaling (e.g., via free-space, light-pipe, optocoupled, or fiber transmission and reception of LED or laser light).
  • Optical signaling can involve modulated reflection or scattering of ambient light, for example using visual patterns that are remotely discernable by the eye, camera, or other sensor.
  • Digital communications as used herein may be synchronous or
  • Digital communications may involve 1 -wire, 2-wire, 3-wire, 4-wire, or more-wire signaling. These signals may utilize an application-specific standard or conform to established standards, such as Ethernet, WiFi, USB, IEEE 1394, modbus, CAN bus, PROFl-bus, one-wire protocols, SPI, I2C, HDMJ, or alternate standards for electronic signaling. Some signaling standards provide acceptable communication bit error rates at the necessary data bandwidth and across the necessary physical disiances in spite of electronic, RF, or optical interference at low cost. Digital signaling at the lowest level in the hierarchy may be the most cost sensitive. Digital signaling at the highest level in the plant hierarchy may be the most bandwidth sensitive.
  • FIG. 7 shows a schematic block diagram of an embodiment of a master/slave arrangement of balancers (700).
  • Element 702 is a master controller that digitally communicates to a network of the plant (for example a cluster-wide level in the plan hierarchy) via signals 704, and digitally communicates to balancer slave circuits 706 via an interface 708 and 710.
  • the transmissions from the master are common (bussed) to balancer slaves, and the transmissions from slaves are separate. Possible alternate arrangements may comprise bussed transmissions from slaves or separate transmissions from the master.
  • the particular arrangement of the interface 708 and 710 reflects the asymmetry in communicated data. For example, a master may frequently need to communicate the common string current to ihe balancers so ihat ihey can perform their power-point tracking. The master may also request status, voltage, or balancer current of all devices frequently to assess the state of the system. Communications to individual devices may also be required.
  • a master/slave balancer architecture may further comprise a diode 712 ihai blocks a reverse cluster current.
  • a diode 712 ihai blocks a reverse cluster current.
  • such a diode may not be favored because of the forward diode drop voltage, l rge required reverse breakdown voltage and cost.
  • Some embodiments may further comprise a switch 714 to provide a direct connection between the cluster output and remote-conduction cable, in some embodiments, this switch may be controlled electrically, e.g., via master 702.
  • Embodiments containing 714 may be used to provide for eliminating the forward diode drop of an element 712 or may be used for synchronous rectification.
  • remote conduction describes a plant-scale length of conduction of power. Some embodiments may have neither 712 nor 714, and the connection between the remotely conducted positive cluster output 716, and local positive cluster voltage 718 may simply be a conductor. Such an arrangement may reduce cost and improve efficiency at the expense of a possible increase in the requirements of the inverter to control power flow to and from a cluster.
  • Some embodiments may comprise switch 714 as a manual isolator switch to provide for servicing. Some embodiments may provide a bypass diode 720 external to the receiver (e.g., to provide a path for current if a collector is grossly underperforming or inoperative). [8188] Some embodiments contain a switch 722 to provide a direct conduction path to bypass a collector. Such a switch may further provide for short-circuiting a receiver to facilitate maintenance, to reduce the string voltage, etc.
  • Such as switch may be manual, mechanically actuated, or electrically actuated.
  • Mechanically actuated switches may comprise solenoid actuated switches such as relays or latching relays. Mechanically actuated switches may further comprise switches having motor or pneumatic actuation, which can provide potential benefits of large contact separation that may be difficult or power intensive to accomplish with solenoids.
  • switches are co-located so a reduced number of actuators may be used.
  • a motor such as a brushless DC motor, stepper motor, or brushed DC motor may be used to select a switch from a group (e.g., 724), and another motor to actuate the selected switch.
  • a first motor selects a switch
  • a solenoid or second motor engages with the selected switch, and the first motor actuates the switch.
  • Embodiments using such a motorized switching array may offer one or more benefits, including but not limited to:
  • Connection 726 represents conductors spanning a distance from a receiver to the point 728 where the receivers are physically connected in series. In some embodiments, this distance may be of the order I to 5 m.
  • Connection 730 represents conductors spanning the distance between the series connection point 728 and the balancer input 732. In some embodiments this distance may be of the order 1 to 30 m.
  • Capacitor 734 may alternatively located or paralleled with a second capacitance at positions 728 and 732.
  • Element 736 is a receiver from an array of N receivers 738, that are series connected at 740.
  • the balancer master may measure the series cluster current, for example by the use of a low-side current-sensing resistor 742.
  • a resistor might comprise a number of low-valued resistor technologies, including metal ribbon, carbon composition, metal wire, and specially-designed printed circuit board trace.
  • the variation in resistance with temperature may optionally be compensated for by providing the master circ it with an ability to measure or infer the resistor temperature. Such a measurement may be accomplished by thermistors, varistors, thermocouples, transistors, diodes, and/or integrated circuits, via capacitively coupled or directly coupled known currents flowing through the same trace or a substantially proximal trace.
  • a possible advantage of the architecture is the ability for the balancer master to measure current directly via a sensing resistor on the low side.
  • the balancer master may measure current via a resistor on the high side or by a non-resistor-based means.
  • the current may be measured using hall effects, and other magnetic-based measurements.
  • a balancer master may update its current calibration via coordination with an inverter.
  • An inverter may allow for a precision or precisely known current to flow to the cluster. This current may be digitally communicated to the balancer, which could revise its calibration to match that from the inverter.
  • this message and recal bration would be performed frequently enough to obviate temperature compensation.
  • An advantage of such an arrangement is that the inverter connected to the cluster may be centrally disposed with a number of other inverters that could time share a common precision current sensing or reference capability to minimize the per-cluster cost of this ability.
  • the balancer master may measure the cluster Kunststoffage, for example via a resistive voltage divider.
  • the balancer master may mea sure each receiver voltage using a chain of voltage dividers.
  • the master may transmit this voltage information to a slave digitally.
  • the balancer master may receive reports of individual balancer voltages from its slaves digitally, if needed.
  • Figure 8 shows a schematic diagram of an embodiment of a balancer slave 800 according to the present invention.
  • the balancer slave circuitry is referenced to the negative voltage from the receiver (802).
  • the slave circuitry could be referenced to the positive voltage from the receiver (804) to the negative or positive voltage of the cluster, to a sculptureage from another receiver, to earth ground, or to anotherroisage.
  • the arrangement of Figure 8 may offer a benefit in that the only necessary voltage isolation is in the digital communications with the master, 806 and 808, for which a large number of effective and inexpensive isolator technologies are available (for example optocouplers, inductively or capacitiveiy coupled isolators).
  • Element 810 is a substantially digital controller, which may comprise an ASIC, microcontroller, microprocessor, PLD, CPLD, FPGA, and the like. This controller may provide for analog-to-digital conversion of the receiver voltage, via for example,, a resistive voltage divider 812, balancer current (such as via current-sensing resistor 814), and / or other parameters, such as temperature, switch temperature, analog signals involved with power maximization, etc. In addition, the controller 810 may provide one or a plurality of analog outputs (for example 816) to a power electronics circuit 818. [8204] One or more of these outputs could be produced in part by pulse-width modulation of digital signals.
  • one such analog signal may comprise a power calculated from the product of receiver voltage and string current. In some embodiments, this signal may comprise a power calculated from the product of the receiver voltage and sensed current, in some embodiments this signal may comprise a combination of both.
  • the relative weighting of these combined powers may be adjusted to account for circuit losses and sensor inaccuracy.
  • an analog signal is proportional to a weighted sum of the receiver and string current wherein the weights are adjusted similarly.
  • Digital control and indicator signals may pass between 810 and pow r er stage 818 over lines 817.
  • Such a power electronics stage may utilize elements of one-eycle- control or analog feedback for performing agile maximum power-point tracking, using analog versions of signals such as the string current or string voltage for this purpose.
  • the string voltage communicated from 810 to 81 8 may be the voltage from the voltage divider 812 or a processed (e.g., filtered or amplified) version of that voltage.
  • the interface may- manipulate an analog signal to adjust the behavior of power stage 818, An example of such manipulation is to adjust the control system to achieve better efficiency.
  • power stage 818 may provide for fast response to transients but less favorable power point optimization.
  • Controller 810 may use analog signaling or manipulation or analog signals 816 or digital signaling 817 to trim the control of 818 to achieve both fast responsiveness and high accuracy.
  • circuitry 812 and 814 may be referenced to a common negative voltage or local ground shared by the circuitry 818 and 810.
  • the balancer master may assist the balancer slave with current and voltage calibration. For example, the balancer master may first calibrate its own. current sensing resistor, for example by disabling all balancers and receiving an accurate current reading from a central inverter. [8210] Next the balancer master may enable a balancer slave to operate. The balancer master may then infer what actual current the balancer is supplying to the cluster by measuring the string current and receiving a report of the cluster current from the inverter.
  • the balancer master may then transmit this information to the balancer slave, which can use it to infer an adjustment calibration factor to apply to its own receiver-side-current sense measurement. This may be done by tweaking an analog signal via a PWM line, by changing a parameter in the calculation of an analog signal produced via PWM or some alternative digital-to-analog conversion.
  • the receiver- side parameters can thereby be adjusted relative to the cluster-side power performance, which implicitly accounts for balancer circuit non-ideality and inefficiency,
  • the balancer master can short-circuit a receiver and receive an accurate voltage report from a central inverter then re-enable the receiver and receive a second accurate voltage report from a central inverter. The difference in these measurements can inform the voltage calibration of the balancer slave.
  • the balancer slave may sweep a calibration parameter over a range of values until the measured cluster power is maximized. This procedure may be requested by the balancer master, who would provide feedback on the results of the sweep experiment. [8215] In some embodiments the effect of sweeps is measured at the central inverter. This can potentially provide better overall system power optimization indications than is possible local to the balancer.
  • both types of optimizations are made at different intervals.
  • the balancer master may undergo such a calibration at one interval utilizing the central inverter.
  • the balancer master may then perform a calibration of its balancer slaves at another interval, either involving the central inverter or not. Calibrations that do not involve the central inverter may be conducted more frequently than those that do, since the central inverter generally services a large plurality of clusters.
  • a balancer master is not connected to a cooperative inverter.
  • the balancer master may have sufficient circuitry to perform power optimization without accurate quantification, because it can perform power maximization without knowing absolute power, or it may have sufficient circuitry for absolute power measurement, for example if it desired to use the balancer for power quantification.
  • a DC-DC power supply may draw power from ihe receiver to produce logic power 822 and power for analog circuitry and switch gates, 824, In some embodiments, this supply does not allow the logic or gate power voltage to drop below a certain level, to avoid improper operation of the balancer.
  • this power may be provided from the cluster voltage, which may be "uninterruptible," or some other power source. However, there may be no need to operate a baiancer when insufficient power is avaiiabie from ihe receiver to ran the balancer slave circuit.
  • Certain embodiments of the present invention may carefully design elements 818, 810, and 820, such that the circuits power up, operate, and power down favorably with wide swings in the power output of the receiver.
  • this bus is separate from the cluster. In some embodiments this bus is isolated, in other embodiments the bus may share a common voltage,
  • the bus is serially connected to the receiver string, for example between intermediate receivers in a string, or before or after a terminal receiver.
  • the bus is connected to a bus voltage derived by a DC to DC converter from the cluster voltage.
  • this converter is a boost converter, a buck, converter, or a buck-boost converter.
  • the sum of the operations of the balancing circuits is minimized. For example, if the balancing circuits work by drawing current from the receiver, an optimal operating condition exists in which at least one, weakest-performing receiver is at its maximum power point with zero current drawn by its balance circuit. Conversely, if the balance circuits supply current, an optimal operating condition exists in which at least one, strongest- performing receiver is at its maximum power point with zero current supplied by its balance circuit,
  • the master In either case, it is possible for the master to stabilize a control loop near this optimal condition, by monitoring the presence of a response or flag set by one or more balance circuits that they are at or past a zero-shunt-current maximum-power condition. Tf the master detects at least one zero-current condition report, it can instruct all balance circuits to increase their average current draw/supply over the following time interval by an increment until no balance controllers are signaling a zero-current condition. If no balance circuits are reporting zero-current, the master can instruct all slaves to reduce their average current draw/supply. By repetitively operating in such a manner, the master can ensure that this optimum operation is closely tracked.
  • the master controller can alternatively force controllers to adjust their balance circuits in a particular direction by intentionally under- or over-reporting the common current.
  • more sophisticated control methods can be employed to improve the maximum power-point tracking frequency response for given signaling bandwidths, or if the balance circuits are bi-directional and the optimal operating point is not sensed by a zero-current condition.
  • Other considerations, such as minimum or maximum operating voltages or currents may require the cluster to operate away from these maximum-efficiency settings.
  • the Balancer is able to measure the receiver voltage(s) and the balance current. The total power can be calculated by multiplying the measured voltage with the total receiver current.
  • Circuitry associated with the balancer can be used to provide benefits for the plant. One example of such a use is the activel control of the maximum cluster voltage, such as to avoid over voltage if the cluster load is low. in some
  • such a function could be performed rapidly via switches associated with the balancers.
  • this function may be hardware supported. For example, a minimum number of collectors could be short-circuited if an overvoltage threatens. This threat could be detected by a fast comparator, allowing the balancer to assist with protection of the cluster's inverter.
  • output of a cluster could be clamped by a conventional over-voltage suppressor such as a zener diode.
  • the suppressor reduces the need for response speed.
  • the balancer microcontroller may be able to force a short circuit in one or more collectors before any device is damaged.
  • the cluster's inverter can be designed such that it can tolerate the full open-circuit voltage of a high-performing cluster. Design tradeoffs in the inverter switches, however, may lead to reduced power efficiency or increased cost.
  • the inverter is designed to handle the full open-circuit voltage.
  • An active clamping scheme utilizing the balancer may provide an additional margin of safety.
  • the balance controller may need to convert the digitally reported common current reading it receives to an analog signal, e.g., via a pulse-width modulation fPWM) or digital to analog (D/A) peripheral, if the maximum power-point optimization is done via an analog control system.
  • the balance controller can intentionally skew this analog signal to force the control loop in a desired direction.
  • An advantage of using an analog control system is the ability to maintain a tight and accurate high-frequency control loop without perturbations from microcontroller latency and multi-tasking.
  • a hybrid of the one-cycle control (OCC) methodology" managed and adjusted by a microcontroller offers a good balance of frequency response and sophisticated controllability. Such a scheme is referred to as a managed OCC (mOCC).
  • mOCC managed OCC
  • This circuitry may require a frequency response of at least several Hz to several tens of Hz if dynamic fluctuations, e.g., from wind-loading are to be compensated.
  • Simple digital control schemes generally require a high degree of oversampling to perform well.
  • FIGS. 2A-2D show a variety of simplified balancer schematic diagrams according to embodiments of the present invention.
  • Figure 2A show s a balancer circuit arrangement (200) in which the balancer circuit for each receiver is separate.
  • the receiver power source equivalent circuit (202) shows interconnect inductance and possibly added inductance (204) in its path to the series connection 206, Additional interconnect inductance and possibly added inductance (208) is in the path to the balancer circuit.
  • Element 212 is drawn as an enhancement mode N-channel MOSFET, but can be any electrically controlled switch.
  • the full bridge 214 drives a coil in step-up transformer 216.
  • Elements 218 and 219 represent the transformer leakage inductance and in some cases an added inductor. Alternately, a half-bridge driver could be employed as is known in the art.
  • the full bridge 220 and filter 222 comprise the side of the balancer circuit that works at the cluster voltage (224 to 226).
  • this balancer circuit can be bidirectional .
  • FIGS. 2AA through 2AC sho simplified schematics of alternative circuits that provide for bi-directional power flow according to embodiments of the present invention.
  • Circuit 230 in Fig. 2AA shows a bidirectional isolated flyback converter.
  • flyback step up transformer 233 must be carefully designed with a substantial leakage inductance. In some embodiments of the present invention, the flyback transformer
  • 233 may comprise additional taps or windings to improve efficiency by recovering demagnetization energy.
  • Figure 2AB shows a simplified schematic diagram of a half-bridge bidirectional converter 235 according the an embodiment of the present invention.
  • This converter comprises two switches on both the receiver and cluster side and a discrete inductor 236.
  • This additional circuitry may improve conversion efficiency over that of the circuit in Fig. 2AA.
  • Figure 2AC shows a simplified schematic diagram of a bi-directional Cuk converter. This converter has the advantage of fewer switches than in the circuit of Fig. 2AB. However, the full converted power must pass through multiple capacitors 239 and other components that are not lossless in practical implementations, which in some cases may reduce conversion efficiency.
  • this bridge works as a synchronous rectifier, which could alternatively be replaced by a diode bridge.
  • the bridge 214 could be replaced by a diode bridge.
  • the diode's forward voltage would have a greater effect on efficiency.
  • element 214 can be used to bypass a receiver. However losses in the filter 210 and perhaps inductance 208 may justify placing an active or passive bypass closer to the receiver.
  • Each balancer can be completely modular, or may share control circuitry to provide for enhanced coordination between bal ncers and reduced component costs.
  • a degree of soft switching can be achieved by judicious use of the inductances and capacitances on the receiver side (204, 208, 210, and 218), and in some cases by coordinating timing between switching of the balance circuits through the series connections 206 on the receiver side and parallel connections 228 on the cluster side.
  • Coupling on the cluster side could be enhanced, for example by the addition of one or more passive elements, such as inductor 230.
  • Figure 2B shows an alternative arrangement or balancer circuitry 240 in which a single multiple-tap transformer 242 is employed. Separate switcher circuits 244 feed isolated taps 246 of the transformer.
  • a common switcher circuit 248 is connected to the cluster voltages. For unidirectional operation, this switcher circuit could be replaced by a diode bridge. However, unlike in Fig. 2A, at least one active switch is required in the circuit 244 to control the relative amount of balancing current flow . [8248]
  • the use of a single transformer produces strong coupling between the balancer circuits 244, providing for soft switching via careful time synchronization. The use of a single transformer may provide additional savings in magnetics.
  • the transformer can be sized for the maximum imbalance power to be processed. This limit is generally less than (he sum of the maximum permissible power imbalances of each individual receiver.
  • Figure 2C shows a balancer circuit 260 that employs a passive rectifier bridge 262.
  • Figure 2D shows a balancer circuit 270 that employs a transformer 272 that has isolated, coupled windings 274. Rather than flowing power to or from the cluster output, this circuit draws and supplies currents as needed to operate each receiver near its maximum power point.
  • Figure 2EA to 2EC shows simplified schematic diagrams of alternative embodiments of unidirectional isolated converter circuits according to elements of the present invention that have switching circuitry solely on the receiver side. In some alternative embodiments, these converters may be reversed such that all switching circuitry lies on the cluster side.
  • Figure 2EA shows an isolated flyback converter 280.
  • the isolation and step-up transformer 282 is designed to have leakage inductance to permit the low- component-count circuit.
  • the transformer is designed to have additional windings or taps that feed circuitry that recovers magnetization energy that would otherwise be lost when switching.
  • Figure 2EB shows a schematic diagram of an embodiment of a two-switch forward isolated converter circuit 288 that may be employed in a balancer according to the present invention.
  • Figure 2EC shows a schematic diagram of an embodiment of an isolated Cuk converter circuit 294 that may be employed in a balancer according to the present invention.
  • the circuit embodiments in Figure 2 may contain additional auxiliary coupling circuitry to provide for soft switching from one phase to the next.
  • this circuitry includes coupling capacitors.
  • this circuitr '- includes inductively coupled windings on an isolation transformer.
  • this circuitry is connected as a daisy chain from one receiver to the next. When a particular balancer is not switching, it may remove itself or be removed from the daisy chain by the use of semiconductor or mechanical switches, such as relays or ganged, motor-actuated switches,
  • the timing of switching or power transfer between receivers is carefully coordinated. In some embodiments, this coordination is performed via one or more handshaking signals.
  • the balancer master coordinates the switch sequence timing. In some embodiments this timing is coordinated in part by the balancer slave circuits.
  • some timing handshaking or clocks is implemented as a bus. In some embodiments some timing handshaking is implemented as a daisy chain.
  • timing handshaking signals may be bypassed by a balancer slave or balancer master. In some cases this bypassing is performed using a semiconductor switch or logic gate. In some other embodiments this bypassing is performed using a meehanical switch, relay, or motor-actuated switch.
  • the switch may comprise several throws that include all circuitry needed to soft, switch to distribute power from one balancer slave circuit to another.
  • the source, destination and magnitude of balance current depends on the time sequencing of the switches. By judicious time sequencing, switching stresses and losses can be reduced. These losses may be further reduced by the use of pa ssive soft-switching and active soft-switching techniques, for example quasi -resonant and resonant switchers.
  • the circuits 200, 240, 260, and 270 are located in a physically compact space that may serve to achieve one or more of the following results: reduce EMI/RFI; facilitate careful time- sequencing; maximize the use of shared components (such as precision clocks, power supplies, communication buses, etc.); and/or maximize the inductance 208, which supplements that of 210.
  • a single, relatively powerful processor may perform all switching timing calculations and control. In other embodiments, several less powerful processors may perform switching calculations and control for individual receivers, coordinating via communications, and handshaking.
  • Certain embodiments may employ OCC or mOCC in order to perform switching control.
  • OCC optical coherence control
  • One objective in the design of power circuitry is the need to operate with reasonable efficiency at relatively low currents, while retaining relatively high current capacity.
  • the maximum- efficiency point should be biased below the maximum permissible power setting, and the roll off in efficiency should be optimized, for example by the use of variable switching frequencies, pulse-skipping, soft-switching, and/or other techniques.
  • a cluster comprises 0(8) receivers in proximity with an enclosure within about 8- 10 m of wire of all receivers, ⁇ Receivers are electrically connected in series to achieve the maximum voltage for the number of die connections.
  • balance circuits Isolated switching circuits, called “balance circuits” (ideally) draw imbalance current, supplement imbalance current or draw and supplement (bi-directional) imbalance current. • The power drawn or injected by balance circuits is consumed or produced locally. That is, power balancing is self-contained, requiring no extra long runs of high- power-bearing cables to a remote location to support power maximization.
  • Balance circuits are able to efficiently bypass receivers that underperform by an excessive amount. This can be accomplished passively by the use of a bypass diode or with a switch, and in some cases a switch that is already used otherwise in the normal operation of the balance circuit if series resistance of the circuit is sufficiently low.
  • ail balance circuits are contained in one enclosure that is mounted for convenient servicing. Co-location also provides for fast communications and shared elements, e.g., clocks. Some elements of balance circuits must be electrically isolated from each other.
  • the enclosure can also house the inflation and tracking control! er(s), which optimize the power distribution on the receiver.
  • This controller(s) can also perform role of "master controller.”
  • Consumable components e.g., capacitors, IGBTs or MOSFETS and their drivers are modular for easy and safe field replacement. The cost of consumables and their replacement is minimized. Consumables are enclosed to prevent secondary damage on failure.
  • high DC voltages may require increased dielectric thickness in the high-heat flux water-cooled primary heat exchanger. This enhanced thickness in turn increases the temperature drop in the dielectric.
  • dielectric thicknesses large enough to stand off many kilovolts without excessive thermal resistance it is practical to use dielectric thicknesses large enough to stand off many kilovolts without excessive thermal resistance
  • FIG. 9 A shows a schematic diagram of an interleaved inverter system 900 according to an embodiment of the present invention.
  • This system comprises an inverter master 902 and a plurality of inverter slaves 904, This system may further provide an uninterruptible power supply system (UPS) 906.
  • UPS uninterruptible power supply system
  • the inverter master may digitally communicate at a high level in the plant network hierarchy via signals 908. In turn it may digitally communicate with its slaves via signals 910.
  • the communication is shown as bussed and differential-signaling-based, such as RS485.
  • embodiments of the present invention are not limited to this form of communication, and as described earlier alternate communications schemes are possible,
  • the blocks share a common "ground" voltage 912. which is distinct from earth ground 914.
  • the rectangle around the inverter 916 depicts the chassis, housing, and metal objects with which an operator may contact. This is connected to earth ground via techniques established by the power industry, for example by conductors driven into the earth. Other features of the inverter system that may be earth grounded include the cooling system, coolant, and other elements.
  • the sole physical earth ground connection referenced by the circuitry occurs at the UPS 906. This earthing arrangement may avoid issues associated with earth ground currents.
  • the central inverter establishes the cluster bus voltage reference. In the embodiment sho wn, the negative voltage of each cluster is tied (e.g. 918) to a common voltage at the inverter. This common voltage is "ground", but not necessarily "earth ground.” The clusters may separately earth ground their chassis, support structure, and cooling system, etc., but may not otherwise tie a voltage in their cluster to "earth ground.”
  • the positive voltage of clusters are connected into a common positive voltage. In some alternative embodiments, one voltage from a plurality of clusters is connected. In some alternative embodiments, one voltage from a plurality of clusters is connected and the other voltage from a different plurality of clusters is connected in common.
  • the voltages of at least one cluster is not connected with any other cluster, e.g., all clusters outputs are maintained separate.
  • the inverter slaves share a negative or positive common voltage that is substantially isolated from the cluster voltage. In some embodiments, this common voltage is constrained to fall within a range relative to one or both of the cluster voltages, for example, to ensure that circuitry is properly biased.
  • One reason for isolating a cluster voltage from another is to allow the inverter slave to switch using a more symmetrical high-side and low-side profile than may be possible if a number of clusiers having different cluster voltages have one voltage in common. For example, if one cluster is producing at one voltage, another cluster is producing at a different voltage, a terminal of the clusters is connected together, and the circuits are switching into the same voltage, the switch timing on the high-side and low- side of the two clusters may be unsymmetrieai. Such a lack of symmetry may increase switching, conduction, and / or core losses over those of a symmetrical profile.
  • a slave inverter operating on an isolated cluster voltage may aitain a more symmetrical switching profile and may achieve a higher inversion efficiency.
  • This possible increase in efficiency may come at the cost of isolated switches and additional isolated power supplies.
  • the extra cost and power required for these isolated elements is justified by efficiency gains. In other embodiments, e.g., in the embodiment shown it is not.
  • some of the inverter-slave circuitry may share a common voltage to provide for simpler interfacing, e.g., of
  • the arrangement of establishing a common voltage reference for each cluster physically proximate to (or within) the inverter may offer a benefit in thai each inverter slave can share a ground with each other and with respect to the master. This potentially obviates the need for a large number of isolated power supplies, isolated communications, etc.
  • grounding scheme may depend upon supplying a sufficiently low impedance and inductance ground plane, such that ground bounce and voltage offsets produced by ground currents do not disrupt communications and other circuit functions.
  • a physically compact inverter, good circuit layout, and thick ground planes/traces may allow mdividual mverter circuitry to operate without isolation.
  • the master inverter contains filter capacitors 920.
  • the mverter slaves in this embodiment each function substantially as current sources, and so may share a common capacitor.
  • the individual filter inductors are contained in the inverter slave blocks 904. By interleaving the switching times of each inverter slave, the necessary size of this filter capacitor may be reduced by a large factor.
  • the inverter slaves ma function substantially as voltage sources and share a series filter inductor whose inductance may be similarly reduced.
  • the master may supply a clock signal 922 to mverter slaves.
  • this clock signal may be from a microcontroller.
  • the master may produce, listen, and/or contribute to a handshaking bus of digital timing signals (924) utilized by the inverter slaves in part for establishing switch timing and synchronization,
  • the logical voltage 926 and gate/analog voltages 928 may be supplied by the uninterruptible power supply 906 and are shared for inverter slaves. To avoid unwanted power-supply inductance, these power supplies, while fed by the UPS may be placed proximate to or within the inverter.
  • the UPS provides an intermediate voltage, and each inverter slave individually produces its operating voltages from this source. Such an arrangement may be fa vorable if the power-supply inductance is large, or extra voltage isolation is desired between inverter phases.
  • each inverter slave may have a simple snubber and capacitor to eliminate power supply voltage excursions without resorting to separate supplies.
  • Each inverter phase may also contain a "test port" containing signals and connections that are normally open in operation, but that support automated testing and troubleshooting when an inverter experiences a fault.
  • Figure 9B shows an embodiment of an inverter system 950 that provides for switch synchronization daisy-chaining via circuitry 952. Soft- switching and high- precision switch interleaving between separate inverter slaves may utilize high- precision daisy-chain handshaking.
  • a slave may await a signal from another slave (e.g. 956) previous in the timing chain on one handshaking line 958, before initiating a switch sequence. At some point in this switch sequence, it may assert a signal on a handshaking line 960 to the next slave in the chain, so that the next inverter's switching achieves a soft-switched, low-stress, or low-noise condition.
  • Maintaining a complete daisy chain may present a challenge when an individual inverter slave or its associated cluster, may be inoperative. Because softswitching may be desirable, but is not necessary for operation, inverter slaves may be coded and designed to operate hard switched or with reduced interleaving performance if the daisy chain is broken.
  • Certain embodiments may bypass one or more inverter slave timing signals in a daisy chain, by the use of a switch 962.
  • a switch 962 may be electronic, mechanical, etc.
  • the signaling electronics are low voltage and share a common ground reference it may be favorable to perform this switching via logic devices or analog switches. Potentially desirable characteristics of such switches include low cost, low power requirements, and low transit-time delay. Such a switch may be thrown mechanically or programmarically when an inverter slave is removed from service. [8299] Removing an inverter slave may involve physically removing the device. Thus, this function may be best handled by the inverter master or on a motherboard that remains in service when inverter slaves are removed.
  • FIG. 10A shows a schematic diagram of an embodiment of an inverter slave ( 1000) according to the present invention.
  • This inverter slave comprises a controller 1002. that may perform one or more of the following functions:
  • the controller may control switches in a one, two, three, or more phase inverter.
  • the particular embodiment shown includes a simplified schematic diagram of a three-phase buck inverter, 1016.
  • an inverter slave may comprise a boost inverter.
  • the particular embodiment shown comprises a boost DC-DC converter.
  • the buck inverter utilizes series inductors 102.4, sharing a common filter capacitor between slaves off out of the unit.
  • a boost inverter may comprise an individual shunt filter capacitor and shared series inductor.
  • One design approach ensures that the cluster bus voltage is normally in excess of the necessary voltage for buck inversion. This approach may employ over specification of switch voltages. This approach may affect average efficiency, since the buck inverter may operate less efficiently with a substantial voltage buck.
  • Adding a boost stage 1018 may provide the ability for an inverter to boost its voltage to a minimum value needed for inversion, allowing the use of a lower peak- production cluster voltage.
  • the boost phase may use an extra switch 1026, diode or synchronous rectifier 1028, and inductor 1030 (in series with the interconnect inductance).
  • the inductor resistance and diode's forward voltage drop and resistance may reduce the inverter efficiency when the boost is not needed. Under such circumstances it may be desirable to close a bypass switch 1032.
  • This bypass switch may be electronically controlled via 1034.
  • This bypass switch may be mechanical switch, relay, latching relay, and the like.
  • this house-keeping power may be supplied through the switches 1020 if the diode 1028 is shunted, for example via switch 1032.
  • this condition could be problematic if the cluster is not producing because it is mis-pointed during the day, leaving the cooling system and tracking system inoperative.
  • a UPS such as 906 may be used to supply power 1036 via diode 1038.
  • This circuit sets the minimum cluster bus differential voltage.
  • this supply could be applied via a switch.
  • diode 1038 resides on circuitry that is not removed when servicing an inverter slave (for example on a mother board that inverter slaves plug to).
  • Switch 1040 may provide for an array to provide power to the UPS. This power could be used by other clusters, and/or could be used to charge a battery. If present, such a switch may be manual or motor actuated as described earlier.
  • the umnterruptible power is diode 1038 connected, it resides on the cluster side of mductor 1030 or the diode 1038 will be forward biased when the boost switch 1026 activates. Because the remote conduction line inductance in series with 1030 may be substantial, the uninterruptible voltage may be sufficiently low compared to normal operating bus voltages, such that the diode does not become forward biased in normal operation. Alternatively, ihe diode could be switched open when the boost circuit operates.
  • a potential advantage of the common ground voltage of the cluster and controller 1014 is that current sensing 1042, bus-voltage sensing 1044, and phase voltage sensing 1046 may be performed accurately and inexpensively. Good attention to analog grounding 1048 should be followed.
  • a test connector 1050 may facilitate automated testing and trouble shooting.
  • the inverter may accurately track the maximum power point by having a signal or calculated value that is monotonia in output power. Nevertheless, it may be desirable for an inverter to be able to report its production power accurately.
  • the current and voltage sensing of the inverter may require calibration.
  • a slave will compare its measurements to precision measurements reported from its master to update its calibration, in turn, the slave may provide similar calibration services to balancer circuitry on the slave's cluster.
  • switch timing is set using one-cycle control, analog feedback.
  • maximum power tracking is performed using one-cycle control, analog feedback.
  • the performance of the one-cycle control may be trimmed and optimized by a microcontroller.
  • the switch timing may be calculated using one or a plurality of digital signal processors or suitably fast digital controllers.
  • Figure 10B shows a diagram of an embodiment of an inverter slave 1080 that uses a daisy chain of handshake signals 1082 and 1084 to perform soft switching, reduced-stress switching, low-noise, switching, or other switching enhancements. This is done via switch timing circuitry, and in some embodiments by auxiliary switching circuitry 1086.
  • FIG. 1A shows an embodiment of a UPS 1100 associated with inverters according to the present invention
  • a UPS controller 1 102 digitally communicates with the plant via connections 1 104.
  • the communication is shared with the inverter slaves.
  • the UPS may communicate at a different level in the plant network hierarchy.
  • This controller performs power management from the grid 1 106. In some embodiments the controller performs power management from a generator 1 108 such as a diesel generator. [8326] In this embodiment, the controller maintains a battery 1 110 at a good state of charge, and supplies an uninterruptible bus voltage at the battery voltage. This embodiment utilizes the battery to provide a low-impedance voltage reference with respect to earth ground 1 112.
  • earth ground is referenced on the low- voltage side of the step-up three-phase transformer.
  • the connection between earth ground and the common, negative-most voltage reference in the plant is made at some position in the battery stack (e.g., 1 1 14, 1 116, or 1 1 18) depending on what negative voltage offset is desired in the common cluster voltage.
  • the controller may start generator 108 to prevent batteries 1 1 10 from depleting their charge.
  • the size of batteries 1 1 10 may be small enough to provide a brief period to start up the generator or to facilitate an orderly safe plant shut down.
  • the UPS controller also produces logic 1120 and gate/analog 1 122 voltages.
  • the UPS system may be physically separate.
  • a generator 1 108 may need to be mounted externally.
  • Batteries 11 10 may be housed where corrosive and explosive gases cannot cause problems.
  • the supplies for 1 20 and 1 122. may be proximate to the inverter slaves to minimize inductive spikes on the voltage supply,
  • Figure 1 IB shows a schematic diagram of an electrical circuit 1 150 to the step up transformers 1 152 that transform plant voltages 1 154 to grid voltages 1 156,
  • transformers 1 152 are connected "Wye" to "Wye.” It may be desirable to connect the plant side of the step up transform in a "Wye" configuration as shown in Fig. 1 IB to limit the secondary damage that can be caused by the failure of a power switch.
  • the circuit inside 1 158 depicts a failed, fused (1 160) power switch 1 162. on the low-side of a buck inverter phase. Some switch failures result in the switch having a low-resistance, presenting a short-circuit state.
  • the resulting high fault, current 1 164 flowing through the failed circuit may be prevented from substantially affecting the common negative voltage (1 166) by conducting a current 1 168 through the plant battery 1 110.
  • Figure 1 1 C shows an alternative circuit 1 180 for ensuring that the negative common voltage 1 182 never rises substantially above the three-phase plant voltages 1184 by the use of diodes 1 186. These diodes must be able to survive very large surge currents. Because 1 182 and 1 184 are common among all inverter slaves, this protection circuit may appear once in an inverter rather than separately for each inverter slave, e.g., in the UPS module or inverter master.
  • such as circuit may establish a common negative voltage without a battery or independently from a battery.
  • uch a circuit may establish a common positive voltage without a battery or independently from a battery ,
  • Protection circuitry such as 1 180 may be applied individually per inverter slave to the non-commoned cluster voltage, that is, the positive cluster voltage if the negative cluster voltage is commoned and vice versa. Because of the need for the protection diodes to survive large fault currents such diodes may be relatively expensive. In some embodiments, this individual protection may not be cost justified and the designer may choose to allow two or three same-side switches to fail in tandem rather than to pay the expense of the individual protection diodes.
  • the switch modules shown in Figs. 10A and 10B may be engineered to be easily replaceable and to minimize secondary damage caused by a switch failure.
  • Figure 12A shows a schematic diagram of such a low -side switch module 1200 comprising a low side driver module 1202 and a. switch module 1204.
  • the switch module depicts an IGBT and tree-wheeling diode, but this is not required by the present invention.
  • a switch module could comprise other elements such as a power MOSFET, solid-state relay, and/or other switches.
  • Power switch failure may result in a short circuit across the gate. Such a short circuit can expose the driver to excessive voltage and current, and result in destruction of the driver circuit 1208.
  • Embodiments of a switch module may prevent or reduce this damage by the use of a o ver- voltage suppressor 1210, Such a suppressor may comprise a zener diode and a gate resistor 1212 and in some embodiments a fuse 1214.
  • the gate resistor may be sized to burn out in an over current situation and provide the fusing function. Such a resistor may also be favorable for avoiding latch up in some IGBTs.
  • the circuit protection element 1210 may be sized to survive without damage long enough for the gate fuse or resistor to open its circuit or reach a sufficiently high impedance that the protection element can withstand the gate current.
  • a gate dri v er module 1202 may still be susceptible to damage and may therefore be packaged as an easily replaced, cost optimized consumable,
  • the power module is fused.
  • the fuse is between the switch and the terminal 1218. This fuse may comprise a conventional fuse, a feature on a PCB trace that breaks or becomes high impedance, a thin or thick film device, a wire, or other forms of fuses that are known.
  • Figure 12.B shows an embodiment of a high-side switch module 1250.
  • This module is similar to that in Figure 12 A, but contains a high-side switch module 1252 that provides boot-strapping capability via elements 1254 and a digital isolator 1256.
  • a high-side driver module may alternatively contain an isolated gate drive power supply.
  • the high-side driver module and switch module may be designed such that failure of the switch does not normally produce a driver failure, but that the driver module is a cost-optimized, easily-replaced consumable.
  • switch modules may be packaged as a cost-optimized and easily-replaced consumable or reparable module that nevertheless possess exceptionally good heat transfer characteristics.
  • Figure 13A shows such a switch module 1300.
  • Element 1302. is a high-thermal conductivity base plate. In some embodiments this plate is constructed from aluminum or copper. In other embodiments this plate may be another metal or a ceramic material.
  • Element 1304 is a. module cover.
  • this module cover is molded or cast from a higb-temperature-tolerant material, for example a thermoset resin such as epoxy or phenolic, or a suitably high-temperature thermoplastic such as polyester or polyamide, with or without fibers or particulate filling. Desirable properties for this material include high-temperature stability, flame resisiance, impact resistance, strength, and insulation.
  • a higb-temperature-tolerant material for example a thermoset resin such as epoxy or phenolic, or a suitably high-temperature thermoplastic such as polyester or polyamide, with or without fibers or particulate filling.
  • a higb-temperature-tolerant material for example a thermoset resin such as epoxy or phenolic, or a suitably high-temperature thermoplastic such as polyester or polyamide, with or without fibers or particulate filling.
  • Desirable properties for this material include high-temperature stability, flame resisiance, impact resistance, strength, and insulation.
  • This module cover ma be relied upon to resist forces from a catastrophic failure of the switch and fuses contained within, which may be accompanied by an over pressure and spray of hot metal and momentary arcing.
  • the cover contains physical effects of such failures, avoiding damage to equipment outside the cover.
  • Elements 1306, 1308, and 1310 are ports of the switch (e.g., the gate, collector, and emitter, respectively).
  • FIG. 13B shows the interior 1320 of the switch module 1300.1n this embodiment, heat transfer plate 1302 is electrically insulated from a heat spreader 1322 by a thin insulator material 1324.
  • This material may be any suitable, high- temperature, high-thermal-conductivity electrical insulator, such as mica and synthetic mica plates, alumina ceramics, polyester, polyamide, or polyimide film, etc.
  • a mechanical preload e.g., via screws 1326.
  • thermal contact resistance may be reduced by the use of heat transfer greases, adhesives, or other known techniques.
  • the heat spreader may be constructed by a high- thermal- conductivity material such as aluminum or copper or alternatively another metal or alloy. This element may be designed to reduce the eat flux needed to pass through the electrical insulator by a fac tor of 2 to 10 to reduce the effective thermal resis tance of the electrical insulator. [8357] This reduction may be accomplished by making the heat spreader thick. For example the heat spreader may be on the order of the size of the die or thicker and correspondingly wide at the base, such that the angle from the edge of the die to the comer of the base of the spreader is a minimum of approximately 45 degrees, as shown. [8358] In certain embodiments, the side walls of the heat spreader may not display such a taper. The base size could have approximately the same cross-sectional area and relative relation to the die as shown.
  • element 1328 is a fast-recovery Schottky "freewheeling" diode die.
  • elements 1330 are paralleled IGBT die. These die are attached to the heat spreader via a conductor using techniques and bonding materials known in the art, such as solder, silver- filled epoxy, and the like,
  • Elements 1332 are wire bonds. Examples of wire-bond materials include but are not limited to aluminum and copper. Other wire materials may include gold.
  • element 1336 is a gate resistor (such as a thin-film 0805, 0604, 0402 or other resistor) designed to fail open or as a high resistance during a sustained high- current pulse.
  • this resister may be a thick film, a printed resistor or alternate resistor. If a resistor does not have adequate fusing properties, it may be series connected with a fuse.
  • Element 1338 is a circuit trace designed to fuse when an excessive emitter current is encountered. This trace is designed not to produce excessive resistive losses in normal operation, but to fail quickly when a switch operates far above its rated current, indicating a fault.
  • Elements 1340 are mechanical supports for the printed circuit board, in some embodiments, these supports are rivets pressed into the heat spreader 1322 that conduct current from the back metallization of the die tlirough the heai spreader to the printed circuit board and then out of the module via a connector (e.g., 1308).
  • Figure 13C shows a view of the base (1350) side of the switch module cover 1304, showing a feature of the cover designed to mitigate external damage in the event of a failure.
  • hot metal particulates, and arcs can spray inside the module cover. These can lead to a dangerous over pressure.
  • vents and/or filters can be used. These vents and/or filters can be combined with the structure of the housing.
  • element 1352 is notch cast or molded into the cover base
  • vent 1364 The gas, now cooled by passage and stripped of most of its particles and all of the liquid metal particles escapes through external vent 1364.
  • a duplicate vent 1366 may provide for reduced back pressure.
  • the necessary area and number of the of vents depends on the expected amount of energy release during a failure and air volume trapped within the cover.
  • the ports for terminals 1368 may be designed to resist venting, since in some embodiments, venting through those ports may put particles in sensitive areas.
  • venting and filtering may employ mechanical filters instead of cyclonic or inertial filter.
  • the cover may he designed with multiple walls to contain particles or with a compressible element to contain expanding gasses without leaking.
  • Figure 14A shows a simplified mechanical drawing of the assembly 1400 of switch modules 1402, low-side modules 1404, and high-side driver modules 1406 into an inverter slave housing 1401.
  • the low-side and high-side driver modules contain a feature 1408 that indicates insertion direction and facilitates module removal.
  • the recesses 14.10 and 1412 in the surface of 1401 establishes the module insertion orientation.
  • the physical design of the module makes it impossible to insert in the incorrect orientation or slot, e.g., the shape of modules 1404 and 1406 are designed not to fit into each other's slots.
  • Switch modules 1402 may be similarly keyed to avoid incorrect orientation and to avoid plugging an incorrect module, e.g., wrong voltage or current rating, switch type, etc. into a module recess, e.g., 1414.
  • the ledge 1416 presses against the module cover. This provides mechanical decoupling of forces normal to the heat transfer plate 1302 and electrical terminals, e.g., 1308. This pressure can also provide an enhanced seal that prevents particles from entering the inverter slave, since gases and particles are vented between the plate 1302 and cover base 1350.
  • Figure 14B shows an arrangement 1440 of low- side 1404 and high-side
  • driver modules and switch modules 1402 inserted into an inverter slave housing 1401 , according to an embodiment.
  • Figure 14C shows a simplified internal assembly 1460 of an embodiment of inverter slave. This figure illustrates one manner, in accordance with one embodiment, of orientation of modules 1402, 1404, and 1406 with respect to the printed circuit board 1462.
  • Elements 1464, 1466, and 1468 are indicators, such as light emitting diodes (LEDs). In some embodiments these indicators provide simple feedback about the state of the inverter. For example, these indicators can indicate:
  • boost circuit activated indicating that it is not safe to close boost-circuit bypass switch (e.g. 1472);
  • red LED it may be undesirable to use a red LED to indicate anything but a fault.
  • flashing LEDs it may be important to use flashing LEDs to indicate faults so that color-blind operators are not at a disadvantage.
  • flashing and red light is used as a fault indication and steady and green light is used as a normal operation indication.
  • Elements 1470, 1472, and 1474 are switches that may be used to optimize inverter efficiency, such as bypass the boost circuitry when it is not needed. In some embodiments there may be no switches, one switch, two switches, three switches or more according, to how many optimizations or operating modes are available. These switches can be actuated manually or via a robotic traverse, and can provide a clear visible indication of switch state.
  • Elements 1476 and 1478 are power inductors.
  • element 1476 may be the inductor for a boost circuit and 1478 may be an inductor in a buck inverter phase. These inductors may generate significant heat and are mounted in good thermal communication with the top of the slave inverter housing 1401, where active cooling may be applied.
  • Figure 15A shows a top view of an inverter slave 1500
  • Figure 15B shows a back side view of an inverter slave 1500, in accordance with an embodiment of the present invention.
  • Elements 1502 are rack slides which may be used to guide the inverter into place in a rack, and to transfer compressive preloads on heat transfer elements to inverter structure.
  • Element 1504 is a raised section of the inverter housing. Element 1504 may provide good thermal contact with an active cooling plate to transfer heat from a power inductor.
  • Element 1506 is an element of the inverter that makes early contact with the mother board.
  • Element 1508 are the high-voltage power connectors.
  • Element 1510 is a lever used to engage and disengage the inverter slave.
  • Element 1510 may alternatively be another physical mechanism that provides mechanical advantage, such as one or a plurality of fevers having different characteristics or orientation from that in 1510, one or a plurality of screws, or a combination of different mechanisms that achieve substantially the same function as element 1510.
  • the invert connectors and electronics may be engineered so that the inverters can be "hot plugged,” in some embodiments via one or more of the following operations.
  • the order of circuit contacting may be: inverter slave ground ( 014), then logic pow r er (1012), then gate power (1010), then processor clock ( 1008), then
  • the clock signal may be applied before the gate power circuit.
  • the unit undergoes a boot up self check and communicates with the master inverter. If the unit checks out, it turns on a green light, such a s a green, slowly flashing light, to indicate to the operator that it is ready to be engaged with high-voltage pow r er. If not, the unit turns on a fast flashing red fight to indicate that the inverter is not ready to be engaged.
  • a green light such as a s a green, slowly flashing light
  • the unit If the unit indicates a fault, the unit is removed and taken to a test fixture for automated diagnosis and troubleshooting. When the unit is repaired, the fixture may set a flag indicating a clear state of health. In general, a fixture may set a usage timer that may expire periodically to prompt an inverter for return to the test fixture for preventive maintenance, diagnostics, and recall bration. 7) If the unit does not indicate a fault, the user then engages the high-voltage power electronics by pulling up on lever. This lever contains a cam which forces the inverter backward with mechanical advantage.
  • an inverter will be housed with a supply of spare consumables, a test fixture, and/or a number of operable spare inverter slaves, so that down, time for an inverter phase is limited to the time required to swap out inverter slaves.
  • a maintenance worker can replace consumables and use the test fixture to re-commission inverter phases offline.
  • FIGS 16A and 16B respectively show isometric top front and back views 1600 of an embodiment of an inverter slave engaged with its active cooling module 1602.
  • the inverter housing top surface has an wedge angle 1601 such that as it slides toward the back of its travel it engages with the bottom surface or cooling plate 1603 of the cooling unit 1602.
  • Element 604 is a coolant inlet port
  • element 1606 is a coolant exit port.
  • Elements 1605 and 1607 are coolant bypass ports, allowing these cooling heads to be arrayed in parallel.
  • Elements 1608 are reinforced rack rails (reinforcements not shown) that maintain a large mechanical preload between the elements 1504 and 1402 and the cooling module bottom surface or cooling plate 1603. Other reinforcements between the cooling module and rack, which do not move with respect to each other, are also not shown for clarity.
  • Raising the fever 1510 causes a cam to bear on rack-mounted pin 1610 with mechanical advantage that slides the inverter slave toward the back.
  • Working with the wedge angle of the inverter top in this manner produces a significant mechanical preload to reduce thermal contact resistance to cooling module.
  • Figures 17A-17D show components of the coolant module embodiment 1700.
  • element 1702 is the coolant module housing which provides a reinforced back wall of the coolant flow conduit and provides for fluid entry and exit through engineered, leak proof connectors employing redundant o-ring seals in a male connector 1704, which mates with an engineered female connector 1706 of another coolant module 1700.
  • a spring clip 1708 holds the mated connector securely.
  • the coolant module housing seals to the cooling plate via an o-ring that is maintained under compression by near continuous spring clips.
  • Figure 17B shows the coolant module with the module housing removed, revealing the flow splitter plate 1710.
  • the flow splitter plate contains arrays of nozzle orifices that direct coolant from the cool side (shown) to the hot side (obscured) by the splitter plate. By inertialiy transporting cool coolant to the coolant plate, these jets efficiently cool against high heat flux with low flow pressure drop.
  • This splitter plate contains features (such as 1712 and 1714) to make a substantially leak- free seal from one side of the splitter plate to the other via the coolant module housing and other featui'es 1716. This makes a substantially leak- free sea l from one side of the plat e to the other via the cooling plate. Leaks from one side to the other of the splitter plate do not result in external coolant leaks.
  • Figure 17C shows the cooling module 1700 with the housing and splitter plate and o-rings removed, leaving the cooling plate 1603 and end clips 1720 remaining.
  • the cooling plate contains clip features 1722 to retain the housing against the internal pressure.
  • the end clips provide this retaining feature (1724) over the region that the cooling plate does not have this feature.
  • Figure 17D shows the full coolmg module 1700 with the location of the cooled components, 1300, 1478, 1476, etc. relative to the cooling plate revealed. Heat from a switch flows from die 1330 through spreader 132.2 through electrical insulator 1324, through plate 1302 through cooling plate 1603 and into the coolant.
  • Figure ⁇ 7 ⁇ shows an alternate embodiment of the interface 1780 between the cooling plate 1782 and a cooled component, e.g., a switch module having cooled plate 1784.
  • Nesting, and in some embodiments intentionally interfering and binding features 1785 and 1786 reduce contact resistance by increasing the total mechanical preload forces between the surfaces for a given normal force applied between the elements 1788. This reduced force may reduce the mechanical reinforcement required by the frame and the loads transferred through the cooling system plate to the cooling system housing for a given thermal resistance.
  • the inclined force 1789 applied, e.g., by a front-panel lever, may further reduce the mechanical effort required of an operator to obtain a high-conductivity thermal interface.
  • Figure 17F shows an expanded edge view 1790 of the coolmg plate 1782. and cooled plate 1784 interface. Because of the wedge geometry a normal preload force 1791 produces much larger opposing preload forces 1792 that are largely borne by stresses internal to the plates, e.g., at 1793. This technique is mechanically efficient because it creates and resolves the large forces locally, using internal stresses rather than requiring physically large and remote structural elements to bear high loads. This arrangement may further minimize detrimental thermal expansion effects on the mechanical preload 1793. in some embodiments this interface is designed to increase the mechanical preload under conditions of relatively high cooled-plate temperatures so that thermal expansion provides a beneficial effect.
  • Figure 17G shows and alternative embodiment of a cooling plate design 1765 that may fitrther reduce the loads and sensitivities to compliance between the cooling system and support rack and inverter slave housing and support rack.
  • one or a plurality of features, e.g., 1796 may mechanically interlock with mating features on a cooled plate such that the interlocking features bear a substantial portion of the normal force between the cooled and cooling plate.
  • These features may be designed to allow multiple cooled plates to be interlocked by staggering the heights between successive patterns as indicated by 1797.
  • Figure 18A illustrates the cold side of the splitter plate 1710.
  • Figure 18B is an enlarged view of the cold side of the splitter plate 1710 illustrated in Figure 18 A.
  • the active splitter elements include nozzles (e.g. 1806) and support posts (e.g. 1808).
  • the support posts transfer preload forces to maintain low thermal contact resistance.
  • Figures 18C illustrates the same patterns 1802 and 1804 on the hot side of the splitter plate.
  • Figure 18D is an enlarged view of the hot side of the splitter plate illustrated in Figure 18C .
  • the rear surfaces of the nozzle (e.g. 1810) and spacer (e.g., 1812) are indicated.
  • the spacers protrude further than the nozzles and establish a nozzle stand-off distance for maximum jet-cooling efficiency
  • ridges and valleys or other features on the cooling plate may alternatively set the nozzle stand-off distance.
  • structure of the nozzle wall may bear on features on the cooling plate, performing a combined function of establishing the jet and the spacing of the jet on the surface.
  • the surface of the cooling plate opposite the jets contains features that mesh and bind with features on the surface of cooled items, such as 1302.
  • the nozzles are designed to direct coolant toward areas were the binding force or normal force between the cooling plate and the cooled items is high.
  • Figure 18E is an illustration showing how the cooled components are arranged physically with respect to the patterns of jets in the splitter plate.
  • Figure 19 shows a ten-by-ten array of coolant modules 1700 assembled into an inverier heat exchanger 1900, The rows of coolant modules are terminated in the right back at a cool-coolant manifold 1902, through which cool coolant enters at the port 1904. Manifold 1902 may be located at the bottom of the array to facilitate the purging of bubbles and establishment of uniform flo throughout the array, [8405] The rows of coolant modifies are terminated in the left front at a hot-coolant manifold 1906 having an exit port 1908 that may be located at the top of the array to facilitate the purging of bubbles. This opposing arrangement of inlet and outlet port helps to establish a substantially uniform flow through the array by creating similar pressure drops in the fluid path.
  • nozzle orifices and piping that is sized so that the nozzles produce the most pressure drop may further assist with maintaining cooling uniformity.
  • the cooling ability of the exchanger may not be substantially affected by how much liquid is contained in the coolant modules, but rather by the coolant fluxes through the orifices.
  • the volume of coolant in the exchanger may define how long an operator has to repair the pump or turn off the inverter. This is because the exchanger could switch to a boiling mode.
  • Figures 20A-20D illustrate an embodiment of an assembly 2000 of inverter slaves 1500, cooling system 1900, motherboard 2002, and back panel 2004, arranged and fitting together.
  • Figures 20A, 20B, 20C, and 20D are illustrations of a front isometric view, a left side view, a right side view, and a top view of assembly 2000, respectively.
  • Elements 2006 are connection points for connections with individual clusters.
  • Element 2008 is a three-phase AC connection to go to step-up transformers.
  • Element 2010 is a connection to the uninterruptible power supply output.
  • Figure 21 shows a mechanical drawing of a housing structure 2100 according to an embodiment of the present invention, that contains the assembly 2000.
  • This structure comprises a sheet-metal rack enclosure 2.102 having vents 2104 located substantially at the base of the structure, and standoffs or legs 2106 that are sufficient to work in concert with the vents to provide for relatively unimpeded air How 2108 to assist with cooling elements of the inverter that are not actively cooled.
  • the natural convection in such an embodiment may be augmented by the use of a top-mounted vent pipe 21 10 having a significant height to produce an updraft via the siack effect.
  • a top-mounted vent pipe 21 10 having a significant height to produce an updraft via the siack effect.
  • Such a pipe may have the additional benefit of venting the smell (which may be poisonous) of out-gassing electronics or failed modules, outside of a secondary inverter enclosure such as a shipping container.
  • natural convection may be augmented by the use of an exhaust fan.
  • Figure 22 shows assembly 2000 placed in housing 2100 with no front panel attached.
  • the significant open space on the right side may be used to house a control computer, batteries for the UPS, UPS control circuitry, coolant pumps, or other elements.
  • one or more of these elements may be designed to reside in a separate container for safety, corrosion, leakage, safety concerns.
  • Figure 22 shows and embodiment where the housing 2100 is larger than the assembly 200 in the lateral direction.
  • Other embodiments can include a housing 2100 that is larger than the assembly in the vertical direction or a housing that is substantially the same size as the assembly. If the housing and the assembly are substantially the same size then elements such as the control computer, batteries for the UPS, UPS control circuitry, and coolant pumps would be disposed outside of the housing 2100.
  • Figures 23A-23E respectively show a top-front isometric view, a front, back isometric view, a back view, and a side view of the inverter assembly 2300 with front- panel attached.
  • the pipe 2302 is the hot-coolant exhaust port.
  • This pipe should lead to a liquid-air heat exchanger, preferably a radiator having at least the option for forced convection.
  • the radiator may reside at the base of a chimney and derive its cooling in part or entirety from the stack effect.
  • a coolant pipe ma rise to a height and terminate in a free-surface reservoir to maintain a limited pressure head in case of boiling.
  • the pipe 2304 is the cool-coolant return line.
  • Element 2306 is a digital communications connector, e.g., an Ethernet connector.
  • Figure 24 shows an embodiment of the interleaved inverter containing a motorized traverse to programmatically operate array s of mechanical switches.
  • the traverse may also actuate the lever 1501 to disengage inverters.
  • the traverse can be moved across (2402) and up and down (2.404) the inverter front control panel.
  • Element 2406 is a traverse stage that may contain a feature or plurality of features to allow it to actuate switches and linear levers. Tn some embodiments it may be able to actuate rotary switches or screws.
  • the traverse may be able to produce motion in the direction normal to the front panel.
  • an alternative mechanical arrangement of a robot may be employed, e.g., and articulated arm, etc.
  • the inverter change out may be entirely performed by a comparatively unsophisticated robot.
  • human operators may be kept far from high-voltage safety hazards.
  • inverter consumable replacement and repair may be performed robotically.
  • the inverter slave self diagnoses faults.
  • the inverter slave can only crudely identify that a fault has occurred by not achieving an expected voltage or current, or by some parameter such as operating temperature going outside of an expected range.
  • the ability to perform thorough automated trouble shooting may be relegated to test equipment.
  • This test, equipment may plug into the normal inverter connectors and in some cases a special test connector providing access to additional signals and controls that may aid in diagnosis,
  • Some embodiments of inverters according to the present invention contain smoke, heat, or fire detectors. Some embodiments may contain fire -suppression apparatus, such as C02, dry chemicals, halon, foam or other fire-suppression means known in the art. [8422] In some embodiments these fsre suppressors are under manual control. In some embodiments, these fire suppressors are under programmatic control. In some embodiments these fire suppressors are controlled by a smoke, heat, or fire detector.
  • fire -suppression apparatus such as C02, dry chemicals, halon, foam or other fire-suppression means known in the art.
  • these fsre suppressors are under manual control. In some embodiments, these fire suppressors are under programmatic control. In some embodiments these fire suppressors are controlled by a smoke, heat, or fire detector.
  • Some embodiments of the present invention contain leak and water detectors. [8424] Some embodiments of the present invention may contain certain elements such as power filter capacitors within explosion-proof vessels. In some embodiments, capacitors are liquid cooled.
  • the coolant comprises dielectric oil.
  • inverter phases may be immersed in circulating coolant rather than isolated from the coolant.
  • inverter slave assemblies are disposed vertically, with controls and indicators facing substantially upward and the remainder of the inverter immersed in circulating coolant.
  • coolant is circulated using a splitter-plate jet architecture as in 1710, [8426]
  • inductors are cooled via a wrap-around sink in contact with the cooling plate. In other embodiments, inductors are cooled via direct impingement or immersion of a conventional on a conformal insulating surface.
  • inductors are cooled via direct immersion or impingement of an insulating coolant.
  • the support structure, the cooling structure, the inverter housing, and the switch modules may contain springs, such as wavy washers, and the like. These springs function to maintain a preload despite thermal expansion, creep, etc.
  • FIG. 3 shows an illustration according to the present invention, of an embodiment of a power plant layout (300).
  • Clusters (302) are arrayed in rows and columns. While site-specific terrain may require a departure from a standardized plant plan (such as a uniform array), standardization is advantageous because it permits a maximal amount of prefabrication of interconnects.
  • Array rows and columns need not be orthogonal. However, large departure from orthogonality may lengthen interconnect lengths appreciably.
  • Individual lines (304, 306) transmit DC power to a massively interleaved central inverter (308) that may be located near the center of the array to reduce interconnect cost and losses.
  • a potentially favorable interconnect geometry involves running cables toward a central point along a ro or column, and then running in the other direction toward the array center. This arrangement results in interconnect lengths that are somewhat longer than more straight-line connection, but eases prefabrication and speeds installation while mitigating potential shading of clusters by the
  • transformers (310) that step the three-phase inverter output to grid (312.) voltages are located within 30 m and even within 10 m of the inverter.
  • Co-locating all inverters reduces maintenance costs, provides for fewer enclosures and environmental seals, and eases water cooling, amongst other advantages. Moreover, the physical proximity of inverters facilitates inexpensive, high-speed timing coordination between inverters (for example via clock and handshaking lines, high-speed synchronous and asynchronous communication).
  • An example of an architecture for each individual inverter is a boost-type three-phase inverter like that outlined in Y. Chen, K. Smedley, and J. Brouwer (2006) "A Cost-effective Three-phase Grid-connected Inverter with Maximum Power Point Tracking," IEEE 1-4244-0365-0/06 and Y. Chen and K. Smedley (2006) “Three- Phase Boost-Type Grid Connected Inverters,” IEEE 0-7803 ⁇ 9547-6/06, both of which are incorporated by reference in their entireties herein for all purposes.
  • This inverter features a series input inductor, in accordance with our requirement that the inverter benefit from the inductance of the DC interconnects.
  • This inductor sees a relatively low ripple current, reducing the size of the output capacitor needed at the cluster (and/or at receivers).
  • the circuit employs six switches to produce a voltage boosted three-phase output. By carefully time-sequencing the switches, two thirds of the power switches can be soft-switched and the hard-switching is distributed evenly on the switches. It is anticipated that this performance can be further improved by judicious interleaving of many inverters. This inverter was successfully operated using OCC circuitry. A simple maximum power-point tracking scheme was also de veloped. These automatic analog controls contain hooks to allow precision digital fine-tuning and optimization from relatively modest microcontrollers.
  • boost inverter performance degrades gracefully with loss of voltage. Its proper function requires that a maximum voltage is not exceeded, which can be accomplished by design, given a photovoltaic source.
  • An inverter system may have the ability control the power factor of the plant directly, to assist in maximizing the production value of a power plant. Such may be required in order to 1 ) comply with the grid interconnection requirements specified by the local Electric Utility, 2) maintain consistent and stable inverter operations, 3) maximize power production revenues (by normally producing at near unity power factor), and 4) provide the opportunity at the plant level to participate in any available ancillary- services markets provided by Utilities or Independent System Operators, [8442] Power factor control may be achieved at the inverter, as a part of the inverter control, preferably by a mOCC technique.
  • FIG. 3 A shows a simplified vie of a power plant according to an embodiment of the present invention.
  • a power plant (350) according to embodiments of the present invention may comprise an array of clusters (352) comprising a plurality of receivers (354).
  • the power from each receiver may be maximized by the use of a separate balancer circuit (356) for each cluster that works by performing a power conversion only on the deviation of a series- connected receiver from its maximum power point.
  • the substantially D.C. output of each cluster conducts along separate twisted pairs of conductors (358) to an interleaved central inverter (364).
  • the inductance of the twisted pairs may be intentionally enhanced by spacing the conductors, in certain embodiments, the inductance of the connections may be intentionally reduced, for example by breaking the conductors into a plurality of smaller, tightly coupled conductors. In particular embodiments, the conductors may be disposed coaxially.
  • the cable pairs (358) are grouped with other cables (360) that run down pairs of rows of clusters. This depiction may indicate placing the cable pairs in physical proximity, but does not require interconnecting.
  • Avoiding the combination of the power from numbers of clusters may offer certain potential benefits.
  • One such benefit may be an ability to perform maximum power point tracking for each cluster efficiently.
  • a possible benefit may be reduced cluster-cluster coupling, such that problems affecting one cluster may have a lessened impact on the performance or health of other clusters.
  • Still another potential benefit may be that the power and current on each interleaved inverter may be strictly limited, reducing the need for protection circuitry associated with excessive D.C.-side power and current.
  • advantages of the use of interleaving may be takers without excessive concern for "load balancing" of the mterieaved circuits.
  • the diameter of the interconnect wire is chosen individually depending on the length of the cable run.
  • the diameter may be chosen to obtain a substantially constant resistance in each cable run, so as to obtain a target D.C. transmission efficiency at or near the minimum required conductor cost.
  • the balancer circuit acts to establish a cluster voltage to permit interconnection of the cables from a plurality of clusters, without a substantial loss in cluster power-point maximization.
  • a plurality of cluster conductors may be interconnected. Cables from clusters may become strands of a cable as they join such a bussed connection in such a way that the diameter of the cable grows as the current-bearing requirements grow. In certain embodiments, this optimization of interconnect conductor mass is performed otherwise.
  • cables from only a single row of clusters rather than a pair of clusters are grouped, in some embodiments, these grouped power cables from rows are further grouped with grouped cables from other rows (362) to converge on a central inverter (364).
  • this central inverter can be a massively interieaved inverter, with each interieaved inverter circuit fed by one or a subset of cluster cables.
  • the central inverter may not employ an isolation transformer.
  • Grid isolation can be provided by stepping up the three phase AC output of the inverter (366) via step-up transformer (368) either to distribution or transmission voltages on fines (370).
  • an array may be disposed in a rectangular grid having ninety-degree angles between cluster axes.
  • an array may be disposed in a parallelogram grid having an angle between cluster rows and columns other than ninety degrees.
  • this array angle is chosen to reduce the impact of self-shadowing on the plant power output.
  • the calculation of optimal angle may take into consideration one or more factors, including but not limited to the local latitude, the lay of the land, details of the cluster design, local weather patterns, utility power pricing schedules, land costs per acre, parcel boundary, and others, [8454]
  • the East- West spacing of clusters (372) may be different from the North- South spacing of clusters (374), according to an optimization calculation that involves substantially the same parameters as the calculation of an optimal array angle. In some preferred embodiments, this spacing ratio is approximately 2: 1. In other preferred embodiments, this spacing ratio may vary from approximately 1.3: 1 to 3.5: 1.
  • parameters including the row and column spacings and array angle may vary across a plant to accommodate uneven ground or flora.
  • the location of clusters may be intentionally staggered to achie ve a particular appearance, including a desired aesthetic appearance, a pixilated image comprising clusters as pixels, a geometric pattern, a random or quasi-random pattern, or others.
  • the term 'row' is defined as a set of clusters having a given constant index m, i.e. mth row
  • the term 'column' is defined as a set of clusters having a given constant index n, i.e., the nth column.
  • a "central inverter” may be located near the center of an array. If a plant is large, such that the interconnect losses or cost between clusters on the periphery and center of the plant is high), the plant may be subdivided into a plurality of sub-arrays, each having an inverter located substantially centrally to the sub-arrays.
  • array can refer to such a sub-array.
  • power from a cluster may be conducted on a substantially balanced pair of conductors.
  • these conductors may be disposed helically about each other to reduce emissions.
  • power from a cluster may be conducted on an unbalanced, coaxial line.
  • the conductors are spaced to increase the inductance of the interconnects.
  • the conductors are spaced only by a minimal insulator to reduce inductance.
  • inductance is further reduced by dividing the cables into a plurality of parallel lines and interspersing the cables.
  • the positive voltage from a cluster, VC+ (382), can vary according to the power output of the cluster, while the negative voltage from a cluster, VC- (384), remains substantially at a zero-Volt reference (e.g., earth ground).
  • this constant value is established at the central inverter. In some embodiments, this constant value is established at the cluster.
  • Arrangement 390 in Fig. 3AB is the same as arrangement 380 except that VC TM (392) is allowed to vary while VC+ (394) remains substantially at a zero-Volt reference, [8461] Some embodiments comprise a combination of cluster cables according to arrangement 380 and 390.
  • Arrangement 396 in Fig. 3 AC is similar to 380, but VC- (398) is maintained at a substantial negative value with respect to ground 397. This type of arrangement may be beneficial for allowing high cluster voltage differences [(VC+) - (VC-)] to be conducted safely and inexpensively through a plant.
  • Arrangement 386 in Fig. 3AE maintains substantially symmetric voltages 387 and 388 about a reference voltage 389 (e.g., 0 V or earth ground). In some embodiments, this substantially symmetrical variation is maintained through a control loop in an inverier circuit. In other embodiments, this symmetry is maintained ai ihe cluster. According to certain embodiments, this arrangement may be maintained by connecting approximately equal numbers of receivers in series on the positive and negative side of earth ground near a cluster. [8465] The absolute magnitude of the difference [(VC+) - (VC-)] can var '- widely, depending on the state of health of a cluster. For example, this absolute magnitude can vary depending upon whether receivers are non-functioning or poorly
  • the clusters should tolerate the variation in this cluster voltage.
  • any internal power supplies derived from the cluster voltage should be able to tolerate a sufficiently wide variation
  • the efficiency with which power is extracted may drop with the number of functioning receivers, in exchange for improved efficiency with all or all-but-one receiver functioning. For example, this efficiency compromise may favor the use of a boost stage in an inverter when one or more than one receivers is not producing.
  • the boost stage may be switched out or not operated, providing high inverter efficiency.
  • the inverter connected to the cluster can likewise tolerate a large voltage swing. For this reason, some embodiments may utilize a voltage-boosting inverter.
  • the mverter comprises a boost stage followed by a buck inverters.
  • the inverter comprises a boost stage that operates only when necessary followed by a buck mverter.
  • Such embodiments may enjoy high efficiency in good illumination and the ability to produce power in less than ideal illumination at a slightly reduced efficiency.
  • the inverter may supply auxiliary power to a cluster by maintaining a nominal cluster voltage.
  • a plurality of converters may be utilized
  • the converters may act on imbalance voltages between clusters, allowing combination of cluster outputs by paralleling while maintaining maximum power-point tracking of indi vidual clusters.
  • the converters may act on imbalance current between clusters, allowing combination of cluster outputs by series connection.
  • outputs of a plurality of clusters may individually feed an interleaved inverter
  • a plurality of outputs from inverters may be combined centrally and stepped up to grid voltage or stepped up individually and combined centrally
  • the central inverter solely establishes the common potential for the power system of the plant. This common potential is commonly called “ground,” but is not to be confused with the "earth ground” potential, because the local potential of the earth may vary considerably across the extent of a power plant.
  • the potential established at the central inverter may be different from that at a cluster as a result of ohmie losses in the current return line.
  • Relatively long transmission-line runs may be unavoidable in designing plants that harvest appreciable amounts of solar power. Accordingly it may be important to 1 ) control the cost of the interconnect wires, 2.) minimize conductance losses, 3) control EMl/ ' R I, and/or 4) control inductance.
  • Material selection may be important. From a cost standpoint. Aluminum wire is favored, costing several times less than a copper conductor of the same resistance. For long runs, difficulties connecting aluminum wires are far outweighed by the cost savings.
  • Material cost should be minimized by judiciously choosing conductor size for a substantially consistent resistance from each cluster to the inverter. In most cases, overall cost is reduced at a small decrease in material efficiency by selecting the wire gauge from a limited number of discrete sizes.
  • Figure 4 A shows a diagram of a pair of DC transmission lines (400).
  • Wire 402 carries current of one sign; wire 404 carries a return current.
  • wire 404 carries a return current.
  • the wires can beneficially have a gap (408) between them.
  • the wires then behave similarly to an air-spaced parallel-sided wire loop, provided the helix angle is small and the spacing between the wires is several wire diameters (406).
  • a modest air gap e.g., 3 to 50 mm, especially - 10 mm, such air-spaced wires posses a considerable inductance over typical plant-scale runs, e.g., O(100 uH).
  • a low r ratios of helix length to spacing significantly more conductor is needed to cover a linear distance than with an un- twisted wire pair, but EMI/RFI shielding is better.
  • Favorable ratios are beiween 1 : 1 and 50: 1 , with ⁇ 2: 1 being a reasonable compromise.
  • the inductor losses should be low, pro vided these cables are kept from low-resistance ferrometals by several pitch distances (410) to avoid hysteresis and eddy-current losses.
  • This series inductance can be used to enhance the operation of properly architected inverters, such as the boost inverter described above. In some cases, it may be possible to eliminate discrete power inductors in these inverters.
  • the spacing of an insulated twisted pair (420) may be maintained by a polymer web (422) having a cross-section like that of 424, which minimizes polymer use.
  • This insulator may he extruded with bare wires or pre-insulated wires.
  • a sufficiently inexpensive superparamagnetic, magnetic, or ferromagnetic powder, such as hematite, Fe 2 03 ⁇ 4, iron powder, iron-silicon powder, etc. could be mixed with the spacer polymer such that the spacer and ./ ' or wire insulators enhance the inductance of the transmission wires. This would further reduce emissions and improve inverter performance.
  • FIG. 4C shows an alternative spacer cross-section (444) that may be adopted if the use of an inductance-modifying filler material is cost justified.
  • FIG. 4C shows an alternative spacer cross-section (444) that may be adopted if the use of an inductance-modifying filler material is cost justified.
  • a boost architecture may be favored so there is tolerance for one or more concentrators in a cluster to be out of service with a modest loss of efficiency.
  • boost architecture allows a plant to operate in relatively low direct normal irradian.ce.
  • Water cooling may be used liberally to enhance component life, reduce size and mass, eliminate costly heat sinks, etc.
  • the standard enclosure for the inverter may be a shipping container into which inverter racks are integrated in a factory.
  • ⁇ Power from individual clusters or small groups of clusters may be inverted individually in a massively interleaved array, e.g., O (200 inverters) per megawatt.
  • Interleaved switching may be coordinated to reduce switching stresses and improve efficiency while reducing RFI and line-voltage distortion.
  • Components that are subject to failure may be individually packaged to minimize the cost of the consumable element and the maintenance cost of its replacement.
  • Consumable component containers may also contain features for mechanical locking, making electrical connections, etc., to assist with simple change out. Some of these connections can be used to detect the absence or repl cement of the device.
  • These component containers may further act as adapters to allow us to replace failed components with ne w ones having different physical geometries as components evolve.
  • Figure 25 shows a schematic diagram of a communications and control network 2500 according to an embodiment of the present inven tion.
  • a challenge with a large-area plant is to maintain tight control to detect and handle faults, and/or to sense and optimize performance, in spite of the potential for intense electrical noise and/or substantial ground-level variations.
  • communications may be handled in part by a '"Row bridge" (2502) that serves as a bridge between a higher-level, in some cases, plant- wide communications network (2504) such as an Ethernet network, RS485 network, or other differential voltage signaling network and a sub network that sendees one or two rows of clusters.
  • a '"Row bridge 2502 that serves as a bridge between a higher-level, in some cases, plant- wide communications network (2504) such as an Ethernet network, RS485 network, or other differential voltage signaling network and a sub network that sendees one or two rows of clusters.
  • sub network communications utilizes a pair of twisted pair cables, 2506 and 2508.
  • these cables comprise a twisted ribbon cable.
  • these cables comprise separate twisted wires, such as those in CATS or telephony cables.
  • at least cable 2508 has a controlled impedance. Examples of such controlled impedance include between about 30-300 ⁇ , and between about 80- 120 ⁇ .
  • the row sub network utilizes the RS485 protocol.
  • the Row bridge establishes a low- voltage communication bus power, for example between about 5 to 24 VDC, that provides power to the sub network side of a bridge 2510 between the sub network and one or more cluster networks. This power is used by nodes on the sub network to transmit differential voltages on the twisted pair 2508. The power may also provide a voltage reference to ensure that the common-mode transmitted voltage lies within the range of the Row- bridge (2502) receiver.
  • Fig. 25 shows the one-or-more cluster bridge as being a bi-cluster bridge.
  • the one-or-more cluster bridge provides voltage isolation between the sub network (2508) and the cluster network (2516).
  • Element 2512 depicts a cluster.
  • the bridge may be desirable to supply primary power to the bridge from one or more of the connected clusters (e.g., via 2514) rather than 2506. This is because the run length of 2506 may be much longer, and that power may be shared by a plurality of cluster bridges.
  • the bridge may need to isolate communications lines (2516) and (2518) between the two clusters. This is because in some embodiments, clusters may have ground references thai vary with respect to each other by more than the common-mode range afforded by the RS485 or other differential signaling specification. This ground-reference variation may be influenced by possible differences between the cluster voltages (2520 and 2522).
  • the communications line 2508 may be desirable to arrange the communications line 2508 as a transmission line having negligible distance 2524 between the line and cluster bridges.
  • the cluster bridges in turn may reside at a node in a cluster network transm ss on line.
  • Communications transmission line terminals can be properly terminated in an appropriate impedance to prevent signal degradation from reflections.
  • Reliable communications rates >1 MBAUD may be achieved in such a system, even for a plant having a span of order of i km.
  • Such a communication rate may support advanced plant-power optimization, even with rapid variations in illumination and collection efficiency (for example from wind gusts and buffeting).
  • communications, cooling, pointing, tracking, focusing, and others may be supplied via the cluster voltage difference [(VC+) - (VC-)].
  • this voltage difference may be produced by the receivers.
  • this voltage difference may be supplied from the central inverter, which normally draws this auxiliary power from the grid,
  • the inverter may have a modest battery to provide and sink bus power momentarily in the event of a grid outage. This battery may be backed up by a diesel generator to provide plant power during extended outages during which no production is possible.
  • embodiments of power system architectures in accordance with the present invention may be determined by one or more factors.
  • One factor is the nature of the basic power-producing unit.
  • this basic power- producing unit may comprise a silicon solar cell that produces only ⁇ 0.6 V and has a particular maximum power point of operation that depends on the device and the level of illumination.
  • Still another factor is the maximum voltage. For safety of maintenance staff. a maximum voltage of electrical transmission within a power plant. This maximum may also be set by device economics, and in some cases by device physics. [6507 ⁇ Still other factors comprise practical constraints. For example, in a system based upon photovoltaic receivers, it may be expensive and difficult to ensure that these receivers share a common maximum-power em'rent without active electronic intervention. [0508] The above considerations may lead to embodiments of plant architectures exhibiting one or more of the following characteristics. First, cel ls may be series connected in correlated strings (for example a module, dense-array receiver, or ganged sparse array), which are generically referred to as receivers.
  • correlated strings for example a module, dense-array receiver, or ganged sparse array
  • Examples of such techniques include but are not limited to, judicious paralleling of compensating substrings, in order to make departures from maximum power point operation acceptably low.
  • active circuitry can be economically employed to improve efficiency. However, this circuitry may operate only on "imbalance" currents. That is, receivers can be series connected in a "cluster” to boost the voltage. Active circuitry can only supply deficit or drain surplus currents to and from receivers such that each receiver operates near its maximum power point.
  • Certain embodiments may employ one or two balancing stages for our system.
  • the last stage of this balancer may comprise a sufficient number of series cell connections to reach the maximum bus voltage deemed safe for intra-plant transmission.
  • power may be transmitted to a single point (which may be at or near a center of a power plant), over separate, spaced twisted wires specifically optimized for increased inductance and a target resistive loss at maximum current.
  • the length of these interconnect wires can be O(100 m to 1 km) depending on the power rating of the plant.
  • a separate three-phase boost inverter can be connected via these wires separately to each cluster. That is, the power-bearing wires may not be bussed on their way to the inverter. Keeping these wires separate helps to avoid issues of maximum-power-point mismatch at the combination point and inverter load balancing at the splitting point.
  • the boost inverters may be massively interleaved. Such configurations may serve a number of purposes, including reducing filtering requirements, and reducing EMI/RFI.
  • Massive interleaving of the boost inverters may permit expansion of the peak efficiency envelope. For example, such configurations may allow variable frequency operation.
  • the outputs of the inverters may be directly connected, e.g., without an isolation transformer.
  • the inverter interleaving can be deterministically coordinated, allowing optimizations such as soft-switching.
  • filtering requirements of a deterministic system ideally scale as where N is the number of inverters.
  • N ⁇ j a threshold number
  • N n d another threshold
  • the outputs of the interleaved inverter array may be boosted directly to grid voltages via transformers located within -10 m of the inverter array.
  • Some embodiments may employ water cooling for increased cooling performance, reduced cost, and reduced parasitic load.
  • the load e.g., an inverter, etc. will not operate if its input voltage is below a threshold.
  • an inverter based on a simple buck inverter may cut out if the input voltage is lower than that needed to supply the peak of the output waveform, in soiar-power applications, the number of series-connected panels or cells is engineered to produce the required voltage with some additional voltage or headroom at normal or nominal conditions so that the inverter does not cut out when the illumination is slightly degra ded.
  • the amount of headroom one may apply may be limited by the maximum input voltage or the maximum bus voltages permitted by focal codes.
  • inverters such as buck inverters typically operate at maximum efficiency when the input bus voltage is only slightly higher than the maximum AC waveform voltage. In some instances, increasing the headroom may reduce system efficiency. Thus many inverter and string combinations are a compromise between the ability to function in nominal and good conditions and the ability to function in reduced light.
  • Some embodiments of the present invention provide the ability to boost the string voltage in low-light or reduced-power conditions so that the inverter may continue to operate, in some embodiments of the present invention, this boost operation requires only the addition of a single substantially D.C. switch.
  • the DC switch may be rated for the maximum intended voltage boost, not the maximum bus voltage. This low-cost and complexity optional feature of the balancer circuit may allow photovoltaic arrays to be productive in mornings, evenings, and in clouded or otherwise sub-nominal conditions.
  • Embodiments of the present invention provide lower average cost per extra-harvested power over the marginal cost of adding solar panels to gain the power. Certain embodiments of the present invention provide faster rate of return on the investment of the balancer resulting from this extra production. The lower average cost partially depends on the cost of photovoltaic panels, which has dropped by a factor of five in recent years and is continually declining. The rate of return partially depends on the uiility price for conventional electricity, which is commoditized and heavily subsidized. Another advantage is the value of information provided by the balancer. Some embodiments of the present invention provide the ability to log and report performance on a panel-by-panel or eeil-by-cell basis.
  • This information can be used for early identification of pro blems and for efficient maintenance deployment. Many aging solar power systems, both in small arrays and large installations are underproductive because of undiscovered and difficult-to-diagnose problems, such as connector corrosion, water ingress, etc.
  • the use of a balancer according to embodiments of the present invention can provide timely and specific information to support maintenance via communicating real-time and logged performance information about each power source over a communication link. This performance data can be used to update software displays, send text messages, voice messages, emails, instant messages, RSS messages, and the like to maintenance or otherwise interested personnel.
  • Figure 26A shows a system A 1000 comprising a series connected string A 1002 of solar panels, a load A1004, such as an inverter, and a balancer system A1006.
  • the series connections A1008 within the siring carry the main string current A1010, normally comprising the majority of the current in nominal operation.
  • a connection A10I2 carries current to load A 1004
  • connection AH) 14 carries the return current from the load to the balancer, e.g., via a connector A1016.
  • Connector A1016 can be one of an MC3, MC4, or other standard PV connector known in the art. Current is returned to the string via connection A 1018.
  • bypass wires connect the balancer with individual modules A1002 in such a way that current can be drawn or supplemented to the modules by the balancer.
  • These bypass wires normally carry imbalance power and are indicated in dashed lines.
  • An objective of the present invention is to minimize the cost of these bypass wires.
  • such connections may use a smaller conductor than the main power connections A1008, A1012, A1014, A1018 for improved economy.
  • the balancer system A 1006 may be mounted proximate to a string A1008 such that the total length of wires A 1020 is substantially minimal, e.g., having an average cable length that is approximately equal to a diagonal, width, or height of an array, half this dimension, or approximately one third or one quarter of this dimension.
  • it may be desirable to position a balancer behind the array e.g., behind a panel.
  • a balancer may be located behind the interior of an array.
  • the bypass cable length may be minimal if the balancer is located at the physical center of a string.
  • other factors such as ease of access to the balancer, routing of the cables to a load or other physical feature of an installation may favor a balancer placement that is less than optimal from a cable length perspective.
  • Advantages of minimizing bypass cable lengths include reducing resistive losses, conductor and insulator costs, cable inductance, EMI/ FI, etc.
  • a connection between A1008 and A1020 is made via a connector A1021 disposed between standard module-to-module connections, e.g., male and female MC3 and MC4 connectors and the like.
  • the intermediate connectors may comprise a male connector mate, a female connector mate and a wire.
  • the connectors may comprise a third connector in lieu of a wire.
  • the wire is assembled into the connector in the field or in manufacturing.
  • a part of the connector assembly is cast, potted, glued, swaged, squeezed, mechanically fastened, screwed, ratcheted, or barbed, to the connector assembly.
  • the wire is sealed using an o-ring, grease, gel, or adhesive, including polyurethane, acrylic, silicone, fiuoro- silicone, epoxy, or other suitable material chosen for long life, thermal cycling, water and humidity resistance, insulating properties, UV, acid, and ozone resistance, hardness, compliance, strain relief, and other properties.
  • the wires A1020 lead to a block of balancer circuits A1022. These circuits exchange power from inputs BAO (A 1024), BA1, ..., BAN (A1020) and isolated outputs A 1026 and A 1028. In some embodiments, power exchange is unidirectional from inputs to outputs or from outputs to inputs or bidirectional.
  • the arrows indicate the direction of current flow in a balancer that exchanges power unidirectionally from input to output.
  • the length of the arrow suggests the typical relative magnitude of the current.
  • the current flowing through an intermediate cable e.g., BA1 is a superposition (Al 030) of the current drawn from the balancer channels that are optimizing adjacent modules (Al 032, Al, A2).
  • Connection A 1026 links the positive output of the balancer with the positive output of the string.
  • the extra power produced by the balancer bank A! 022, indicated by current A 1034 (the result of the superposition of current s A1032) flows out through the bypass cable A! 036.
  • the combined currents Al 037 provide additional power to the load A1004.
  • cable Al 036 may use a reduced conductor size, similar to the other bypass cables because the extra harvested current may be less than the main current,
  • node A 1042 may be advantageous to use as a ground reference for the current sensing circuitry.
  • This "ground reference” may generally bear no relation to earth ground.
  • node A1042 also provides a ground reference for a controller circuit A 1044.
  • controller circuit A 1044 manages auxiliary power generation circuitry A 1046 via switch, configuration, and feedback signals A 1048.
  • the auxiliary power circuitry may provide power to the balancer bank A 1022 via connections A1050.
  • the auxiliary power is derived from the bus voltage, i.e., the difference between the voltage at A! 026 and A1024.
  • this controller may communicate with balancer banks via a communication fink A1052.
  • information exchanged over this link may include measurements of the main current, temperature, bus voltage, measurements of bypass currents, power, module voltages, flags, control and command signals, etc.
  • Some embodiments contain a mode switch A1054 that may open to provide a voltage-boost capability. Such a switch may be controlled by controller A1044 via a signal A 1056. In some embodiments, switch A1054 may be replaced with a short circuit.
  • mode switch refers to an element that can block current or Jet current flow with low loss, it may be distinguished from the term “switch” by not requiring the high-frequency switching performance of switches used in switch-mode power supply circuitry. Moreover, the mode switch may have comparatively lower on-resistance requirements than those of switches because, in normal operation, the main current flows through this switch and excessive on- resistance may reduce power efficiency and produce heat excessively.
  • Fig. 26B shows an alternative arrangement Al 100 of a string A 1 102, load A1004, and alternate balancer A ! 106 in which the connection between two modules Al 108 is made using connections Al 110 and Al 1 12 that pass through the balancer.
  • a balancer system Al 106 may be located to reduce the total length of the bypass wires A 1020.
  • current through connections Al l 10 and Al 1 12 passes through the balancer's current-sensing circuitry A 1040 and, in some embodiments, a switch A 1054 or alternatively, a short- circuit.
  • the base of the string connects directly to the negative input terminal of the load via connection A 1 1 14.
  • connection A 1 1 16, internal to the balancer or Al 1 18 external to the balancer may be made to support this arrangement.
  • Connection Al 120 may also be needed to support this arrangement.
  • connection Al l 16/A 1 118 it could alternatively be made external to the balancer.
  • Advantages of having internal connections include a reduction in the external complexity of the balancer as well as the cost of external interconnect wires and external connectors.
  • Advantages of external connections are an improved ability for an end user to customize an installation. In some embodiments, such configuration connections may be made via a sealed access hole on the balancer, conferring the advantage of configurability without as much additional cost.
  • the extra power supplied by the balancer flows out A1036 and a separate connection Al 122.
  • the balancer current sensing circuit may be positioned at any point along the string or in the negative path to the load (e.g., as in Fig. 26A) or the positive path to the load. If the balancer is positioned along the positive or negative path to the load, then one bypass cable may be omitted (e.g., Al 122), since it would duplicate a connection that is already made to the balancer. Consequently a balancer so positioned (e.g., balancer A1006 of Fig. 26A) may have one bypass connection per panel in the string.
  • a balancer positioned within the string e.g., balancer Al 106 of Fig.
  • the main current sensing may be performed external to the balancer. In some embodiments this entails a powered satellite circuit or an external passive sensing circuit,
  • FIG. 26C shows a system A 1200 comprising a string 'A' having N elements Al 008 and a string 'B' having M elements A 1202, a load A A1004, a load B A1204, and an alternate balancer system A1206,
  • System A1206 comprises two banks of balancers, A1208 and A 1210. In this arrangement balancer A A 1208 draws power from string A A1008 and supplies extra power to load B A1204.
  • Balancer B A1210 draws power from string B A1202 and supplies extra power to load A A1004.
  • the power flow direction may be reversed or be bi-directional.
  • An advantage of such a "crossed" power-balancing arrangement may be an improved ability to coordinate the power delivered to the two loads.
  • load A A 1004 may be a positive -half-only transformerless buck inverter.
  • Load B may be a complementary negative-half-only buck inverter.
  • the power supplied to the inverters should be substantially equal for the resulting waveform(s) to be accurately sinusoidal, which can be achieved robustly via a coordinated, crossed power-balancing arrangement.
  • strings A 1008 and A1202 may be electrically isolated from each other. The need to measure the main current of both strings may be complicated by the absence of a single 'ground' reference.
  • circuitry that uses a reference at node A 1042 and isolated circuitry that uses a reference at node A1212.
  • the circuitry referenced to node A1212 may sense the main current in string B via signal A1214. This circuitry may control a mode switch A1216.
  • Figure 27A shows an arrangement A2000 of a string A1008, load A 1004, and balancer A 1006 operating in a "boost" mode according to an embodiment of the present invention.
  • the mode switch A 1054 is open, so no current flows through A 1040 and a substantial voltage may build between A 1014 and A 1018 as a result of the operation of the balancer.
  • the string voltage thus boosted may allow the load A 1004 to continue to operate despite an insufficient string voltage. Because the main current is blocked by the A 1054, all power delivered to the load A! 004 is processed through the balancer bank A 1022.
  • this mode may appear to violate the minimalist processing philosophy of the balancer, this mode of operation may only be reverted to when the st ing power is substantially below its nominal power, e.g. , mornings, evenings, cloudy days, etc. leading to a collapse in the string voltage.
  • the balancer may only be processing a fraction of the rated siring power and therefore not require additional power-handling over a balancer that is not equipped to perform this boost function.
  • the extra power harvested would otherwise be completely lost (0% efficiency) so even a modestly efficient balancer circuit (e.g., 85-92%) would be a substantial improvement.
  • FIG. 27B shows an alternative arrangement A2100 of string Al 102, load A 1004, and balancer A 1 106 operating in the "boost" mode with mode switch A.1054 open according to another embodiment of the present invention.
  • a mode switch may be needed for permitting the boost operating mode.
  • This mode switch must have low on-resisiance because the main current passes through it in normal operation.
  • the required voltage rating of the switch is set by the maximum amount of voltage boost, not the full bus voltage.
  • the bus voltage may be, for example, 400- 1000 V
  • the switch is closed, so there is negligible voltage across it.
  • a typical maximum boost voltage may be about 200 V.
  • a maximum boost voltage may be a percentage of the nominal siring voltage between 5% and 75% and preferably in the range 10% to 50%.
  • the on-state resistance of typical semiconductor switches e.g., MOSFETS, may scale typically with the square of the rated voltage. Thus one may achieve a sufficiently low 'on' resistance for a modest boost circuit at 1/9* - 1/20* the cost of a similar switch that must hold off the full bus voltage.
  • FIG. 28 illustrates a mode switch circuit A3000 according to an embodiment of the present invention.
  • Element A3002 is a bank of low-on-resistance MOSFETs arranged in parallel to further reduce the On' resistance.
  • this bank may also or instead comprise lGBTs, BJTs, solid-state relays, mechanical relays, actuated switches, etc. in various parallel combinations to attain low operating losses and long life at low cost.
  • These switches act to short or open-circuit conductors A3004 (e.g., connections A1014, Al 1 12, A1214 of Figs.
  • Resistors A3008 to the positive bus voltage rail A3010 and voltage-limiting Zener diode A3012 set a default power-on state in which switches A3002 are 'closed' or On' (i.e. conducting). In some embodiments, resistors A3008 may have a value of about 220 i ' l.
  • Element A3014 is an optocoupler that provides voltage isolation between a control signal A3016 and ground referenced logic voltage A3018 on one side and a low-voltage circuit referenced to A3004.
  • FIG. 26A illustrates a circuit diagram A4000 that depicts decomposition of functions within the balancer system A1006 according to an embodiment of the present invention.
  • Element A4002 is herein called a "master;" element A4004 is a bank of balancer channels connected to the master via board-to-board connectors and wires within a chassis.
  • Elements AH) 16 may comprise male and female MC3, MC4, or similar standard connectors. In some embodiments, ihe connections A1020 go directly to the balancer bank. Circuits needed for operation of the master pass through the balancer bank through connectors, wires, or traces to the master.
  • Connector A4008 conveys power to the balancer bank and bi-directional
  • An advantage of this method of decomposition is an ability to produce balancers that serve strings of different numbers of modules cost effectively. Because of the large number of wiring configurations in use, it is desirable to be able to serve a range of installation configurations without a correspondingly large variety of inventoried boards.
  • a stock, un-modified embodiment of the present invention efficiently supports strings containing any number of modules between 3 and 32. This range is engineered to cover the most commonly encountered installations, but can be readily modified for best efficiency with smaller or larger string counts.
  • FIG. 29B shows a diagram A4100 that depicts the system A 1200 with the internal modularity of the multi-string balancer A1206 exposed, according to an embodiment of the present invention.
  • Element A4102 is an embodiment of the master that supports two isolated banks of balancers A4104 and A4106, which may be identical to element A4004, except for being cross-wired to the loads.
  • cross wired or not cross wired arrangements can be selected via jumpers, external connections, internal connections or traces on a circuit board.
  • routing of power from balancer to load is substantially performed via the master printed circuit board and, in some embodiments, short wire jumpers to standard photovoltaic connectors (e.g., MC4), A4108 and A4.1 10.
  • Jumpers A41 12 and A41 14 are used to configure the board for dual or single-string operation.
  • Element A4102 is shown with its jumpers in the crossed dual-string configuration: the positi v e output A41 16 of balancer B connects via circuit A 1036 to the positive input of load A A 1004.
  • the negative output A41 18 of balancer A connects via circuit A4120 to the negative input of load B A 1204.
  • Figure 29C shows an arrangement A 4200 of strings Al 008 and A .1002, load A1004, and balancer system A4202 configured as a single string, according to an embodiment of the present invention.
  • the master configuration A4204 has its jumpers set for one-string operation.
  • String B A 12.02 is placed in series with string A A 1008 via external connection A4206.
  • a wire, trace, or board-board connector makes the connection A4208.
  • Jumper A4112 connects the positive output of balancer B to A4210 connecting it with the positive output of bal ancer A.
  • Juniper .41 14 connects the negative output A41 18 of balancer B with the negative output A4212 of balancer A.
  • balancer A and balancer B outputs are paralleled and connected across the single load Al 004.
  • Each balancer may require a logic- level VCC (e.g., 3.3 V) and a voltage suitable for switching MOSFETS or IGBTs effectively, e.g., 7-15 V and a negative voltage source to facilitate analog sensing circuitr ''.
  • VCC logic- level VCC
  • a balancer circuit is ground referenced to the negative voltage of the module from which it draws excess power.
  • a balancer may derive its own power from that of its panel. However, this requires the use of multiple switching power converters per channel These power converters may be called upon to work over a wide range of panel voltages.
  • the master supplies each channel with bused signals from which each channel may draw its power without any active switching circuitry.
  • This embodiment may comprise two parts: one associated with the master and one with each balancer.
  • Figure 30 shows a schematic diagram of a switching circuit A5000 according to an embodiment of the present invention.
  • Controller A5002 which in some preferred embodiments is incorporated in controller A1044, provides judicious pulse trains A5004 and A5006 to control two simple power switchers.
  • a controller independently produces an intermediate power supply A5008 at a stable, low voltage (e.g., 3 to 20 V and preferably modestly above the logic-level voltage such that a low-dropout voltage linear regulator may be used with reasonable efficiency, e.g., 3.4 to 6 V) that is capable of sourcing enough current to operate the entire balancer.
  • This controller may also be incorporated into A5002 or Al 044.
  • this low- voltage supply is derived from a bus voltage.
  • this supply is derived from a single-stage buck converter.
  • this supply is derived from a two-stage buck converter.
  • the controller can switch between one-and two-stage operation.
  • one buck converter employs a synchronous rectifier.
  • optimum control of the synchronous rectifier is achieved by making adjustments to the pulse duration of the rectifier and measuring the resulting output voltage at substantially constant load.
  • a synchronous rectifier switch duration is adjusted to attain a maximal voltage at a given buck-switch duty cycle.
  • one or more switch timing is adjusted by a controller in nesied or concurrent loops.
  • Controller A5002 switches A5004 periodically, producing a spiky voltage waveform at ⁇ 5 ⁇ 14 whose amplitude increases with the switch 'on' duration.
  • Signal A50I4 is supplied via a bus to each balancer circuit.
  • a feedback signal is derived by capacifively coupling ground reference A50 I6 to the waveform at A5014 to a half-wave rectifier A5018 and filter A5020.
  • the filtered voltage at node A5022 may be used as a 10 V voltage supply for gate drivers.
  • a resistive voltage divider A5024 produces a proportional signal A5026 that can be sensed by A5002 and used to control the duty cycle and/or switch frequency of A5004.
  • Signal A5006 is used in a similar fashion to produce a waveform A5028 that is bused to each balancer channel. This waveform will be used by each balancer to supply its logic-level voltage (e.g., 3.3V).
  • Filtered rectifier circuit A5030 and voltage divider A5032 are used to produce a substantially proportional feedback signal A5034 for use in regulating the waveform.
  • Filtered rectifier circuit A5036 is grounded (A5038) to produce a negative voltage, which may be coarsely regulated using a series resistor A5040 and Zener diode A5042 to produce a reasonably stable negative voltage for biasing and compensating input voltage offsets from op-amps, etc.
  • Figure 31 shows a schematic diagram A6000 of the bused signals A5014 and A5028 and their common return path, e.g., A5038 and the balancer auxiliary power circuitry A6002, A6004, they supply.
  • Coupling capacitors A6006 provide high-voltage isolation.
  • the filtered rectifier circuit A60Q8 provides a sufficiently stable 10 V supply A6010 for driving switch gates.
  • Filtered rectifier circuit A6012 provides a sufficient voltage to a low-dropout regulator A6014 to achieve a stable and sufficiently noise free logic-level voltage A6Q16, for example, to allow 10 or more bit precision on A/D conversions performed by a balancer controller.
  • Low-voltage capacitor A6018 feeds a negative filtered rectifier circuit A6020.
  • the negative voltage is coarsely regulated via the resistor and Zener diode pair A6022. to produce a negative voltage supply, in some embodiments of the present invention, this negative voltage is used to power the negative rail of one or more op amps. In some embodiments, this negative voltage is further used in connection with a pulse-width modulated signal from a controller to null an input offset voltage of an op amp.
  • the circuit elements of A6004 perform identical functions at a different ground reference. The total cost of the three isolated power supplies on each balancer is about ten times cheaper than a switch-mode supply and occupies a smaller footprint.
  • FIG 32A shows a schematic diagram A7000 of an isolated, bussed communications link (A7002, A7004) between a master controller (A 1044) and array of balancer controllers (A7006) according to an embodiment of the present invention.
  • the master transmits data on bus A7002.
  • a capacitor e.g., A7008 couples this signal, while providing DC isolation up to high voltage.
  • This signal may be low -pass filtered with an C filter with a corner frequency many times higher than the baud rate.
  • the baud rate is between 20 kB.AUD - 1.4 MBAUD, with preferred rates between 250 and 750 kBAUD.
  • a resistor (e.g., A70I0) may assist with establishing a quiescent voltage state and the internal Schottky diodes that protect the balancer input clamp the voltage at 7014 to ⁇ 0.3 V past either logic voltage rail.
  • the AC coupled signal is re-centered on the supply rails, substantially mitigating voltage sag during a transmission.
  • Some preferred embodiments use an asynchronous serial protocol including a start and stop bit, thereby guaranteeing two 're-centering' events per byte.
  • a channel may also elect to force A7014 to a known state by momentarily making the pin an output and driving it to that state following reception of data.
  • the master may always maintain an output on its transmit pin A7016.
  • Some embodiments employ a series resistor A7018 of low value, e.g., 47 ⁇ , to damp reflections and noise.
  • Communications from a balancer to the master may utilize a second bus A7004. This bus may be shared between channels. Only one channel at a time may transmit on this bus. One preferred way to ensure this is to require all channel transmissions to be responses to commands or specific broadcasts from the master over a limited window of time.
  • a transmit pin e.g., A7020
  • the master listens during the transmission window.
  • the received bits are filtered and centered between the voltage rails A7002. using a load resistor and RC filter A7022, and protection diodes.
  • the communications between master and balancers are important for the operation of an optimizer because the main current measurements may be needed in the calculations of module power used by the balancer in its power-optimization loop.
  • Balancers based on an isolated flyback circuit also benefit from knowing the total output voltage, which may be measured or summed from individual balancer measurements of module voltage by the master.
  • Balancers also may derate their power processing based on ambient temperature measurements reported by the master.
  • the masier receives measurement data from channels, such as processed power, current, and module voltage.
  • the master may log these data and use them to select different operating modes, e.g., boost mode, sleep mode, etc.
  • conversions are scheduled according to transmissions from the master.
  • the master may complete a sequence of A/D conversions and broadcas t the results to all channels, signaling this broadcast with a special token.
  • the channels receive this token, they record the data from the broadcast, in some embodiments, one channel will then report a packet of its measurement data back to the master.
  • all channels and master initiate a new sequence of A/D conversions.
  • the masier transmits a new packei and may receive a data block from the next channel in the chain in response.
  • the master may produce alternate broadcast tokens to perform other functions, such as to report alternative, low- frequency data, such as temperature, to reset the channel counter to maintain synchronization with channels that are reporting back, etc.
  • these broadcasts may contain commands such as 'reduce current,' 'increase current,' 'emergency stop,' 'switch operating mode' etc. These broadcast commands may be useful to assist the master with maintaining operation within a safe envelope, e.g., to avoid excessive voltage boost, etc.).
  • a broadcast repetition rate between about 40 kHz and 400 Hz. In some embodiments, it may be possible to utilize a broadcast repetition rate down to 1 Hz or lower, however, such a low rate may lead to long optimization periods and poor performance in systems having rapid illumination changes, e.g., caused by shadows from wind-blown branches, fluttering mirrors, etc.
  • a master may issue its own channel-specific commands and may forward channel-specific commands from an external communications link and forward command responses from a channel to an external communications link.
  • FIG.B shows a schematic diagram A7100 of a physical bus that carries the communications signals, power waveforms, power-return signals, and low-noise DC reference.
  • this bus may pass from one balancer channel to the next via circuit -board traces.
  • this bus may pass from a balancer channel to another through a board-board connector.
  • This bus may pass from the master to a balancer via circuit-board traces, a board-to-board connector or a plurality of connectors.
  • this bus may pass between stacks of balancers via at least one connector.
  • a master connection to the bus is physically located substantially centrally such that the bus spreads from this feed point in multiple directions.
  • the master feeds the bus at a plurality of redundant points, e.g., to facilitate reduced resistive losses or increase current capacity.
  • a master feeds one physical level of balancers in a stack and secondary connectors feed the bus signals to a second level.
  • the master may connect directly to multiple levels of balancers in a stack. Such an arrangement may reduce the distance signals and power must propagate by a factor of ⁇ 4, reducing attenuation and noise pickup.
  • the isolated power and communications hardware disclosed in Figs. 30, 31, and 32 may similarly benefit the economics of a massively interleaved inverter, which may face similar requirements for isolation, power, and communication between a master and plurality of inverter channels.
  • FIG 33 shows a schematic diagram A8000 of an embodiment of a balancer channel circuit according to an embodiment of the present invention.
  • a controller A8002 senses analog channels including the bypass current the circuit is transferring (A8004) and the voltage of the module it is optimizing (A8006). In some embodiments, this sensing is performed using an analog to digital converter followed by digitally processing the digitized readings.
  • the controller A8002 may also control the switching of the power-converter circuitry, in some embodiments judiciously adjusting both the period and on-time of the switch signal A8Q08 to optimize converter efficiency and module power production simultaneously.
  • the controller may also control (A8010) an active circuit A8012 to drive the gate of an active module bypass switch.
  • Circuitry A8014 provides for in-circuit programming of the controller A8002,
  • controller A8002 is configured with initial firmware via a programmer that links with A8014.
  • A8002 is pre-configured with initial firmware before circuit assembly.
  • firmware may be updated via commands sent on a communication bus (A7020 and A7014).
  • Element A8100 is the power converter used to optimize module
  • Element A8104 is a gate driver for the main switch A8106.
  • Element A8106 is a current-sensing resistor that is preferably in the 1 - 100 mQ range.
  • Node A81 10 is a low-level current sense signal.
  • Resistor A81 12 may be a zero- ⁇ resistor or trace that ties the local ground reference A6026 to a low-noise analog ground A81 14.
  • the flyback transformer A81 16 connects to a signal A811 8 that is in communication with the positive module terminal, possibly through a fuse.
  • signal A81 18 is filtered via at least on local capacitor to local ground (A6026).
  • circuitry in communication with A81 18 is protected from voltage spikes and arcs via one or more protection devices including, diodes, Zener diodes, metal oxide varistors, spark-gap arresters, etc.
  • the flyback transformer may perform several important functions: 1) it provides primary to secondary voltage isolation, 2) its winding ratio produces a nominal voltage step up, 3) it stores energy in such a way that its output may be boosted above or bucked below this nominal voltage step up.
  • the ability to buck and boost provides for the use of identical power circuitry to sendee strings having different numbers of modules.
  • the transformer turns ratio or voltage step up should be approximately equal to the number of modules in the array.
  • Elements A8120 comprise a snubber circuit. Coupling capacitor A8122 is a novel circuit addition that boosts efficiency and reduces EMI. Diodes A8124 rectify the output of the flyback converter and capacitor A8126 may locally filter this output to reduce EMI and output ripple. In some embodiments, the main filtering on an output is located on the master board or otherwise remote from the balancer board. Element A8200 amplifies the current-sensing signal to a level that can be accurately digitized (A8004). This op-amp circuit may require a large gain. The action of a large gain on the input offset voltage of the amp may be problematic.
  • One solution may be to employ a low-offset voltage or chopper-stabilized op-amp.
  • the controller may generate an offset-voltage compensating signal, A8202, The controller may periodically, on command, or on an event such as a thermal excursion, null the effect of the offset voltage on signal A8004 using a self-calibration procedure.
  • ibis procedure may be to cease switching A8008 long enough that the current signal A81 10 settles to its zero setting, then adjust a duty-cycle of a pulse-width modulated (PWMed) pin A8204 while digitizing signal A8004 until A8004 reaches a target voltage, such as a voltage that is sufficiently above the negative voltage reference A8114 to eliminate problems sensing near a voltage rail, e.g., improper averaging of noise, nonlinearities, etc.
  • PWMed pulse-width modulated
  • Other self-calibration procedures may be adopted that fulfill the same offset-compensating objective.
  • a further function of signal A8202 may be to add a systematic dither signal via stage A8200 to A8Q04 to extend the resolution of the A/D converter in A8002.
  • the frequency of PWM signal A8204 is judiciously chosen in accord with RC filter A8206 to add an oscillation having approximately 1-bit of voltage excursion to A8004. With averaging, such dithering may practically increase the A/D resolution by ⁇ 2-6 bits.
  • Element A83Q0 produces a buffered signal A8006 that is proportional to the module voltage A81 18. This signal may be digitized and used in the calculation of module power and the optimization of the switch signal (A8008) duty cycle and period.
  • FIG. 34 shows a schematic diagram A9000 of a master according to an embodiment of the present invention.
  • Element A9002 is a microcontroller that may perform multiple functions. This controller may communicate bi-directionally with balancer channels via signals A7024 and A7016. This controller may also communicate externally directly or via a secondary controller, via isolated or nonisolated channels including asynchronous, synchronous, differential, RS232, RS485, Ethernet, I2C, SPI, USB, optical, IrDA, fiber, wireless, ZigBee, Bluetooth,WiFi, AM, FM, PSK, FSK, SSB, DSB-SC, DSSS, frequency-hopping, QAM, QPSK, OOK, cellular, telephony, POTS, etc.
  • the controller may communicate externally via a wireless module, e.g., A9004 using handshaking, control, and data lines A9006.
  • Microcontroller A9002 may also log performance data.
  • A9002 maintains a real-time table of balancer channel performance data in RAM.
  • A9002 periodically, on command, or on an event, such as a substantial parameter change, record data, in some embodiments time- or ensemble-averaged data to internal or external storage, e.g., RAM, SRAM, removable or non-removable EPROM, EEPROM, flash, thumb drives, memory cards, and the like.
  • some embodiments of the present invention may include element A9008, a serial EEPROM module that communicates with A9002 via an I2C bus.
  • microcontroller A9002 may need to operate o ver a wide range in available power. It may be advantageous to turn off unused peripherals that draw significant power.
  • signal A9012 may turn off hardware peripherals, such as A9004 via switch A9014.
  • Some low-power circuits, e.g., the sensing circuits A9100 and A9200 may be powered directly via a signal from a microcontroller pin, A9012, Controller A9002 may further provide ambient temperature measurements via measuring the change in forward voltage drop in A9018 with current (making use, in this embodiment, of a programmable current source peripheral of the microcontroller).
  • the controller may measure the temperature via an internal peripheral, var stor, thermocouple, external sensor, etc. as known in the art.
  • a low -power 'watch crystal' A9020 may drive a low-power counter that can operate in sleep mode and trigger a wake up on roll-over event to facilitate night-time or low-power real-time clock functionality.
  • Signals A9022, A9024, and A9026 are manipulated by A9002 to produce low-voltage system power from the string voltage.
  • the crystal signal may drive an internal or external real-time clock peripheral.
  • Signal A9022 is connected to a hardware PWM microcontroller peripheral.
  • the pin connected to A9016 is tri-stated and resistor A9036 couples A9022 to A9034 so that signals A9028 and A9030 are substantially identical.
  • the pin connected to A9016 is made an output at the inverse of the desired state of A9030.
  • the function of signals A9026, A9G2.8, and A9030 are detailed in Fig. 35.
  • Signal A9038 is proportional to the low-voltage system voltage and is used by the microcontroller to control signals A9022, A9024, and A9026.
  • this control employs the use of an internal comparator peripheral, in some embodiments this control may further employ the use of hardware peripherals such as voltage-level flags and interrupts as well as automatic PWM inhibition modes that are triggered by voltage levels. Alternatively, some switching may be controlled by an external switch-mode power supply controller,
  • Signals A5004 and A5006 control the auxiliary power supply circuits shown in Fig. 30, using feedback from A5034 and A5026.
  • signals A5004 and A5006 are connected to an internal hardware PWM peripheral to support this functionality.
  • Element A9I00 amplifies the main current sense signal (e.g., A1041 , A1214). As with balancer sensing circuit A8200, this circuit may amplif the current sense signal by a large factor.
  • A9002 can PWM A9016, which is lo -pass filtered by C filter A9104.
  • the output of this conditioning and gain stage A9106 may be digitized, processed, including averaged, scaled, offset, calibrated, etc., and digitally broadcast or otherwise communicated to channels for use in their calculations of module power.
  • Element A9200 produces a low-pass filtered and buffered signal that is proportional to the overall string voltage A9202. This signal may be useful for performance monitoring and may assist channels with optimizing their switching period and frequency, in some embodiments, the master may alternatively calculate this value by summing module voltages reported by individual channels. Knowledge of the bus voltage is also important for the master to establish the proper operating state, e.g., unpowered, boost-mode, normal mode, etc. In operation at low power levels, controller A9002 may need to sample the bus voltage without having the ability to power op-amps. In such a mode, an un-buffered signal A9206 may be digitized.
  • all power for operating the balancer is solely derived from the solar panel array. Because the amount of illumination varies dramatically over the course of day and night, the power circuitry must have flexibility that is not needed when there is a stable supply of power.
  • Figure 35 shows a schematic diagram A10000 of a system power solution according to an embodiment of the present invention.
  • the circuit draws power from voltage A 10002, which may be protected against arcing and spikes on the power source Al 0001, e.g., by resistor and metal oxide varistor A10004 or one or more other protection devices known in the art.
  • the power source A 10001 may be connected to any voltage in a string.
  • a 10001 is a maximal string voltage.
  • A10001 is a voltage between two modules in the interior of a string.
  • the ground reference A6026 may be a minimal string voltage.
  • the ground reference may be a voltage between two modules in the interior of a string.
  • Element A10100 is a buck regulator stage controlled by a switch signal, e.g., A9030.
  • Elements A 10102 comprise a level shifter circuit that translates the ground- reference signal A9030 to a signal referenced from A1002 that drives the gate on the P-channel MOSFET Al 0104. in conjunction with Al 0106 and AI 0108, this forms a buck converter with snubber A101 10 that produces an intermediate voltage A101 12.
  • Element A 10200 is a cascaded buck regulator stage controlled by signal A9028.
  • the architecture of this stage is similar to that of AlOlOO, with the exception of the substitution of a synchronous rectifier A 10200 in the place corresponding to A1G106.
  • a low-forward voltage drop rectifier may be utilized in place of A10106.
  • This synchronous rectifier may be driven by a gate driver A10204. Because the on-resistance of the rectifier drops with gate voltage, it is desirable to drive the gate with up to about 10 V. However, 10 V is not always available, particularly when the system power is being turned on.
  • diodes A10206 may be employed to 'or' the system power voltage A5008 and the 10 V supply A5022 to facilitate system supply bootstrapping.
  • more than two buck stages are cascaded.
  • Element A10300 is a circuit that provides typically ⁇ '8 of current to enable a microprocessor to maintain its RAM state and to boot strap from a complete power down.
  • Element A10302 is a depletion-mode
  • MOSFET Metal-oxide-semiconductor
  • auxiliary power When the auxiliary power is not operating, its gate voltage will be low and it will therefore conduct current from 1000 through resistors A 10304 to node A 10306 whose voltage is limited by Zener diode A10308.
  • diode A10310 On startup or in the dark, current flows through diode A10310 to trickle -charge capacitor A10312.
  • This capacitor may be sized to hold a sufficient charge to allow a microcontroller to wake up and momentarily enter a substantial power-consuming state to attend its real-time clock- functions, to check for adequate bus voltage to start the system power, etc. before either starting system power or returning to sleep mode.
  • This low-power functionality may be maintained even on dark nights from ambient light.
  • a purpose of element A10302 is to turn off the current flowing through A10304 when the balancer is in normal operation, since that current is wasted.
  • the values of A10304 are high enough that this loss is tolerable and element A10302 may be replaced by a short circuit.
  • Elements A10400 produce a well-regulated output with a short rise time.
  • Element A10402 is a 'supervisory' circuit that switches its output when its voltage reaches a threshold value. This output enables the output of regulator A 10404, providing a sufficiently fast rise time for microcontroller A9002 and other sensitive components to power up properly.
  • Elements A 10500 produce a voltage A9038 proportional to the system voltage for use in active feedback of the system power switching.
  • a two-stage buck controller can be optimized using more common components and may perform more efficiently that a one-stage buck controller at the large buck ratios employed in the balancer, e.g., 1/100 - 1 /150.
  • Some embodiments of the present invention support the use of two or more isolated strings.
  • a microcontroller circuit such as Al 1000 in Fig. 36 that employs a ground reference (Al 1002) related to an alternate string.
  • This circuit may comprise a microcontroller A 1 1004, an auxiliary power receiver circuit Al 1100, that functions like that used by the balancer channels (Fig. 31) to produce a regulated logic-level voltage Al 1 102 and semi-regulated negative voltage Al l 104.
  • the secondary controller may communicate on the bus using the same circuitry Ai 1200 and protocols as a balancer channel.
  • element Al 1006 facilitates ill-circuit programming of Al 1004.
  • Microcontroller A 1 1004 may also be pre-loaded with firmware and may allow firmware updates via a digital communications bus, e.g., via Al 1200.
  • the purpose of this secondary controller may be to measure the main current flowing through an alternate string, which may be achieved using a simple current sensing resistor and amplifier combination Al 1300, similar to that used in Fig, 33 and Fig. 34.
  • circuit Al 1000 may include a mode switch Al 1400. Because the mode switch may contain isolation circuitry, such a switch may be actuated from any ground reference. However there may be an advantage to grouping the sensing and control of an alternative string. For example, if a single-string system is desired, the entire block of circuitry Al 1000 may be unloaded.
  • circuitry Al 1000 may be loaded on a separate board that can be readily installed or removed as needed to configure a balancer for an application.
  • one or more isolated controllers may be used similarly to that illustrated in Fig. 36 to perform an alternative function that is best implemented using an alternative ground reference, e.g., providing for directly coupled or ground referenced communication, e.g., RS232, RS485, USB, I2C, SPL etc.
  • FIG. 37 A shows an end-on view A! 2000 of a 24-channel balancer according to an embodiment of the present invention.
  • Element A12100 is one bank of balancers.
  • Element A12102 is ihe printed circuii board.
  • Element A12104 is a bypass wire for a balancer in bank A12100.
  • Component A8002 (microcontroller) and sensitive analog circuitry is placed far from the power switching circuitry, e.g., switch A8106, diodes A8124, snubber network A8120, and flyback transformer AS 116. These power switching components are the primary heat generators in the balancer and are located in such a way to facilitate heat removal.
  • Element A12200 is a second bank of balancers, including printed circuii board A12202.
  • Element A12204 is a bypass wire in bank A12200. This second bank identical to A12.100, but is oriented oppositely from A12100 and offset to provide clearance and isolation between the banks. Stacking the balancer banks in this manner does not adversely affect heat removal since the heat generating components of the second bank, A 12206, are far removed from those of the first bank.
  • Element A 12300 is the master board.
  • FIG. 37B shows a rotated view A 12400 of the balancer system that shows an embodiment of how balancer channels may be arrayed.
  • Elements A12402 are arrays of four balancer channels, e.g., A12404, with bus connections made between the arrayed channels via printed circuit board traces.
  • Elements A 12406 are arrays of ceramic capacitors that filter high-frequency, e.g., typically 40 kHz - 250 kHz switching current and voltage fluctuations from the associated module and bypass wire.
  • Figure 37C shows a rotated view A12500 showing the transformer and master-board side of the balancer system.
  • the bused connections A7100 propagate along the line A12502. along traces within the boards and across external board-board connections (A 12504). In this view the mode switches Al 054 and A1216 are visible.
  • Power filter capacitors e.g., A 12508 are ceramic rather than electrolytic for long life.
  • the region of the hoard containing the isolated string controller A8000 is delineated by a component-free surrounding. Some elements, e.g., A12510 are present for debugging purposes only.

Abstract

L'invention porte sur un système de chaîne et d'équilibrage de charge qui fournit la capacité d'amplifier la tension de chaîne dans des conditions de faible lumière ou de courant réduit de telle sorte que l'onduleur peut continuer à fonctionner. L'opération d'amplification peut être obtenue par ajout d'un commutateur sensiblement à courant continu (CC) unique. Le commutateur CC peut être nominal pour l'amplification de tension prévue maximale, pas la tension de bus maximale. Une chaîne et un dispositif d'équilibrage de charge fournis dans la présente invention peuvent permettre à des réseaux photovoltaïques d'être productifs le matin, le soir, et dans des conditions nuageuses ou par ailleurs sous-nominales.
PCT/US2014/020862 2013-03-15 2014-03-05 Architecture pour une centrale électrique comprenant des groupes de dispositifs de génération d'énergie électrique WO2014149775A1 (fr)

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CN113098549A (zh) * 2016-06-21 2021-07-09 苹果公司 谐波抑制本地振荡器信号生成
CN113645113A (zh) * 2021-08-12 2021-11-12 上海海达通信有限公司 一种3.3v供电rs485通讯系统
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DE102014220079A1 (de) * 2014-10-02 2016-04-07 Robert Bosch Gmbh Verfahren zur Kalibrierung eines Sensors eines Batteriemanagementsystems
CN113098549A (zh) * 2016-06-21 2021-07-09 苹果公司 谐波抑制本地振荡器信号生成
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CN113645113B (zh) * 2021-08-12 2022-09-20 上海海达通信有限公司 一种3.3v供电rs485通讯系统

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