WO2014143942A2

WO2014143942A2 - Ultrasonic transducer with driver, control, and clock signal distribution

Info

Publication number: WO2014143942A2
Application number: PCT/US2014/028133
Authority: WO
Inventors: Matthew ANGLE; Marc Berte
Original assignee: uBeam Inc.
Priority date: 2013-03-15
Filing date: 2014-03-14
Publication date: 2014-09-18
Also published as: WO2014143942A3; EP2974376A4; CA2902443A1; EP2974376A2; KR20150129854A

Abstract

An ultrasonic transducer having a membrane and a container having a base and at least one wall element. The ultrasonic transducer can include a driver side and a bias voltage side. A first controller can have a greater number of output lines than a second controller has input lines. The first controller can receive an ultrasonic transducer control signal and provide a first portion of the control signal to the first processor, where the length of the first portion is less than or equal to the number of input lines of the second processor. An array of the ultrasonic transducers can be controlled to produce a steerable beam. Beam steering can be skewed by buffer delays in the distribution of a clock signal.

Description

ULTRASONIC TRANSDUCER WITH DRIVER, CONTROL, AND CLOCK SIGNAL

DISTRIBUTION

BACKGROUND

[1] Ultrasonic transducers receive electrical energy as an input and provide acoustic energy at ultrasonic frequencies as an output. An ultrasonic transducer can be a piece of piezoelectric material that changes size in response to the application of an electric field. If the electric field is made to change at a rate comparable to ultrasonic frequencies, then the piezoelectric element can vibrate, causing it to generate acoustic pressure waves, such as ultrasonic frequency acoustic waves.

BRIEF SUMMARY

[2] In an implementation, an ultrasonic transducer can include a membrane and a container having a base and at least one wall element. The one or more wall elements can be situated over at least part of the base to form a cavity that can have an at least partially open end. The open end can be sealed with the membrane and the interior of the container can be maintained at a lower atmospheric pressure than the ambient pressure. Within the container, a piezoelectric flexure can be fixed at one end to a location at a wall element. The other end of the flexure can be in mechanical communication with the membrane, either directly or through a stiffener that is itself in communication with the membrane.

[3] The flexure can include a substrate, a piezoelectric material and an electrode. The piezoelectric material may be disposed in one or more layers as part of the flexure. The flexure may include one or more electrodes. In an embodiment of a flexure, a thin film piezoelectric material can be disposed between a substrate and a conductor. In another embodiment, a substrate may be surrounded on both sides by piezoelectric layers, which in turn can be at least partially covered by conductors. [4] The ultrasonic transducer can receive an electrical control signal, causing the flexure to vibrate at or around ultrasonic frequencies. The flexure can thereby cause the membrane to vibrate and create ultrasonic frequency acoustic waves.

[5] An implementation can include an ultrasonic transducer that can include a driver side and a bias voltage side. A higher voltage source can be electrically connected to the bias voltage side through a first resistor. A lower voltage source can be electrically connected to the driver side of through a second resistor. A field effect transistor or other suitable switch (such as a BJT, IGBT, thyristor, etc.) can be included, having a source, a gate and a drain. The source can be electrically connected to ground and the gate can be electrically connected to a control signal source. The drain can be electrically connected to the lower voltage source through a second resistor and be electrically connected to the driver side of the ultrasonic transducer. The gate can be electrically connected to a signal source through a third resistor.

[6] An implementation can include a system for distributing information to ultrasonic transducers including a first controller having 8 available first controller output lines that include a first subset of 4 first controller output lines. The system can include a second controller having 4 second controller input lines and 16 second controller output lines. The 16 second controller output lines can be electrically connected to a first set of ultrasonic transducers. The first controller can be adapted and configured to receive a 16-bit ultrasonic transducer control signal. The first controller can separate the 16-bit ultrasonic transducer control signal into four 4-bit intermediate ultrasonic transducer control signals and send each of the 4-bit intermediate ultrasonic transducer control signals to the second controller through the first subset of 4 output lines. The second controller can be adapted and configured to receive each of the four 4-bit intermediate ultrasonic transducer control signals through the 4 second controller input lines, to reassemble the 16 bit ultrasonic transducer control signal based on the received four 4-bit intermediate ultrasonic transducer control signals and to send the 16-bit ultrasonic transducer control signal through the 16 second controller output lines to the first set of ultrasonic transducers.

[7] In an implementation, an array of the ultrasonic transducers can be controlled by a set of controllers. Each controller can have a corresponding buffer. A first controller buffer can receive a clock signal and send it to second and third controller buffers. The second controller buffer can be horizontally adjacent to the first controller buffer. The third board controller buffer can be vertically adjacent to the first controller buffer. The second and third controller buffers can further distribute the clock signal to horizontally and vertically controller buffers, respectively.

[8] A clock skew can be determined based on the buffer delays and/or propagation delays in distributing the clock signal. A tilt can be determined based on the determined clock skew. A beam steering command can be corrected for the determined tilt.

[9] Additional features, advantages, and implementations of the disclosed subject matter may be set forth or apparent from consideration of the following detailed description, drawings, and claims. Moreover, it is to be understood that both the foregoing summary and the following detailed description provide examples of implementations and are intended to provide further explanation without limiting the scope of the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[10] The accompanying drawings, which are included to provide a further understanding of the disclosed subject matter, are incorporated in and constitute a part of this specification. The drawings also illustrate implementations of the disclosed subject matter and together with the detailed description serve to explain the principles of implementations of the disclosed subject matter. No attempt is made to show structural details in more detail than may be necessary for a fundamental understanding of the disclosed subject matter and various ways in which it may be practiced.

[11] Figure 1 shows an ultrasonic transducer according to an implementation of the disclosed subject matter.

[12] Figure 2 shows a flexure according to an implementation of the disclosed subject matter. [13] Figure 3 shows an ultrasonic transducer configuration according to an implementation of the disclosed subject matter.

[14] Figure 4 shows a flexure in communication with a membrane according to an implementation of the disclosed subject matter.

[15] Figure 5 shows an ultrasonic transducer with a driver circuit according to an implementation of the disclosed subject matter.

[16] Figure 6 shows first and two second controllers with two sets of ultrasonic transducers according to an implementation of the disclosed subject matter.

[17] Figure 7 shows a distribution of a clock signal among board buffers according to an implementation of the disclosed subject matter.

[18] Figure 8 shows a computer according to an implementation of the disclosed subject matter.

[19] Figure 9 shows a network configuration according to an implementation of the disclosed subject matter.

DETAILED DESCRIPTION

[20] According to the present disclosure, an ultrasonic transducer can include a piezoelectric flexure that can be mechanically fixed at one end to a location at a wall of a container and that can be in mechanical contact with a membrane at one end of the container. The piezoelectric flexure can be driven by an electrical control signal to displace the membrane at or around ultrasonic frequencies, thereby generating ultrasonic waves.

[21] An embodiment of the ultrasonic transducer can include a membrane over a cavity.

The membrane can be made of monocrystalline silicon, which can be resistant to fatigue.

However, any other suitable material can be used for the membrane, including, for example, any material that can be formed into a thin layer, be resistant to fatigue, be naturally or through doping conductive, and be bondable to the other materials. Such materials include single-crystal materials such as Silicon Carbide, Silicon Nitride, Silica, Alumina, Diamond, and super-elastic metal alloys such as NiTi. The cavity can have at least one wall element situated over a base to form a container having an open end. The one or more wall elements over the base can form the container as a cylinder, a box, or any suitable shape. The open end of the container can be sealed with the membrane. The sealed container can be maintained at a lower atmospheric pressure than the ambient environment. This can pretension the membrane and improve its effectiveness as an ultrasonic vibrator. In various implementations, the interior of the container can be maintained at or about the ambient atmospheric pressure or at a pressure that is higher than the ambient pressure.

[22] Embodiments of the transducer can include at least one piezoelectric flexure. Around one end of the flexure, the flexure can be fixed at a location at the at least one wall element. Around the other end of the flexure, the flexure can be in mechanical contact with the membrane. In an embodiment, the flexure may be in direct contact with the membrane itself. In another embodiment, the flexure can be in mechanical contact with a stiffener that can be disposed between the membrane and the flexure. One side of the stiffener can be in mechanical contact with the membrane and the other side of the stiffener can be in mechanical contact with the flexure. In this way, the stiffener can transmit mechanical vibration of the flexure to the membrane. The stiffener can be made of silicon, or any other suitable material, such as the materials listed above for the membrane. The stiffener need not be made of the same material as the membrane. The stiffener can improve the resonant properties of the transducer.

[23] In embodiments, the piezoelectric flexure can include a substrate, a piezoelectric material and an electrode. The piezoelectric layer can be a thin film piezoelectric material or any other suitable piezoelectric material, such as PZT, PMN-PT, PVDF for example. The substrate can be made of a variety of materials including standard metals (brass, stainless steel,

aluminum), composite materials (CFRP), or homogeneous polymer materials. The electrode can be made, for example, of screen printed or vapor deposited compatible conductive materials such as gold, platinum, alloys of those, along with other pure metals and alloys. The substrate, piezoelectric material and electrode can be configured in any suitable arrangement. For example, in an embodiment, the piezoelectric material can be disposed at least partly between the substrate and the electrode layer. In another embodiment, the substrate layer can be disposed between the electrode layer and the piezoelectric material. In yet another embodiment, the flexure can include a first electrode layer disposed over at least part of a first layer of piezoelectric material, which in turn can be disposed at least partly over the substrate material. The substrate material can be disposed at least partly over a second thin film piezoelectric material, which in turn can be disposed at least partly over a second electrode.

[24] The at least one wall can include a wall element that includes two parts that can be electrically isolated from each other. One part of the wall element can be electrically connected to the electrode of the flexure and the second part can be electrically connected to the substrate. A control signal can be conveyed through one or both of the parts of the wall element to the flexure. In response, the flexure can cause the membrane to vibrate at ultrasonic frequencies, thereby creating ultrasonic frequency acoustic waves.

[25] In an implementation, the ultrasonic transducer can include a membrane that seals one side of a container. The transducers can be arranged in an array that can produce a focused beam of ultrasonic energy. A transducer may include at least one Capacitive Micro machined Ultrasonic Transducer (CMUT), a Capacitive Ultrasonic Transducer (CUT), an electrostatic transducer, a hybrid-type transducer or any other transducer suitable for converting electrical energy into acoustic energy. A hybrid transducer can include a piezoelectric flexure that can be mechanically fixed at one end to a location at a wall of a container and that can be in mechanical contact with a membrane at one end of the container. The piezoelectric flexure can be driven by an electrical control signal to displace the membrane at or around ultrasonic frequencies, thereby generating ultrasonic waves.

[26] An implementation of, for example, a CMUT transducer, can have a driver side and a bias voltage side. Such a transducer can have a membrane on one side such as the bias voltage side and the driver on the other side. A higher voltage from a higher voltage source can be applied to the bias side and a lower voltage from a lower voltage source can be applied to the driver side. A field effect transistor having a source, a gate and a drain can control the application of a control signal to the driver side of the ultrasonic transducer. The source can be electrically connected to ground. The gate can be electrically connected to a control signal source that specifies the waveform to be delivered as the driving signal for the transducer. The drain can be electrically connected to the lower voltage source through a first resistor and be electrically connected to the driver side of the ultrasonic transducer. This arrangement can permit the driver circuit to operate at a lower voltage than the bias voltage, and allow the controller signals applied to the gate to be at a lower voltage than the bias or lower voltage source

[27] The ultrasonic transducer can be electrically connected to the higher voltage source through a second resistor. This can prevent the occurrence of a current surge on the driver side of the transducer when the transducer is initially powered up, that is, when the bias voltage is first applied to the bias side of the transducer. This current surge can arise due the capacitative nature of some implementations of the transducer and could damage the driver circuit. The second resistor can help to protect the driver circuit from current surges during power up.

[28] The field effect transistor can be a N-type MOSFET. The first resistor can have a resistance of between A third resistor can be disposed between the gate and a control signal source that can generate a waveform that can be used to drive the ultrasonic transducer

[29] The higher voltage can be substantially higher than the lower voltage. For example, the higher voltage can be about an order of magnitude higher than the lower voltage, although there is no fundamental limitation on the magnitude of the difference between the higher and lower voltage.

[30] An implementation in accordance with the present disclosure can include a first controller having a greater number of output lines than a second controller has input lines. The first controller can receive an ultrasonic transducer control signal and provide a first portion of the control signal to the first processor, where the length of the first portion is less than or equal to the number of input lines of the second processor. In an implementation, the first processor can send portions (which may be of different size) of the control signal to a plurality of second processors. Each of the plurality of second processors can have a number of input lines less than the number of output lines of the first processor. Not all of the plurality of second processors need have the same number of input lines or output lines. In an implementation, the portions of the control signal can be sent through the output lines of the first processor to the plurality of second processors at substantially the same time. [31] If the length of a control signal word is longer than the number of input lines of a second processor, the second processor can accumulate bits of the control signal received through the second controller input lines and assemble them into a control signal word. In an implementation, once the control signal word is assembled by the second processor, the control signal can be sent by the second processor to a set of the ultrasonic transducers.

[32] In an implementation, a first controller can have 8 available first controller output lines that can include a first subset of 4 first controller output lines. The system can include a second controller that can have 4 second controller input lines and 16 second controller output lines. The 16 second controller output lines can be electrically connected to a first set of the ultrasonic transducers.

[33] The first controller can receive a 16-bit ultrasonic transducer control signal. The first controller can separate the 16-bit ultrasonic transducer control signal into four 4-bit intermediate ultrasonic transducer control signals and send each of the 4-bit intermediate ultrasonic transducer control signals to the second controller through the first subset of 4 output lines.

[34] The second controller can receive each of the four 4-bit intermediate ultrasonic transducer control signals through the 4 second controller input lines, reassemble the 16 bit ultrasonic transducer control signal based on the received four 4-bit intermediate ultrasonic transducer control signals and send the 16-bit ultrasonic transducer control signal through the 16 second controller output lines to the first set of the ultrasonic transducers.

[35] In an implementation, each of the 4 first controller output lines can transport one bit at a time of the 4-bit intermediate ultrasonic transducer control signal to the second controller. Each of the 16 second controller output lines can transport one bit of the 16-bit ultrasonic transducer control signal to one of the first set of ultrasonic transducers. Any or all of the ultrasonic transducers can be Capacitive Micromachined Ultrasonic Transducers (CMUT) and/or a hybrid transducer that uses a piezoelectric flexure.

[36] An implementation in accordance with the present disclosure can include an array of the ultrasonic transducers at a transmitter. The transducers can be caused to vibrate as a phased array to form a steerable beam of ultrasonic acoustic energy. The steerable beam can be directed to a receiver. The receiver can convert received ultrasonic acoustic energy to electrical energy. The rate of power transfer can depend at least partly on the shape of the beam and the accuracy with which the beam can be steered by the transmitter to the receiver.

[37] The transducers can be controlled by a system that is arranged in a hierarchical architecture. For example, an array of ultrasonic transducers (a "tile") can be controlled by a tile controller. A controller can refer to a general purpose microprocessor, an Application Specific Integrated Circuit or any suitable electronic control system. A controller can include a buffer that stores and /or amplifies a clock signal. An array of tiles can be arranged in one or more subarrays. A subarray can be controlled by a subarray controller. One or more subarrays can be arranged in a board. A board can be controlled by a board controller. One or more boards can be arranged in a board array that can be controlled by a board array controller, and so on. Each controller can have a clock signal supplied by a local buffer.

[38] Figure 1 shows an embodiment of the disclose subject matter that includes two ultrasonic transducers. The container 101 of one transducer 100 can be defined by base 102 and a wall element 103. The wall element 103 can have an upper part 104 and a lower part 105. The upper part 104 can be electrically connected to an electrode portion of a flexure 106. The lower part 105 can be electrically connected to a substrate of the flexure 106. The top of the container can be sealed by a membrane 107. A stiffener 108 can be provided in conjunction with the membrane 107. The flexure 106 can be in mechanical communication with the stiffener 108. A control signal can be fed to the upper part 104 and/or the lower part 105 of the wall element 103.

[39] Figure 2 shows an embodiment of a flexure. The flexure includes an upper electrode

201 and a metal substrate 202 with a piezoelectric material 203 disposed therebetween. A bump 204 can be fixed toward one end of the flexure to facilitate the flexure's mechanical

communication with the stiffener 108 and/or membrane 107.

[40] Figure 3 shows the configuration of an embodiment of four transducers, 301, 302,

303 and 304. Flexures 305, 306, 307 and 308 extend from corners of the transducers. The flexures can be placed diagonally to increase their length. The tip displacement of a flexure can be a function of its length. Output acoustic pressure can be a function of diaphragm

displacement. That is, the more the diaphragm moves, the more pressure can be created in the air. A design with increased flexure length can increase membrane motion, thereby generating more powerful ultrasonic acoustic waves.

[41] In yet another embodiment, a single container can include more than one membrane.

Each of the more than one membranes can be powered by a separate flexure. Such an

arrangement could provide opportunities to have longer flexures. For example, a flexure could be fixed to a wall location and be in mechanical communication not necessarily with the closest membrane to the wall location, but with a membrane that is more distant from the wall location. The additional length could cause the flexure/membrane combination to generate more powerful ultrasonic acoustic waves. For example, in Figure 3, the four transducers may be modified into a single container with four membranes, each membrane at a location 301, 302, 303 and 304. Flexure 305 can be in mechanical contact with membrane 303 rather than membrane 301, thereby lengthening flexure 305. The other flexures can be arranged similarly. A crossing point of one flexure with another can be managing by forming one flexure to pass underneath or over the other, thereby preventing them from interfering with each other in operation. The vacuum of the container can avoid acoustic interference within the single container between different flexures and membranes.

[42] Figure 4 shows flexure 401 in mechanical communication with stiffener 402 through bump 403. Stiffener 401 is in mechanical communication with the membrane 404.

[43] Figure 5 shows an implementation of the disclosed subject matter that includes the ultrasonic transducer 501 having a bias side 502 and a driver side 503. The bias side is electronically connected to a higher voltage source through the first resistor 504. The driver side is electronically connected to the drain 505 of a field effect transistor 506. The drain 505 is electrically connected to a lower voltage source through a second resistor 507. The source 508 of the field effect transistor is electronically connected to ground. The gate is electronically connected to a signal source through a third resistor 509. In an implementation, the second resistor can be replaced with another switch, such as a CMOS switch.

[44] In various implementations, without limitation, the first resistor can have, for example, a resistance of between 2 kilo-ohms and 5 mega-ohms and the higher voltage source can have a voltage of, for example, between 200 volts and 1000 volts. The second resistor can, for example, have a resistance of between 200 kilo-ohms and 500 kilo-ohms and the lower voltage source can have a range of, for example, between 10 volts and 120 volts. The third resistor can, for example, limit the current at the gate of to between 100 ohms and 10 kilo-ohms. The first resistor can, for example, limit the current at the high voltage side of the ultrasonic transducer to between 20mA and 500 niA in response to changes in voltage at the bias voltage side from zero volts to between 200 volts and 1000 volts.

[45] Figures 6 shows an implementation of the disclosed subject matter with a first controller 601 having first controller output lines 602 connected a second controllers 603.

Second controller output lines 604 are connected to subsets 605 of ultrasonic transducers 606. Each second controller output lines 104 can include 16 lines, with each line connected to one of the ultrasonic transducers 606 shown in Figure 6.

[46] An implementation can include a first controller having 2^a available first controller output lines having a first subset of 2^b first controller output lines, where a > b.

A second controller having 2^b second controller input lines and 2° second controller output lines, where b < c and each of the 2° second controller output lines is electrically connected to a first set of ultrasonic transducers. The first controller can receive a 2^c-bit ultrasonic transducer control signal, separate the 2^c-bit ultrasonic transducer control signal into (c-b) 2^b-bit intermediate ultrasonic transducer control signals and send each of the 2^b-bit intermediate ultrasonic transducer control signals to the second controller through the first subset of 2^b output lines. The second controller can receive each of the (c-b) 2^b-bit intermediate ultrasonic transducer control signals through the 2^b second controller input lines, reassemble the 2° bit ultrasonic transducer control signal based on the received (c-b) 2^b-bit intermediate ultrasonic transducer control signals and send the 2^c-bit ultrasonic transducer control signal through the 2° second controller output lines to the first set of ultrasonic transducers.

[47] In an implementation, a first controller can have a larger number of available first controller output lines that can be divided into subsets of controller output lines, such as a first subset of such controller lines. A second controller can have a number of second controller input lines that is less than the number of first controller output lines. The second controller can also have any number of second controller output lines that can be electrically connected to a first set of the ultrasonic transducers. The first controller can receive an ultrasonic transducer control signal that has any number of bits and separate it into subsets of intermediate ultrasonic transducer control signals. The intermediate ultrasonic transducer control signals can be sent to the second controller through the first subset first controller output lines. The second controller can receive each of the intermediate ultrasonic transducer control signals through some or all of the second controller input lines and reassemble the ultrasonic transducer control signal based on the received intermediate ultrasonic transducer control signals. The reassembled ultrasonic transducer control signal can be sent through the second controller output lines to the first set of the ultrasonic transducers.

[48] For an implementation such as that shown in Figure 7, a clock signal can be received from a board array controller buffer (not shown) at a board controller buffer 701. The clock signal can be received at a second board controller buffer 702 and a third board controller buffer 703 at substantially the same time. As shown in Figure 7, the second board controller buffer 702 can be horizontally adjacent to the first board controller buffer 701 and the third board controller buffer 103 can be vertically adjacent to the first board controller buffer 701.

[49] The clock signal can then be received from the second board controller buffer 702 at a fourth board controller buffer 104 and a fifth board controller buffer 705. The fourth board controller buffer can be horizontally adjacent to the second board controller buffer and the fifth board controller buffer can be vertically adjacent to the second board controller buffer 702. Likewise, the clock signal received at the third board controller buffer 703 can be received by a seventh board controller buffer 707. Optionally, the clock signal can also be received from the third board controller buffer 703 at the fifth board controller buffer 705. The fifth board controller buffer 705 can buffer the first of the clock signals received from the second board controller buffer 702 and the third board controller buffer. In an implementation, the fifth board controller buffer can average the clock signals received from the second board controller buffer 702 and the third board controller buffer 703. In an implementation, the fifth board controller buffer 705 can buffer the last of the clock signals received from the second board controller buffer 702 and the third board controller buffer 703. The third board controller buffer can treat the two clock signals in any suitable way. [50] In like fashion, each board-level buffer can send the clock signal to the board-level buffers to which it is horizontally adjacent and vertically adjacent, for example 708-711 as shown in Figure 7. An adjacent board controller buffer to which a sending board controller buffer sends a clock signal can be one that has not yet received the clock signal.

[51] The disclosed implementations for distributing the clock signal across buffers can render the delay in clock skew across the boards approximately linear. The resulting tilt in the array due to clock skew can be a linear tilt. It can be simpler to compensate for a linear tilt than a nonlinear tilt. For example, it can be relatively straightforward to determine the tilt angle based on the delay properties of the buffers. A known tilt angle can be corrected by adjusting the beam steering accordingly. This can enable a controller to more accurately steer the beam, which can result in more accurate and efficient power transfer from an ultrasonic power transmitter to a ultrasonic power receiver.

[52] In an implementation, a clock signal that is received at a board controller buffer can be propagated at substantially the same time to the subarray controller buffers for subarray controllers that are controlled by the board controller. A subarray controller buffer can further distribute the clock signal at substantially the same time to the tile controller buffers for tile controllers that are controlled by the subarray controller. In this way, clock signals can be propagated down the hierarchy of buffers in an orderly way. The diagonal propagation of the clock signal across the board controller buffers can linearize clock skew and make it easier to compensate for tilt that arises from buffer and other delays in clock signal distribution.

[53] In an implementation, the clock signal is distributed by a board controller buffer to corresponding subarray controller buffers in the same way as the clock signal is distributed among the board controller buffers. For example, the clock signal can be received by a first subarray controller buffer and be distributed substantially at the same time to second and third subarray controller buffers, where the second subarray controller buffer is horizontally adjacent to the first subarray controller buffer and the third subarray controller buffer is vertically adjacent to the first subarray controller buffer. Each of the second and third subarray controller buffers can further distribute the clock signal as the second and third board controllers distribute the clock signal. [54] Similarly, a subarray controller buffer can distribute the clock signal to corresponding tile controllers. This can be done in the same way at the tile controller buffer level as described above for the subarray controller buffers and for the board controller buffers.

[55] Any suitable hierarchy can be used to distribute a clock signal in accordance with the disclosed subject matter. For example, in an implementation, the clock signal can be distributed as shown in Figure 7 directly to subarray controller buffers. In such a case, there may or may not be a board controller level. Likewise, the clock signal can be similarly distributed directly to tile controller buffers. In that case, there may or may not be subarray or board level controllers. If there are only tile controllers, the hierarchy can have only a single level.

[56] Known or measured buffer delays in distributing the clock signal can be used to determine clock skew. Determined clock skew can be used to determine tilt in beam steering caused by the buffer delays. Steering commands to the system can be changed to compensate for the determined tilt. For example, if the determined tilt includes a -3 degree tilt in azimuth, then the steering commands can be adjusted to add a +3 degree change in azimuthal beam direction when steering the beam from the transmitter to the receiver.

[57] Implementations of the presently disclosed subject matter may be implemented in and used with a variety of component and network architectures. Figure 8 is an example computer 20 suitable for implementations of the presently disclosed subject matter. The computer 20 includes a bus 21 which interconnects major components of the computer 20, such as a central processor 24, a memory 27 (typically RAM, but which may also include ROM, flash RAM, or the like), an input/output controller 28, a user display 22, such as a display screen via a display adapter, a user input interface 26, which may include one or more controllers and associated user input devices such as a keyboard, mouse, and the like, and may be closely coupled to the I/O controller 28, fixed storage 23, such as a hard drive, flash storage, Fibre Channel network, SAN device, SCSI device, and the like, and a removable media component 25 operative to control and receive an optical disk, flash drive, and the like.

[58] The bus 21 allows data communication between the central processor 24 and the memory 27, which may include read-only memory (ROM) or flash memory (neither shown), and random access memory (RAM) (not shown), as previously noted. The RAM is generally the main memory into which the operating system and application programs are loaded. The ROM or flash memory can contain, among other code, the Basic Input-Output system (BIOS) that controls basic hardware operation such as the interaction with peripheral components.

Applications resident with the computer 20 are generally stored on and accessed via a computer readable medium, such as a hard disk drive (e.g., fixed storage 23), an optical drive, floppy disk, or other storage medium 25. The bus 21 also allows communication between the central processor 24 and the ultrasonic transducer 38. For example, data can be transmitted from the processor 24 to a waveform generator subsystem (not shown) to form the control signal that can drive the ultrasonic transducer 39.

[59] The fixed storage 23 may be integral with the computer 20 or may be separate and accessed through other interfaces. A network interface 29 may provide a direct connection to a remote server via a telephone link, to the Internet via an Internet service provider (ISP), or a direct connection to a remote server via a direct network link to the Internet via a POP (point of presence) or other technique. The network interface 29 may provide such connection using wireless techniques, including digital cellular telephone connection, Cellular Digital Packet Data (CDPD) connection, digital satellite data connection or the like. For example, the network interface 29 may allow the computer to communicate with other computers via one or more local, wide-area, or other networks, as shown in Figure 9.

[60] Many other devices or components (not shown) may be connected in a similar manner. Conversely, all of the components shown in Figure 8 need not be present to practice the present disclosure. The components can be interconnected in different ways from that shown. The operation of a computer such as that shown in Figure 8 is readily known in the art and is not discussed in detail in this application. Code to implement the present disclosure can be stored in computer-readable storage media such as one or more of the memory 27, fixed storage 23, removable media 25, or on a remote storage location. For example, such code can be used to provide the waveform and other aspects of the control signal that drives a flexure.

[61] Figure 9 shows an example network arrangement according to an implementation of the disclosed subject matter. One or more clients 10, 11, such as local computers, smart phones, tablet computing devices, and the like may connect to other devices via one or more networks 7. The network may be a local network, wide-area network, the Internet, or any other suitable communication network or networks, and may be implemented on any suitable platform including wired and/or wireless networks. The clients may communicate with one or more servers 13 and/or databases 15. The devices may be directly accessible by the clients 10, 11, or one or more other devices may provide intermediary access such as where a server 13 provides access to resources stored in a database 15. The clients 10, 11 also may access remote platforms 17 or services provided by remote platforms 17 such as cloud computing arrangements and services. The remote platform 17 may include one or more servers 13 and/or databases 15.

[62] More generally, various implementations of the presently disclosed subject matter may include or be implemented in the form of computer-implemented processes and apparatuses for practicing those processes. Implementations also may be implemented in the form of a computer program product having computer program code containing instructions implemented in non-transitory and/or tangible media, such as floppy diskettes, CD-ROMs, hard drives, USB (universal serial bus) drives, or any other machine readable storage medium, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing implementations of the disclosed subject matter. Implementations also may be implemented in the form of computer program code, for example, whether stored in a storage medium, loaded into and/or executed by a computer, or transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation, wherein when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing implementations of the disclosed subject matter. When implemented on a general-purpose microprocessor, the computer program code segments configure the microprocessor to create specific logic circuits. In some configurations, a set of computer-readable instructions stored on a computer-readable storage medium may be implemented by a general-purpose processor, which may transform the general-purpose processor or a device containing the general-purpose processor into a special- purpose device configured to implement or carry out the instructions. Implementations may be implemented using hardware that may include a processor, such as a general purpose

microprocessor and/or an Application Specific Integrated Circuit (ASIC) that implements all or part of the techniques according to implementations of the disclosed subject matter in hardware and/or firmware. The processor may be coupled to memory, such as RAM, ROM, flash memory, a hard disk or any other device capable of storing electronic information. The memory may store instructions adapted to be executed by the processor to perform the techniques according to implementations of the disclosed subject matter.

[63] The foregoing description, for purpose of explanation, has been described with reference to specific implementations. However, the illustrative discussions above are not intended to be exhaustive or to limit implementations of the disclosed subject matter to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The implementations were chosen and described in order to explain the principles of implementations of the disclosed subject matter and their practical applications, to thereby enable others skilled in the art to utilize those implementations as well as various

implementations with various modifications as may be suited to the particular use contemplated.

Claims

1. A device, comprising:

a membrane;

a container having a base and at least one wall element, the at least one wall element situated over at least part of the base to form a cavity having an least partially open end, the at least partially open end of the cavity substantially sealed with the membrane; and

a piezoelectric flexure having a first end and a second end, the first end of the flexure fixed at a location at the at least one wall element, the second end of the flexure in mechanical communication with the membrane.

2. The device of claim 1, wherein the membrane is mono crystalline silicon.

3. The device of claim 1, wherein the membrane has an upper part and a lower part and further comprising a stiffener element having an first side and a second side, the first side of the stiffener fixed to at least a portion the lower part of the membrane and the second side of the stiffener in mechanical communication with the second end of the flexure.

4. The device of claim 1, wherein the piezoelectric flexure comprises a substrate layer, an electrode layer and a piezoelectric material disposed at least partly between the substrate and the electrode layer.

5. The device of claim 1, wherein the piezoelectric flexure comprises a first electrode layer disposed over at least part of a first piezoelectric material disposed at least partly over a substrate material, disposed at least partly over a second piezoelectric material disposed at least partly over a second electrode.

6. The device of claim 1, wherein the piezoelectric material is a thin film piezoelectric material.

7. The device of claim 1, wherein the cavity encloses a region having a pressure lower than ambient pressure.

8. The device of claim 1, wherein the at least one wall element comprises a first part and a second part, the first part electrically connected to the electrode of the flexure and the second part electrically connected to the substrate of the flexure.

9. The device of claim 1, wherein the membrane is electrically connected to the electrode of the flexure.

10. The device of claim 1, further comprising a control signal source electrically connected to the electrode of the flexure.

11. The device of claim 8, further comprising a control signal source electrically connected to at least the first part of the wall element.

12. The device of claim 8, further comprising a control signal source electrically connected to at least the second part of the wall element.

13. A circuit, comprising :

an ultrasonic transducer having a driver side and a bias voltage side;

a higher voltage source electrically connected to the bias voltage side of the ultrasonic transducer through a first resistor; a lower voltage source electrically connected to the driver side of the ultrasonic transducer through a second resistor; and

a switch having a source, a gate and a drain, the source electrically connected to ground, the gate electrically connected to a control signal source, the drain electrically connected to the lower voltage source through the first resistor and electrically connected to the driver side of the ultrasonic transducer.

14. The circuit of claim 13, wherein the switch is a field effect transistor.

15. The circuit of claim 13, wherein the first resistor has a resistance of between 2kilo-ohms and 5mega-ohms and the higher voltage source has a voltage of between 200 volts and 1000 volts.

16. The circuit of claim 13, wherein the second resistor has a resistance of between 200 kilo- ohms and 500 kilo-ohms and the lower voltage source has a range of between 10 volts and 120 volts.

17. The circuit of claim 13, wherein the ultrasonic transducer is a capacitive micromachined ultrasonic transducer.

18. The circuit of claim 13, further comprising a third resistor and wherein the gate is electrically connected to the control signal source through the third resistor.

19. The circuit of claim 18, wherein the third resistor is adapted and configured to limit the current at the gate of to between 100 ohms and 10 kilo-ohms.

20. The circuit of claim 13, wherein the first resistor is adapted and configured to limit the current at the high voltage side of the ultrasonic transducer to between 20mA and 500 niA in response to changes in voltage at the bias voltage side from zero volts to between 200 volts and 1000 volts.

21. A system, comprising :

a first controller having 8 available first controller output lines comprising a first subset of 4 first controller output lines;

a second controller having 4 second controller input lines and 16 second controller output lines, the 16 second controller output lines electrically connected to a first set of ultrasonic transducers;

the first controller adapted and configured to receive a 16-bit ultrasonic transducer control signal, separate the 16-bit ultrasonic transducer control signal into four 4-bit intermediate ultrasonic transducer control signals and send each of the 4-bit intermediate ultrasonic transducer control signals to the second controller through the first subset of 4 output lines; and

the second controller adapted and configured to receive each of the four 4-bit

intermediate ultrasonic transducer control signals through the 4 second controller input lines, to reassemble the 16 bit ultrasonic transducer control signal based on the received four 4-bit intermediate ultrasonic transducer control signals and to send the 16-bit ultrasonic transducer control signal through the 16 second controller output lines to the first set of ultrasonic transducers.

22. The system of claim 21, wherein each of the 4 first controller output lines transports one bit of the 4-bit intermediate ultrasonic transducer control signal to the second controller.

23. The system of claim 21, wherein each of the 16 second controller output lines transport one bit of the 16-bit ultrasonic transducer control signal to one of the first set of ultrasonic transducers.

24. The system of claim 21, wherein the ultrasonic transducers are Capacitive

Micromachined Ultrasonic Transducers.

25. The system of claim 21, wherein the ultrasonic transducers are comprised of a

piezoelectric flexure in communication with a membrane.

26. The system of claim 21, further comprising:

a second subset of 4 first controller output lines;

a third controller having 4 third controller input lines and 16 third controller output lines, each of the 16 second controller output lines electrically connected to each of a second set of ultrasonic transducers;

the first controller adapted and configured to receive a second 16-bit ultrasonic transducer control signal, separate the second 16-bit ultrasonic transducer control signal into four second 4- bit intermediate ultrasonic transducer control signals and send each of the second 4-bit intermediate ultrasonic transducer control signals to the third controller through the second subset of 4 output lines; and

the third controller adapted and configured to receive each of the four 4-bit intermediate ultrasonic transducer control signals through the 4 third controller input lines, to reassemble the second 16 bit ultrasonic transducer control signal based on the received second four 4-bit intermediate ultrasonic transducer control signals and to send the second 16-bit ultrasonic transducer control signal through the 16 third controller output lines to the second set of ultrasonic transducers.

27. A system, comprising:

a first controller having 2^a available first controller output lines comprising a first subset of 2^b first controller output lines, where a > b;

a second controller having 2^b second controller input lines and 2° second controller output lines, where b < c and each of the 2° second controller output lines is electrically connected to a first set of ultrasonic transducers;

the first controller adapted and configured to receive a 2^c-bit ultrasonic transducer control signal, separate the 2^c-bit ultrasonic transducer control signal into (c-b) 2^b-bit intermediate ultrasonic transducer control signals and send each of the 2^b-bit intermediate ultrasonic transducer control signals to the second controller through the first subset of 2^b output lines; and the second controller adapted and configured to receive each of the (c-b) 2^b-bit intermediate ultrasonic transducer control signals through the 2^b second controller input lines, to reassemble the 2° bit ultrasonic transducer control signal based on the received (c-b) 2^b-bit intermediate ultrasonic transducer control signals and to send the 2^c-bit ultrasonic transducer control signal through the 2° second controller output lines to the first set of ultrasonic transducers.

28. A method, comprising:

receiving a clock signal at a first board controller buffer of a plurality of board controller buffers; and

receiving the clock signal received at the first board controller buffer at a second board controller buffer and a third board controller buffer at substantially the same time from the first board controller buffer, the second board controller buffer being horizontally adjacent to the first board controller buffer and the third board controller buffer being vertically adjacent to the first board controller buffer.

29. The method of claim 28, wherein the second board controller buffer has not yet received the clock signal at the time it receives the clock signal from the first board controller buffer.

30. The method of claim 28, wherein the third board controller buffer has not yet received the clock signal at the time it receives the clock signal from the first board controller buffer.

31. The method of claim 28, further comprising receiving at substantially the same time the clock signal from the first board controller buffer at a plurality of subarray controller buffers corresponding to the first controller buffer.

32. The method of claim 31 , further comprising receiving at substantially the same time the clock signal from the first subarray controller buffer at a plurality of tile controller buffers corresponding to the first controller buffer.

33. The method of claim 28, further comprising receiving the clock signal received at the first board controller buffer at a first subarray controller buffer; and

receiving the clock signal at a second and a third subarray controller buffer at

substantially the same time from the first subarray controller buffer, the second subarray buffer being horizontally adjacent to the first subarray controller buffer and the third subarray controller buffer being vertically adjacent to the first subarray controller buffer.

34. The method of claim 33, further comprising receiving the clock signal received at the first subarray controller buffer at a first tile controller buffer; and

receiving the clock signal at a second and a third tile controller buffer at substantially the same time from the first tile controller buffer, the second tile controller buffer being horizontally adjacent to the first tile control buffer and the third tile controller buffer being vertically adjacent to the first subarray controller buffer.

35. The method of claim 28, further comprising determining a clock skew.

36. The method of claim 35, further comprising determining a tilt based on the determined clock skew.

37. The method of claim 36, further comprising correcting a beam steering command based on the determined tilt.

38. A system, comprising:

a plurality of buffers;

a clock signal generator; and

a computer-implemented clock signal distributor that sends a clock signal from a first buffer of the plurality of buffers at substantially the same time to a second buffer and third buffer, the second buffer being horizontally adjacent to the first buffer and the third board buffer being vertically adjacent to the first buffer.

39. A system, comprising: a first set of ultrasonic transducers, each ultrasonic transducer comprising:

a membrane,

a container having a base and at least one wall element, the at least one wall element situated over at least part of the base to form a cavity having an least partially open end, the at least partially open end of the cavity substantially sealed with the membrane,

a piezoelectric fiexure having a first end and a second end, the first end of the flexure fixed at a location at the at least one wall element, the second end of the flexure in mechanical communication with the membrane, and

a driver side and a bias voltage side;

a circuit for each ultrasonic transducer, each circuit comprising:

a higher voltage source electrically connected to the bias voltage side of the ultrasonic transducer through a first resistor,

a lower voltage source electrically connected to the driver side of the ultrasonic transducer through a second resistor, and

a switch having a source, a gate and a drain, the source electrically connected to ground, the gate electrically connected to a control signal source, the drain electrically connected to the lower voltage source through the first resistor and electrically connected to the driver side of the ultrasonic transducer;

a second controller having 4 second controller input lines and 16 second controller output lines, the 16 second controller output lines electrically connected to the first set of ultrasonic transducers,

the first controller adapted and configured to receive a 16-bit ultrasonic transducer control signal, separate the 16-bit ultrasonic transducer control signal into four 4-bit intermediate ultrasonic transducer control signals and send each of the 4-bit intermediate ultrasonic transducer control signals to the second controller through the first subset of 4 output lines, and

the second controller adapted and configured to receive each of the four 4-bit

intermediate ultrasonic transducer control signals through the 4 second controller input lines, to reassemble the 16 bit ultrasonic transducer control signal based on the received four 4-bit intermediate ultrasonic transducer control signals and to send the 16-bit ultrasonic transducer control signal through the 16 second controller output lines to the first set of ultrasonic transducers;

a plurality of buffers;

a clock signal generator; and