WO2014132861A1 - Semiconductor chip - Google Patents

Semiconductor chip Download PDF

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Publication number
WO2014132861A1
WO2014132861A1 PCT/JP2014/053916 JP2014053916W WO2014132861A1 WO 2014132861 A1 WO2014132861 A1 WO 2014132861A1 JP 2014053916 W JP2014053916 W JP 2014053916W WO 2014132861 A1 WO2014132861 A1 WO 2014132861A1
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Prior art keywords
power supply
resistance
semiconductor chip
input
wiring
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PCT/JP2014/053916
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French (fr)
Japanese (ja)
Inventor
秀則 戸堀
久之 長峰
Original Assignee
ピーエスフォー ルクスコ エスエイアールエル
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Publication of WO2014132861A1 publication Critical patent/WO2014132861A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals

Definitions

  • the present invention relates to a semiconductor chip.
  • a semiconductor chip such as a semiconductor memory has an input / output circuit for inputting / outputting signals to / from the outside.
  • Such an input / output circuit is arranged between a power supply wiring and a ground (GND) wiring, and is supplied with power through these wirings to receive a signal from the outside of the semiconductor chip and transmit a signal to the outside of the semiconductor chip. It can be performed.
  • Such an input / output circuit is composed of an input circuit and an output circuit.
  • an output buffer constituting the output circuit of the input / output circuit is provided. Since a plurality of operations are performed, the potential difference between the power supply wiring and the GND wiring may fluctuate due to noise caused by the operation of the output buffer.
  • Patent Document 1 Japanese Patent Laid-Open No. 2011-233765
  • Patent Document 2 Japanese Patent Laid-Open No. 2010-67661
  • Patent Document 3 Japanese Patent Laid-Open No. 2006-253393 disclose power supply wiring and GND wiring. Disclosed is a technique for suppressing potential fluctuation between wirings by arranging a compensation capacitor between them.
  • a semiconductor chip is sealed (packaged) in a package composed of a sealing material such as resin or ceramic and wiring that connects the semiconductor chip to the outside.
  • a method of packaging a semiconductor chip a method of connecting a corresponding terminal of one semiconductor chip to one terminal of the package, and a method of connecting corresponding terminals of a plurality of semiconductor chips to one terminal of the package.
  • packaging methods such as a method (DDP: Dual Die Package).
  • the compensation capacitance of the semiconductor chip is sufficiently suppressed so that output signal noise is sufficiently suppressed before packaging.
  • the noise of the output signal may not be sufficiently suppressed when the semiconductor chip is packaged.
  • the semiconductor chip of the present invention is An input / output circuit; First and second power supply lines for supplying an operating voltage to the input / output circuit; Between the first power supply wiring and the second power supply wiring, a capacitive element and a resistance portion provided in series are provided, The resistance value of the resistance portion can be changed.
  • noise included in the output signal can be reduced.
  • FIG. 4B It is a figure which shows schematic structure of a general semiconductor chip. It is a schematic block diagram of the input / output block which comprises the input / output part shown in FIG. It is a figure which shows an example of the layout of the input-output part shown in FIG. It is a figure which shows another example of the layout of the input-output part shown in FIG. It is a figure which shows another example of the layout of the input-output part shown in FIG. It is a schematic block diagram of a general semiconductor chip. It is a schematic block diagram of the semiconductor chip in one Embodiment of this invention. It is a figure which shows an example of the layout on the board
  • FIG. 1 is a diagram showing a schematic configuration of a general semiconductor chip 100.
  • the semiconductor chip 100 is assumed to be a semiconductor memory.
  • the semiconductor chip 100 includes a memory cell array 101, an internal voltage generation circuit 103, an X decoder 104, a Y decoder 105, an X control circuit 106, a Y control circuit 107, an input / output unit 109, a compensation capacitor 110, Have
  • the memory cell array 101 includes a plurality of word lines WL and a plurality of bit lines BL.
  • a memory cell 102 is formed at the intersection of each word line WL and bit line BL.
  • the internal voltage generation circuit 103 transforms the voltage supplied via the power supply terminals (VCC, GND), and supplies an operating voltage to the X decoder 104, the Y decoder 105, and the input / output unit 109.
  • the X decoder 104 receives an address signal indicating the address of the memory cell 102 to be read, decodes the input address signal, and outputs the decoded address signal to the X control circuit 106.
  • the Y decoder 105 receives an address signal indicating the address of the memory cell 102 to be read, decodes the input address signal, and outputs the decoded address signal to the Y control circuit 107.
  • the X control circuit 106 selects the word line WL according to the address signal decoded by the X decoder 104. Further, the Y control circuit 107 selects the bit line BL according to the address signal decoded by the Y decoder 105. By selecting the word line WL and the bit line BL, the memory cell 102 corresponding to the address signal is selected.
  • the signal recorded in the selected memory cell 102 is read through the bit line BL and amplified by the sense amplifier circuit 108 provided in the Y control circuit 107.
  • the input / output unit 109 outputs the signal amplified by the sense amplifier circuit 108 to the outside of the semiconductor chip 100.
  • the input / output unit 109 includes a plurality of input / output blocks which are functional units related to input / output, which will be described later.
  • the compensation capacitor 110 is disposed between the GND terminal and the power supply wiring that supplies the operating voltage from the internal voltage generation circuit 103 to the X decoder 104, the Y decoder 105, and the input / output unit 109.
  • the compensation capacitor 110 suppresses fluctuations in the operating voltage supplied to the X decoder 104, the Y decoder 105, and the input / output unit 109.
  • FIG. 2 is a diagram showing a schematic configuration of an input / output block constituting the input / output unit 109.
  • the input / output unit 109 includes an input / output block 206 and an input / output block 207, and the input / output block 206 and the input / output block 207 are equally and repeatedly arranged.
  • the input / output block 206 includes a VSSQ PAD 201, a DQ PAD 203, an input / output circuit 204, and a compensation capacitor 205.
  • the input / output block 207 includes a VDDQ PAD 202, a DQ PAD 203, an input / output circuit 204, and a compensation capacitor 205.
  • the VSSQ PAD 201 is connected to an internal voltage generation circuit 103 (not shown in FIG. 2), and is supplied with the potential VSSQ.
  • the VSSQ PAD 201 is connected to a power supply line VSSQ as a first power supply line. Therefore, the potential of the power supply line VSSQ becomes the potential VSSQ.
  • the potential VSSQ is, for example, a ground potential.
  • the VDDQ PAD 202 is connected to an internal voltage generation circuit 103 (not shown in FIG. 2) and is supplied with the potential VDDQ. Further, the VDDQ PAD 202 is connected to a power supply line VDDQ as a second power supply line. Therefore, the potential of the power supply line VDDQ becomes the potential VDDQ.
  • the input / output circuit 204 is connected to the power supply line VDDQ and the power supply line VSSQ, and an operating voltage is supplied through these power supply lines.
  • the input / output circuit 204 is connected to the DQ PAD 203 and inputs / outputs signals to / from the outside of the semiconductor chip 100 (not shown in FIG. 2) via the DQ PAD 203.
  • the compensation capacitor 205 is disposed between the power supply line VSSQ and the power supply line VDDQ. That is, the compensation capacitor 205 has one end connected to the power supply line VSSQ and the other end connected to the power supply line VDDQ.
  • the input / output block 206 and the input / output block 207 are repeatedly arranged. Therefore, hereinafter, the layout of one input / output circuit 204 and the corresponding VSSQ PAD 201, VDDQ PAD 202, DQ PAD 203, and compensation capacitor 205 will be described with reference to FIGS. 3A to 3C. 3A to 3C, the same reference numerals are given to the same components as those in FIG. 2, and the description thereof is omitted.
  • FIG. 3A is a diagram illustrating an example of the layout of the input / output unit 109.
  • the input / output circuit 204 is connected to each power supply PAD (VSSQ PAD201 and VDDQ PAD202) via the power supply line VSSQ and the power supply line VDDQ.
  • the compensation capacitor 205 is disposed between the power supply line VSSQ and the power supply line VDDQ.
  • protection elements 301 that absorb current between VSSQ PAD201 and power supply line VDDQ, between VDDQ PAD202 and power supply line VSSQ, between DQ PAD203 and power supply line VSSQ, and between DQ PAD203 and power supply line VDDQ, respectively. Has been placed.
  • the protection elements 301 are between the VSSQ PAD201 and the power supply line VDDQ, between the VDDQ PAD202 and the power supply line VSSQ, between the DQ PAD203 and the power supply line VSSQ, and between the DQ PAD203 and the power supply line VDDQ, respectively. Is arranged. Therefore, these protection elements 301 absorb a current exceeding the rating flowing from each power supply PAD to the input / output circuit 204, so that the possibility of ESD breakdown of the input / output circuit 204 is reduced.
  • the protection element 301 may not be able to absorb the current flowing from each power supply PAD to the input / output circuit 204. In such a case, a current that could not be absorbed by the protection element 301 flows into the input / output circuit 204 and ESD damage to the input / output circuit 204 may occur.
  • FIG. 3B is a diagram illustrating another example of the layout of the input / output unit 109.
  • the input / output circuit 204 is further connected to each power supply PAD via wirings 302 and 303, and the compensation capacitor 205 is connected to the power supply line VSSQ and The difference is that each power supply PAD is connected without going through the power supply line VDDQ.
  • the wiring length between each power supply PAD and the input / output circuit 204 is longer than the wiring length between each power supply PAD and the input / output circuit 204 shown in FIG. 3A. Therefore, the parasitic resistance of the wiring between each power supply PAD and the input / output circuit 204 is large. Therefore, the current that could not be absorbed by the protection element 301 is attenuated by the parasitic resistance, and the possibility of ESD damage of the input / output circuit 204 is reduced.
  • the compensation capacitor 205 is connected to each power supply PAD without passing through the power supply line VSSQ and the power supply line VDDQ.
  • the parasitic resistance of the wiring between each power supply PAD is small. Therefore, the current that could not be absorbed by the protection element 301 flows into the compensation capacitor 205 without being sufficiently attenuated by the parasitic resistance of the wiring between the compensation capacitor 205 and each power supply PAD. More likely to happen.
  • FIG. 3C is a diagram illustrating another example of the layout of the input / output unit 109.
  • the input / output circuit 204 is connected to each power supply PAD via wirings 302 and 303 as in FIG. 3B. Therefore, the wiring length between each power supply PAD and the input / output circuit 204 is long, and the parasitic resistance of the wiring between each power supply PAD and the input / output circuit 204 is also large. Therefore, as described with reference to FIG. 3B, the possibility of ESD destruction of the input / output circuit 204 is reduced.
  • the compensation capacitors 304 and 305 are arranged between the wiring 302 and the wiring 303.
  • the wiring 302 is connected to the power supply line VDDQ
  • the wiring 303 is connected to the power supply line VSSQ. Therefore, the compensation capacitors 304 and 305 are equivalent to those connected to each power supply PAD through the power supply line VSSQ and the power supply line VDDQ.
  • the compensation capacitor 304 is arranged using an area under each PAD (VSSQ PAD201, VDDQ PAD202, and DQ PAD203) (the direction opposite to the stacking direction in the semiconductor chip 100).
  • the compensation capacitor 305 is disposed in the vicinity of the input / output circuit 104.
  • the wiring length between the compensation capacitors 304 and 305 and each power supply PAD is longer than the wiring length between the compensation capacitor 205 and each power supply PAD shown in FIGS. 3A and 3B. Therefore, the parasitic resistance of the wiring between the compensation capacitors 304 and 305 and each power supply PAD is also large. Therefore, the current that could not be absorbed by the protection element 301 is attenuated by the parasitic resistance, the inflow into the compensation capacitors 304 and 305 is suppressed, and the possibility that the ESD destruction of the compensation capacitors 304 and 305 occurs is reduced.
  • FIG. 4A a schematic configuration of a general semiconductor chip is shown in FIG. 4A. Since the present invention mainly aims to reduce noise included in the signal output from the input / output circuit, only the configuration in the vicinity of the input / output circuit is shown, and the description of the configuration of other parts is omitted. .
  • FIG. 4A is a diagram showing a configuration of a main part of a semiconductor chip having an input / output unit whose layout is shown in FIG. 3C.
  • a compensation capacitor 304 as a first compensation capacitor and a compensation capacitor 305 as a second compensation capacitor are arranged between the power supply line VSSQ and the power supply line VDDQ, respectively.
  • each of the compensation capacitors 304 and 305 has one end connected to the power supply line VSSQ and the other end connected to the power supply line VDDQ.
  • the compensation capacitor 304 is arranged so that the wiring length between the compensation capacitor 304 and the input / output circuit 204 is longer than that of the compensation capacitor 305.
  • FIG. 4B is a diagram showing a main configuration of a semiconductor chip according to an embodiment of the present invention.
  • the same components as those in FIG. 4A are denoted by the same reference numerals, and description thereof is omitted.
  • FIG. 4B is different from the semiconductor chip 400A shown in FIG. 4A in that a resistor 401 is added.
  • the resistance value of the resistance unit 401 can be changed, one end is connected to the power supply line VDDQ, and the other end is connected to the other end of the compensation capacitor 304.
  • the inventors of the present application have a greater effect of reducing noise as the capacitance value of the compensation capacitor is larger.
  • the capacitance value of the compensation capacitor exceeds a certain value, the effect of noise reduction is increased. Revealed that saturates. Therefore, noise is not sufficiently reduced only by changing the capacitance values of the compensation capacitors 304 and 305.
  • the inventors of the present application have clarified that the effect of reducing noise in the output signal is higher when the resistance value between the compensation capacitor and the input / output circuit 204 is smaller.
  • the compensation capacitor 305 has a shorter wiring length with the input / output circuit 204 than the compensation capacitor 304. Therefore, the parasitic resistance of the wiring between the compensation capacitor 305 and the input / output circuit 204 is smaller than the parasitic resistance of the wiring between the compensation capacitor 304 and the input / output circuit 204. For this reason, in this embodiment, the compensation capacitor 305 is not added with a resistance portion and is kept at a low resistance, so that the effect of reducing noise is kept high, and the compensation capacitor 304 has a resistance. Section 401 has been added.
  • the inventors of the present application have a combination of a resistance value of the resistance portion and a capacitance value of the compensation capacitor that has a high effect of reducing noise, and the combination depends on the package method, the wiring pattern, and the driving frequency of the semiconductor chip. Revealed different things. Therefore, in the present embodiment, by making the resistance value of the resistance unit 401 variable, noise in the output signal of the semiconductor chip 400 can be reduced with respect to various package methods, wiring patterns, and semiconductor chip drive frequencies. did.
  • a compensation capacitor having various capacitance values and resistance elements having various resistance values are arranged, and a combination having high noise reduction effect is made by selectively connecting them.
  • FIG. 5 is a diagram showing an example of the layout on the substrate of the semiconductor chip shown in FIG. 4B.
  • the same components as those in FIG. 4B are denoted by the same reference numerals, and description thereof is omitted.
  • FIG. 5 only the wirings related to the present invention are shown, and the description of wirings and other configurations not directly related to the present invention is omitted.
  • the circuit 501 is various circuits other than the input / output circuit constituting the semiconductor chip 400.
  • VSSQ PAD201 As described above, VSSQ PAD201, VDDQ PAD202, and DQ PAD203 are repeatedly arranged on the substrate. In FIG. 5, description of VSSQ PAD201 is omitted.
  • the input / output circuit 204 is divided into an output circuit 204A and an input circuit 204B and arranged on the substrate. In FIG. 5, only the wiring related to the output circuit 204A is shown, and the wiring related to the input circuit 204B is omitted.
  • the protection circuit 301 is arranged in the vicinity of the VDDQ PAD 202 and the DQ PAD 203.
  • the compensation capacitor 304 is arranged using the area under VDDQ PAD202 and DQ PAD203.
  • the compensation capacitor 305 is disposed in the vicinity of the output circuit 204B. Therefore, the compensation capacitor 304 is disposed so that the wiring length between the compensation capacitor 304 and the input / output circuit 204 is longer than that of the compensation capacitor 305.
  • the resistance unit 401 is provided on the wiring between the power supply line VDDQ connected to the output circuit 204A and the compensation capacitor 304.
  • the semiconductor chip 400 includes the capacitive element 304 provided between the power supply line VSSQ and the power supply line VDDQ that supplies the operating voltage to the input / output circuit, and the capacitive element 304 in series. And a resistance portion 401 whose resistance value can be changed.
  • noise in the output signal of the semiconductor chip 400 can be reduced.
  • FIG. 6 is a schematic configuration diagram of the semiconductor chip 600 according to the first embodiment of the present invention.
  • the same components as those in FIG. 4A are denoted by the same reference numerals, and description thereof is omitted.
  • variable resistance element 601 whose resistance value can be changed is provided as the resistance portion 401.
  • Noise in the output signal of the semiconductor chip 600 is reduced by adjusting the resistance value of the variable resistance element 601 and changing the resistance value of the resistance unit 401 according to the package method, wiring pattern, and driving frequency of the semiconductor chip. be able to.
  • a value for adjusting the resistance value of the variable resistance element 601 may be stored in a register in the semiconductor chip in a volatile or non-volatile manner, or may be supplied from the outside of the semiconductor chip.
  • FIG. 7 is a schematic configuration diagram of a semiconductor chip in the second embodiment of the present invention.
  • the same components as those in FIG. 4A are denoted by the same reference numerals, and description thereof is omitted.
  • a plurality of resistance elements 701 are provided as the resistance portion 401.
  • the plurality of resistance elements 701 are connected in series.
  • the wiring pattern between the plurality of resistance elements 701 can be changed by the master slice method.
  • the resistance value of the resistance portion 401 can be changed.
  • the resistance value of the resistance unit 401 can be finely changed by setting the resistance values of the plurality of resistance elements 701 to different values that change with a power of 2 ratio (1, 2, 4, 8). .
  • FIG. 8 is a diagram for explaining a method of changing the resistance value of the resistance unit 401 including the plurality of resistance elements 701 shown in FIG.
  • the resistance unit 401 includes a resistance element 701A having a resistance value of 1 ohm, a 701B having a resistance value of 2 ohms, a 701C having a resistance value of 4 ohms, and a 701D having a resistance value of 8 ohms.
  • Resistance elements 701A to 701D are formed by using the same tungsten wiring as the wiring constituting the gate electrode of the memory cell. Each resistive element is connected by using an upper metal wiring layer such as copper or aluminum connected to the resistive elements 701A to 701D via contacts. Therefore, the resistance value can be changed by changing the wiring pattern of the metal wiring layer.
  • One end of the resistance element 701A is connected to the other end of the compensation capacitor 304 (not shown in FIG. 8) at the connection point 801, and the other end is connected to one end of the resistance element 701B at the connection point 802.
  • Resistance element 701B has one end connected to the other end of resistance element 701A at connection point 802, and the other end connected to one end of resistance element 701C at connection point 803.
  • Resistance element 701C has one end connected to the other end of resistance element 701B at connection point 803, and the other end connected to one end of resistance element 701D at connection point 804.
  • the resistance element 701D has one end connected to the other end of the resistance element 701C at a connection point 804, and the other end connected to a power supply line VDDQ (not shown in FIG. 8) at a connection point 805.
  • the resistance elements from the resistance element 701A to the resistance element 701D are connected in series. Therefore, when all the resistance elements from the resistance element 701A to the resistance element 701D are connected, the resistance value of the resistance unit 401 is 15 ohms.
  • the resistance value of the resistance unit 401 becomes 13 ohms. In this manner, the resistance value of the resistance unit 401 becomes a predetermined value by short-circuiting the connection points of the respective resistance elements.
  • FIG. 9 is a schematic configuration diagram of a semiconductor chip in the third embodiment of the present invention.
  • the same components as those in FIG. 4A are denoted by the same reference numerals, and description thereof is omitted.
  • a plurality of resistance elements 901 a plurality of MOS (Metal Oxide Semiconductor) switches 902 provided corresponding to each of the plurality of resistance elements 901, and a control Block 903 is provided.
  • MOS Metal Oxide Semiconductor
  • the plurality of resistance elements 901 are connected in series.
  • Each of the plurality of MOS switches 902 is connected in parallel with the corresponding resistance element 901.
  • the MOS switch 902 is turned on, the resistance element 901 corresponding to the MOS switch 902 is short-circuited, and the resistance value of the resistance unit 401 is changed.
  • the MOS switch 902 is operated by changing the voltage applied to the MOS switch 902 using a fuse (FUSE), a bonding option (BOP), or the like.
  • the control block 903 may be configured to generate a control signal for operating the MOS switch 902 according to an input from the outside, or may be configured to generate a control signal based on a value stored in a nonvolatile manner. You may do it.
  • the MOS switch 902 is controlled to be turned on and off according to the package method, the wiring pattern, and the driving frequency of the semiconductor chip, and the resistance value of the resistance unit 401 is changed. Noise can be reduced.
  • the present invention can also be applied to an external clock input unit, a buffer unit having a large number of simultaneous operations, a logic unit for generating an internal clock, and the like.
  • the present invention can achieve the same effect when applied to many semiconductors such as a DRAM (Dynamic Random Access Memory), a flash memory, and a logic circuit.
  • DRAM Dynamic Random Access Memory

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Provided is a semiconductor chip comprising: an input/output circuit; first and second power supply lines that supply operating voltage to the input/output circuit; and a capacitance element and a resistor that are provided in series between the first power supply line and the second power supply line.

Description

半導体チップSemiconductor chip
　本発明は半導体チップに関する。 The present invention relates to a semiconductor chip.
　一般に、半導体メモリのような半導体チップは、外部との間の信号の入出力を行う入出力回路を備えている。このような入出力回路は、電源配線とグランド（ＧＮＤ）配線との間に配置され、これらの配線を介して給電され、半導体チップ外部からの信号の受信や、半導体チップ外部への信号の送信を行うことができる。このような入出力回路は、入力回路と出力回路とによって構成されており、半導体メモリのように同時に複数のデータを出力する場合には、例えば、入出力回路の出力回路を構成する出力バッファが複数動作するため、当該出力バッファの動作に起因するノイズなどにより電源配線とＧＮＤ配線との電位差が変動することがある。 Generally, a semiconductor chip such as a semiconductor memory has an input / output circuit for inputting / outputting signals to / from the outside. Such an input / output circuit is arranged between a power supply wiring and a ground (GND) wiring, and is supplied with power through these wirings to receive a signal from the outside of the semiconductor chip and transmit a signal to the outside of the semiconductor chip. It can be performed. Such an input / output circuit is composed of an input circuit and an output circuit. When a plurality of data are output simultaneously as in a semiconductor memory, for example, an output buffer constituting the output circuit of the input / output circuit is provided. Since a plurality of operations are performed, the potential difference between the power supply wiring and the GND wiring may fluctuate due to noise caused by the operation of the output buffer.
　そこで、特許文献１（特開２０１１－２３３７６５号公報）、特許文献２（特開２０１０－６７６６１号公報）、および、特許文献３（特開２００６－２５３３９３号公報）には、電源配線とＧＮＤ配線との間に補償容量を配置することで、配線間の電位変動を抑制する技術が開示されている。 Therefore, Patent Document 1 (Japanese Patent Laid-Open No. 2011-233765), Patent Document 2 (Japanese Patent Laid-Open No. 2010-67661), and Patent Document 3 (Japanese Patent Laid-Open No. 2006-253393) disclose power supply wiring and GND wiring. Disclosed is a technique for suppressing potential fluctuation between wirings by arranging a compensation capacitor between them.
特開２０１１－２３３７６５号公報JP 2011-233765 A 特開２０１０－６７６６１号公報JP 2010-67661 A 特開２００６－２５３３９３号公報JP 2006-253393 A
　一般に、半導体チップは、樹脂やセラミックなどの封止材と半導体チップを外部と接続する配線とで構成されるパッケージに封入される（パッケージ化される）。 Generally, a semiconductor chip is sealed (packaged) in a package composed of a sealing material such as resin or ceramic and wiring that connects the semiconductor chip to the outside.
　ここで、半導体チップのパッケージ化の方法としては、パッケージの１端子に１つの半導体チップの対応する端子が接続される方法、および、パッケージの１端子に複数の半導体チップの対応する端子が接続される方法（ＤＤＰ：Ｄｕａｌ　Ｄｉｅ　Ｐａｃｋａｇｅ）など、様々なパッケージ方法がある。 Here, as a method of packaging a semiconductor chip, a method of connecting a corresponding terminal of one semiconductor chip to one terminal of the package, and a method of connecting corresponding terminals of a plurality of semiconductor chips to one terminal of the package. There are various packaging methods such as a method (DDP: Dual Die Package).
　本願発明者らは、種々のシミュレーションを行った結果、同じ半導体チップを用いた場合であっても、パッケージの方法や配線パターンに応じて出力信号に含まれるノイズを十分に低減することができる補償容量の最適値が変わることを明らかにした。 As a result of various simulations, the inventors of the present application have compensated for sufficiently reducing noise included in the output signal according to the package method and wiring pattern even when the same semiconductor chip is used. It was clarified that the optimum value of capacity changes.
　すなわち、上述したようなパッケージの方法や配線パターンに応じた補償容量の最適値の変動のために、パッケージ化する前の段階で出力信号のノイズが十分に抑制されるように半導体チップの補償容量を調整しても、その半導体チップをパッケージ化した段階では、出力信号のノイズが十分に抑制されないことがあるという問題がある。 In other words, due to fluctuations in the optimum value of the compensation capacitance in accordance with the packaging method and wiring pattern as described above, the compensation capacitance of the semiconductor chip is sufficiently suppressed so that output signal noise is sufficiently suppressed before packaging. However, there is a problem that the noise of the output signal may not be sufficiently suppressed when the semiconductor chip is packaged.
　本発明の半導体チップは、
　入出力回路と、
　前記入出力回路に動作電圧を供給する第１および第２の電源配線と、
　前記第１の電源配線と前記第２の電源配線との間に、直列に設けられた容量素子と抵抗部と、を有し、
　前記抵抗部は抵抗値が変更可能である。 The semiconductor chip of the present invention is
An input / output circuit;
First and second power supply lines for supplying an operating voltage to the input / output circuit;
Between the first power supply wiring and the second power supply wiring, a capacitive element and a resistance portion provided in series are provided,
The resistance value of the resistance portion can be changed.
　本発明によれば、出力信号に含まれるノイズを低減することができる。 According to the present invention, noise included in the output signal can be reduced.
一般的な半導体チップの概略構成を示す図である。It is a figure which shows schematic structure of a general semiconductor chip. 図１に示す入出力部を構成する入出力ブロックの概略構成図である。It is a schematic block diagram of the input / output block which comprises the input / output part shown in FIG. 図１に示す入出力部のレイアウトの一例を示す図である。It is a figure which shows an example of the layout of the input-output part shown in FIG. 図１に示す入出力部のレイアウトの他の一例を示す図である。It is a figure which shows another example of the layout of the input-output part shown in FIG. 図１に示す入出力部のレイアウトの別の一例を示す図である。It is a figure which shows another example of the layout of the input-output part shown in FIG. 一般的な半導体チップの概略構成図である。It is a schematic block diagram of a general semiconductor chip. 本発明の一実施形態における半導体チップの概略構成図である。It is a schematic block diagram of the semiconductor chip in one Embodiment of this invention. 図４Ｂに示す半導体チップの基板上のレイアウトの一例を示す図である。It is a figure which shows an example of the layout on the board | substrate of the semiconductor chip shown to FIG. 4B. 本発明の第１の実施例における半導体チップの概略構成図である。It is a schematic block diagram of the semiconductor chip in the 1st Example of this invention. 本発明の第２の実施例における半導体チップの概略構成図である。It is a schematic block diagram of the semiconductor chip in the 2nd Example of this invention. 図７に示す半導体チップにおける抵抗部の構成の一例を示す図である。It is a figure which shows an example of a structure of the resistance part in the semiconductor chip shown in FIG. 本発明の第３の実施例における半導体チップの概略構成図である。It is a schematic block diagram of the semiconductor chip in the 3rd Example of this invention.
（実施の形態）
　図１は、一般的な半導体チップ１００の概略構成を示す図である。なお、図１においては、半導体チップ１００は、半導体メモリであるものとする。 (Embodiment)
FIG. 1 is a diagram showing a schematic configuration of a general semiconductor chip 100. In FIG. 1, the semiconductor chip 100 is assumed to be a semiconductor memory.
　半導体チップ１００は、メモリセルアレイ１０１と、内部電圧発生回路１０３と、Ｘデコーダ１０４と、Ｙデコーダ１０５と、Ｘ制御回路１０６と、Ｙ制御回路１０７と、入出力部１０９と、補償容量１１０と、を有する。 The semiconductor chip 100 includes a memory cell array 101, an internal voltage generation circuit 103, an X decoder 104, a Y decoder 105, an X control circuit 106, a Y control circuit 107, an input / output unit 109, a compensation capacitor 110, Have
　メモリセルアレイ１０１は、複数のワード配線ＷＬと複数のビット配線ＢＬとを備えている。また、各ワード配線ＷＬとビット配線ＢＬとの交点に、メモリセル１０２が形成されている。 The memory cell array 101 includes a plurality of word lines WL and a plurality of bit lines BL. A memory cell 102 is formed at the intersection of each word line WL and bit line BL.
　内部電圧発生回路１０３は、電源端子（ＶＣＣ、ＧＮＤ）を介して供給される電圧を変圧し、Ｘデコーダ１０４、Ｙデコーダ１０５、および、入出力部１０９に動作電圧を供給する。 The internal voltage generation circuit 103 transforms the voltage supplied via the power supply terminals (VCC, GND), and supplies an operating voltage to the X decoder 104, the Y decoder 105, and the input / output unit 109.
　Ｘデコーダ１０４は、メモリの読み出しを行うために、読み出すメモリセル１０２のアドレスを示すアドレス信号が入力され、入力されたアドレス信号をデコードし、デコードしたアドレス信号をＸ制御回路１０６に出力する。 In order to read out the memory, the X decoder 104 receives an address signal indicating the address of the memory cell 102 to be read, decodes the input address signal, and outputs the decoded address signal to the X control circuit 106.
　Ｙデコーダ１０５は、メモリの読み出しを行うために、読み出すメモリセル１０２のアドレスを示すアドレス信号が入力され、入力されたアドレス信号をデコードし、デコードしたアドレス信号をＹ制御回路１０７に出力する。 In order to read out the memory, the Y decoder 105 receives an address signal indicating the address of the memory cell 102 to be read, decodes the input address signal, and outputs the decoded address signal to the Y control circuit 107.
　Ｘ制御回路１０６は、Ｘデコーダ１０４によりデコードされたアドレス信号に応じて、ワード配線ＷＬを選択する。また、Ｙ制御回路１０７は、Ｙデコーダ１０５によりデコードされたアドレス信号に応じて、ビット配線ＢＬを選択する。ワード配線ＷＬおよびビット配線ＢＬが選択されることにより、アドレス信号に対応するメモリセル１０２が選択される。 The X control circuit 106 selects the word line WL according to the address signal decoded by the X decoder 104. Further, the Y control circuit 107 selects the bit line BL according to the address signal decoded by the Y decoder 105. By selecting the word line WL and the bit line BL, the memory cell 102 corresponding to the address signal is selected.
　選択されたメモリセル１０２に記録された信号は、ビット配線ＢＬを介して読み出され、Ｙ制御回路１０７が備えるセンスアンプ回路１０８によって増幅される。 The signal recorded in the selected memory cell 102 is read through the bit line BL and amplified by the sense amplifier circuit 108 provided in the Y control circuit 107.
　入出力部１０９は、センスアンプ回路１０８により増幅された信号を半導体チップ１００の外部へ出力する。なお、入出力部１０９は、後述する、入出力に関する機能単位である複数の入出力ブロックにより構成されている。 The input / output unit 109 outputs the signal amplified by the sense amplifier circuit 108 to the outside of the semiconductor chip 100. The input / output unit 109 includes a plurality of input / output blocks which are functional units related to input / output, which will be described later.
　補償容量１１０は、内部電圧発生回路１０３からＸデコーダ１０４、Ｙデコーダ１０５、および、入出力部１０９に動作電圧を供給する電源配線とＧＮＤ端子との間に配置されている。補償容量１１０によって、Ｘデコーダ１０４、Ｙデコーダ１０５、および、入出力部１０９に供給される動作電圧の変動が抑制される。 The compensation capacitor 110 is disposed between the GND terminal and the power supply wiring that supplies the operating voltage from the internal voltage generation circuit 103 to the X decoder 104, the Y decoder 105, and the input / output unit 109. The compensation capacitor 110 suppresses fluctuations in the operating voltage supplied to the X decoder 104, the Y decoder 105, and the input / output unit 109.
　図２は、入出力部１０９を構成する入出力ブロックの概略構成を示す図である。 FIG. 2 is a diagram showing a schematic configuration of an input / output block constituting the input / output unit 109.
　入出力部１０９は、入出力ブロック２０６および入出力ブロック２０７により構成されており、入出力ブロック２０６および入出力ブロック２０７が、均等に繰り返し配置されている。 The input / output unit 109 includes an input / output block 206 and an input / output block 207, and the input / output block 206 and the input / output block 207 are equally and repeatedly arranged.
　入出力ブロック２０６は、ＶＳＳＱ　ＰＡＤ２０１と、ＤＱ　ＰＡＤ２０３と、入出力回路２０４と、補償容量２０５と、で構成される。入出力ブロック２０７は、ＶＤＤＱ　ＰＡＤ２０２と、ＤＱ　ＰＡＤ２０３と、入出力回路２０４と、補償容量２０５と、で構成される。 The input / output block 206 includes a VSSQ PAD 201, a DQ PAD 203, an input / output circuit 204, and a compensation capacitor 205. The input / output block 207 includes a VDDQ PAD 202, a DQ PAD 203, an input / output circuit 204, and a compensation capacitor 205.
　ＶＳＳＱ　ＰＡＤ２０１は、図２においては不図示の内部電圧発生回路１０３と接続され、電位ＶＳＳＱが供給される。また、ＶＳＳＱ　ＰＡＤ２０１は、第１の電源線としての電源線ＶＳＳＱと接続される。したがって、電源線ＶＳＳＱの電位は、電位ＶＳＳＱとなる。なお、電位ＶＳＳＱは、例えば、グランド電位である。 The VSSQ PAD 201 is connected to an internal voltage generation circuit 103 (not shown in FIG. 2), and is supplied with the potential VSSQ. The VSSQ PAD 201 is connected to a power supply line VSSQ as a first power supply line. Therefore, the potential of the power supply line VSSQ becomes the potential VSSQ. Note that the potential VSSQ is, for example, a ground potential.
　ＶＤＤＱ　ＰＡＤ２０２は、図２においては不図示の内部電圧発生回路１０３と接続され、電位ＶＤＤＱが供給される。また、ＶＤＤＱ　ＰＡＤ２０２は、第２の電源線としての電源線ＶＤＤＱと接続される。したがって、電源線ＶＤＤＱの電位は、電位ＶＤＤＱとなる。 The VDDQ PAD 202 is connected to an internal voltage generation circuit 103 (not shown in FIG. 2) and is supplied with the potential VDDQ. Further, the VDDQ PAD 202 is connected to a power supply line VDDQ as a second power supply line. Therefore, the potential of the power supply line VDDQ becomes the potential VDDQ.
　入出力回路２０４は、電源線ＶＤＤＱおよび電源線ＶＳＳＱと接続され、これらの電源線を介して動作電圧が供給される。また、入出力回路２０４は、ＤＱ　ＰＡＤ２０３と接続され、ＤＱ　ＰＡＤ２０３を介して、図２においては不図示の半導体チップ１００の外部と信号の入出力を行う。 The input / output circuit 204 is connected to the power supply line VDDQ and the power supply line VSSQ, and an operating voltage is supplied through these power supply lines. The input / output circuit 204 is connected to the DQ PAD 203 and inputs / outputs signals to / from the outside of the semiconductor chip 100 (not shown in FIG. 2) via the DQ PAD 203.
　補償容量２０５は、電源線ＶＳＳＱと電源線ＶＤＤＱとの間に配置される。すなわち、補償容量２０５は、一端が電源線ＶＳＳＱと接続され、他端が電源線ＶＤＤＱと接続される。 The compensation capacitor 205 is disposed between the power supply line VSSQ and the power supply line VDDQ. That is, the compensation capacitor 205 has one end connected to the power supply line VSSQ and the other end connected to the power supply line VDDQ.
　次に、入出力部１０９のレイアウトについて説明する。 Next, the layout of the input / output unit 109 will be described.
　上述したように、入出力部１０９においては、入出力ブロック２０６と入出力ブロック２０７とが繰り返し配置されている。そのため、以下では、１つの入出力回路２０４と、それに対応するＶＳＳＱ　ＰＡＤ２０１、ＶＤＤＱ　ＰＡＤ２０２、ＤＱ　ＰＡＤ２０３、および、補償容量２０５のレイアウトについて、図３Ａから図３Ｃを参照して説明する。図３Ａから図３Ｃにおいて、図２と同様の構成については同じ符号を付し、説明を省略する。 As described above, in the input / output unit 109, the input / output block 206 and the input / output block 207 are repeatedly arranged. Therefore, hereinafter, the layout of one input / output circuit 204 and the corresponding VSSQ PAD 201, VDDQ PAD 202, DQ PAD 203, and compensation capacitor 205 will be described with reference to FIGS. 3A to 3C. 3A to 3C, the same reference numerals are given to the same components as those in FIG. 2, and the description thereof is omitted.
　図３Ａは、入出力部１０９のレイアウトの一例を示す図である。 FIG. 3A is a diagram illustrating an example of the layout of the input / output unit 109.
　図３Ａにおいては、入出力回路２０４は、各電源ＰＡＤ（ＶＳＳＱ　ＰＡＤ２０１およびＶＤＤＱ　ＰＡＤ２０２）と、電源線ＶＳＳＱおよび電源線ＶＤＤＱを介して、接続されている。 In FIG. 3A, the input / output circuit 204 is connected to each power supply PAD (VSSQ PAD201 and VDDQ PAD202) via the power supply line VSSQ and the power supply line VDDQ.
　補償容量２０５は、電源線ＶＳＳＱと電源線ＶＤＤＱとの間に配置されている。 The compensation capacitor 205 is disposed between the power supply line VSSQ and the power supply line VDDQ.
　また、ＶＳＳＱ　ＰＡＤ２０１と電源線ＶＤＤＱの間、ＶＤＤＱ　ＰＡＤ２０２と電源線ＶＳＳＱの間、ＤＱ　ＰＡＤ２０３と電源線ＶＳＳＱの間、および、ＤＱ　ＰＡＤ２０３と電源線ＶＤＤＱの間にそれぞれ、電流を吸収する保護素子３０１が配置されている。 In addition, there are protection elements 301 that absorb current between VSSQ PAD201 and power supply line VDDQ, between VDDQ PAD202 and power supply line VSSQ, between DQ PAD203 and power supply line VSSQ, and between DQ PAD203 and power supply line VDDQ, respectively. Has been placed.
　一般に、半導体チップにおいては、配線が高精細なため、回路のレイアウトによっては、静電気放電（ＥＳＤ：Ｅｌｅｃｔｒｏ　Ｓｔａｔｉｃ　Ｄｉｓｃｈａｒｇｅ）による破壊（ＥＳＤ破壊）がおこる可能性がある。そのため、ＥＳＤ破壊を考慮して、回路のレイアウトを決定する必要がある。 Generally, since a semiconductor chip has high-definition wiring, there is a possibility of breakdown (ESD breakdown) due to electrostatic discharge (ESD) depending on the circuit layout. Therefore, it is necessary to determine the circuit layout in consideration of ESD destruction.
　図３Ａにおいては、入出力回路２０４が信号を出力する際に、瞬間的に各電源ＰＡＤから入出力回路２０４に定格以上の電流が流入し、入出力回路２０４がＥＳＤ破壊されるおそれがある。 In FIG. 3A, when the input / output circuit 204 outputs a signal, a current exceeding the rated value instantaneously flows from each power supply PAD to the input / output circuit 204, and the input / output circuit 204 may be damaged by ESD.
　ここで、上述したように、ＶＳＳＱ　ＰＡＤ２０１と電源線ＶＤＤＱの間、ＶＤＤＱ　ＰＡＤ２０２と電源線ＶＳＳＱの間、ＤＱ　ＰＡＤ２０３と電源線ＶＳＳＱの間、および、ＤＱ　ＰＡＤ２０３と電源線ＶＤＤＱの間にそれぞれ保護素子３０１が配置されている。そのため、これらの保護素子３０１により、各電源ＰＡＤから入出力回路２０４に流れる定格以上の電流が吸収されるため、入出力回路２０４のＥＳＤ破壊が起こる可能性が低減される。 Here, as described above, the protection elements 301 are between the VSSQ PAD201 and the power supply line VDDQ, between the VDDQ PAD202 and the power supply line VSSQ, between the DQ PAD203 and the power supply line VSSQ, and between the DQ PAD203 and the power supply line VDDQ, respectively. Is arranged. Therefore, these protection elements 301 absorb a current exceeding the rating flowing from each power supply PAD to the input / output circuit 204, so that the possibility of ESD breakdown of the input / output circuit 204 is reduced.
　しかし、各電源ＰＡＤから入出力回路２０４に流れる電流を保護素子３０１で吸収しきれない場合がある。そのような場合には、保護素子３０１で吸収しきれなかった電流が、入出力回路２０４へ流入し、入出力回路２０４のＥＳＤ破壊が起こる可能性がある。 However, the protection element 301 may not be able to absorb the current flowing from each power supply PAD to the input / output circuit 204. In such a case, a current that could not be absorbed by the protection element 301 flows into the input / output circuit 204 and ESD damage to the input / output circuit 204 may occur.
　図３Ｂは、入出力部１０９のレイアウトの他の一例を示す図である。 FIG. 3B is a diagram illustrating another example of the layout of the input / output unit 109.
　図３Ｂに示すレイアウトと図３Ａに示すレイアウトとを比較すると、入出力回路２０４が、さらに配線３０２、３０３を介して各電源ＰＡＤと接続されている点と、補償容量２０５が、電源線ＶＳＳＱおよび電源線ＶＤＤＱを介さずに、各電源ＰＡＤと接続されている点と、が異なる。 Comparing the layout shown in FIG. 3B with the layout shown in FIG. 3A, the input / output circuit 204 is further connected to each power supply PAD via wirings 302 and 303, and the compensation capacitor 205 is connected to the power supply line VSSQ and The difference is that each power supply PAD is connected without going through the power supply line VDDQ.
　図３Ｂにおいては、各電源ＰＡＤと入出力回路２０４との間の配線長は、図３Ａに示す各電源ＰＡＤと入出力回路２０４との配線長よりも長い。したがって、各電源ＰＡＤと入出力回路２０４との間の配線の寄生抵抗が大きい。そのため、保護素子３０１で吸収しきれなかった電流が寄生抵抗で減衰され、入出力回路２０４のＥＳＤ破壊が起こる可能性が低減される。 3B, the wiring length between each power supply PAD and the input / output circuit 204 is longer than the wiring length between each power supply PAD and the input / output circuit 204 shown in FIG. 3A. Therefore, the parasitic resistance of the wiring between each power supply PAD and the input / output circuit 204 is large. Therefore, the current that could not be absorbed by the protection element 301 is attenuated by the parasitic resistance, and the possibility of ESD damage of the input / output circuit 204 is reduced.
　一方で、図３Ｂに示すレイアウトと図３Ａに示すレイアウトとを比較すると、補償容量２０５は、電源線ＶＳＳＱおよび電源線ＶＤＤＱを介さずに、各電源ＰＡＤと接続されているため、補償容量２０５と各電源ＰＡＤとの間の配線の寄生抵抗が小さい。したがって、保護素子３０１で吸収しきれなかった電流が補償容量２０５と各電源ＰＡＤとの間の配線の寄生抵抗で十分に減衰されずに補償容量２０５へ流入するため、補償容量２０５のＥＳＤ破壊が起こる可能性が高くなる。 On the other hand, comparing the layout shown in FIG. 3B with the layout shown in FIG. 3A, the compensation capacitor 205 is connected to each power supply PAD without passing through the power supply line VSSQ and the power supply line VDDQ. The parasitic resistance of the wiring between each power supply PAD is small. Therefore, the current that could not be absorbed by the protection element 301 flows into the compensation capacitor 205 without being sufficiently attenuated by the parasitic resistance of the wiring between the compensation capacitor 205 and each power supply PAD. More likely to happen.
　図３Ｃは、入出力部１０９のレイアウトの別の一例を示す図である。 FIG. 3C is a diagram illustrating another example of the layout of the input / output unit 109.
　入出力回路２０４は、図３Ｂと同様に、配線３０２、３０３を介して各電源ＰＡＤと接続されている。したがって、各電源ＰＡＤと入出力回路２０４との間の配線長が長く、各電源ＰＡＤと入出力回路２０４との間の配線の寄生抵抗も大きい。そのため、図３Ｂにおいて説明したように、入出力回路２０４のＥＳＤ破壊が起こる可能性は低減される。 The input / output circuit 204 is connected to each power supply PAD via wirings 302 and 303 as in FIG. 3B. Therefore, the wiring length between each power supply PAD and the input / output circuit 204 is long, and the parasitic resistance of the wiring between each power supply PAD and the input / output circuit 204 is also large. Therefore, as described with reference to FIG. 3B, the possibility of ESD destruction of the input / output circuit 204 is reduced.
　補償容量３０４、３０５は、配線３０２と配線３０３との間に配置されている。ここで、配線３０２は電源線ＶＤＤＱと接続されており、配線３０３は電源線ＶＳＳＱと接続されている。したがって、補償容量３０４、３０５は、各電源ＰＡＤと電源線ＶＳＳＱおよび電源線ＶＤＤＱを介して接続されているものと等価である。 The compensation capacitors 304 and 305 are arranged between the wiring 302 and the wiring 303. Here, the wiring 302 is connected to the power supply line VDDQ, and the wiring 303 is connected to the power supply line VSSQ. Therefore, the compensation capacitors 304 and 305 are equivalent to those connected to each power supply PAD through the power supply line VSSQ and the power supply line VDDQ.
　補償容量３０４は、各ＰＡＤ（ＶＳＳＱ　ＰＡＤ２０１、ＶＤＤＱ　ＰＡＤ２０２、および、ＤＱ　ＰＡＤ２０３）の下（半導体チップ１００における積層方向と反対の方向）の領域を利用して配置されている。一方、補償容量３０５は、入出力回路１０４の近傍に配置されている。 The compensation capacitor 304 is arranged using an area under each PAD (VSSQ PAD201, VDDQ PAD202, and DQ PAD203) (the direction opposite to the stacking direction in the semiconductor chip 100). On the other hand, the compensation capacitor 305 is disposed in the vicinity of the input / output circuit 104.
　図３Ｃにおいては、補償容量３０４、３０５と各電源ＰＡＤとの間の配線長は、図３Ａおよび図３Ｂに示す補償容量２０５と各電源ＰＡＤとの間の配線長よりも長い。したがって、補償容量３０４、３０５と各電源ＰＡＤとの間の配線の寄生抵抗も大きい。そのため、保護素子３０１で吸収しきれなかった電流が寄生抵抗で減衰され、補償容量３０４、３０５への流入が抑制され、補償容量３０４、３０５のＥＳＤ破壊が起こる可能性は低減される。 In FIG. 3C, the wiring length between the compensation capacitors 304 and 305 and each power supply PAD is longer than the wiring length between the compensation capacitor 205 and each power supply PAD shown in FIGS. 3A and 3B. Therefore, the parasitic resistance of the wiring between the compensation capacitors 304 and 305 and each power supply PAD is also large. Therefore, the current that could not be absorbed by the protection element 301 is attenuated by the parasitic resistance, the inflow into the compensation capacitors 304 and 305 is suppressed, and the possibility that the ESD destruction of the compensation capacitors 304 and 305 occurs is reduced.
　次に、本実施形態における半導体チップの概略構成を説明する。 Next, a schematic configuration of the semiconductor chip in this embodiment will be described.
　まず、比較のために、一般的な半導体チップの概略構成を図４Ａに示す。なお、本発明は主に、入出力回路から出力される信号に含まれるノイズの低減を図るものであるため、入出力回路近傍の構成のみを示し、その他の部分の構成については説明を省略する。 First, for comparison, a schematic configuration of a general semiconductor chip is shown in FIG. 4A. Since the present invention mainly aims to reduce noise included in the signal output from the input / output circuit, only the configuration in the vicinity of the input / output circuit is shown, and the description of the configuration of other parts is omitted. .
　図４Ａは、図３Ｃにレイアウトを示した入出力部を有する半導体チップの要部構成を示す図である。 FIG. 4A is a diagram showing a configuration of a main part of a semiconductor chip having an input / output unit whose layout is shown in FIG. 3C.
　図４Ａに示す半導体チップ４００Ａにおいては、第１の補償容量としての補償容量３０４、および、第２の補償容量としての補償容量３０５がそれぞれ、電源線ＶＳＳＱと電源線ＶＤＤＱとの間に配置されている。すなわち、補償容量３０４、３０５はそれぞれ、一端が電源線ＶＳＳＱと接続され、他端が電源線ＶＤＤＱと接続されている。ここで、補償容量３０４は、補償容量３０５と比較して、入出力回路２０４との間の配線長が長くなるように配置されている。 In the semiconductor chip 400A shown in FIG. 4A, a compensation capacitor 304 as a first compensation capacitor and a compensation capacitor 305 as a second compensation capacitor are arranged between the power supply line VSSQ and the power supply line VDDQ, respectively. Yes. That is, each of the compensation capacitors 304 and 305 has one end connected to the power supply line VSSQ and the other end connected to the power supply line VDDQ. Here, the compensation capacitor 304 is arranged so that the wiring length between the compensation capacitor 304 and the input / output circuit 204 is longer than that of the compensation capacitor 305.
　図４Ｂは、本発明の一実施形態の半導体チップの要部構成を示す図である。なお、図４Ｂにおいて、図４Ａと同様の構成については同じ符号を付し、説明を省略する。 FIG. 4B is a diagram showing a main configuration of a semiconductor chip according to an embodiment of the present invention. In FIG. 4B, the same components as those in FIG. 4A are denoted by the same reference numerals, and description thereof is omitted.
　図４Ｂに示す半導体チップ４００は、図４Ａに示す半導体チップ４００Ａと比較して、抵抗部４０１が追加されている点が異なる。 4B is different from the semiconductor chip 400A shown in FIG. 4A in that a resistor 401 is added.
　抵抗部４０１は、抵抗値が変更可能であり、一端が電源線ＶＤＤＱと接続され、他端が補償容量３０４の他端と接続される。 The resistance value of the resistance unit 401 can be changed, one end is connected to the power supply line VDDQ, and the other end is connected to the other end of the compensation capacitor 304.
　本願発明者らは、種々のシミュレーションを行った結果、補償容量の容量値が大きいほど、ノイズの低減の効果は大きくなるが、補償容量の容量値がある値を超えると、ノイズの低減の効果が飽和することを明らかにした。したがって、補償容量３０４、３０５の容量値を変更するだけでは、十分にノイズが低減されない。 As a result of various simulations, the inventors of the present application have a greater effect of reducing noise as the capacitance value of the compensation capacitor is larger. However, when the capacitance value of the compensation capacitor exceeds a certain value, the effect of noise reduction is increased. Revealed that saturates. Therefore, noise is not sufficiently reduced only by changing the capacitance values of the compensation capacitors 304 and 305.
　さらに、本願発明者らは、概ね、補償容量と入出力回路２０４との間の抵抗値は小さい方が、出力信号におけるノイズの低減の効果が高いことを明らかにした。上述したように、補償容量３０５は、補償容量３０４よりも、入出力回路２０４との間の配線長が短い。したがって、補償容量３０５と入出力回路２０４との間の配線の寄生抵抗の方が、補償容量３０４と入出力回路２０４との間の配線の寄生抵抗よりも小さい。そのため、本実施形態においては、補償容量３０５には、抵抗部を付加せず低抵抗のままにしておくことで、ノイズの低減の効果を高いまま維持し、また、補償容量３０４には、抵抗部４０１を付加した。 Furthermore, the inventors of the present application have clarified that the effect of reducing noise in the output signal is higher when the resistance value between the compensation capacitor and the input / output circuit 204 is smaller. As described above, the compensation capacitor 305 has a shorter wiring length with the input / output circuit 204 than the compensation capacitor 304. Therefore, the parasitic resistance of the wiring between the compensation capacitor 305 and the input / output circuit 204 is smaller than the parasitic resistance of the wiring between the compensation capacitor 304 and the input / output circuit 204. For this reason, in this embodiment, the compensation capacitor 305 is not added with a resistance portion and is kept at a low resistance, so that the effect of reducing noise is kept high, and the compensation capacitor 304 has a resistance. Section 401 has been added.
　さらに、本願発明者らは、抵抗部の抵抗値と補償容量の容量値にはノイズの低減の効果の高い組み合わせがあり、その組み合わせはパッケージの方法や配線パターンおよび半導体チップの駆動周波数に応じて異なることを明らかにした。そのため、本実施形態においては、抵抗部４０１の抵抗値を可変とすることで、種々のパッケージの方法や配線パターンおよび半導体チップの駆動周波数について、半導体チップ４００の出力信号におけるノイズを低減できるようにした。 Furthermore, the inventors of the present application have a combination of a resistance value of the resistance portion and a capacitance value of the compensation capacitor that has a high effect of reducing noise, and the combination depends on the package method, the wiring pattern, and the driving frequency of the semiconductor chip. Revealed different things. Therefore, in the present embodiment, by making the resistance value of the resistance unit 401 variable, noise in the output signal of the semiconductor chip 400 can be reduced with respect to various package methods, wiring patterns, and semiconductor chip drive frequencies. did.
　また、様々な容量値の補償容量、および、様々な抵抗値の抵抗素子が配置され、それらが選択的に接続されることにより、ノイズの低減の効果が高い組み合わせが作られる。 Also, a compensation capacitor having various capacitance values and resistance elements having various resistance values are arranged, and a combination having high noise reduction effect is made by selectively connecting them.
　図５は、図４Ｂに示す半導体チップの基板上におけるレイアウトの一例を示す図である。なお、図５において、図４Ｂと同様の構成については同じ符号を付し、説明を省略する。なお、図５においては、本発明に関する配線のみを記載し、本発明と直接関係しない配線や他の構成については記載を省略している。 FIG. 5 is a diagram showing an example of the layout on the substrate of the semiconductor chip shown in FIG. 4B. In FIG. 5, the same components as those in FIG. 4B are denoted by the same reference numerals, and description thereof is omitted. In FIG. 5, only the wirings related to the present invention are shown, and the description of wirings and other configurations not directly related to the present invention is omitted.
　回路５０１は、半導体チップ４００を構成する入出力回路以外の種々の回路である。 The circuit 501 is various circuits other than the input / output circuit constituting the semiconductor chip 400.
　上述したように、ＶＳＳＱ　ＰＡＤ２０１、ＶＤＤＱ　ＰＡＤ２０２、および、ＤＱ　ＰＡＤ２０３は、基板上において繰り返し配置されている。なお、図５においては、ＶＳＳＱ　ＰＡＤ２０１については記載を省略している。 As described above, VSSQ PAD201, VDDQ PAD202, and DQ PAD203 are repeatedly arranged on the substrate. In FIG. 5, description of VSSQ PAD201 is omitted.
　入出力回路２０４は、出力回路２０４Ａと入力回路２０４Ｂとに分かれて基板上に配置されている。なお、図５においては、出力回路２０４Ａに関連する配線だけを記載し、入力回路２０４Ｂに関連する配線は記載を省略している。 The input / output circuit 204 is divided into an output circuit 204A and an input circuit 204B and arranged on the substrate. In FIG. 5, only the wiring related to the output circuit 204A is shown, and the wiring related to the input circuit 204B is omitted.
　保護回路３０１は、ＶＤＤＱ　ＰＡＤ２０２およびＤＱ　ＰＡＤ２０３の近傍に配置されている。 The protection circuit 301 is arranged in the vicinity of the VDDQ PAD 202 and the DQ PAD 203.
　補償容量３０４は、ＶＤＤＱ　ＰＡＤ２０２およびＤＱ　ＰＡＤ２０３の下の領域を利用して配置されている。補償容量３０５は、出力回路２０４Ｂの近傍に配置されている。そのため、補償容量３０４は、補償容量３０５と比較して、入出力回路２０４との間の配線長が長くなるように配置されている。 The compensation capacitor 304 is arranged using the area under VDDQ PAD202 and DQ PAD203. The compensation capacitor 305 is disposed in the vicinity of the output circuit 204B. Therefore, the compensation capacitor 304 is disposed so that the wiring length between the compensation capacitor 304 and the input / output circuit 204 is longer than that of the compensation capacitor 305.
　抵抗部４０１は、出力回路２０４Ａと接続される電源線ＶＤＤＱと補償容量３０４との間の配線上に設けられている。 The resistance unit 401 is provided on the wiring between the power supply line VDDQ connected to the output circuit 204A and the compensation capacitor 304.
　このように、本実施形態によれば、半導体チップ４００は、入出力回路に動作電圧を供給する電源線ＶＳＳＱと電源線ＶＤＤＱとの間に設けられた容量素子３０４と、その容量素子３０４に直列に接続され、抵抗値が変更可能な抵抗部４０１と、を有する。 As described above, according to the present embodiment, the semiconductor chip 400 includes the capacitive element 304 provided between the power supply line VSSQ and the power supply line VDDQ that supplies the operating voltage to the input / output circuit, and the capacitive element 304 in series. And a resistance portion 401 whose resistance value can be changed.
　そのため、半導体チップ４００の出力信号におけるノイズを低減することができる。 Therefore, noise in the output signal of the semiconductor chip 400 can be reduced.
　（第１の実施例）
　図６は、本発明の第１の実施例における半導体チップ６００の概略構成図である。なお、図６において、図４Ａと同様の構成については同じ符号を付し、説明を省略する。 (First embodiment)
FIG. 6 is a schematic configuration diagram of the semiconductor chip 600 according to the first embodiment of the present invention. In FIG. 6, the same components as those in FIG. 4A are denoted by the same reference numerals, and description thereof is omitted.
　図６に示す半導体チップ６００においては、抵抗部４０１として、抵抗値が変更可能な可変抵抗素子６０１が設けられている。 In the semiconductor chip 600 shown in FIG. 6, a variable resistance element 601 whose resistance value can be changed is provided as the resistance portion 401.
　パッケージの方法や配線パターンおよび半導体チップの駆動周波数に応じて、可変抵抗素子６０１の抵抗値を調整し、抵抗部４０１の抵抗値を変更することで、半導体チップ６００の出力信号におけるノイズを低減することができる。可変抵抗素子６０１の抵抗値を調整する値は、半導体チップ内のレジスタに揮発又は不揮発に記憶されても良いし、半導体チップの外部から供給されても良い。 Noise in the output signal of the semiconductor chip 600 is reduced by adjusting the resistance value of the variable resistance element 601 and changing the resistance value of the resistance unit 401 according to the package method, wiring pattern, and driving frequency of the semiconductor chip. be able to. A value for adjusting the resistance value of the variable resistance element 601 may be stored in a register in the semiconductor chip in a volatile or non-volatile manner, or may be supplied from the outside of the semiconductor chip.
　（第２の実施例）
　図７は、本発明の第２の実施例における半導体チップの概略構成図である。なお、図７において、図４Ａと同様の構成については同じ符号を付し、説明を省略する。 (Second embodiment)
FIG. 7 is a schematic configuration diagram of a semiconductor chip in the second embodiment of the present invention. In FIG. 7, the same components as those in FIG. 4A are denoted by the same reference numerals, and description thereof is omitted.
　図７に示す半導体チップ７００においては、抵抗部４０１として、複数の抵抗素子７０１が設けられている。 In the semiconductor chip 700 shown in FIG. 7, a plurality of resistance elements 701 are provided as the resistance portion 401.
　複数の抵抗素子７０１は、直列に接続されている。ここで、複数の抵抗素子７０１間の配線パターンは、マスタースライス方式により変更可能である。複数の抵抗素子７０１間の配線パターンを変更することで、抵抗部４０１の抵抗値を変更することができる。 The plurality of resistance elements 701 are connected in series. Here, the wiring pattern between the plurality of resistance elements 701 can be changed by the master slice method. By changing the wiring pattern between the plurality of resistance elements 701, the resistance value of the resistance portion 401 can be changed.
　なお、複数の抵抗素子７０１の抵抗値を、２のべき乗（１、２、４、８）の比で変化するそれぞれ異なる値とすることで、抵抗部４０１の抵抗値を細かく変更することができる。 In addition, the resistance value of the resistance unit 401 can be finely changed by setting the resistance values of the plurality of resistance elements 701 to different values that change with a power of 2 ratio (1, 2, 4, 8). .
　図８は、図７に示す複数の抵抗素子７０１によって構成される抵抗部４０１の抵抗値の変更方法を説明するための図である。 FIG. 8 is a diagram for explaining a method of changing the resistance value of the resistance unit 401 including the plurality of resistance elements 701 shown in FIG.
　抵抗部４０１は、抵抗値が１オームの抵抗素子７０１Ａと、抵抗値が２オームの７０１Ｂと、抵抗値が４オームの７０１Ｃと、抵抗値が８オームの７０１Ｄとから構成されている。 The resistance unit 401 includes a resistance element 701A having a resistance value of 1 ohm, a 701B having a resistance value of 2 ohms, a 701C having a resistance value of 4 ohms, and a 701D having a resistance value of 8 ohms.
　メモリセルのゲート電極を構成する配線と同じタングステン配線を使って抵抗素子７０１Ａから７０１Ｄが形成されている。抵抗素子７０１Ａから７０１Ｄとコンタクトを介して接続された上層の銅又はアルミなどのメタル配線層を使って各抵抗素子が結線されている。そのため、メタル配線層の配線パターンを変更することによって、抵抗値を変更することができる。 Resistance elements 701A to 701D are formed by using the same tungsten wiring as the wiring constituting the gate electrode of the memory cell. Each resistive element is connected by using an upper metal wiring layer such as copper or aluminum connected to the resistive elements 701A to 701D via contacts. Therefore, the resistance value can be changed by changing the wiring pattern of the metal wiring layer.
　抵抗素子７０１Ａは、一端が図８においては不図示の補償容量３０４の他端と接続点８０１において接続され、他端が抵抗素子７０１Ｂの一端と接続点８０２において接続される。 One end of the resistance element 701A is connected to the other end of the compensation capacitor 304 (not shown in FIG. 8) at the connection point 801, and the other end is connected to one end of the resistance element 701B at the connection point 802.
　抵抗素子７０１Ｂは、一端が抵抗素子７０１Ａの他端と接続点８０２において接続され、他端が抵抗素子７０１Ｃの一端と接続点８０３において接続される。 Resistance element 701B has one end connected to the other end of resistance element 701A at connection point 802, and the other end connected to one end of resistance element 701C at connection point 803.
　抵抗素子７０１Ｃは、一端が抵抗素子７０１Ｂの他端と接続点８０３において接続され、他端が抵抗素子７０１Ｄの一端と接続点８０４において接続される。 Resistance element 701C has one end connected to the other end of resistance element 701B at connection point 803, and the other end connected to one end of resistance element 701D at connection point 804.
　抵抗素子７０１Ｄは、一端が抵抗素子７０１Ｃの他端と接続点８０４において接続され、他端が図８においては不図示の電源線ＶＤＤＱと接続点８０５において接続される。 The resistance element 701D has one end connected to the other end of the resistance element 701C at a connection point 804, and the other end connected to a power supply line VDDQ (not shown in FIG. 8) at a connection point 805.
　このように、抵抗素子７０１Ａから抵抗素子７０１Ｄまでの各抵抗素子は直列に接続されている。そのため、抵抗素子７０１Ａから抵抗素子７０１Ｄまでの各抵抗素子が全て接続されている場合には、抵抗部４０１の抵抗値は１５オームとなる。ここで、例えば、接続点８０２と接続点８０３とが短絡されると、抵抗部４０１の抵抗値は１３オームとなる。このように、各抵抗素子の接続点間を短絡させることにより、抵抗部４０１の抵抗値が所定の値となる。 Thus, the resistance elements from the resistance element 701A to the resistance element 701D are connected in series. Therefore, when all the resistance elements from the resistance element 701A to the resistance element 701D are connected, the resistance value of the resistance unit 401 is 15 ohms. Here, for example, when the connection point 802 and the connection point 803 are short-circuited, the resistance value of the resistance unit 401 becomes 13 ohms. In this manner, the resistance value of the resistance unit 401 becomes a predetermined value by short-circuiting the connection points of the respective resistance elements.
　このように、パッケージの方法や配線パターンおよび半導体チップの駆動周波数に応じて、マスタースライス方式によって抵抗部４０１の抵抗値を変更することで、半導体チップ７００の出力信号におけるノイズを低減することができる。 As described above, by changing the resistance value of the resistance unit 401 by the master slice method according to the package method, the wiring pattern, and the driving frequency of the semiconductor chip, noise in the output signal of the semiconductor chip 700 can be reduced. .
　（第３の実施例）
　図９は、本発明の第３の実施例における半導体チップの概略構成図である。なお、図９において、図４Ａと同様の構成については同じ符号を付し、説明を省略する。 (Third embodiment)
FIG. 9 is a schematic configuration diagram of a semiconductor chip in the third embodiment of the present invention. In FIG. 9, the same components as those in FIG. 4A are denoted by the same reference numerals, and description thereof is omitted.
　図７に示す半導体チップ９００においては、抵抗部４０１として、複数の抵抗素子９０１と、それら複数の抵抗素子９０１のそれぞれに対応して設けられた複数のＭＯＳ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）スイッチ９０２と、コントロールブロック９０３と、が設けられている。 In the semiconductor chip 900 shown in FIG. 7, as the resistance unit 401, a plurality of resistance elements 901, a plurality of MOS (Metal Oxide Semiconductor) switches 902 provided corresponding to each of the plurality of resistance elements 901, and a control Block 903 is provided.
　複数の抵抗素子９０１は、直列に接続されている。 The plurality of resistance elements 901 are connected in series.
　複数のＭＯＳスイッチ９０２はそれぞれ、対応する抵抗素子９０１と並列に接続されている。ＭＯＳスイッチ９０２がオンとなることで、そのＭＯＳスイッチ９０２に対応する抵抗素子９０１が短絡され、抵抗部４０１の抵抗値が変更される。 Each of the plurality of MOS switches 902 is connected in parallel with the corresponding resistance element 901. When the MOS switch 902 is turned on, the resistance element 901 corresponding to the MOS switch 902 is short-circuited, and the resistance value of the resistance unit 401 is changed.
　なお、ＭＯＳスイッチ９０２は、ヒューズ（ＦＵＳＥ）やボンディングオプション（ＢＯＰ）などを用いてＭＯＳスイッチ９０２に印加される電圧が変更されることにより操作される。コントロールブロック９０３は、外部からの入力に応じて、ＭＯＳスイッチ９０２を操作する制御信号を生成するように構成してもよいし、不揮発的に記憶した値に基づいて制御信号を生成するように構成しても良い。 The MOS switch 902 is operated by changing the voltage applied to the MOS switch 902 using a fuse (FUSE), a bonding option (BOP), or the like. The control block 903 may be configured to generate a control signal for operating the MOS switch 902 according to an input from the outside, or may be configured to generate a control signal based on a value stored in a nonvolatile manner. You may do it.
　このように、パッケージの方法や配線パターンおよび半導体チップの駆動周波数に応じて、ＭＯＳスイッチ９０２のオン、オフを制御し、抵抗部４０１の抵抗値を変更することで、半導体チップ９００の出力信号におけるノイズを低減することができる。 As described above, the MOS switch 902 is controlled to be turned on and off according to the package method, the wiring pattern, and the driving frequency of the semiconductor chip, and the resistance value of the resistance unit 401 is changed. Noise can be reduced.
　なお、本発明は、同じ回路が複数配置されランダムにＨｉｇｈ信号とＬｏｗ信号が出力される入出力ブロックに対して適用することにより、同様の効果を得ることが出来る。そのため、外部からのＣｌｏｃｋ入力部や、同時動作台数の多いバッファ部、内部Ｃｌｏｃｋを発生するための論理部などに対しても適用することができる。 It should be noted that the same effect can be obtained by applying the present invention to an input / output block in which a plurality of the same circuits are arranged and a High signal and a Low signal are randomly output. Therefore, the present invention can also be applied to an external clock input unit, a buffer unit having a large number of simultaneous operations, a logic unit for generating an internal clock, and the like.
　また、本発明はＤＲＡＭ（Ｄｙｎａｍｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）、フラッシュメモリ、論理回路など多くの半導体に適用しても、同様の効果を得ることができる。 Further, the present invention can achieve the same effect when applied to many semiconductors such as a DRAM (Dynamic Random Access Memory), a flash memory, and a logic circuit.

Claims (11)

  1. 　入出力回路と、
    　前記入出力回路に動作電圧を供給する第１および第２の電源配線と、
    　前記第１の電源配線と前記第２の電源配線との間にて、直列に設けられた第１の容量素子と抵抗部と、を有し、
    　前記抵抗部は抵抗値が変更可能であることを特徴とする半導体チップ。     An input / output circuit;
    First and second power supply lines for supplying an operating voltage to the input / output circuit;
    A first capacitor element and a resistance unit provided in series between the first power supply wiring and the second power supply wiring;
    The resistance value of the resistance portion can be changed.
  2. 　請求項１に記載の半導体チップにおいて、
    　さらに、前記第１の電源配線と前記第２の電源配線との間にて、前記第１の容量素子よりも前記入出力回路から近い領域に設けられた第２の容量素子を、有することを特徴とする半導体チップ。     The semiconductor chip according to claim 1,
    And a second capacitive element provided in a region closer to the input / output circuit than the first capacitive element between the first power supply wiring and the second power supply wiring. A featured semiconductor chip.
  3. 　請求項１または２に記載の半導体チップにおいて、
    　前記抵抗部は、可変抵抗素子であることを特徴とする半導体チップ。     The semiconductor chip according to claim 1 or 2,
    The semiconductor chip according to claim 1, wherein the resistance portion is a variable resistance element.
  4. 　請求項１または２に記載の半導体チップにおいて、
    　前記抵抗部は、
    　直列に接続された複数の抵抗素子からなり、
    　前記複数の抵抗素子の少なくとも１つは短絡可能であることを特徴とする半導体チップ。     The semiconductor chip according to claim 1 or 2,
    The resistance portion is
    It consists of multiple resistance elements connected in series,
    A semiconductor chip, wherein at least one of the plurality of resistance elements can be short-circuited.
  5. 　請求項１または２に記載の半導体チップにおいて、
    　前記抵抗部は、
    　直列に接続された複数の抵抗素子と、
    　各々が前記複数の抵抗素子に対応して設けられ、対応する抵抗素子と並列に接続された複数のＭＯＳスイッチと、からなることを特徴とする半導体チップ。     The semiconductor chip according to claim 1 or 2,
    The resistance portion is
    A plurality of resistance elements connected in series;
    A semiconductor chip comprising: a plurality of MOS switches each provided corresponding to the plurality of resistance elements and connected in parallel with the corresponding resistance elements.
  6. 　請求項４または５に記載の半導体チップにおいて、
    　前記複数の抵抗素子の抵抗値は、２のべき乗の比で変化するそれぞれ異なる値であることを特徴とする半導体チップ。     The semiconductor chip according to claim 4 or 5,
    The semiconductor chip according to claim 1, wherein the resistance values of the plurality of resistance elements are different values that change at a power-of-two ratio.
  7. 　第１の電源配線と、
    　第２の電源配線と、
    　前記第１及び第２の電源配線との間に設けられると共に入出力パッドに接続された入出力回路と、
    　前記第１の電源配線と前記第２の電源配線との間に直列に接続された第１の容量素子と、抵抗素子とを備えることを特徴とする半導体装置。     A first power supply wiring;
    A second power supply wiring;
    An input / output circuit provided between the first and second power supply wirings and connected to the input / output pad;
    A semiconductor device comprising: a first capacitor element connected in series between the first power supply wiring and the second power supply wiring; and a resistance element.
  8. 　前記第１の電源配線と前記第２の電源配線との間に接続された第２の容量素子をさらに備えることを特徴とする請求項７記載の半導体装置。 8. The semiconductor device according to claim 7, further comprising a second capacitor element connected between the first power supply wiring and the second power supply wiring.
  9. 　前記抵抗素子は、抵抗値を変更することができる可変抵抗素子であることを特徴とする請求項７記載の半導体装置。 8. The semiconductor device according to claim 7, wherein the resistance element is a variable resistance element capable of changing a resistance value.
  10. 　前記抵抗素子は、タングステン配線によって構成されていることを特徴とする請求項７記載の半導体装置。 8. The semiconductor device according to claim 7, wherein the resistance element is made of tungsten wiring.
  11. 　前記抵抗素子は、複数のタングステン配線を前記タングステン配線の上層に形成された配線層の接続パターンによって抵抗値を変更するように形成されていることを特徴とする請求項７記載の半導体装置。 8. The semiconductor device according to claim 7, wherein the resistance element is formed so as to change a resistance value according to a connection pattern of a wiring layer formed on the tungsten wiring on a plurality of tungsten wirings.
PCT/JP2014/053916 2013-02-26 2014-02-19 Semiconductor chip WO2014132861A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002222918A (en) * 2001-01-23 2002-08-09 Nec Microsystems Ltd Semiconductor device
JP2011061114A (en) * 2009-09-14 2011-03-24 Elpida Memory Inc Method of manufacturing semiconductor device
JP2012123881A (en) * 2010-12-10 2012-06-28 Elpida Memory Inc Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002222918A (en) * 2001-01-23 2002-08-09 Nec Microsystems Ltd Semiconductor device
JP2011061114A (en) * 2009-09-14 2011-03-24 Elpida Memory Inc Method of manufacturing semiconductor device
JP2012123881A (en) * 2010-12-10 2012-06-28 Elpida Memory Inc Semiconductor device

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