WO2014130874A1 - Circuit de pilotage - Google Patents

Circuit de pilotage Download PDF

Info

Publication number
WO2014130874A1
WO2014130874A1 PCT/US2014/017805 US2014017805W WO2014130874A1 WO 2014130874 A1 WO2014130874 A1 WO 2014130874A1 US 2014017805 W US2014017805 W US 2014017805W WO 2014130874 A1 WO2014130874 A1 WO 2014130874A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
signal
coupled
node
tap
Prior art date
Application number
PCT/US2014/017805
Other languages
English (en)
Inventor
Georgios KALOGERAKIS
Jason Y. MIAO
The' Linh Nguyen
Original Assignee
Finisar Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/774,817 external-priority patent/US8912827B2/en
Application filed by Finisar Corporation filed Critical Finisar Corporation
Publication of WO2014130874A1 publication Critical patent/WO2014130874A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]
    • H03K19/017527—Interface arrangements using a combination of bipolar and field effect transistors [BIFET] with at least one differential stage

Definitions

  • the pre and/or post cursor signal may be used as a wave-shaping signal that is a scaled version of a signal to shape the signal transmitted from the output node 204 to the load 260.
  • the pre and post cursor signals may assist in compensating for signal loss as a signal is transmitted from the output node 204 to the load 260.
  • the driver circuit 300 may have reduced power consumption as compared to known drivers that only drive approximately one-half of current on an output node to a load as discussed with respect to FIGS. 1 and 2.
  • the input node 402, the output node 404, the first circuit 420, the second circuit 410, and the delay circuit 440 can be similar to and/or correspond to the input node 202, the output node 204, the first circuit 210, the second circuit 220, and the delay circuit 240, respectively of FIG. 2.
  • the pre and post cursor signals may be used as wave-shaping signals to shape a signal transmitted from the output node 404 to a load.
  • the pre and post cursor signals may assist in compensating for signal loss or other losses or effects as the signal is transmitted from the output node 404 to the load.
  • the current summed at the intermediate node 416 may reduce the total current at the intermediate node 416 or increase the total current at the intermediate node 416.
  • applying the pre and/or post cursor signal to the driving circuit 700 may increase a voltage level at the intermediate node 416. As noted above with respect to FIG.
  • the transistors 312, 322, 411, 419, 421, 422, 423, 424, 682, 684, 692, 694, 782, 784, 792, and 794 and the transistors within the delay circuits 340, 440 in FIGS. 3 and 4 may be MOSFETs.
  • the transistors within the active devices 330, 430 may be BJTs.
  • FIGS. 3, 4, 6, and 7 depict the transistors as being n-channel transistors. P- channel transistors or some combination of n-channel and p-channel transistors may also be used. In some embodiments, additional active and/or passive circuit elements may be included in the driver circuits 300, 400, 600, and 700.
  • FIG. 8 is a perspective view of an example optoelectronic module 800 (hereinafter “module 800") that may include a driver circuit 822, arranged in accordance with at least some embodiments described herein.
  • the module 800 may be configured for use in transmitting and receiving optical signals in connection with a host device (not shown).
  • the module 800 may include, but is not limited to, a bottom housing 802; a receive port 804 and a transmit port 806, both defined in the bottom housing 802; a PCB 808 positioned within the bottom housing 802, the PCB 808 having a driver circuit 822 and a first circuit 820 positioned hereon; and a receiver optical subassembly (ROSA) 810 and a transmitter optical subassembly (TOSA) 812 also positioned within the bottom housing 802.
  • An edge connector 814 may be located on an end of the PCB 808 to enable the module 800 to electrically interface with the host device.
  • the PCB 808 facilitates electrical communication between the host device and the ROSA 810 and TOSA 812.
  • the module 800 may be configured in any of a variety of different form factors including, but not limited to, the Small Form-factor Pluggable (SFP), the enhanced Small Form-factor Pluggable (SFP+), the 10 Gigabit Small Form Factor Pluggable (XFP), the C Form-factor Pluggable (CFP) and the Quad Small Form-factor Pluggable (QSFP) multi-source agreements (MSAs).
  • SFP Small Form-factor Pluggable
  • SFP+ enhanced Small Form-factor Pluggable
  • XFP 10 Gigabit Small Form Factor Pluggable
  • CFP C Form-factor Pluggable
  • QSFP Quad Small Form-factor Pluggable multi-source agreements
  • the driver circuit 822 which may be similar to and/or correspond to the driver circuits 101, 201, 300, 400, 600, and/or 700 of FIGS. 1, 2, 3, 4, 6, or 7 respectively, and may be configured to drive electrical signals relayed to the PCB 808 through the electrical interface 816 to the host device.
  • the electrical signals may pass through the first circuit 820 before being driven by the driver circuit 822.
  • the first circuit 820 may be a clock and data recovery circuit.
  • the module 800 may omit the first circuit 820.
  • the driver circuit 820 may drive the electrical signals from the PCB 808 to the TOSA 812.
  • a driver circuit such as the driver circuits 101, 201, 300, 400, 600, or 700 of FIGS. 1, 2, 3, 4, 6, or 7 respectively may be incorporated into the ROSA 810 and may be used to drive electrical signals from the ROSA 810 through the electrical interface 816 to the PCB 808.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Amplifiers (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention porte sur un circuit qui peut comprendre un nœud d'entrée configuré pour recevoir un signal et un nœud de sortie configuré pour être couplé à une charge. Le circuit peut également comprendre un premier circuit couplé entre le nœud d'entrée et le nœud de sortie. Le premier circuit peut être configuré pour recevoir le signal et pour piloter le signal sur le nœud de sortie à une première tension. Le circuit peut également comprendre un dispositif actif couplé au nœud de sortie et un second circuit couplé au dispositif actif et au nœud d'entrée. Le second circuit peut être configuré pour recevoir le signal et pour piloter le signal sur le dispositif actif à une seconde tension. Le circuit peut également comprendre un circuit de prise configuré pour appliquer sélectivement une version modifiée du signal sur le signal piloté par le second circuit avant que le signal piloté par le second circuit atteigne le dispositif actif.
PCT/US2014/017805 2013-02-22 2014-02-21 Circuit de pilotage WO2014130874A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/774,817 2013-02-22
US13/774,817 US8912827B2 (en) 2012-07-09 2013-02-22 Driver circuit

Publications (1)

Publication Number Publication Date
WO2014130874A1 true WO2014130874A1 (fr) 2014-08-28

Family

ID=51391867

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2014/017805 WO2014130874A1 (fr) 2013-02-22 2014-02-21 Circuit de pilotage

Country Status (1)

Country Link
WO (1) WO2014130874A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020109527A1 (en) * 2000-06-02 2002-08-15 Enam Syed K. High-speed output driver
JP2005027178A (ja) * 2003-07-04 2005-01-27 Toshiba Corp 遅延回路
US20090231015A1 (en) * 2008-03-13 2009-09-17 Mitsubishi Electric Corporation Driver circuit
US20100109794A1 (en) * 2007-07-12 2010-05-06 Martin Groepl Circuit and method for driving at least one differential line
JP2012105135A (ja) * 2010-11-11 2012-05-31 Renesas Electronics Corp 差動出力回路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020109527A1 (en) * 2000-06-02 2002-08-15 Enam Syed K. High-speed output driver
JP2005027178A (ja) * 2003-07-04 2005-01-27 Toshiba Corp 遅延回路
US20100109794A1 (en) * 2007-07-12 2010-05-06 Martin Groepl Circuit and method for driving at least one differential line
US20090231015A1 (en) * 2008-03-13 2009-09-17 Mitsubishi Electric Corporation Driver circuit
JP2012105135A (ja) * 2010-11-11 2012-05-31 Renesas Electronics Corp 差動出力回路

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