WO2014111969A1

WO2014111969A1 - Design method, program, memory medium, and designing device

Info

Publication number: WO2014111969A1
Application number: PCT/JP2013/000139
Authority: WO
Inventors: 誠之守屋
Original assignee: 株式会社図研
Priority date: 2013-01-16
Filing date: 2013-01-16
Publication date: 2014-07-24
Also published as: JP5922802B2; JPWO2014111969A1

Abstract

This design method for designing a circuit board having a PLD and an IC disposed thereon by using a computer includes: an acquisition step for acquiring an arrange ment of the PLD and the IC on the circuit board, and a design standard for the circuit board; and a determination step for determining a pin assignment for the PLD according to the arrangement and the design standard for the circuit board as acquired in the acquisition step.

Description

DESIGN METHOD, PROGRAM, MEMORY MEDIUM, AND DESIGN DEVICE

The present invention relates to a design method for designing a board on which a PLD and an IC are arranged, a program for causing a computer to execute the design method, a memory medium storing the program, and a design apparatus for designing the board.

PLDs (Programmable Logic Devices) such as FPGA (Field Programmable Gate Array) and CPLD (Complex PLD) are known. A PLD is a device that allows a user to set pin assignments and functions. A PLD can be mounted on a substrate such as a printed wiring board together with an IC (Integrated Circuit) to constitute various electronic circuits.

A CAD (Computer Aided Design) system is used to design a wiring pattern on a board such as a printed wiring board on which a PLD and an IC are mounted. Conventionally, after the pin assignment of the PLD to be mounted on the board is determined, the wiring of the board is designed using a CAD system.

JP 2001-92857 A

However, if the wiring design of the board is performed after the pin assignment of the PLD is determined, the degree of freedom of the wiring design is constrained by the pin assignment, so that a poor quality wiring pattern can be obtained. Here, the poor quality wiring pattern is, for example, (a) a wiring pattern having a long wiring length, (b) a wiring pattern having many intersections, and / or (c) a wiring pattern having a large number of wiring layers. FIG. 15 illustrates a poor quality wiring pattern WP. A circle drawn in the PLD 210 indicates a pin of the PLD 210. The pins of the PLD 210 may include user I / O pins, GND pins (ground pins), I / O drive power pins for each bank, and internal power pins. In the example shown in FIG. 15, a PLD 210 and a plurality of ICs 221 to 228 are mounted on a substrate 200 such as a printed circuit board. The wiring pattern WP connecting the PLD 210 and the plurality of ICs 221 to 228 has a long wiring length and many intersections.

The present invention has been made with the above problem recognition as an opportunity, and an object thereof is to provide a technique advantageous in improving the quality of wiring.

A first aspect of the present invention relates to a design method for designing a board on which a PLD and an IC are arranged by a computer. The design method includes an arrangement of the PLD and the IC on the board, and a design standard for the board. And a determination step of determining pin assignment of the PLD in accordance with the arrangement acquired in the acquisition step and the design criteria of the substrate.

The second aspect of the present invention relates to a program, and the program causes a computer to execute the design method according to the first aspect.

A third aspect of the present invention relates to a memory medium, and the memory medium stores a program that causes a computer to execute the design method according to the first aspect.

A fourth aspect of the present invention relates to a design apparatus for designing a board on which a PLD and at least one IC are arranged, and the design apparatus determines the arrangement of the PLD and the IC on the board and the design criteria of the board. An acquisition unit for acquiring, and a determination unit for determining the pin assignment of the PLD according to the arrangement acquired by the acquisition unit and the design criteria of the substrate.

According to the present invention, a technique advantageous for improving the quality of wiring is provided.

The figure which shows schematic structure of the design apparatus of one Embodiment of this invention. The flowchart explaining the design method of one Embodiment of this invention. The figure explaining the design method of one embodiment of this invention. The figure explaining the design method of one embodiment of this invention. The figure explaining the design method of one embodiment of this invention. The figure explaining the design method of one embodiment of this invention. The figure explaining the design method of one embodiment of this invention. The flowchart explaining the wiring process in the design method of one embodiment of this invention. The figure explaining the wiring process in the design method of one Embodiment of this invention. The figure explaining the wiring process in the design method of one Embodiment of this invention. The figure explaining the wiring process in the design method of one Embodiment of this invention. The figure explaining the wiring process in the design method of one Embodiment of this invention. The figure explaining the wiring process in the design method of one Embodiment of this invention. The figure which illustrates the user interface provided through a display. The figure which illustrates the user interface provided through a display. The figure which shows a modification. The figure which shows a modification. The figure which shows a modification. The figure which shows a modification. The figure which shows a modification. The figure which shows a modification. The figure which shows a modification. The figure which shows a modification. The figure which shows a modification. The figure which illustrates the wiring pattern of a board | substrate.

Hereinafter, the present invention will be described through exemplary embodiments thereof with reference to the accompanying drawings.

In this specification, the term PLD (Programmable Logic Device) includes FPGA (Field Programmable Gate Array) and CPLD (Complex PLD).

FIG. 1 shows a schematic configuration of a design apparatus 100 according to one embodiment of the present invention. The design apparatus 100 can be typically configured by incorporating the program 50 into the computer 10. The computer 10 can include a CPU 15, a display 16, a RAM 17, a communication interface 18, a media drive 19, and an HDD (hard disk drive) 14. A program 50 can be stored in the HDD 14. The program 50 may be stored in a medium (memory medium) 60 such as a CD, provided to the computer 10, and installed in the computer 10. The computer 10 may include input devices such as a touch pad 11, a keyboard 12, and a mouse 13, for example.

FIG. 2 is a flowchart illustrating a design method according to an embodiment of the present invention that is executed by the design apparatus 100. The design method shown in this flowchart can be defined by the program 50. The design method shown in FIG. 2 is a method of designing a board on which a PLD and an IC are arranged by a computer. The design method includes an acquisition step S100 for acquiring a layout of PLDs and ICs on a substrate and a design standard of the substrate, and a pin of the PLD according to the layout and the design standard of the substrate acquired in the acquisition step S100. Determining step S110 for determining allocation. The design method may further include a wiring step S120 for generating a wiring pattern for connecting the pins of the PLD and the pins of the IC for which the pin assignment has been determined in the determination step S110. The design apparatus 100 can be grasped as an apparatus including an acquisition unit that executes the acquisition step S100 and a determination unit that executes the determination step S110.

The following (1) to (5) are examples of design criteria acquired in the acquisition step S199. The design criteria can be provided to the design apparatus 100 via, for example, input devices such as the touch pad 11, the keyboard 12, and the mouse 13, the communication interface 18 (that is, other apparatuses), or the media drive 19.

(1) The first design criterion is that the pin assignment cannot be changed in the determination step S110 for power supply pins, ground pins, reserved pins, pins for which replacement is prohibited, and clock signal pins. including.

(2) The second design criterion is that when the voltage of the first bank is different from the voltage of the second bank, the signal assigned to the pin of the first bank is applied to the pin of the second bank. It cannot be assigned, and includes a restriction that a signal assigned to a pin of the second bank cannot be assigned to a pin of the first bank. In this case, when the voltage of the first bank and the voltage of the second bank are the same, the second design criterion is that the signal assigned to the pin of the first bank is The signal assigned to the pin of the second bank can be assigned to the pin of the first bank.

Alternatively, the second design criteria may be that the signal assigned to the first bank pin is the second bank voltage regardless of whether the first bank voltage and the second bank voltage are the same or different. It includes a restriction that it cannot be assigned to a bank pin, and a signal assigned to a second bank pin cannot be assigned to a first bank pin. In other words, the second design standard includes a constraint that the PLD pin assignment can be changed only within each bank.

(3) The third design criterion includes a constraint that pin pairs to which differential signals are assigned are limited to adjacent pin pairs.

(4) The fourth design standard includes a restriction that a pin to which a signal should be assigned can be changed only within a swap group specified by the user. For example, if the pins A1, A2, and A3 are the swap group A and the pins B1, B2, and B3 are the swap group B, the signal assignment is converted in the swap group A (pins A1, A2, and A3). In the swap group B (pins B1, B2, and B3), the signal assignment can be converted, but the signal assignment cannot be changed between the swap group A and the swap group B. Is.

(5) The fifth design standard includes a restriction that signal allocation can be changed only between pins having common I / O attributes.

The determination step S110 includes, for example, a provisional determination step S112 that provisionally determines the pin assignment so that the distances between the plurality of pins of the PLD and the plurality of pins of the IC to be connected to each of them satisfy the distance criterion, In step S112, when a plurality of signals are assigned to one of the plurality of pins of the PLD, the pin assignment is performed such that the plurality of signals are assigned to different pins among the plurality of pins of the PLD. If there is an intersection in the ratsnest between the PLD and the IC according to the pin assignment modified in the first modification step S114, the pin assignment is performed so that the intersection is eliminated. 2nd correction process S115 which corrects.

Hereinafter, the design method shown in FIG. 2 will be described more specifically. FIG. 3 schematically shows the substrate 200 before the design according to the design method shown in FIG. 2 is made. The substrate 200 is, for example, a printed wiring board, and the PLD 210 and the ICs 221 to 228 are arranged on the substrate 200. The PLD 210 has a plurality of pins shown in a circle. The plurality of pins of the PLD 210 include, for example, a user I / O pin indicated by a white circle, a GND pin (ground pin) indicated by a black circle, and an I / O for each bank indicated by a hatched circle. O drive power supply pins and internal power supply pins indicated by circles with cross-hatching may be included.

The PLD 210 can include, for example, a plurality of banks (I / O banks) BANK0 to BANK4. A bank (I / O bank) means an area in which pins having common interface specifications are arranged. However, interface specifications may be common even in different banks. In one example, the power supply voltage of the bank BANK0 may be 2.5V, the power supply voltage of the bank BANK1 may be 1.2V, the power supply voltage of the bank BANK3 may be 2.5V, and the power supply voltage of the bank BANK4 may be 2.5V.

In FIG. 3, the correspondence relationship between the pins of the PLD 210 and the pins of the plurality of ICs 221 to 228 is represented by a ratsnest RN drawn by dotted lines. The two pins connected by the ratsnest RN should be connected to each other by the wiring pattern.

In the acquisition step S100, the design apparatus 100 acquires the arrangement of the PLD 210 and the ICs 221 to 228 on the substrate 200 and the design standard of the substrate 200. The arrangement of the PLD 210 and the ICs 221 to 228 on the substrate 200 can include the coordinates of the PLD 210 and the ICs 221 to 228 on the substrate 200, for example.

In the determination step S110, the design apparatus 100 determines the pin assignment of the PLD 210 according to the arrangement acquired in the acquisition step S100 and the design standard of the substrate 200. More specifically, in the determination step S110, the design apparatus 100 may determine the pin assignment so that the distances between the plurality of pins of the PLD 210 and the plurality of pins of the IC to be connected to each of them satisfy the distance constraint. . Here, the distance constraint is a constraint that requires, for example, that the distance from the connection target pin in the PLD 210 is equal to or less than a predetermined distance, for example, that the distance from the connection target pin in the PLD 210 is the shortest distance. . FIG. 6 schematically shows the substrate 200 after the pin assignment is determined in the determination step S110.

The determination step S110 can include a provisional determination step S112, a first correction step S114, and a second correction step S116. FIG. 4 schematically shows the substrate 200 after the provisional determination step S112. In this example, in the provisional determination step S112, the pin assignment of the PLD 210 is performed so as to satisfy the distance constraint that the distance between the plurality of pins of the PLD 210 and the plurality of pins of the ICs 221 to 28 to be connected to them is the shortest distance. Is provisionally determined. When the pin assignment of the PLD 210 is provisionally determined under such a distance constraint, as illustrated in FIG. 4, one pin of the PLD 210 overlaps two or more of the plurality of pins of the ICs 221 to 228. Thus, the pin assignment of the PLD 210 can be provisionally determined so as to be connected. That is, the state illustrated in FIG. 4 is a state in which a plurality of signals are assigned to one pin of the PLD 210.

In the first modification step S114, as illustrated in FIG. 5, the design apparatus 100 may assign a plurality of signals assigned to one pin of the PLD 210 to different pins among the plurality of signals of the PLD 210. Next, the pin assignment of the PLD 210 is corrected. Specifically, in the first correction step S114, a signal other than one signal among a plurality of signals assigned to one pin is assigned to another pin. For example, in the first modification step S114, the design apparatus 100 is adjacent to a pin to which the one signal is assigned, except for one signal among a plurality of signals assigned to one pin. Assign to a pin.

Here, an intersection may occur in the ratsnest RN between the PLD 210 and the ICs 221 to 28 according to the pin assignment of the PLD 210 modified in the first modification step S114. Therefore, in the second correction step S116, as illustrated in FIG. 6, the pin assignment of the PLD 210 is corrected so that the intersection does not exist. In order to eliminate the intersection, for example, signals assigned to the pins related to the intersection among the plurality of pins of the PLD 210 may be exchanged. For example, if the ratsnest connected to pin A of PLD 210 and the ratsnest connected to pin B of PLD 210 intersect, the signal assigned to pin A and the signal assigned to pin B are Replace it.

Note that when the execution of the provisional determination step S112 does not cause an error such that a plurality of signals are assigned to one pin of the PLD 210, the first correction step S114 is unnecessary, and the provisional determination step S112 and / or When the crossing of the rats nest RN does not occur due to the execution of the first correction step S114, the second correction step S116 is not necessary.

When the first correction step S114 is not performed, in the second correction step S116, when there is an intersection in the ratsnest RN between the PLD 210 and the ICs 221 to 228 according to the pin assignment of the PLD 210 determined in the provisional determination step S112, Modify the pin assignment of PLD 210 so that there are no crossings.

In the wiring step S120, the design apparatus 100 generates a wiring pattern WP for connecting two pins connected to each rats nest RN (that is, two pins to be connected) as illustrated in FIG. . The wiring pattern WP illustrated in FIG. 7 has a shorter wiring length and fewer intersections than the wiring pattern WP illustrated in FIG. That is, the wiring pattern WP illustrated in FIG. 7 has higher wiring quality than the wiring pattern WP illustrated in FIG. The PLD 210 is programmed according to the pin assignment determined in the determination step S110.

As described above, the wiring pattern WP that connects the pins of the PLD 210 and the pins of the ICs 221 to 228 by determining the arrangement of the PLD 210 and the ICs 221 to 228 on the substrate 200 and the pin assignment of the PLD 210 according to the design criteria of the substrate 200. Can enhance the quality.

Hereinafter, a more specific processing example of the wiring step S120 will be described with reference to FIG. 8 and FIGS. 9A to 9E. 9A to 9E, the squares indicate the pins of the ICs 221 to 228, and the circles indicate the pins of the PLD 210.

First, in step S210, as illustrated in FIG. 9A, the design apparatus 100 divides a wiring region (a region where wiring can be performed) on the substrate 200 into a plurality of divided regions DR. Next, in step S220, the design apparatus 100 selects a pin pair to be connected. Here, as an example, a pin pair to be connected is composed of a pin P1 which is one of a plurality of pins of the ICs 221 to 228 and a pin P2 which is one of a plurality of pins of the PLD 210. A case where the route of the wiring pattern is determined toward P2 will be described. The pin P1 is a connection source pin of the wiring pattern, and the pin P2 is a connection destination pin of the wiring pattern.

In step S230, as illustrated in FIG. 9B, the design apparatus 100 determines a divided region DR1 that is adjacent to the connection source pin P1 and exists in the direction of the connection destination pin P2. Here, the divided region DR1 is determined from the region DR in which no wiring pattern exists. In step S240, the design apparatus 100 arranges the wiring pattern WP in the divided region DR1, as illustrated in FIG. 9C.

In step S250, as illustrated in FIG. 9D, the design apparatus 100 determines a divided region DR2 that is adjacent to the divided region DR1 in which the wiring pattern WP is disposed immediately before and exists in the direction of the connection destination pin P2. Here, the divided region DR2 is determined from the region DR in which no wiring pattern exists. In step S260, the design apparatus 100 arranges the wiring pattern WP in the divided region DR2, as illustrated in FIG. 9E.

In step S270, the design apparatus 100 determines whether or not the connection by the wiring pattern WP between the selected pin pair (pin P1, pin P2) is completed. If not, the design apparatus 100 performs step S250 and step S260. Is additionally performed, and when completed, the process proceeds to step S280.

In step S280, the design apparatus 100 determines whether or not the connection between all the pin pairs has been completed. If the connection has not been completed, the design apparatus 100 returns to step S220 and executes the same processing as described above for the new pin pair. If completed, the process shown in FIG. 8 ends.

The user interface provided through the display 16 will be exemplarily described with reference to FIGS. The design apparatus 100 displays the substrate 200 under design on the display 16. In the example illustrated in FIGS. 10 and 11, a plurality of PLDs (FPGA1, FPGA2, FPGA3, FPGA4) are mounted on the substrate 200. Each PLD (FPGA1, FPGA2, FPGA3, FPGA4) may have a plurality of banks (I / O banks).

The design device 100 (or the program 50) can display the command menu 310 on the display 16. The command menu 310 includes, for example, a “pin assignment optimization (entire part)” command, a “pin assignment optimization (within I / O bank)” command, an “auto wiring” command, and a “pin assignment optimization / wiring”. Contains commands.

The “optimization of pin assignment (whole component)” command is a command for instructing the optimization (change) of pin assignment of the PLD (FPGA in this example) for the entire pin in each PLD. .

The “Optimize pin assignment (in I / O bank)” command executes optimization (change) of pin assignment of PLD (FPGA in this example) in each bank (I / O bank) of each PLD. Is a command for instructing.

The “automatic wiring” command is a command for instructing automatic wiring according to the current pin assignment of the PLD (FPGA in this example).

The “pin assignment optimization / wiring” command is a command for instructing to perform optimization (change) of pin assignment of PLD (FPGA in this example) and automatic wiring.

The “pin assignment optimization / wiring” command can be provided with a submenu 320. When there are a plurality of PLDs (FPGAs in this example), the submenu 320 allows the user to specify a target for which pin assignment is optimized (changed). In addition, the submenu 320 allows the user to execute a mode in which the pin assignment optimization (change) of the PLD (FPGA in this example) is performed on the entire pins of each PLD, or in the PLD (FPGA in this example). A mode in which optimization (change) of pin assignment is executed in each bank (I / O bank) of each PLD can be selected.

In the submenu 320, a submenu 330 can be further provided. The user can designate a bank (I / O bank) to which pin assignment is to be performed by using the submenu 330.

Hereinafter, modifications of the above embodiment will be described with reference to FIGS. 12A to 12C, 13A to 13C, and 14A to 14C. In the above embodiment, the pin assignment of the PLD is determined or optimized (changed) in a state where there is no wiring pattern for connecting the PLD and the IC, but FIGS. 12 to A to 12C, As illustrated in 13A to 13C and 14A to 14C, the pin assignment of the PLD 210 is determined or optimized (changed) in a state where the wiring pattern WP0 for connecting them partially exists between the PLD 210 and the IC 220. May be.

In the example shown in FIGS. 12A, 13A, and 14A, the wiring pattern WP0 partially extends between the pin of the IC 220 and the pin of the PLD 210, but the wiring pattern WP0 does not connect the pin of the IC 220 and the pin of the PLD 210. . In the states shown in FIGS. 12A, 13A, and 14A, the ratsnest RN that connects the pins of the IC 220 and the pins of the PLD 210 intersect with each other. Crossing occurs in the pattern.

Therefore, as in the above-described embodiment, the design apparatus 100 acquires the arrangement of the PLD 210 and the IC 220 on the substrate and the design standard of the substrate in the acquisition step S100. In the determination step S110, the design apparatus 100 determines the pin assignment of the PLD 210 according to the arrangement acquired in the acquisition step S100 and the design criteria of the substrate. Here, as illustrated in FIGS. 12B, 13B, and 14B, the pin assignment of the PLD 210 may be performed such that the intersection of the ratsnest RN is eliminated or the intersection of the ratsnest RN is decreased.

In S120, as illustrated in FIGS. 12C, 13C, and 14C, the design apparatus 100 generates a wiring pattern WP for connecting the pins of the PLD 210 and the pins of the IC 220 whose pin assignments have been determined in the determination step S110. To do. Here, the wiring pattern WP is typically generated so as to use the wiring pattern WP0 in consideration of the already existing wiring pattern WP0.

Claims

A design method for designing a substrate on which a PLD and an IC are arranged by a computer,
An acquisition step of acquiring the placement of the PLD and the IC on the substrate and the design criteria of the substrate;
Determining a pin assignment of the PLD according to the arrangement acquired in the acquisition step and the design criteria of the substrate,
A design method characterized by that.
2. The design method according to claim 1, further comprising a wiring step of generating a wiring pattern for connecting the pin of the PLD and the pin of the IC for which the pin assignment has been determined in the determination step.
In the determining step, the pin assignment is determined so that distances between a plurality of pins of the PLD and a plurality of pins of the IC to be connected to the pins satisfy a distance constraint,
The design method according to claim 1, wherein:
The determination step includes
A tentative determination step of tentatively determining the pin assignment such that distances between the plurality of pins of the PLD and the plurality of pins of the IC to be connected to the pins satisfy a distance constraint;
In the provisional determination step, when a plurality of signals are assigned to one of the plurality of pins of the PLD, the plurality of signals are assigned to different pins among the plurality of pins of the PLD. Modifying the pin assignment,
The design method according to claim 1 or 2, wherein
The determination step includes
A tentative determination step of tentatively determining the pin assignment such that distances between the plurality of pins of the PLD and the plurality of pins of the IC to be connected to the pins satisfy a distance constraint;
Modifying the pin assignment to eliminate the intersection when there is an intersection in the ratsnest between the PLD and the IC according to the pin assignment determined in the provisional decision step,
The design method according to claim 1, wherein:
The determination step includes
A provisional determination step of tentatively determining the pin assignment such that distances between the plurality of pins of the PLD and the plurality of pins of the IC to be connected to the pins each satisfy a distance criterion;
When a plurality of signals are assigned to one of the plurality of pins of the PLD in the provisional determination step, the plurality of signals are assigned to different pins among the plurality of pins of the PLD. A first modification step for modifying the pin assignment;
A second modification step of modifying the pin assignment so that the intersection is eliminated when there is an intersection in a ratsnest between the PLD and the IC that follows the pin assignment modified in the first modification step; Including,
The design method according to claim 1, wherein:
A plurality of PLDs are disposed on the substrate,
The acquisition step allows a user to select a PLD from which the pin assignment is to be determined through the acquisition step and the determination step from among the plurality of PLDs, and acquires the arrangement of the PLD selected by the user on the substrate.
The design method according to any one of claims 1 to 6, wherein:
The PLD includes a plurality of banks, and the design criteria includes a constraint that the pin assignment can be changed only within each bank.
The design method according to any one of claims 1 to 7, wherein:
A program for causing a computer to execute the design method according to any one of claims 1 to 8.
A memory medium storing a program for causing a computer to execute the design method according to any one of claims 1 to 8.
A design apparatus for designing a substrate on which a PLD and at least one IC are arranged,
An acquisition unit for acquiring the placement of the PLD and the IC on the substrate and the design criteria of the substrate;
A determination unit that determines the pin assignment of the PLD according to the arrangement acquired by the acquisition unit and the design criteria of the substrate,
A design device characterized by that.