WO2014111637A3 - Procédé de fabrication d'un réseau de conducteurs sur un substrat au moyen de copolymères à blocs - Google Patents

Procédé de fabrication d'un réseau de conducteurs sur un substrat au moyen de copolymères à blocs Download PDF

Info

Publication number
WO2014111637A3
WO2014111637A3 PCT/FR2014/000010 FR2014000010W WO2014111637A3 WO 2014111637 A3 WO2014111637 A3 WO 2014111637A3 FR 2014000010 W FR2014000010 W FR 2014000010W WO 2014111637 A3 WO2014111637 A3 WO 2014111637A3
Authority
WO
WIPO (PCT)
Prior art keywords
mask
holes
substrate
producing
patterns
Prior art date
Application number
PCT/FR2014/000010
Other languages
English (en)
Other versions
WO2014111637A2 (fr
Inventor
Jérôme BELLEDENT
Original Assignee
Commissariat À L' Énergie Atomique Et Aux Énergies Alternatives
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat À L' Énergie Atomique Et Aux Énergies Alternatives filed Critical Commissariat À L' Énergie Atomique Et Aux Énergies Alternatives
Priority to EP14704379.8A priority Critical patent/EP2946401A2/fr
Priority to US14/760,382 priority patent/US9564328B2/en
Publication of WO2014111637A2 publication Critical patent/WO2014111637A2/fr
Publication of WO2014111637A3 publication Critical patent/WO2014111637A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

Le procédé de fabrication de motifs en premier matériau comporte les étapes suivantes : - prévoir un substrat (1) recouvert par une couche de couverture (2), - former un premier masque au moyen d'une structure auto-organisée de copolymères à blocs, le premier masque comportant des premiers motifs, - déposer et insoler une résine (9) pour former un masque intermédiaire sur le premier masque, le masque intermédiaire recouvrant une partie des premiers motifs formés dans le premier masque et comportant des deuxièmes trous faisant face aux premiers trous, - graver la couche de couverture (2) à travers les premiers et deuxièmes trous se faisant face pour former des troisièmes trous (12), - remplir les troisièmes trous (12) par un premier matériau pour former les motifs en premier matériau.
PCT/FR2014/000010 2013-01-18 2014-01-17 Procédé de fabrication d'un réseau de conducteurs sur un substrat au moyen de copolymères à blocs WO2014111637A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP14704379.8A EP2946401A2 (fr) 2013-01-18 2014-01-17 Procédé de fabrication d'un réseau de conducteurs sur un substrat au moyen de copolymères à blocs
US14/760,382 US9564328B2 (en) 2013-01-18 2014-01-17 Method for fabricating a template of conductors on a substrate by means of block copolymers

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1300113A FR3001306A1 (fr) 2013-01-18 2013-01-18 Procede de fabrication d'un reseau de conducteurs sur un substrat au moyen de copolymeres a blocs
FR1300113 2013-01-18

Publications (2)

Publication Number Publication Date
WO2014111637A2 WO2014111637A2 (fr) 2014-07-24
WO2014111637A3 true WO2014111637A3 (fr) 2014-11-13

Family

ID=49322404

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2014/000010 WO2014111637A2 (fr) 2013-01-18 2014-01-17 Procédé de fabrication d'un réseau de conducteurs sur un substrat au moyen de copolymères à blocs

Country Status (4)

Country Link
US (1) US9564328B2 (fr)
EP (1) EP2946401A2 (fr)
FR (1) FR3001306A1 (fr)
WO (1) WO2014111637A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10056265B2 (en) 2016-03-18 2018-08-21 Taiwan Semiconductor Manufacturing Co., Ltd. Directed self-assembly process with size-restricted guiding patterns
CN110828466B (zh) * 2019-11-11 2022-03-29 上海华力微电子有限公司 字线制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070224819A1 (en) * 2006-03-23 2007-09-27 Micron Technology, Inc. Topography directed patterning
US20090236309A1 (en) * 2008-03-21 2009-09-24 Millward Dan B Thermal Anneal of Block Copolymer Films with Top Interface Constrained to Wet Both Blocks with Equal Preference
US20110008956A1 (en) * 2009-07-10 2011-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. Self-assembly pattern for semiconductor integrated circuit

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56137627A (en) * 1980-03-28 1981-10-27 Nec Corp Pattern forming
FR2925746B1 (fr) 2007-12-21 2010-01-01 Commissariat Energie Atomique Dispositif d'affichage comportant des filtres colores et des elements photoemissifs alignes electroniquement
FR2960657B1 (fr) 2010-06-01 2013-02-22 Commissariat Energie Atomique Procede de lithographie a dedoublement de pas
FR2960700B1 (fr) 2010-06-01 2012-05-18 Commissariat Energie Atomique Procede de lithographie pour la realisation de reseaux de conducteurs relies par des vias
US8673541B2 (en) 2010-10-29 2014-03-18 Seagate Technology Llc Block copolymer assembly methods and patterns formed thereby
US8835082B2 (en) * 2012-07-31 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method and system for E-beam lithography with multi-exposure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070224819A1 (en) * 2006-03-23 2007-09-27 Micron Technology, Inc. Topography directed patterning
US20090236309A1 (en) * 2008-03-21 2009-09-24 Millward Dan B Thermal Anneal of Block Copolymer Films with Top Interface Constrained to Wet Both Blocks with Equal Preference
US20110008956A1 (en) * 2009-07-10 2011-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. Self-assembly pattern for semiconductor integrated circuit

Also Published As

Publication number Publication date
EP2946401A2 (fr) 2015-11-25
FR3001306A1 (fr) 2014-07-25
US20150340232A1 (en) 2015-11-26
US9564328B2 (en) 2017-02-07
WO2014111637A2 (fr) 2014-07-24

Similar Documents

Publication Publication Date Title
WO2012047042A3 (fr) Procédé de formation d'un micromotif et procédé de formation d'un transistor à microcanal et d'un transistor électroluminescent à microcanal l'utilisant
WO2012057517A3 (fr) Dispositif à semi-conducteur composite et procédé de fabrication d'un semi-conducteur composite
WO2015195178A3 (fr) Intégration de monolithes polymères poreux fabriqués ex situ dans des puces fluidiques
WO2013049042A3 (fr) Structures de nanofils en coalescence avec lacunes interstitielles et procédé pour leur fabrication
WO2014112954A8 (fr) Substrat pour boîtier de semi-conducteur et méthode de formation de celui-ci
WO2012169550A9 (fr) Stratifié à motifs de feuille de métal, stratifié de feuille de métal, substrat de stratifié de feuille de métal, module de cellule solaire et procédé de fabrication de stratifié à motifs de feuille de métal
EP2645415A3 (fr) Cadre de connexion, dispositif semi-conducteur et procédé de fabrication du cadre de connexion
WO2013033273A3 (fr) Procédé et appareil de fabrication 3d
MY184096A (en) Method and apparatus for forming backside die planar devices and saw filter
EP2680331A3 (fr) Élément semi-conducteur recouvert d'une couche d'encapsulation, son procédé de production et dispositif semi-conducteur
SG194478A1 (en) Out-of-plane spacer defined electrode
SG169948A1 (en) Reliable interconnect for semiconductor device
JP2014011456A5 (fr)
TW200943473A (en) Method for fabricating pitch-doubling pillar structures
WO2009057927A3 (fr) Boîtier pour dispositif à semi-conducteur et procédé de mise en boîtier de celui-ci
WO2013003522A3 (fr) Substrat semi-conducteur et procédé de formation de celui-ci
SG10201401166YA (en) Integrated circuit packaging system with embedded pad on layered substrate and method of manufacture thereof
WO2015187210A3 (fr) Isolation active par entretoise pour un dispositif à circuit intégré
WO2014042779A3 (fr) Revêtement de couche mince poreuse conforme et procédé de fabrication
WO2012045511A3 (fr) Procédé de fabrication d'un film en silicone, film en silicone et composant semi-conducteur optoélectronique muni d'un film en silicone
FR3014876B1 (fr) Procede de realisation d'un film de copolymere a blocs sur un substrat
PT3875248T (pt) Método para produzir uma estrutura tridimensional numa superfície de um substrato plano
WO2014089557A3 (fr) Dispositif photovoltaïque et procédé de fabrication
EP2750211A3 (fr) Élément semi-conducteur optique recouvert d'une couche d'encapsulation, son procédé de production et dispositif semi-conducteur
EP2565948A3 (fr) Procédé d'encapsulation d'un dispositif de diode électroluminescente

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14704379

Country of ref document: EP

Kind code of ref document: A2

WWE Wipo information: entry into national phase

Ref document number: 2014704379

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 14760382

Country of ref document: US