WO2014110701A1

WO2014110701A1 - Independent active member and functional active member assembly module and member disassembly method

Info

Publication number: WO2014110701A1
Application number: PCT/CN2013/001370
Authority: WO
Inventors: 龙建
Original assignee: Long Jian
Priority date: 2013-01-18
Filing date: 2013-11-11
Publication date: 2014-07-24
Also published as: CN103473032B; CN103473032A

Abstract

Provided are an independent active member and functional active member assembly module and member disassembly method, the independent active member assembly module being set P=｛a first layer active member, a second layer active member subset… an n-th layer active member subset｝，wherein n≥2; each active member in the n-th layer active member subset is assembled based on an n-th layer virtual message bus to obtain a single active member in the n-1-th layer active member subset; the same process is followed until each active member in the second layer active member subset is assembled based on a second layer virtual message bus to obtain the first layer active member, each active member in each layer complying with the same protocol. An independent member function can be accomplished independent of a specific application environment, thus enabling a member to be easily and effectively reused, reconstituted and combined, and enabling an entire member system to have high reusability.

Description

Independent active component and operational active component assembly model. and component splitting method. The present application claims priority from the following Chinese patent application:

Submitted to the China Patent Office on January 18, 2013, the application number is 201310020477. 1. The invention is entitled "Independent Active Components and Runnable Active Component Assembly Models and Component Splitting Methods", the entire contents of which are incorporated by reference. In this application. Technical field

The invention belongs to the technical field of computers, and in particular relates to an independent active component and a configurable active component assembly model and a component splitting method. Background technique

As we all know, the ultimate goal of software design is: What the real world looks like, and what software should be designed to achieve the purpose of simulating the real world through software. Since the real world is complex, it is often not easy to realistically simulate the real world. After years of practice, the predecessors found that the more realistic the software system simulates every detail of the real world, the easier it is to design, understand, and maintain the software. Because object-oriented programming truly simulates real-world things, it is easy to understand, easy to maintain, and easy to change. Therefore, object-oriented programming has replaced process-oriented programming and has become the mainstream programming method.

However, due to various factors such as hardware cost, in the real world, the ubiquitous "parallel" activities of multiple objects moving simultaneously, in a single computer, are rarely realistically simulated. In modern computer software systems, most of them only present "pseudo-parallel" activities: From a macro perspective, a computer can execute multiple tasks, multiple programs at the same time, and several objects are running at the same time; but microscopically, incumbent For a moment, at any time, only one program is running. Because the processor is very fast, it switches back and forth between several programs. After a long period of time, we feel that these programs are executing at the same time and active at the same time. This phenomenon, often referred to as "concurrency", distinguishes between "parallel" activities in the strict sense.

Generally, in the middle and low-level software such as the operating system, the corresponding concurrent technology implementation mechanism is provided, and a special concurrent service interface is provided externally, so that the upper program can complete concurrent activities. The upper-level application calls these concurrent service interfaces to render itself as one or more concurrent tasks.

Scheduling operations (for operating systems, software buses, etc.) between concurrent entities (tasks, processes, threads, fibers, etc.) provide an implementation mechanism for concurrent technologies. In modern operating systems, deprivation scheduling is common The scheduling strategy adopted. But it has a number of Achilles heel, and the trials are as follows:

(1) Stacking space problem: Deprivation scheduling may interrupt the execution process of concurrent entities at any time. Therefore, it is necessary to protect and restore the concurrent entity running environment (at least including instruction registers, etc.), which requires RAM heap space. In normal operating situations (such as PCs), this problem is not outstanding. However, in the case of a large number of concurrent entities (such as a microcontroller with thousands of network connections), the problem will become quite prominent; in special cases where RAM is scarce (such as WSN applications), scheduling will become infeasible.

(2) Execution efficiency problem: Due to the need to protect and restore the concurrent entity operating environment, the execution of this part of the code must be increased. In the case of very lightweight scheduling (such as TinyOS), the increased execution time relative to the overall execution time of the scheduling is very significant, which seriously affects the execution efficiency of the lightweight scheduling.

(3) Competition sharing problem: Deprivation scheduling may interrupt the execution process of concurrent entities at any time. Therefore, the data and resources shared by all concurrent entities become the objects of competition and become critical resources. If all of these competing objects are protected by critical sections or other uniform general measures, the overall operational efficiency of the system will be reduced to an unacceptable level. If you carefully design the shared structure and only use common measures to protect some objects, when you program and maintain the code, a little care will lead to timing failure caused by the competition of critical resources (such faults are especially difficult to reproduce and locate). The professional quality requirements of personnel and maintenance personnel will be much improved, the design and maintenance costs will be increased, and the system reliability will be reduced. Especially for a large number of irregular shared concurrent data (such as hundreds of different special threads), in the programming practice, the average developer is daunting, unless it is particularly necessary, to avoid it.

(4) Competitive reuse problem: The data sharing design optimized for efficiency improvement will bring

Code reusability issues. Due to the competitive environment for the project, shared data protection codes that specifically eliminate competition are used, and these codes are generally not universally versatile. Even for other very similar projects, it is very likely to face other different data race conditions. Therefore, an optimized data sharing design needs to be made, and the original modules cannot be directly reused.

TinyOS is a microkernel operating system developed by UC Berkeley for the wireless sensor network WSN (Wireless Sensor Network). The two-tier scheduling mode of TinyOS is: task scheduling and hardware transaction scheduling. Hardware transaction scheduling is activated by hardware interrupts, which can preempt ordinary tasks and is mainly used for high-priority fast real-time response. It is basically the same as the general interrupt handler. The slight difference is that it can send signals to the task schedule to activate common tasks. At the same time, it can also be used. The asynchronous ability of the nesC keyword async directly calls into the nesC component system, calls the command handler in the component, and sends asynchronous events to the component.

The basic task of TinyOS is a parameterless function. Task scheduling uses a collaborative first-in, first-out (FIFO) algorithm, where tasks do not preempt each other and there is no priority. Once a task has acquired the processor, it runs straight to the end. Generally used for time-critical applications, it is essentially a Deferred Procedure Call (DPC) mechanism. The TinyOS 2. x scheduler can be customized and replaced by the user.

As shown in Figure 1, the TinyOS 2.x core PCB is a fixed-length byte array that forms a FIFO-ready task queue and a waiting task pool. Each task in the system is represented by a byte of task ID, numbered (Γ255, where 255 represents the empty task NO-TASK: that is, the task does not exist. Therefore, the system can accommodate up to 255 valid tasks. The actual number of tasks in the application system, ie the actual length of the byte array, is automatically generated by the compiler during source code compilation.

This byte array holds the task ready flag. If a task ID does not receive an event and does not need to be added to the FIFO ready queue, the NO-TASK flag is stored and the waiting task pool is entered. If an event occurs in the task ID and the activation enters the ready state, the task ID byte stores the next ready task, indicating that the ID has entered the FIFO ready task queue and is waiting for execution.

When the activation task ID is entered in parallel, the blocking critical section protection method is adopted. If the ID is already in the state, the busy flag is returned, otherwise it is added to the ready queue from the end of the queue. Since only one byte of ID is enqueued, the critical section can pass at high speed, which does not affect the interrupt response speed. This algorithm can avoid the potential problem of multiple IDs entering the queue: If the same ID can occupy multiple byte positions, in some cases, it may fill up the byte array, causing other tasks to fail to join the system and the system to die.

When the Ready Task ID is dequeued from the team, the blocking critical section protection method is also used. If there is no ready task, a signal is sent to the power saver to enter the power save state. Otherwise, the entry address of the task is retrieved and the task is executed. Because there is only a task ID in the scheduler, there are no additional parameters, so the task must be a parameterless function. At the same time, the task is collaborative, and the previous task must be completely exited (the stack is empty) before the next task can be executed. Therefore, all tasks share the same memory heap space.

TinyOS 2. x All basic tasks are parameterless functions. Each basic task only assigns a task ID of one byte. This byte stores the task ready flag and has no space for other parameters. So, in essence, it is just a signal light system. There are several weaknesses compared to message systems that can be accompanied by several parameters. The trials are as follows:

(1) The task cannot carry the entry parameters: After the task exits execution, the stack is emptied and the signal system is System

Unable to carry or save parameters. Therefore, the scope of the task is limited. Only extra measures can be used to make up for it. Such as: Self-counting module implemented with tasks.

(2) Task information cannot be managed uniformly: Since the signal system cannot carry parameters, the external environment and each

The way in which information is exchanged between tasks depends entirely on the external environment and the tasks themselves, and there is no unified and standardized means of representation. Therefore, information exchanged between the external environment and tasks, tasks, and tasks cannot be collected, monitored, filtered, controlled, and managed directly by a unified means. It can only be compensated for with additional measures. This is a great limitation on the debugging, testing, control, etc. of the software system.

(3) The active message cannot be fully expressed: Since the signal light system cannot carry parameters, the information exchange method

It needs to be separately agreed between the environment and the task, not a unified norm. The sent message can only be notified to the receiving task that a message has occurred, but it cannot be fully expressed at one time. Therefore, the task of receiving information needs to rely on a specific information exchange method, and adopts a pull mode mechanism to retrieve specific information content by function calling. This is a fatal limitation (for reasons to be described later) for implementing fully reusable modules and fully transparent distributed computing systems, which is difficult to compensate.

TinyOS 2.X uses the blocking critical section protection method when the task ID is entered in parallel and serially dequeued. Since only one byte of ID is enqueued, the critical section can pass at high speed, which does not affect the interrupt response speed and system performance. This is due to its very simple signalling mechanism. If you want to switch to the message mechanism according to the system requirements, in addition to the known blocking type of synchronous deadlock, priority inversion, interrupt can not be locked, critical sections can not be concurrent, and other issues, there are other problems, the test is as follows:

(1) Real-time performance problems: Compared to single-byte task IDs, messages are generally longer, enqueue and dequeue

It takes a long time, which will lead to a much longer execution time in the critical section. In a general-purpose microcontroller system, the protection of the critical area is generally completed by the shutdown. In this way, the system interrupt response speed is slow, which affects the system real-time performance and reduces the overall system efficiency.

(2) Hardware implementation issues: Parallel enqueue critical zone protection on each processor and software system

The technical means are varied and it is not easy to export a concise, efficient and unified parallel enrollment model. Therefore, it is not easy to implement key operations in hardware, assist in parallel enqueue, and it is impossible to improve execution efficiency or bring other advantages. TinyOS 1. x and the general-purpose operating system directly store the entry address of the task function in its scheduler data structure. When the scheduler selects the task and completes the necessary preparations, it jumps directly to the address to execute the task code. There are several disadvantages compared to the way in which the task ID and the ID address mapping table are used.

(1) The entry address has a single meaning: it cannot contain other meaningful information (such as static priority).

(2) The entry address is meaningful only in a single machine: After crossing a computer, the address has no meaning. Therefore, it is a fatal limitation for distributed parallel task computing that requires complete transparency.

TinyOS 2.X uses a one-byte base task ID to make the scheduling kernel simple and efficient. However, this limits the maximum number of tasks it can accommodate to 255. For systems that are slightly larger and have more tasks, they cannot accommodate processing and affect system scalability.

TinyOS 2.X uses a one-byte base task ID, as both a FIFO ready queue pointer and a task ready flag. This, like most other operating systems, has a non-zero-length task PCB table stored in RAM memory. With a number of weaknesses, try to enumerate as follows:

(1) Execution efficiency problem: Due to the need to perform various operations on the task PCB table (such as waiting for the task)

The state is changed to the ready state. The execution of this part of the scheduling code must be increased. In the case of very lightweight scheduling (such as TinyOS), the increased execution time relative to the overall execution time of the schedule is extraordinarily significant, which affects the execution efficiency of lightweight scheduling.

(2) Hardware implementation issues: On each processor and each software system, the contents of the task PCB table, implementation

Various measures such as technology and optimization methods are ever-changing, and it is not easy to export a simple, efficient, and unified concurrent technology implementation model. Therefore, it is not easy to implement key operations in hardware, and to implement concurrent implementations, which cannot improve execution efficiency or bring other advantages.

(3) Space occupation problem: Since there is a task PCB table stored in RAM, even if the RAM usage is very small (such as TinyOS 2. X can essentially characterize the task's wait state and ready state with a single BIT bit), in RAM memory In the case of scarcity (such as WSN system), if there are tens of thousands of tasks (described later in the case), the system will not be able to implement the concurrent scheduling process, which becomes a fatal technical defect and limits the scope of application of the technology.

When building the TinyOS system, the components are written in the nesC language, the components are connected through the interface specification, and statically assembled by function calling during program compilation. Therefore, in essence, its components The function name (link period valid) and function address (valid time) are announced. Compared with the component scheme of the published ID, there are many weaknesses. The trials are as follows:

(1) The module model is inconsistent: The TinyOS 2.x task uses the ID scheme, and its components use the address scheme.

The two are inconsistent, and there are two models, which complicate the model of the basic modules of the system.

(2) The adaptability of the address scheme is weak: the ID scheme is easier to cross-language and cross-heterogeneous systems, and the universality is better.

(3) The address scheme is difficult to adapt dynamically: During the code running period, unless it is specially maintained, the function address has been

No tracking. The predefined ID component scheme makes it easier to reference, change, replace, and maintain code, making it easier to implement single-block or overall code hot upgrades.

(4) The function address is meaningful only in a single machine: After crossing a computer, the address has no meaning. Cause

This is a fatal limitation for distributed parallel task computing that requires full transparency.

The current TinyOS system, structured programming, modular programming, object-oriented programming, component programming, and many other techniques are all done in a function call when assembled into smaller modules using small module links. This approach has a fatal flaw and is one of the core issues that make software modules difficult to reuse in complex software systems. The following details:

For the sake of simplicity, borrow two terms, briefly explain:

The Pull mode and the Push mode are originally used to indicate a way of disseminating information on the Internet. Pull (Pull) means that the user actively browses the website information and retrieves the information from the website he is interested in (pull). Push means that the website actively sends (push) messages to certain users.

A module that obtains the result by calling a function in another module. This function call, which is the information acquisition process, is similar to the process of pulling information on the Internet, so it is also called pull mode. If one module is a concurrent entity (thread, etc.), another concurrent entity sends a message. This process of sending a message is similar to the process of pushing information on the Internet, so it is also called push mode.

Pull mode and push mode, the most significant difference is: each time you pull, the user needs to specify the object to be pulled, and the specific conditions of the pull (content); and each time you push, you do not need any user Actions (of course, before doing this, you need to do some one-off work, such as booking, etc.).

Referring to Figure 2, there are two modules that operate in pull mode. The D module represents the called module, except D All other parts of the module are modules that make active function calls. In order to analyze the calling process, a functional equivalent decomposition of the above calling module is performed.

In the figure, In represents the input parameters (messages) required by the module, Out represents the information (message) output by the module, F module is the core function that the module must complete, and B module is another part of the function completed by the module. Therefore, in essence, the function of F+B is the meaning of the existence of this module.

The C module represents a direct function call, which is equivalent to the assembled CALL instruction, after which the execution right of the CPU is directly transferred to the D module. In the pull mode, this is a must-have. The D module requires a certain parameter Pm. This parameter is obtained through the A module: that is, the parameter is transformed, and is transmitted to the D module when the C module is called.

The A module performs parameter conversion, mainly for the input parameter In, combined with other variables 1, to perform parameter format conversion and matching, and obtain the parameter Pm necessary for the C module and the parameter Pc necessary for the F module.

In some cases, in order to obtain the parameters Pm and Pc, the parameter conversion in the A module must obtain another part of the information Pb. This part of the information Pb must be obtained while completing some of the module functions (B pre-function). Therefore, the pre-function of the B module is a non-essential module that may not exist. However, if it exists, the parameter Pf is obtained from the A module, part of the predetermined module function is completed, and then the information Pb is fed back to the A module, and at the same time, the possible parameter P is provided to the F module if the F core module requires it.

The information 0d returned from the called function of the D module, combined with the variable 2, is sorted by the E module information, and then converted into a parameter Pr that can be directly utilized by the F module, and transmitted to the F core function module.

After obtaining the parameters Pc, Pr, and P, the F module completes the core function and obtains the output information 0ut. The parameters Pc and Pm may be exactly the same as the parameter In, so that the A module may not need to exist. The information returned by the D module after the called function is 0d, which may be identical to the parameter Pr, so that the E module may not need to exist. The function call of the C module is a link that must exist in the pull mode.

As mentioned before, for the calling module, the parameter transformation in the A module in the figure and the function call in the C module have nothing to do with the function of the module itself. Purely because the work is in pull mode, in order to obtain the information Pr, the code has to be placed. From the perspective of module cohesion, their presence reduces the cohesion of the calling module. The pre-function of the B module, from the perspective of pure code reuse and module cohesion, it is also preferable to strip out the calling module. The E module performs information sorting. In some cases, it can be retained to meet the interface requirements, but it is best to strip it. From a design point of view, there should generally be another solution to strip out the B and E modules. Thus, when working in no pull mode, only the F core function module remains, as the only code to call the module. In this way, the highest reusability of the module can be achieved. And portability.

As shown in Figure 2, the most fatal disadvantages in pull mode are: Incomparable, C-block function calls that must exist (otherwise it is not pull mode). Since the C module must explicitly list the function name (or address) and the parameter Pm, this part of the code must be embedded in the calling module. Therefore, when the calling module is ported and reused, the influence of the D module on the calling module has to be considered. To solve this effect, there are three typical methods:

(1) Do not analyze or modify the called module and the called module represented by the D module.

use.

This is the best solution, with minimal migration, efficiency and reliability. The problem is that the calling module and the called module represented by the D module generally have other subordinate modules. Unless all the subordinate modules (that is, a subtree starting from the calling module) are all transplanted and reused, otherwise Facing the adaptation and adaptation of the subordinate modules. At the same time, whether the business logic of the new project can exactly and completely need this whole subtree is still a big problem. In this way, the application scope of the subtree transplant reuse scheme is greatly narrowed, and it is suitable only in very similar projects, and is not universal.

(2) The module is not analyzed or modified, and only the input, output, and corresponding functions of the D module are simulated.

This method is relatively simple to implement, but you should also be familiar with the professional business knowledge and models involved in the D module. If this expertise is crossed, this is a big burden in itself.

At the same time, there is a big problem with this solution, leaving a bunch of useless waste code. Wasting space and time reduces the space-time efficiency of the code. This problem is more prominent when the system is more complex and requires greater time and space efficiency. In extreme cases, designers are often forced to start a new stove, redevelop, and not be able to take advantage of existing modules and code.

(3) Analyze, modify the calling module, change the input, output, and function of the D module, or simply cancel.

This kind of implementation is more complicated. You need to understand and understand the code logic of A module, B module, C module, E module and the whole calling module. You must have a thorough understanding of the professional business knowledge and model of the calling module, and familiar with the D module. Professional business knowledge and models. If these two professional knowledge spans, it is a big burden. At the same time, the analysis of the modified code is also closely related to the original reusability design. Badly designed code, or code that has been repeatedly maintained, can be confusing. Reusability is very poor. It often prompts designers to start a new stove, redevelop, and not use existing modules and code. Summary of the invention

In view of the defects existing in the prior art, the present invention provides an independent active component and a operative component assembly model and a component splitting method, which can effectively overcome the weakness of the existing "concurrent" implementation technology, and realize the "concurrent" technology efficiently and reliably. Parallel programming, with a series of advantages such as universality, low cost, high efficiency, reliability, energy saving, multiplexing, transparent distribution, microkernel, and intrinsic support object technology.

The technical solution adopted by the present invention is as follows - the present invention provides an independent active component assembly model, and the independent active component assembly model is a collection

P = {Layer 1 active component, 2nd active component subset... nth active component subset}, where n^2 _; each active component in the nth active component subset is based on the nth layer The virtual message bus performs component assembly to obtain a single active component in the n-1th active component subset; each active component in the n-1th active component subset is based on the n-1th virtual message bus Assembled, a single active component in the n-2th active component subset is obtained; and so on, until each active component in the second active component subset is assembled based on the second layer virtual message bus, and the first 1 layer active component;

Each of the active components of each layer in the set P conforms to the same protocol.

Preferably, each active component in the first layer active component to the nth layer active component subset in the set P includes: the virtual message bus, the interface operator ID mapping table, the alias link table, and More than one operator; wherein the interface operator ID mapping table is configured to store a correspondence between an interface operator ID and an entry function; the alias link table is configured to store a reference operator ID and the interface operator ID Corresponding relationship; wherein, the interface operator ID is an operator identifier of the active component itself; and the reference operator ID is an operator identifier that is attached to an active component on the message bus.

Preferably, each active component in the n-th active component subset is assembled according to the n-th virtual message bus, and a single active component in the n-1th active component subset is obtained, where n 3 is specifically - each active component in the nth active component subset includes an nth layer virtual message bus, an nth layer interface operator ID mapping table, an nth layer alias link table, and one or more nth layer operators; The single active component in the n-1th active component subset obtained after component assembly includes the n-1th layer virtual The quasi-message bus, the n-1th interface operator ID mapping table, the n-1th layer alias link table, and one or more n-1th layer operators;

When component assembly is performed, each of the nth layer virtual message bus is bus-fused to obtain an n-1th layer virtual message bus; and each of the nth layer interface operator ID mapping tables is table-fused to obtain a nth a layer 1 interface operator ID mapping table; table fusion of each of the nth layer alias link tables to obtain an n-1th layer alias link table; and fusing each of the nth layer operators to obtain an nth- 1 layer operator.

Preferably, each active component in the second layer active component subset is assembled according to a layer 2 virtual message bus, and the first layer active component is specifically - the active in the second layer active component subset The components respectively include a layer 2 virtual message bus, a layer 2 interface operator ID mapping table, a layer 2 alias link table, and one or more layer 2 operators; the layer 1 active component includes a layer 1 virtual message bus , a layer 1 interface operator ID mapping table, a layer 1 alias link table, and one or more layer 1 operators;

When component assembly is performed, each of the second layer virtual message buses is bus-fused to obtain a layer 1 virtual message bus; each of the layer 2 interface operator ID mapping tables is table-fused to obtain a layer 1 interface. An operator ID mapping table; table fusion of each of the second layer alias link tables to obtain a first layer alias link table; and fusing each of the second layer operators to obtain a first layer operator.

Preferably, the correspondence between the reference operator ID and the interface operator ID stored in the alias link table is an equivalence mapping relationship.

Preferably, the independent active component assembly model has a built-in concurrent bus interface, and the cooperative concurrent bus interface is used for hooking onto a coordinated concurrent bus.

Preferably, the collaborative concurrent bus comprises: an information acquisition module, a parallel ring distributor, a linear memory block, a message filling module, a parallel enqueue, a message queue pool, a queue order manager, an entry mapping table, and a system stack;

The information obtaining module is configured to obtain a target operator ID and a message length value from the received external parallel message to be processed; wherein the target operator ID is an operator identifier for processing the message; An additional management message length value for obtaining an additional management message, and then calculating a sum of the additional management message length value and the obtained message length value to obtain a message occupied space value; wherein the additional management message length value

The parallel ring distributor is a non-blocking parallel space ring distributor for continuously and dynamically cutting the line according to the ring division principle according to the message occupation space value acquired by the information acquisition module. a non-blocking parallelly obtained blank message slot having the same value as the message footprint; the message padding module for populating the message and the additional management message to the parallel ring distributor allocation Blank message slot, get a non-blank message slot;

The parallel enroller is configured to perform a non-blocking parallel enqueue operation on the blank message slot or the non-blank message slot;

The message queue pool is used to cache an queried message that has not been processed;

The queuing sequence manager is configured to select a specified message to be processed from the message queue pool according to a preset scheduling policy, and perform a coordinated dequeuing operation on the specified message;

The entry mapping table searches the entry mapping table according to the target operator ID to obtain a function entry address corresponding to the target operator ID; and according to the function entry address and the specified message slot address of the specified message Calling the corresponding operator execution function to process the specified message of the team; the system stacking is the stacking space shared by all the operators in the coordinated concurrent bus; the system stack shared by each operator Spaces overlap each other, overlapping, ie non-cascading;

Moreover, the operator in the cooperative concurrent bus only has a ready state, even when there is no message in the coordinated concurrent bus, the operator in the cooperative concurrent bus is still in a ready state; When a coordinated intra-bus arrival message is described, and when the operator corresponding to the message is scheduled, the dispatched operator immediately obtains the processor.

Preferably, the message is a fixed length message or a variable length message.

Preferably, when the parallel ring distributor scribes a blank message slot at the end of the linear memory block, if the remaining free space of the least end of the linear memory block is smaller than the message space value, directly discarding The remaining free space in the most end, the remaining free space in the last end forms a discarding slot.

Preferably, the message filling module first fills the message and the additional management message to the blank message slot allocated by the parallel ring distributor to obtain a non-blank message slot; then the parallel enqueue pair The non-blocking parallel enqueue operation of the non-blank message slot is specifically as follows:

The parallel ring distributor is configured with a first head pointer and a first tail pointer. When a new blank message slot needs to be allocated, the same space as the message occupied space value is directly drawn after the first tail pointer of the current position. Obtaining the new blank message slot, and then moving the first tail pointer non-blocking parallel to the tail of the new blank message slot;

The parallel enqueue is configured with a second head pointer and a second tail pointer; and the non-blocking parallel enqueue operation is performed on the non-blank message slot by moving the second tail pointer in parallel by non-blocking; The first head pointer and the first tail pointer of the parallel ring distributor configuration are different from the second head pointer and the second tail pointer of the parallel enqueue configuration.

Preferably, the parallel enroller first performs a non-blocking parallel enqueue operation on the blank message slot, and then the message filling module fills the blank message slot of the enqueue with the message and the additional management. The message is specifically - the parallel ring distributor shares the same head pointer and tail pointer with the parallel enqueue, and when the parallel ring distributor allocates a blank message slot from the linear memory block, the blank The message slot is also enqueued by the parallel enqueue; the message padding module then populates the message and the additional management message with the blank message slot enqueued.

Preferably, in the preemptive environment, before the parallel ring distributor allocates the blank message slot from the linear memory block, the blank message slot is pre-sleeped, wherein the blank message slot in the sleep state is called a dormant message slot; the message padding module then populates the dormant message slot with the message and the additional management message, and when the padding message slot is activated, the cell is transitioned to an active state, The active message slot is called an active message slot; wherein, the dormant message slot is a message slot that is not scheduled to be executed by the cooperative concurrent bus to the operator; the active message slot belongs to the coordinated concurrent bus normal scheduling The range of message slots.

Preferably, when the variable length message is used, the dormant message slot and the active message slot are distinguished by whether the message length parameter written in the message slot is 0; when the message length parameter written in the message slot is 0, The message slot is the dormant message slot; when the message length parameter written in the message slot is not 0, the message slot is the active message slot.

Preferably, the method further includes: a monitoring management center; the monitoring management center is configured to perform centralized monitoring, analysis, control, filtering, and management on messages within the coordinated concurrent bus.

Preferably, the method further includes: a space reclamation module; the space reclamation module is configured to recover the dequeued message itself and the message slot in the collaborative concurrent bus.

Preferably, the method further includes: a power saving device; the power saving device is configured to: immediately notify an application system that uses the collaborative concurrent bus to perform energy saving scheduling when there is no message in the coordinated concurrent bus.

The present invention also provides an operational active component assembly model based on the above independent active component assembly model, wherein the set P further includes a layer 0 active component; the first layer active component is assembled based on a message bus. The 0th layer active component is described.

Preferably, the layer 0 active component comprises: the message bus, a layer 0 interface operator ID mapping a shot table, a layer 0 alias link table, and one or more layer 0 operators; the layer 1 active component includes a layer 1 virtual message bus, a layer 1 interface operator ID map, and a layer 1 alias link table And more than one layer 1 operator;

The first layer active component performs component assembly based on the message bus, and the obtained 0th layer active component is specifically - when the component assembly is performed, the first layer virtual message bus is bus-fused to obtain the message. a bus; the table layer operator ID mapping table is table-fused to obtain a layer 0 interface operator ID mapping table; the first layer alias link table is table-fused to obtain a layer 0 alias link table; The first layer operator is fused to obtain a layer 0 operator.

The present invention also provides a component splitting method for the above-described runnable active component assembly model, comprising the following steps:

The component splitting rule is preset, and when the operative active component assembly model satisfies the component splitting rule, the configurable active component assembly model is split according to the component splitting rule.

Preferably, the component splitting rule is: when the scheduler of the message bus is executed by two or more cores or processors, splitting the message bus into the same number of the cores or the number of processors a distributed peer-to-peer sub-bus; each of the active components of each layer in the executable component assembly model is respectively hooked onto the corresponding sub-bus; or

The component splitting rule is: dynamically counting the load of each active component in the executable component assembly model, and dynamically splitting the message bus into distributed peers according to a preset load balancing principle. a bus; each of the active components or operators of each layer in the configurable active component assembly model is respectively hooked onto the corresponding sub-bus; or

The component splitting rule is: dynamically counting the energy efficiency ratio of each active structure in the executable active component assembly model, and dynamically splitting the message bus into distributed peers according to a preset energy saving principle a bus; each of the active components or operators of each layer in the configurable active component assembly model is respectively hooked onto the corresponding sub-bus; or

The component splitting rule is: dynamically counting the failure rate of each active component in the executable component assembly model, and dynamically splitting the message bus into distributed peers according to a preset reliability principle. Each sub-bus; each of the active components or operators of each layer in the executable component assembly model is respectively hooked onto the corresponding sub-bus.

The beneficial effects of the present invention are as follows: The independent active component and the operative active component assembly model and the component splitting method provided by the invention assemble a plurality of small active components into components, and finally obtain a large active component identical to the component protocol of each small active component. The large active component completely eliminates the call dependency on the lower active component, so that there is only loose connection between the components. Can be separated from the specific application environment to complete independent component functions. It enables components to be reused, reconstructed, and combined in a simple and efficient manner, making the entire component system highly reusable. DRAWINGS

1 is a schematic structural diagram of a TinyOS 2.x basic task scheduler provided by the prior art; FIG. 2 is a schematic diagram of an equivalent model of a function call in a pull mode provided by the prior art;

3 is a schematic view showing an example of assembly of components provided by the present invention;

4 is a schematic diagram of a general model of a collaborative concurrent message bus provided by the present invention;

FIG. 5 is a schematic diagram of a specific application model of a collaborative concurrent message bus provided by the present invention. detailed description

The technical solutions provided by the specific embodiments of the present invention are further described below in conjunction with the accompanying drawings and specific embodiments.

The present invention will be described in detail below with reference to the accompanying drawings:

Embodiment 1: Independent active component assembly model

As shown in FIG. 3, the present invention provides an independent active component assembly model, which is a set P = {Layer 1 active component, a second layer active component subset... The nth active component subset }, wherein n 2 _; each active component in the n-th active component subset is assembled according to an n-th virtual message bus, to obtain a single active component in the n-1th active component subset; Each active component in the n-1th active component subset is assembled based on the n-1th virtual message bus to obtain a single active component in the n-2 active component subset; and so on, until Each active component in the second layer active component subset is assembled based on the second layer virtual message bus to obtain a first layer active component;

Each of the active components of each layer in the set P conforms to the same protocol. In the present invention, a plurality of small active members are assembled into members, and finally a large active member having the same component protocol as each of the small active members is obtained. The large active component completely eliminates the call dependency on the lower active component, making the structure There is only a loose connection between the pieces. Can be separated from the specific application environment to complete independent component functions. It enables components to be reused, reconstructed, and combined in a simple and efficient manner, making the entire component system highly reusable.

Each of the active components of the first layer active component to the nth active component subset of the set P includes: the virtual message bus, the interface operator ID mapping table, the alias link table, and one or more The interface operator ID mapping table is configured to store a correspondence between the interface operator ID and the entry function; the alias link table is configured to store a correspondence between the reference operator ID and the interface operator ID; The interface operator ID is an operator identifier of the active component itself; the reference operator ID is an operator identifier that is attached to an active component on the message bus.

The following refers to the reference operator ID, alias link table, and interface operator ID mapping table:

(1) Reference operator ID:

When a component exists in the form of a source code or an intermediate library alone, the reference operator ID referenced inside the component is only the symbol name to be confirmed by the connection, and after the related components are compiled and connected with the configuration file, those references are used. The operator ID is assigned as a formal ID value or variable.

(2) Alias link table

The alias link table is used to store the correspondence between the reference operator ID and the interface operator ID. Preferably, the correspondence between the reference operator ID and the interface operator ID stored in the alias link table is an equivalence mapping relationship. The alias link table, in operation, tells the compiler that the other reference operator IDs referenced within a component should be linked with the interface operator IDs of which components. Essentially, the data communication connection between the component and the component is determined and delineated to complete the predetermined function of the system.

When an alias is linked, only the reference operator ID is bound to the predetermined interface operator ID, and the operator's entry function and its parameters and message format are not concerned. Whether the parameters of the two entry functions match the specific specifications and forms of the message, the application system determines and decides on its own, thereby giving the component link operation maximum freedom. Generally, it can be checked by the compiler when the component is statically compiled. It can also be checked and confirmed by the operator when the system is running dynamically.

The concrete implementation of the alias link is very simple. Just bind the reference ID variable and the known ID variable to the same value or variable, which can be done by alias operation or assignment operation in the programming language. For example, refld is the reference operator ID, and calcld is the known interface operator ID. In C++, the implementation is: alD—t ferefld = calcld; using C i to achieve: alD—t refld = calcld.

(3) Interface operator ID mapping table The interface operator ID mapping table is used to store the correspondence between the interface operator ID and the entry function.

The message entry function within the component can be separated from the interface operator ID. That is, the function of the component implements the code part, which may not include the name of the interface operator ID, and only the code of the entry function. The binding mapping between the two can be lagging behind, and when the component or system is assembled, it is done with the alias link. Multiple interface operator IDs can be mapped to the same entry function. This is extremely valuable when implementing statically referenced multi-instance objects.

Among them, the virtual message bus is a logical, conceptual bus, without actually concerned about coding, not a separate explicit bus entity. The component is always plugged into a bus, and by calling the bus API function, the component is hard-coded to attach to the bus. However, when the component exists in the form of source code or intermediate library alone, the component is not actually connected to a certain bus, and the code of the bus is not included in the component. Only when the entire bus node or the entire system is compiled and connected, the component is connected with the code of a certain bus to become a hook component of the bus. When the independent active component assembly model is attached to the bus, it becomes available. The active component assembly model is run, which will be described in the second embodiment. The component assumes that it is operating on a bus, but this bus does not yet exist, so it is called a virtual message bus. It does not exist inside the component and does not affect the independence of the component.

Each of the active components in the n-th active component subset is assembled based on the n-th virtual message bus, and a single active component in the n-1th active component subset is obtained, where n 3 is specifically: Each active component in the nth active component subset includes an nth layer virtual message bus, an nth layer interface operator ID mapping table, an nth layer alias link table, and one or more nth layer operators; The obtained single active component in the n-1th active component subset includes the n-1th virtual message bus, the n-1th interface operator ID mapping table, the n-1th alias link table, and more than one The n-1th layer operator;

Each active component in the second layer active component subset is assembled based on the second layer virtual message bus, and the first layer active component is specifically - each active component in the second layer active component subset includes Layer 2 virtual message bus, Layer 2 interface operator ID mapping table, Layer 2 alias link table, and more than one Layer 2 operator; The layer 1 active component includes a layer 1 virtual message bus, a layer 1 interface operator ID mapping table, a layer 1 alias link table, and one or more layer 1 operators;

Specifically, when components are assembled, the virtual message bus is just a logical concept, and there is no need to actually care about coding. Therefore, it is only necessary to complete the interface operator ID mapping table and the alias link table, which can be placed in the same configuration file. Therefore, the component assembly operation simplifies the correspondence to complete a compact configuration file. The actual operator function code can be stored in an operator function library. There is no mutual calling relationship between the operator functions of the library, just a simple list relationship, and everyone exists in the same library in parallel.

The contents of the configuration file are simply listed: the correspondence between the interface operator ID and the entry function, and the correspondence between the reference operator ID and the interface operator. The reference, split, modification, reuse, etc. of the components are also just changing the corresponding relationship, which is very simple and clear. When you need to completely include another component and make it a part of itself, simply include the component's configuration file without changing its function code portion.

Concurrent operators are the most basic building blocks that can be assembled to form larger, more advanced components. After the formation of larger components, there is still no direct function call relationship between the operators as the basis, only the data communication relationship, and still maintain the communication characteristics of each other through the bus. The data connection and communication relationship between the operators within the component is determined by a partial alias link table. Since the message scheduling efficiency of this message bus is close to or the same as the order-level call call at the assembly level, there are very few operators that exist or do not degrade the efficiency of the system.

As shown in FIG. 3, it is a schematic diagram of the assembly of the components provided by the present invention. As can be seen from the figure, the components 3 and 4 need to form a large component Ca, which is the independent initiative provided by the first embodiment of the present invention. Component; then member Ca and member 1, member 2 need to constitute a larger member Cb, which is the operable active member provided by the second embodiment of the present invention; The data transfer relationship between component 1, component 2, component 3, and component 4 is shown in the left half of the figure; the actual component assembly operation structure is shown in the right half of the figure.

The actual function code of component 1, component 2, component 3, component 4, stored in parallel in another In the operator function library, don't care. The configuration file of the component Ca includes: the correspondence between the operator ID3a, ID3b and the entry function in the member 3, the correspondence between the operator ID4 and the entry function in the member 4; the correspondence between the member 3 reference ID4 and the member 4 reference ID3b The operator ID3a and the operator referenced by component 4 are published. The configuration content of the component Cb is similar and will not be described again.

In the above, the general model and specific implementation case of the independent active component assembly model are described.

In addition, the independent active component assembly model provided by the present invention has a built-in bus interface for hooking onto the bus, thereby converting the independent active component into a runnable active component. The present invention also provides a special example of a bus interface, namely: a cooperative concurrent bus interface for hooking onto a coordinated concurrent bus. The collaborative concurrency bus that is adapted to the collaborative concurrent bus interface provided by the present invention is described in detail below:

As shown in FIG. 4, the present invention provides a coordinated concurrent message bus that is adapted to a cooperative concurrent bus interface. The concurrent common model of the message bus is: parallel enqueue, coordinated dequeue, that is, a multi-entry and single-out model. Messages are non-blocking parallel operations before entering the message queue pool; after entering the message queue pool, they are cooperative serial operations. These include: information extraction module, parallel ring distributor, linear memory block, message filling module, parallel enqueue, message queue pool, queue order manager, entry map, and system stack. The following details of each component are described below:

(1) Information acquisition module

The information obtaining module is configured to obtain the target operator ID and the message length value from the received external parallel message to be processed; wherein the target operator ID is an operator identifier for processing the message. And obtaining an additional management message length value of the additional management message, and then calculating a sum of the additional management message length value and the obtained message length value to obtain a message occupied space value; wherein the additional management message length value 0.

It should be noted that the term operator used in the present invention is a free translation of an English computer term Actor, which is generally translated as a "role". Personally, I feel that borrowing the concept of "operator" in mathematics can more accurately express the meaning of Actor. Therefore, in this paper, the term "operator" is used as the Chinese translation of English Actor.

From the perspective of scheduling efficiency, an operator is a more lightweight concurrent entity than a task, process, or thread, and is more heavyweight than a callback function. Equivalent to fiber, coroutine, slightly lighter than fiber and coroutine. In the present invention, the operator in the message bus only has a ready state, even when there is no message in the message bus, the operator in the message bus is still in the ready state; once the message bus arrives in the message At the time of the message, and when the operator corresponding to the message is scheduled, the dispatched operator immediately obtains the processor. The target operator IDs may be simply arranged in order, or may imply some other meaning, such as: priority, fixed service number, distributed ID number, and the like. For example: You can simply split the target operator ID into two parts: the external bus node number and the operator number in the message bus. With this structure, simply replacing the referenced target operator ID, it is easy to abandon the reference to the local operator, and instead refer to the operator existing on another external node, to achieve transparent distributed computing and transfer. More complicated methods of partitioning can even use the concept of IP address division similar to the Internet to implement more complex distributed application logic.

In the practical message bus, the target operator ID in the message is usually hidden with other useful information (such as the external node number). Therefore, it is necessary to explicitly convert the correct local target operator ID. Several other parameters contained within the message may also require uniform format matching and conversion. Therefore, parameter extraction and format conversion are required. The normal result is that you get a correct target operator ID and the first address of the message (slot).

(two) parallel ring distributor

The parallel ring distributor is a non-blocking parallel space ring allocator for continuously and dynamically scribing the linear memory block according to the ring division principle according to the message occupation space value acquired by the information acquisition module, and is non-blocking In parallel, a blank message slot with the same message footprint value is obtained.

When there are multiple messages to be queued, the parallel ring distributor dynamically divides the linear memory block into multiple message slots (Slots), each message slot accommodating a complete message. Of course, according to actual needs, the message slot It can also accommodate other additional information for system management. These message slots are continuously allocated and reclaimed adjacent to each other. Therefore, logically, the linear memory block becomes a circular slot space. When the parallel ring distributor scribes a blank message slot at the end of the linear memory block, if the remaining free space of the least end of the linear memory block is smaller than the message occupied space value, directly discarding the most The remaining free space at the end, the remaining free space at the end of the end forms a discarding slot, thereby ensuring that the space used by each message slot is plane, linear, and not wrap-around, so that the operator and the application to the slot space The logical view is simple, clean, and natural.

The parallel ring distributor is an efficient and compact non-blocking parallel space ring distributor, which eliminates deadlock, priority inversion, interruption cannot be locked, and critical sections cannot be concurrent with respect to the blocking type distributor; Free software-only method for lock-free allocation; low-cost hardware method for efficient allocation of single assembly instructions without waiting. Specifically, you can use interrupt masking, CAS/CAS2, LL/SC Processor primitives, etc., are allocated by a software-only method through a lock-free algorithm; hardware can also be used to directly implement the same function, and the effect of the Wait-Free algorithm is obtained, and high efficiency is obtained. Effect of the allocation: An assembly instruction completes the space allocation. The lock-free algorithm implemented in pure software is left to be described later.

(3) Linear memory blocks

This linear memory block acts as a message buffer and should be large enough. In modern conventional applications, in addition to fixed-length memory allocation, common behavioral logic and guidelines are: All the remaining memory RAM space is allocated as heap space. Correspondingly, in an application system using the message bus provided by the present invention, the stack size of the application system should be fixed first, and then the remaining memory RAM space should be all allocated as a message buffer. This is because a large number of concurrent operator Actors are the main components of the system, so there are a large number of uncertain messages that require a large amount of uncertain message buffers. At the same time, in this application system, the level of functions called by each operator is not particularly large, and generally it is only a very simple direct call, and the stacking space of all operators overlaps each other because of collaborative execution. Therefore, it is easy to estimate the maximum RAM stack space that needs to be used, so it can be allocated as a fixed-length RAM memory.

If the message buffer is not large enough, causing the application to overflow during runtime, it will no longer be able to receive new messages and cause system failure or crash. Then the error is handled by: the application system is responsible for processing; or re-expanding the message buffer, or modifying the processing logic of the application system, or directly stopping the application system, and the like. This is exactly the same as the modern routine application's troubleshooting solution for system heap overflows. By adopting such logic and mechanism, the message bus is unloaded with a responsibility that should be guaranteed by the user: Unconditionally guarantee that the application system is not washed by large amounts of data. This greatly simplifies the design logic and code of the message bus, and obtains the widest range of software and hardware adaptability and portability.

In order to increase the universality of the message bus, the invention only makes a minimum specification for the internal structure of the message transmitted on the message bus: the message is divided into a fixed length message and a variable length message; for an application system of fixed length messages, generally Used in relatively specific application environments, such as ATM switches and the like. For variable-length messaging applications, it is the most widely used and has the most common use value.

For fixed-length messages and variable-length messages, the target operator ID must be included; in addition, for fixed-length messages, the message length value is defined by the specific application system and its message bus, and does not have to explicitly appear in the message structure; Messages, message length values must be explicitly present in the message structure. Message length value and The length of the target operator ID itself is closely related to the processor word length. It is defined by the specific application system and its message bus. It is generally recommended to be 1, 2, 4, 8, or 16 bytes, but it is not mandatory. Kind of length. The total length of a single message, whether it contains other management information (such as dynamic priority), etc., is also defined by the specific application system and its message bus.

(4) Message filling module

The message filling module is configured to fill the message and the additional management message to the blank message slot allocated by the parallel ring distributor to obtain a non-blank message slot.

After the parallel ring distributor spatially distributes and allocates a message slot for any message i in parallel, the message slot space is privately occupied by the message. Therefore, the message slot can be arbitrarily processed. At this point, the message filling operation can be performed. Even if this phase has a very long time delay, it has no effect on the rest of the system.

Specifically, the message filling module can use the following two schemes for message filling:

(1) The first option: first fill, then enter the team:

Specifically, the message filling module first fills the message and the additional management message to the blank message slot allocated by the parallel ring distributor to obtain a non-blank message slot; then the parallel enroller pairs the non-blank message The non-blocking parallel enqueue operation of the blank message slot is specifically as follows:

The parallel enqueue is configured with a second head pointer and a second tail pointer; performing non-blocking parallel enqueue operation on the non-blank message slot by non-blocking parallel movement of the second tail pointer;

Wherein the first head pointer and the first tail pointer of the parallel ring distributor configuration are different from the second head pointer and the second tail pointer of the parallel enqueue configuration.

(2) The second option: first enter the team, then fill:

The parallel enroller first performs a non-blocking parallel enqueue operation on the blank message slot, and then the message filling module fills the blank message slot of the enqueue with the message and the additional management message as follows:

The parallel ring distributor shares the same head pointer and tail pointer with the parallel enqueue, and when the parallel ring distributor allocates a blank message slot from the linear memory block, the blank message slot is also The enqueue operation is performed by the parallel enqueue; then the message filling module populates the message and the additional management message with the blank message slot enqueued.

In addition, in the preemptive environment, before the parallel ring distributor allocates the blank message slot from the linear memory block, the blank message slot is pre-sleeped, wherein the blank message slot in the sleep state is called The message padding module fills the message and the additional management message into the dormant message slot, and when the padding message slot is activated, the message is changed to an active state, where The active message slot is called an active message slot; wherein, the dormant message slot is a message slot that is not scheduled to be executed by the message bus to the operator; the active message slot is a message slot that belongs to the normal scheduling range of the message bus.

The dormant message slot and the active message slot are generally distinguished by adding a management flag in the message slot. As a simplification, you can hide the management space by hiding the management flags in other information. For example: When using a variable length message, the useful message length is certainly not zero; therefore, it can be agreed that the dormant message slot and the active message slot are distinguished by whether the message length parameter written in the message slot is 0; when the message When the message length parameter written in the slot is 0, the message slot is the dormant message slot; when the message length parameter written in the message slot is not 0, the message slot is the active message slot. In this way, the message slot can be activated by simply writing the message length parameter into the message slot.

(5) Parallel enrollment

The parallel enroller is configured to perform a non-blocking parallel enqueue operation on the blank message slot or the non-blank message slot.

Specifically, the parallel enqueue is a key component of message parallel-to-serial, which requires very careful parallelism of the preemptive behavior of the encoding operations, and then turns into a very easy collaborative serial behavior. Since the message bus is a multi-input and single-out model, when the parallel enqueue is implemented, in most applications, the model can be simplified according to the actual situation.

Parallel enqueue is an efficient and concise non-blocking parallel enqueue component. Compared with blocking enqueue, it eliminates deadlock, priority inversion, interrupt can not be locked, and critical section can not be concurrent. The pure software method, the realization of lock-free team; with cheap hardware methods, to achieve efficient single-assembly instructions without waiting for the queue. Specifically, you can use the interrupt mask, CAS/CAS2, LL/SC processor primitives, etc., to implement the lock-free algorithm for the enqueue operation using pure software methods. You can also use the hardware to directly implement the same function. , get the effect of the Wait-Free algorithm, and get the effect of high efficiency enqueue: an assembly instruction can complete the enrollment operation. Non-blocking, especially lock-free, linked list Operation, there have been many public paper statements, and will not be repeated here. The specific implementation of the parallel enqueue is closely related to the specific structure and implementation of the message queue pool inside the bus. Usually, a single or multiple singly linked list with head and tail pointers is operated, and the tail parallel enqueue operation is completed. In order to reduce the complexity of parallel operations, a dedicated single-linked list queue can also be arranged for the parallel-to-serial enqueue operation; after that, the parallel-serial queue is subsequently managed. In special cases, there are other special solutions for entering the team. A special succinct model will be described later.

(vi) Message queue pool

The message queue pool is used to cache queued messages that have not yet been processed.

The message queue pool is the core data structure area of the message bus. It is used to cache all the queued messages that have not been processed, and cooperate with filtering, management, scheduling, and picking up messages that should be processed first. Since it is completely coordinated at this time, various scheduling management algorithms can be designed simply and naturally.

The specific implementation of the message queue pool is closely related to the specific application system. Usually, it is a single-linked list with head and tail pointers, which can implement simple scheduling algorithms, such as: FIFO FIFO (First

In First Out) algorithm, simple prioritization algorithm, etc. In complex situations, for example, multiple simple scheduling algorithms exist in one system at the same time. In this case, multiple single-linked lists are needed to implement relatively complex scheduling algorithms, such as: time-optimized dynamic priority algorithm, earliest deadline task priority.

EDF (Earliest Deadline First) algorithm and so on. In special cases, it may be necessary to use complex data structures such as double-linked lists and hash tables to complete the special functions and requirements of the system.

In the present invention, for the message queue pool, zero PCB is used, thereby simplifying the concurrency model, and the communication bus has the widest adaptability. More critical, it can save RAM space. For applications that use this message bus for concurrency, it is quite normal to have thousands of operator Actors at a time due to component assembly. Therefore, zero PCB makes the number of operators unrelated to the occupation of RAM space. No matter how many operators exist, the RAM space occupied by them is unchanged. In this way, the message bus can be easily applied to various RAM scarce situations, such as: WSN application system.

Zero PCB means that the operator can no longer dynamically express multiple states of its tasks, so the convention: The operators in the bus no longer have a wait state, but only the ready state and the running state. Even if there are no messages in the message bus, the operators in the message bus are in the ready state. When the message arrives in the message bus, the operators in the message bus get the processor immediately after sorting, and thus become the running state. Therefore, whether the entire application system is in a wait state depends on whether there is a message inside the message bus. This has laid a profound theoretical and technical support point for system energy conservation. Zero PCB means that the general operator can be dynamically expressed without RAM space. However, this does not preclude certain special-purpose operators or queues that can take up a lot of RAM space, that is, with a non-zero PCB. For example: In the EDF queue, record the deadline for each real-time operator.

Therefore, the zero-length task control block PCB of the RAM, that is, the zero PCB, reduces the scheduling execution time relative to the non-zero-length task PCB in the RAM memory, and forms an efficient, concise, unified concurrent basic model, which reduces the RAM space. Occupancy makes this concurrent base model universally applicable to any existing computer system.

(7) Queueing order manager

The queuing sequence manager is configured to select a specified message to be processed from the message queue pool according to a preset scheduling policy, and perform a coordinated dequeuing operation on the specified message.

Specifically, the queuing sequence manager utilizes a message queue pool, various scheduling algorithms, and the like to perform scheduling management on all unprocessed enqueue messages. For example: Set the priority of the message, put the highest priority message at the beginning of the team, and facilitate the message to leave the team. Among them, when selecting the head of the queue, it is very easy to extract the message from the head of the queue. If there are multiple queues, you need to select the highest priority queue first. Since the message format is generally complex and unpredictable, it is also possible to simply extract the address of the message slot as the message address. For the simplest FIFO algorithm, the Queueing Sequence Manager can even be implemented in a clear, independent form, but implicitly in other relevant organizations and code. By placing the queued sequence manager behind the parallel queue, you can avoid complex, cumbersome, and dangerous parallel preemption operations. Since it is completely cooperative operation at this time, various scheduling management algorithms can be designed simply and naturally.

(8) Entrance mapping table

An entry mapping table, searching the entry mapping table according to the target operator ID, obtaining a function entry address corresponding to the target operator ID; calling according to the function entry address and the specified message slot address of the specified message The corresponding operator executes the function to process the specified message of the team.

The entry mapping table is used to store the mapping relationship between the operator ID and the function entry address, and the entry mapping table is searched according to the target operator ID, and the function entry address corresponding to the target operator ID can be obtained, so that the next step is to jump to the entry and execute The function of this operator. This is actually an assembly level indirect address jump mechanism. The entry mapping table is generally an address table arranged in order of operator IDs, from small to large, and the operator ID itself does not explicitly appear inside the table. In order to compress the size of the task entry table and make full use of the space, the operator ID is generally encoded in a continuous manner.

In order to save RAM space and adapt to the application system where RAM space is scarce, the entry mapping table can be stored. In the ROM. The entry mapping table may also implicitly or explicitly list other useful information, such as: static priority of the operator, and the like. Since it is a cooperative operation at this time, the entry mapping table can be easily and consistently modified even during the running of the program to implement hot upgrade during the running of the system code. This is of great practical value for a 24 hour*7 day/week, continuously operating, highly reliable system. In addition, the entry mapping table stores the mapping relationship between the operator ID and the function entry address. For the scheme using the task entry address, the parallel operator can be indicated across the computer to directly support the completely transparent distributed parallel computing. Support for code hot upgrades during runtime.

(9) System stacking and execution tasks

The system stacks the stacking space shared by all the operators in the message bus; the system stacking space shared by each operator overlaps each other and is overlapped, that is, non-cascading.

The execution function of the operator is directly called according to the function entry address obtained earlier and the first address of the message (slot). Compared with TinyOS 2. x, the biggest difference is that this technical solution carries a message pointer when it is executed; therefore, it becomes an active message mode, and the information transfer mechanism of the push mode can be realized. After an operator completely quits, the heap space occupied by it is completely emptied. Since all the operators in the system are coordinated, they all share the same system heap space. That is to say, the stacking space of all the operators is overlapped, and the overlapping collaborative system stacking provided by the invention substantially reduces the occupation of the RAM stacking space and makes the system more universal than the stacked task stacking. Sexuality; It is easy to evaluate the maximum usage of stacking space, which is convenient for RAM space allocation management. During the operator's operation, the message (slot) belongs to the operator that is completely private. Therefore, the operator can arbitrarily process the message without hindering the bus operation. For example: Repeat or prioritize, send, forward, change the message (slot) to improve system efficiency.

(10) Monitoring Management Center

The monitoring management center is used for centralized monitoring, analysis, control, filtering and management of messages inside the message bus. For example: statistics on the actual running time of all operators in the message bus; clearing certain types of messages sent to an operator; even forcibly terminating the running of an operator that is out of control, and so on. It is mainly used in the system debugging and testing phase, and does not have to exist during the official operation of the system.

(11) Space recovery module

The space reclamation module is configured to recover the dequeued message itself in the message bus and the message slot, that is, the discarding and recycling of the message itself, and the discarding and recycling of the message slot space. The obsolescence of the message itself belongs to the dequeue operation in the multi-entry and single-out mode of the parallel enqueue. In a very simple application system, it can be uniformly performed when the team leader chooses, so that when the operator is running, the waste standard can be easily eliminated. Zhi, reuse the message. Recycling of the message slot space: Under normal circumstances, the space reclamation operation in the multi-input single-out mode belonging to the parallel ring distributor can also be implemented by hardware.

(12) Power saving device

The specific implementation of the power saving device is closely related to the application system hardware. Since the message bus can know whether the system is in a wait state based on whether there is a message internally. Therefore, when there is no message inside the bus, the application system using the message bus is immediately notified to perform energy saving scheduling. When a message occurs, the hardware is notified to resume normal operation.

In many applications (eg, 8051 microcontrollers), the processor does not have CAS/CAS2 instructions, nor does it have advanced synchronization primitives for parallel operation such as LL/SC. Therefore, similar primitives can only be implemented by means of a switch interrupt. This will reduce the scheduling efficiency of the bus. At this time, some simple adaptive changes can be made to the general model to adapt to the specific application environment and improve system efficiency. For example: The bus internal operator generates more messages, while the external interrupt environment generates fewer messages. At this time, you can use this feature to set up 2 bus message buffer spaces. Interrupting messages into the queue is competitive, using switches to implement primitives. Operators Messages are coordinated, eliminating the need for switch interrupts, thus improving scheduling efficiency. Even more efficient technical corrections can be made for interrupt-priority features so that both can share the same message cache.

For hard real-time systems, certain critical operations are required and must be completed within the time limits within the determination. This general collaborative model can be implemented with a slight change in the case of priority scheduling. For very fast, rigorous response times, it can be done directly inside the hardware interrupt handler. For cases where the response time can be slightly delayed and the bus can be scheduled, the operator can be scheduled to run at the highest synergy priority. The enrollment operation is also scheduled at the highest priority, ensuring that there is no waiting for lag when enrolling. At the same time, split all the operators over the specified time. So that the bus can be executed in time for any operator within the specified time. Further, the operator of the highest priority can be scheduled within a predetermined time to complete the hard real-time response. Since this model has a centralized monitoring center, it is easy to monitor the running time of each operator. Therefore, it is easy to locate operators that run beyond the specified time to help complete the design of hard real-time response.

The message bus provided by the present invention has a specific and simple and efficient special case. The special case is not particularly well-functioning, but its execution performance is particularly efficient, enabling operator concurrent operations to satisfy a typical concurrent application environment or as a basis for other concurrent applications. When borrowing hardware to implement key atomic operations, its execution efficiency can be the same or very close to that of assembly-level subroutine calls.

In this particular case, the parallel ring distributor and the parallel enqueue are combined into one. The sleep message slot and the message activation mechanism are used to implement simple FIFO sorting, and the queue operation is naturally completed while enqueuing. Specific The work steps are -

51, dormant identification, space allocation, enrollment. Special hardware is completed, a single assembly instruction can be completed.

52. The external message is copied into the message slot.

53. The simplest FIFO queue. Implicit in the S1 operation, does not consume time.

54. The news team debuted. A single assembly instruction can be completed. Parameter extraction, general conditions can be omitted.

55, operator ID lookup table, jump execution. Assembly-level indirect call instructions can be completed.

56. Space recycling. Special hardware is completed, a single assembly instruction can be completed.

Compared with the assembly-level subroutine calling process, S1 is equivalent to changing the stack pointer, S2 is equivalent to parameter compression, S5 is equivalent to indirect CALL assembly instruction, and S6 is equivalent to parameter retirement. S3 does not consume time. Therefore, only S4 is an extra execution time, which is a very simple operation, and a single assembly instruction can be completed. Therefore, the total execution time is only one more assembly instruction time. When the number of messages (or parameters) is large, the proportion of time taken is very small. Therefore, very close execution performance can be achieved. If you optimize your operation and use more complex hardware, you can achieve the same performance.

The special case is described in detail below:

For the sake of simplicity, first define two terms: Let the environment first, and preempt the environment.

Generally, in a low-end embedded application environment, a single-core single-processor microcontroller is commonly used, and no operating system is used. The application software uses structured, modular, sequential programming techniques to assemble the entire application system and run directly in bare metal. When an external environment event occurs, the interrupt handler is used to preempt the main program, capture external events, and save the event state at certain pre-agreed specific locations. At the same time, the main program uses a large endless loop to check if there are external events. If it happens, check the status of the external event according to the prior agreement, and output it after processing.

For many applications, similar to the above application scenario, the main loop is always preempted by external interrupts, but the main loop does not preempt external interrupts. That is, as long as there is an external interrupt code running, the main loop will definitely suspend execution. This kind of software execution environment is called the first execution environment, which is simply referred to as "letting the environment first." For example, when a single-core single-processor is used, LINUX executes the real-time priority scheduling policy, resulting in a real-time thread running environment. When its lowest priority thread acts as the main loop, it constitutes the prior environment.

In contrast, in a multi-core processor, or a single-core multi-processor, or a normal time slice preemptive scheduling, the main thread and other threads can preempt each other, or concurrently cross-execution. This software execution environment is called the preemptive execution environment, referred to as the "preemptive environment".

When implementing this message bus, the main loop acts as a scheduler, completing message dequeue, scheduling, and coordinated operation. The function of the row operator; other external interrupts, preempt each other, send messages to the system queue. In the preemptive environment, the scheduler and the external interrupts preempt each other and cross-execute. Therefore, the dispatcher is likely to run when the external interrupt fills the message slot but has not been fully populated. At this point, the scheduler has access to the semi-finished incomplete message. Therefore, certain measures need to be taken to ensure that the scheduler does not use the semi-finished message as a normal message. In the preemptive environment, when the external interrupt fills the message slot, the scheduler has no chance to be executed. The scheduler either can't see the new message, or it sees a complete message after the queue. With this feature, the parallel enqueue algorithm can be simplified in a pre-emptive environment without having to put a sleep flag on the message (slot).

This embodiment can be used for preemptive environment and transparent distribution environment, based on x86 32bit multi-core system. The core technical point of this embodiment is that the parallel ring distributor and the parallel enqueue are combined to operate, and the head and tail pointers of the ring space are regarded as the head and tail pointers of the message queue at the same time. The two queues use the same head and tail pointer. In this way, the message slot has just been allocated from the linear space and into the circular slot space, which means that the message slot has entered the system message queue.

At this time, in the preemptive environment, in order to prevent the scheduler from misusing the new message slot (the message data has not been filled at this time), the message slot needs to be written with a sleep flag in advance. The sleep flag is implicit in the length parameter of the message slot. When the length is 0, it means the message slot is sleeping, the data has not been filled, and the scheduler should ignore it.

The message format is indefinitely long binary data, which is divided into two parts: the message header and the message body. The message body can be any data, any length less than 65536-8 bytes. It is also legal for the message body to be 0 bytes. In this case, the entire message has no message body and only the message header. The header has three parts: 2-byte message length Parameter size, 2 bytes CAS2 counter cas2cnt, 4-byte operator id. A total of 8 bytes, just within one CAS2 operation of the 32BIT x86 CPU.

In a preemptive environment, using the lock-free algorithm, the pre-write sleep flag requires the use of a CAS2 operation. To prevent ABA problems when CAS2 has no lock operation, the _Cas 2cnt counter is required. The specific principles can be found in related papers, and will not be described here. In the pre-emptive environment, there is no need to use the sleep flag, and there is no need to use the CAS2 operation. Therefore, cas2cnt does not need to exist and can be discarded.

In this case, the CAS operation is completed with the x86 assembly instruction cmpxchg, which can operate 4 bytes at a time; the CAS2 operation is completed with the assembly instruction cmp _XC hg8b, which can operate 8 bytes at a time. In the x86 architecture, the memory bus lock is completed with the assembly instruction lock to complete the CAS/CAS2 operation at the time of multi-core.

The 32BIT operator ID number can be easily divided into two parts: node number, operator number. Node When the number is 0, the subsequent operator number is treated as an operator in the bus. When the node number is not 0, it means that the target operator is not in the bus, but in other external nodes: the subsequent operator number, and therefore is regarded as an operator in the external node. How many BIT bits are occupied by the node number and the operator number, which can be agreed in advance in the application system. Each external node needs a local operator to handle some necessary transactions, such as: forwarding the message to a communication pipe to the external node, and so on. This local operator is called a proxy operator.

The circular slot space queue has a head pointer head and a tail pointer tail, which double as the head and tail pointers of the system message queue. When the head and tail pointers are equal, it means that there is no message (slot) in the ring slot space, which is an empty queue. This case is not considered by the user application itself. Therefore, the tail pointer always points to the free area of the linear memory block.

When the message slot is allocated, directly at the tail pointer, after the 8-byte boundary is aligned, the corresponding length of free space is drawn, and then the tail pointer is moved: This also means that the message slot also enters the system message queue. When the linear memory block is allocated at the very end, the remaining free space may not be able to accommodate a complete message, and the end space is allocated as an obsolete message slot. New messages are continuously allocated in the next free position (the beginning of the linear space). Since the message slot boundary is always 8-byte aligned, it is equal to the length of the message header. Therefore, the last discarded message slot can at least accommodate the header of the message, so that when the CAS2 is operated and the sleep flag is written concurrently, the fault of the super-boundary read/write occurs.

Since the length of the message slot just accommodates a message, the length of the message slot can be directly calculated from the length of the message. The message slots are allocated consecutively, so the length of the message slot actually implies the location of the next message slot. Therefore, no additional information is required and all messages can form a single linked list of FIFOs. Starting from the first pointer, you can traverse all the messages in the queue in the order of enqueue.

The message is directly dequeued from the queue head pointer. Then, the queue head pointer head points to the next message slot: This also means that the previous message slot space has been discarded and discarded into a free-free linear space. After the message is used, it can be discarded without leaving the team. The obsolete flag is implicit in the operator ID of the header.

An ID of 0 means the message has been discarded and the scheduler is no longer concerned about it. The ID is not 0, which means it is a valid message and needs to be scheduled for execution.

In this way, the messages entering the queue in parallel are only enqueued from the tail of the queue, and only the tail pointer tail of the queue is modified; and the message of the dequeue is only dequeued from the head of the queue, and only the head pointer of the queue is modified. Therefore, without using other critical resource protection measures, it is also natural and easy to complete concurrent competitive entry and exit operations, and improve execution efficiency. Referring to Figure 5, there are three core operations in this case:

Al, allocate empty slots to enter the queue; A2, submit the activation slot; A3, schedule execution.

The external environment or internal operator that needs to send the message, according to the length of the message, invokes the A1 operation to get the dormant private message slot. Then, copy the rest of the message to the message slot. Finally, according to the target operator ID of the message and the length parameter of the message, the A2 operation is called to activate the message. Wait for the bus to schedule processing of this message.

The bus A3 operation in this case is very simple and intuitive. Simply handle the dormancy and discarding problems. Among them, the concept of the agent operator, implemented in the scheduler, has great benefits for transparent distribution calculation. In this way, the ID number used in the component can be directly linked to the external node in the link configuration file of the component assembly. Instead of using another encoding to generate a local operator, the operator forwards the message to the external node.

When the bus A3 is operating, for the ordinary operator, the message is discarded and the target operator corresponding to the message is executed. The reason is that this gives the operator a chance to reuse the message. As long as the operator clears the discard flag, the message can be reused to improve system execution efficiency. For example: In the error handling operator, by changing the ID of the message to another operator, the message can be quickly and preferentially forwarded to the subsequent error handling operator. Since the message is still at the head of the message queue at this time, priority execution can be obtained.

The bus A2 operation, when the length parameter sz greater than 0 is instantaneously written into the size field of the sleep message header, the sleep message slot is activated (the size field of the header is 0 when the message slot is sleeping). To improve execution efficiency, the signal is sent to wake up the sleep scheduler only when the message queue is just empty, that is, when the message is the first message in the message queue. The wake-up signal can also be sent multiple times.

The bus A1 operation is a lock-free designation, assignment and enqueue operation, and uses CAS/CAS2 operation.

(1) Make a snapshot snap to the tail pointer tai l and the message slot head it points to. At this time, the snap may actually be useless garbage data, or it may be a valid header that it has processed: it may be the header of the flag, or the message being filled, or it may be completely filled. Good news head. It is then compared in real time with the tai l pointer to ensure that the snapshot obtained is taken from the latest tail. After the success of the snap, it is no longer possible to fill or fill the header. Because, in that case, the tai l pointer must have been changed by others.

(2) Write the same flag M to the memory corresponding to the snapshot snap: the sleepy and valid message, the size field of the header is 0, and the id field is not 0. Sometimes it is preemptively populated, to prevent damage to the same piece of memory, using CAS2 atomic operations. When CAS2 operates, its counter cas2cnt field (sent), in the original snap Add 1 to the value obtained, and then write it back together with the flag M. In this way, the CAS2 operation ensures that: before writing the flag M, when competing for parallel writing, there is only one write of the flag M successfully; after writing the flag M, only the cas2cnt field of the header can be modify. Therefore, it is ensured as a whole that the flag M is reliably written ahead of time without destroying other useful header information that is subsequently written by the person.

(3) Modify the queue tail pointer tai l to preempt the queue. Since the annular space needs to wrap around a full circle, it is possible to return to its original position with a very small probability. Therefore, the new and old message slot pointers are basically impossible to be equal, and there is no ABA problem. With CAS operation only, competitive tai l pointer writing can be completed, and space allocation and enqueue operations can be completed.

The above is a specific embodiment of a non-blocking enqueue coordinated concurrent message bus.

The non-blocking and enrolled collaborative concurrent message bus provided by the invention can effectively overcome the weaknesses of the existing "concurrent" implementation technology, and realize the "concurrency" technology and parallel programming efficiently and reliably, and is universal, cheap, efficient, reliable, and Energy saving, multiplexing, transparent distribution, microkernel, and intrinsic support object technologies. Specifically, it includes the following advantages:

(1) Universality: Can be widely used in various computer architectures, such as: single processor systems, multi-vector systems, massively parallel systems, symmetric multiprocessing systems, cluster systems, vector machines, supercomputers, embedded System, etc.; can also be widely used in various processor architectures or various CPUs, such as: X86 architecture, RISC architecture, ARM processor, 8051 microprocessor, microcontroller, etc.; can also be widely used in various operating systems, each Software-like systems, such as: IBM 0S/400 systems, Windows systems, Unix systems, iOS systems, vxWorks systems, ucOS II systems, sequential programming, structured programming, modular programming, database systems, and more. For these ever-changing hardware and software environments, a unified concurrency technology model can be implemented.

(2) Cheapness: It can be directly realized by using existing software and hardware environments, and is fully compatible with existing software and hardware systems and technologies. In order to gain more advantages, it is also possible to implement key atomic operations in the technical model using very inexpensive and uniform hardware facilities.

(3) Efficient: Space efficiency: The core C language source code does not exceed hundreds of lines. High time efficiency: Concurrency efficiency is better than existing common thread technology, which can exceed one order of magnitude; if hardware facilities are used and key atomic operations are completed, the concurrency efficiency can reach the same level compared with assembly level subroutine call instructions; That is, a concurrent scheduling operation can be completed in several or dozens of machine instruction cycles. High development efficiency: Matching the unique programming model and assembly multiplexing technology, compared with the existing common modular programming and object-oriented programming, the development efficiency can exceed one order of magnitude. (4) High reliability: The core code is very small, it is very easy to check and test correctly; the use of lock-free or no-wait technology to achieve concurrency, the core will never deadlock collapse; using collaborative concurrency technology to eliminate a large number of unnecessary critical condition competition, Avoid application timing failures; use component reuse programming models to reuse proven component assembly systems.

(5) Energy-saving features: Adopt message and event-driven mechanism. When there is no load, the system can automatically detect and enter the energy saving state.

(6) Transparent distribution calculation features. Only the ID number represents the concurrent operator Actor in the system, and the concurrent operator Actor communicates only through the message, and there is no correlation between where the operator is stored and where it is executed. Therefore, the natural multi-processor CMP (Chip Multi-Processor) structure, Symmetrical Multi-Processor (SMP) structure, Asymmetrical Multi-Processor (AMP) structure, non-uniform storage access NUMA (Non_Uniform) Memory Access) Structure, massive parallel processing MPP (Massive Paral Lel Process) structure, computer clustering, distributed computing, etc. Parallel and distributed environments. Easily perform functions such as load balancing and calculation transfer to easily improve computing performance and achieve a globally unified computing environment.

(7) Microkernel features: The core code is small, and the concurrency mechanism is implemented through an efficient message bus. The operating system can be fully architected on top of it, competing with single-core systems.

(8) Support for object-oriented technology: It can accommodate very large-scale concurrent operator Actor components. All operators communicate through high-efficiency message bus, which perfectly simulates and implements the behavior and mechanism of active objects in object technology.

Embodiment 2 The active component assembly model can be run

The difference between the embodiment and the first embodiment is that the layer P active component is further included in the set P of the first embodiment. The first layer active component of the first embodiment performs component assembly based on the message bus to obtain the layer 0 active component. member.

The layer 0 active component includes: the message bus, a layer 0 interface operator ID mapping table, a layer 0 alias link table, and one or more layer 0 operators; the layer 1 active component includes the first Layer virtual message bus, layer 1 interface operator ID mapping table, layer 1 alias link table, and more than one layer 1 operator;

The first layer active component performs component assembly based on the message bus, and the obtained 0th layer active component is specifically - when component assembly is performed, the first layer virtual message bus is bus-fused to obtain the cancellation The first bus interface operator ID mapping table is table-fused to obtain a layer 0 interface operator ID mapping table; the first layer alias link table is table-fused to obtain a layer 0 alias link table. The first layer operator is fused to obtain a layer 0 operator.

Through the embodiment, the independent active component assembly model obtained by the implementation is hooked onto the message bus, that is, the operational active component assembly model is obtained. The message bus may be any one of the physical bus in the prior art, or may be the coordinated concurrent message bus introduced in the first embodiment. The present invention is not limited thereto.

Embodiment 3 Component splitting method

This embodiment provides a component splitting method for an operational active component assembly model, including the following steps:

The present invention provides the following four component splitting rules:

(1) The first component splitting rule

The component splitting rule is: when the scheduler of the message bus is executed by more than two cores or processors, splitting the message bus into distributed peers having the same number of cores or the number of processors a sub-bus; each of the active components of each layer in the active component assembly model is respectively hooked onto the corresponding sub-bus.

Specifically, since the bus is cooperatively scheduled and executed, a bus is only suitable for executing a bus scheduler by one core of one processor, and the scheduler of the same bus cannot be simultaneously executed by multiple cores or multiple processors. In a multi-core or multi-processor system, if the message load of one bus is very large, it is not enough to execute the scheduler of the bus by only one core of one processor. Then, the bus can be split into two or even multiple sub-buses according to the number of cores and processors, and each processor core is responsible for running one sub-bus. In this way, the automatic transfer of the load can be completed. Since the operators are all message communication, which sub-bus is running on an individual sub-bus does not affect the data communication relationship of the operators on the original single-system bus. Due to the locality principle of information, the communication between the operators inside the component should be much more frequent than the communication outside the component. Therefore, the principle of bus splitting should be divided into components. In this way, the virtual message bus that did not exist inside the component is now re-materialized into the actual sub-bus. Of course, if you need bus splitting, then when you compile the link, many of the component information that can be discarded need to keep records to ensure that the original component structure and letter can be reconstructed and reproduced. (2) The second component splitting rule

The component splitting rule is: dynamically counting the load of each active component in the active component assembly model, and dynamically splitting the message bus into distributed peer-to-peer multiple sub-buses according to a preset load balancing principle; Each of the active components or operators of each layer in the active component assembly model is respectively hooked onto the corresponding sub-bus.

(3) The third component splitting rule

The component splitting rule is: dynamically counting energy efficiency ratios of the active components in the active component assembly model, and dynamically splitting the message bus into distributed peer-to-peer multiple sub-buses according to a preset energy-saving principle; Each of the active components or operators of each layer in the active component assembly model is respectively hooked onto the corresponding sub-bus.

(4) The fourth component splitting rule

The component splitting rule is: dynamically counting the failure rate of each active component in the active component assembly model, and dynamically splitting the message bus into distributed peer-to-peer multiple sub-buses according to a preset reliability principle Each of the active components or operators of each layer in the active component assembly model is respectively hooked onto the corresponding sub-bus.

The independent active component and the operative active component assembly model and the component splitting method provided by the invention assemble a plurality of small active components into components, and finally obtain a large active component identical to the component protocol of each small active component. The large active component completely eliminates the call dependency on the lower-level small active components, so that there is only loose connection between the components. Can be separated from the specific application environment to complete independent component functions. The components can be reused, reconstructed, and combined in a simple and efficient manner, making the entire component system highly reusable. The above description is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can also make several improvements and retouchings without departing from the principles of the present invention. The scope of protection of the invention should be considered.

Claims

Rights request

1. An assembly model of independent active components, characterized in that, the assembly model of independent active components is a set P = {the first layer active component, the second layer active component sub-set...the n-th layer active component sub-set}, where , n 2 _; each active component in the n-th layer active component sub-set performs component assembly based on the n-th layer virtual message bus, and obtains a single active component in the n-1-th layer active component sub-set; the n-th layer Each active component in the sub-set of active components in layer 1 is assembled based on the virtual message bus in layer n-1 to obtain a single active component in the sub-set of active components in layer n-2; and so on, until the layer 2 Each active component in the active component subset is assembled based on the layer 2 virtual message bus to obtain the layer 1 active component;

Wherein, each active component of each layer in the set P complies with the same protocol.

2. The independent active component assembly model according to claim 1, characterized in that each active component in the first-layer active component to the n-th layer active component sub-set in the set P respectively includes: the virtual message bus , the interface operator ID mapping table, the alias link table, and more than one operator; wherein, the interface operator ID mapping table is used to store the corresponding relationship between the interface operator ID and the entry function; the alias link The table is used to store the corresponding relationship between the reference operator ID and the interface operator ID; wherein the interface operator ID is the operator identification of the active component itself; the reference operator ID is the operator ID attached to the message bus. The operator identifier inside the active component.

3. The independent active component assembly model according to claim 2, characterized in that each active component in the n-th layer active component subset is assembled based on the n-th layer virtual message bus to obtain the n-1th layer A single active component in a sub-collection of active components, where n 3 is specifically:

Each active component in the nth layer active component subset includes an nth layer virtual message bus, an nth layer interface operator ID mapping table, an nth layer alias link table, and more than one nth layer operator; proceed A single active component in the n-1 layer active component subset obtained after component assembly includes the n-1 layer virtual message bus, the n-1 layer interface operator ID mapping table, the n-1 layer alias link table, and More than one n-1 level operator;

When assembling components, perform bus fusion on each of the n-th layer virtual message buses to obtain the n-1th layer virtual message bus; perform table fusion on each of the n-th layer interface operator ID mapping tables to obtain the n-th layer interface operator ID mapping table. -Layer 1 interface operator ID mapping table; perform table fusion of each of the nth layer alias link tables, Obtain the n-1th layer alias link table; fuse each n-th layer operator to obtain the n-1th layer operator.

4. The independent active component assembly model according to claim 2, characterized in that each active component in the second layer active component subset is assembled based on the second layer virtual message bus to obtain the first layer active component. Specifically, each active component in the subset of layer 2 active components includes a layer 2 virtual message bus, a layer 2 interface operator ID mapping table, a layer 2 alias link table, and one or more layer 2 operators. The first layer active component includes a layer 1 virtual message bus, a layer 1 interface operator ID mapping table, a layer 1 alias link table, and more than one layer 1 operator;

When assembling components, perform bus fusion on each of the layer 2 virtual message buses to obtain a layer 1 virtual message bus; perform table fusion on each of the layer 2 interface operator ID mapping tables to obtain a layer 1 interface. Operator ID mapping table; Table fusion is performed on each of the second-layer alias link tables to obtain a first-layer alias link table; Fusion of each of the second-layer operators is performed to obtain a first-layer operator.

5. The independent active component assembly model according to claim 2, characterized in that the corresponding relationship between the reference operator ID and the interface operator ID stored in the alias link table is an equivalent mapping relationship.

6. The independent active component assembly model according to claim 1, characterized in that the independent active component assembly model has a built-in cooperative concurrent bus interface, and the cooperative concurrent bus interface is used to be connected to the cooperative concurrent bus. superior.

7. The independent active component assembly model according to claim 6, characterized in that the cooperative concurrent bus includes: an information acquisition module, a parallel ring allocator, a linear memory block, a message filling module, a parallel queue enqueuer, a message Queue pool, queuing order manager, entry mapping table and system heap;

Wherein, the information acquisition module is used to obtain the target operator ID and message length value from the received external parallel message to be processed; wherein the target operator ID is the operator identification for processing the message; and Used to obtain the additional management message length value of the additional management message, and then calculate the sum of the additional management message length value and the obtained message length value to obtain the message occupied space value; wherein, the additional management message length value

The parallel ring allocator is a non-blocking parallel space ring allocator, used to continuously and dynamically divide the linear memory block according to the ring division principle according to the message occupied space value obtained by the information acquisition module, Obtain an empty message slot with the same space value as the message occupied in a non-blocking manner in parallel;

The message filling module is used to fill the message and the additional management message into the parallel ring. The blank message slot allocated by the shape allocator is used to obtain a non-blank message slot;

The parallel enqueuing device is used to perform non-blocking parallel enqueuing operations on the blank message slot or the non-blank message slot;

The message queue pool is used to cache queued messages that have not yet been processed;

The queuing order manager is used to select designated messages to be processed from the message queue pool according to the preset scheduling policy, and perform coordinated dequeuing operations on the designated messages;

The entry mapping table searches the entry mapping table according to the target operator ID and obtains the function entry address corresponding to the target operator ID; according to the function entry address and the designated message slot address of the designated message , call the corresponding operator execution function to process the specified message dequeued; the system stack is the stack space shared by all operators in the cooperative concurrent bus; the system stack shared by each operator The spaces cover each other and are overlapping, that is, non-laminated;

Moreover, the operators in the cooperative concurrent bus only have a ready state. Even when there is no message in the cooperative concurrent bus, the operators in the cooperative concurrent bus are still in a ready state; once when the cooperative concurrent bus When a message arrives in the cooperative concurrent bus, and when the operator corresponding to the message is scheduled, the scheduled operator immediately obtains the processor.

8. The independent active component assembly model according to claim 7, characterized in that the message is a fixed-length message or a variable-length message.

9. The independent active component assembly model according to claim 7, characterized in that, when the parallel ring allocator cuts a blank message slot at the end of the linear memory block, if the linear memory block is the last If the free space remaining at the end is less than the message occupied space value, the free space remaining at the end is directly discarded, and the free space remaining at the end forms a discard slot.

10. The independent active component assembly model according to claim 7, wherein the message filling module first fills the message and the additional management message into the empty message slot allocated by the parallel ring distributor , obtain a non-blank message slot; and then the parallel enqueueer performs a non-blocking parallel enqueuing operation on the non-blank message slot, specifically as follows:

The parallel ring allocator is configured with a first head pointer and a first tail pointer. When a new empty message slot needs to be allocated, a space that is the same as the message occupied space is directly drawn behind the first tail pointer at the current position. , obtain the new blank message slot, and then move the first tail pointer to the end of the new blank message slot in a non-blocking manner in parallel; The parallel queue enqueuer is configured with a second head pointer and a second tail pointer; non-blocking parallel movement of the second tail pointer enables non-blocking parallel enqueuing operations on the non-blank message slot;

Wherein, the first head pointer and the first tail pointer configured by the parallel ring allocator are different from the second head pointer and the second tail pointer configured by the parallel queue enqueuer.

11. The independent active component assembly model according to claim 7, characterized in that, the parallel enqueueer first performs a non-blocking parallel enqueuing operation on the empty message slot, and then the message filling module then enters the queue. The empty message slot of the queue is filled with the message and the additional management message specifically as follows: The parallel ring allocator and the parallel queue enqueuer share the same head pointer and tail pointer. When the parallel ring allocator starts from When a blank message slot is allocated in the linear memory block, the blank message slot is also enqueued by the parallel queue enqueuer; then the message filling module fills all the blank message slots in the queue. the above message and the additional management message.

12. The independent active component assembly model according to claim 11, characterized in that, in a preemptive environment, before the parallel ring allocator allocates a blank message slot from the linear memory block, the blank message slot is pre-empted The message slot is in a dormant state, where a blank message slot in a dormant state is called a dormant message slot; then the message filling module fills the dormant message slot with the message and the additional management message. When the filling is completed, When the dormant message slot is activated, it changes to an active state. The message slot in the active state is called an active message slot. The dormant message slot is one that will not be scheduled by the cooperative concurrent bus for operator execution. Message slot; an active message slot is a message slot that belongs to the normal scheduling range of the cooperative concurrent bus.

13. The independent active component assembly model according to claim 12, characterized in that when using variable length messages, the dormant message slot and the active message slot are distinguished by whether the message length parameter written in the message slot is 0; when When the message length parameter written in the message slot is 0, the message slot is the dormant message slot; when the message length parameter written in the message slot is not 0, the message slot is the active message groove.

14. The independent active component assembly model according to claim 7, further comprising: a monitoring and management center; the monitoring and management center is used to conduct centralized monitoring and analysis of messages inside the collaborative concurrent bus. Control, filter and manage.

15. The independent active component assembly model according to claim 7, further comprising: a space recovery module; the space recovery module is used to recover the dequeued messages in the collaborative concurrent bus. the message itself and the message slot.

16. The independent active component assembly model according to claim 7, further comprising: a power saving device; the power saving device is used to: when there is no message in the cooperative concurrent bus, immediately notify the use This collaborative concurrent bus application system performs energy-saving scheduling.

17. An operable active component assembly model based on the independent active component assembly model according to any one of claims 1 to 16, characterized in that the set P also includes the 0th layer of active components; the first layer The active component performs component assembly based on the message bus to obtain the layer 0 active component.

18. The runnable active component assembly model according to claim 17, characterized in that the layer 0 active component includes: the message bus, the layer 0 interface operator ID mapping table, and the layer 0 alias link table and more than one layer 0 operator; the layer 1 active components include a layer 1 virtual message bus, a layer 1 interface operator ID mapping table, a layer 1 alias link table, and more than one layer 1 operator ; The layer 1 active component performs component assembly based on the message bus, and the layer 0 active component is obtained. Specifically, during component assembly, the layer 1 virtual message bus is bus-fused to obtain the layer 0 active component. Message bus; Perform table fusion on the layer 1 interface operator ID mapping table to obtain the layer 0 interface operator ID mapping table; Perform table fusion on the layer 1 alias link table to obtain the layer 0 alias link table ; Fusion of the first layer operators to obtain the layer 0 operators.

19. A method for component disassembly of the operable active component assembly model described in any one of claims 17-18, characterized in that it includes the following steps:

The component splitting rules are preset, and when the runnable active component assembly model satisfies the component splitting rules, the runnable active component assembly model is split according to the component splitting rules.

20. The component splitting method according to claim 19, characterized in that, the component splitting rule is: when the scheduler of the message bus is executed by more than two cores or processors, the message bus Split into distributed peer-to-peer sub-buses with the same number of cores or processors; each active component at each layer in the runnable active component assembly model is respectively hooked to the corresponding sub-bus on; or

The component splitting rules are: dynamically count the load of each active component in the runnable active component assembly model, and dynamically split the message bus into distributed, peer-to-peer sub-components according to the preset load balancing principle. bus; each of the active components or calculations at each layer in the runnable active component assembly model The sub-buses are respectively connected to the corresponding sub-buses; or

The component splitting rules are: dynamically count the energy efficiency ratio of each active component in the runnable active component assembly model, and dynamically split the message bus into distributed, peer-to-peer components according to the preset energy-saving principle. Bus; each active component or operator at each layer in the runnable active component assembly model is respectively hooked to the corresponding sub-bus; or

The component splitting rules are: dynamically count the failure rate of each active component in the runnable active component assembly model, and dynamically split the message bus into distributed peer-to-peer multiple components according to the preset reliability principle. Sub-bus; each active component or operator at each layer in the runnable active component assembly model is respectively connected to the corresponding sub-bus.