WO2014110018A1

WO2014110018A1 - Hold-up circuit, power converter system and method of providing a regulated output during hold-up time

Info

Publication number: WO2014110018A1
Application number: PCT/US2014/010458
Authority: WO
Inventors: Alexander Asinovski; Joseph Gonsalves
Original assignee: Murata Manufacturing Co., Ltd.; Murata Power Solutions
Priority date: 2013-01-08
Filing date: 2014-01-07
Publication date: 2014-07-17

Abstract

A hold-up circuit for providing power to a power converter during a power interruption includes a hold-up capacitor arranged to be connected to the power converter and a control circuit arranged and programmed to, after a beginning of a power interruption, disable an under-voltage lockout function of the power converter.

Description

HOLD-UP CIRCUIT, POWER CONVERTER SYSTEM AND METHOD OF PROVIDING A REGULATED OUTPUT DURING HOLD-UP TIME

BACKGROUND OF THE INVENTION

1. Field of the Invention

[0001] The present invention relates to power converters. More specifically, the present invention relates to power converters that provide a regulated output voltage during a hold-up time after line power has been interrupted.

2. Description of the Related Art

[0002] Several conventional techniques are known for providing a hold-up time after line power has been interrupted in a power converter.

[0003] A known regulated power converter provides regulation for a fixed input voltage range of V_min≤ V_in≤ V_max, where V_in is the input voltage, V_min is the minimum operating voltage, and V_max is the maximum operating input voltage of the power converter. Under normal startup conditions, the power converter will not begin to operate properly until the rising input voltage V_in exceeds a start-up threshold voltage V_tn. Once operating, the power converter will not turn off until the input voltage drops below the under-voltage lockout (UVLO) voltage V_UV|₀, at which point the power converter will turn off even though the power converter can provide an output voltage at lower input voltages. To provide stable shut off, the under-voltage lockout voltage Vuvio is less than the start-up threshold voltage V_tn. The absolute minimum operating input voltage V_{a bs}-min is the lowest voltage at which the power converter will provide an output. For voltages below the absolute minimum operating input voltage Vabs-min, the power converter is off. Thus, the following is satisfied for a known regulated power converter: V_abs-min < V_UV|₀ < V_tn

^ V_mj_n < V_max.

[0004] According to the first conventional technique, after the input power P_in has been interrupted, a hold-up capacitor C that is connected across the input terminals of the power converter supports the input power P_in. During the hold-up time T_n, the input voltage V_in, which is initially equal to the voltage across hold-up capacitor C_n, decays from the initial input voltage n to the under-voltage lockout voltage V_UV|₀, which is typically slightly below the minimum operating voltage V_min: C_h x in

2 2 h (1)

[0005] Based on equation (1), equations for the hold-up time T_h and for the hold-up capacitor C are determined as follows:

where P₀ is the output power, and r\ is the efficiency of the power converter, such that P₀ = η. * Pin. The capacitance value of the hold-up capacitor C_h required to support the output voltage V_out for a given value of the hold-up time T_h is determined according to equation (2), and the hold-up time T_h for a given hold-up capacitor C_h is determined according to equation (3).

[0006] The first conventional technique has several drawbacks. One drawback is that the hold-up capacitance value of the hold-up capacitor C_h is calculated according to equation (2), and thus, the size of a capacitor capable of providing a sufficient capacitance value for hold-up capacitor C_h is relatively large. Another drawback is that, according to equation (3), the hold-up time T_h is quite small at low line voltage, e.g., when the input voltage V_in is equal to the minimum operating voltage V_min or slightly greater than the minimum operating voltage V_min.

[0007] According to the second conventional technique for providing the hold-up time T_h, a wide-input-range power converter is used to obtain lower voltages for the minimum operating voltage V_min and the under-voltage lockout voltage V_UV|₀. In the second conventional technique, according to equation (2), the value of the hold-up capacitor C_h for a given hold-up time T_h is decreased, and according to equation (3), the hold-up time T_h for a given hold-up capacitor C_h is increased.

[0008] The third conventional technique for providing the hold-up time T_h uses an auxiliary boost converter that converts the decaying voltage across the hold-up capacitor C_h to a fixed voltage greater than the minimum operating voltage V_mi_n- The third conventional technique is discussed, for example, in U.S. Patent No. 6,504,497. The auxiliary boost converter supplies power during interruption of the input power P_in. This arrangement allows a much larger capacitive energy to be utilized and to increase the hold-up time T_h. [0009] The second and the third conventional techniques suffer the drawbacks of being more complex and more expensive than the first conventional technique.

[0010] Thus, there is a need for an effective method and apparatus that provide a less complicated and less expensive hold-up time operation.

SUMMARY OF THE INVENTION

[0011] To overcome the problems described above, preferred embodiments of the present invention provide a hold-up circuit, a power converter system and a method of hold-up time operation that provides less complicated and less expensive hold-up time operation .

[0012] A hold-up circuit according to a preferred embodiment of the present invention for providing power to a power converter during a power interruption includes a hold-up capacitor arranged to be connected to the power converter and a control circuit arranged and

programmed to, after a beginning of a power interruption, disable an under-voltage lockout function of the power converter.

[0013] The hold-up capacitor is preferably arranged to be connected to an input terminal of the power converter or to an auxiliary output terminal of the power converter, and the control circuit is preferably arranged and programmed to connect the hold-up capacitor to the auxiliary output terminal to charge the hold-up capacitor and, after the beginning of the power interruption, to connect the hold-up capacitor to the input terminal of the power converter while disabling the under-voltage lockout function of the power converter.

[0014] When the power interruption ends, the control circuit is preferably arranged and programmed to enable the under-voltage lockout function of the power converter.

[0015] Alternatively, when the power interruption ends, the control circuit is preferably arranged and programmed to enable the under-voltage lockout function of the power converter and to connect the hold-up capacitor to the auxiliary output terminal of the power converter.

[0016] The control circuit is preferably arranged and programmed to disable the under- voltage lockout function of the power converter at least until a voltage provided by the hold-up capacitor reaches an absolute minimum operating input voltage. [0017] The hold-up circuit further preferably includes a first current-limiting resistor and a diode arranged in parallel. The hold-up circuit further preferably includes a second current- limiting resistor connected in series with the diode. A resistance value of the second current- limiting resistor is preferably less than a resistance value of the first current-limiting resistor.

[0018] The hold-up circuit further preferably includes two switches connected in series between an input terminal and an auxiliary terminal of the power converter. The hold-up circuit further preferably includes a first current-limiting resistor and a diode arranged in parallel, and a midpoint of the two switches is preferably connected to the first current-limiting resistor and the diode. The hold-up circuit further preferably includes a diode connected between one of the two switches and an auxiliary terminal of the power converter.

[0019] The hold-up circuit further preferably includes an input voltage slope detector arranged to detect a slope S = dV_in/dt of an input voltage, and the control circuit is preferably arranged and programmed to, if the slope is less than zero and if an absolute value of the slope I S I exceeds a predetermined slope threshold S_th, disable the under-voltage lockout function of the power converter. The control circuit is preferably arranged and programmed to disable the under-voltage lockout function of the power converter at least until a voltage provided by the hold-up capacitor reaches an absolute minimum operating input voltage.

[0020] A power converter system according to a preferred embodiment of the present invention includes a power converter and a hold-up circuit according to one of the various preferred embodiments of the present invention connected to the power converter.

[0021] A power converter system according to a preferred embodiment of the present invention includes a power converter including an input terminal and an auxiliary output terminal and a hold-up circuit according to one of the various preferred embodiments of the present invention connected to the power converter.

[0022] The power converter system further preferably includes an additional auxiliary output terminal and an auxiliary output capacitor connected between the auxiliary output terminal and the additional auxiliary output terminal.

[0023] The power converter system further preferably includes an additional input terminal; the input terminal and the auxiliary output terminal are preferably positive terminals; the additional input terminal and the additional auxiliary output terminal are preferably negative terminals; and the additional input terminal and the additional auxiliary output terminal are preferably connected to each other.

[0024] The power converter system further preferably includes an additional input terminal; the input terminal and the auxiliary output terminal are preferably positive terminals; the additional input terminal and the additional auxiliary output terminal are preferably negative terminals; and the input terminal and the additional auxiliary output terminal are preferably connected to each other.

[0025] The above and other features, elements, characteristics, steps, and advantages of the present invention will become more apparent from the following detailed description of preferred embodiments of the present invention with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Fig. 1 shows a hold-up circuit according to a first preferred embodiment of the present invention.

[0027] Fig. 2 shows operation of the control circuit according to the first preferred embodiment of the present invention.

[0028] Fig. 3 shows operation of the control circuit according to a second preferred embodiment of the present invention.

[0029] Fig. 4 shows a hold-up circuit according to a third preferred embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0030] Fig. 1 shows a hold-up circuit 100 according to a first preferred embodiment of the present invention. The hold-up circuit 100 includes input terminals +V_in, -V_in and auxiliary terminals +V_aux, -V_aux of a power converter 101. The input voltage V_in is equal to the voltage across the input terminals +V_in, -V_in, and the auxiliary voltage V_aux is equal to the voltage across the auxiliary terminals +V_aux, -V_aux. The hold-up circuit 100 also includes an input capacitor Cb across the input terminals +V_in, -V_in; auxiliary capacitor C_aux across the auxiliary terminals +V_aux, - V_aux; switches Ql, Q2; a control circuit 102 that controls the switches Ql, Q2 according to the under-voltage lockout voltage V_UV|₀ of the power converter 101; and the hold-up capacitor C_n.

[0031] The negative terminal of the hold-up capacitor C is connected to the negative input terminal -V_in, and the positive terminal of the hold-up capacitor C_n is connected to the circuit defined by the parallel combination of the current-limiting resistor R2 and the diode Dl in series with the current-limiting resistor Rl. The negative auxiliary terminal -V_aux is connected to the negative input terminal -V_in. The switches Ql, Q2 are connected in series between the positive input terminal +V_in and positive auxiliary terminal +V_aux. The midpoint of the switches Ql, Q2 is connected to the second terminal of the circuit defined by the combination of the current-limiting resistor R2, the diode Dl, and the current-limiting resistor Rl. The current- limiting resistor R2 limits a charging current to the hold-up capacitor C_n from the positive auxiliary terminal +V_aux through the switch Ql, and the current-limiting resistor Rl limits a discharging current from the hold-up capacitor C_n through the switch Q2 when the input power P_in is interrupted. Because charging time is usually not critical, the resistance of resistor R2 can be relatively large. Because discharging time is a portion of the hold-up time, the resistance of resistor Rl can be relatively small. As a non-limiting example, the current-limiting resistor Rl can have a resistance value of about 1 Ω to about 5 Ω, and the current-limiting resistor R2 can have a resistance value of about 100 Ω.

[0032] The hold-up circuit 100 shown in Fig. 1 operates in the following manner. After the power converter 101 is turned on, if the input voltage V_in detected by the control circuit 102 is within the operating range (i.e., V_min≤ V_in≤ V_max) and if the output voltage V_out and the auxiliary voltage V_aux have reached steady state levels, control circuit 102 turns ON the switch Ql to allow the hold-up capacitor C to be charged to the voltage on the auxiliary terminal +V_aux through the switch Ql and the current-limiting resistor R2.

[0033] The auxiliary voltage V_aux can be constant (regulated), can be proportional to the input voltage V_in (non-regulated), or can have any suitable relationship with the input voltage V_in. The auxiliary voltage V_aux can be chosen to be any value in the range of V_abs-min < V_aux≤ V_max; however, the auxiliary voltage V_aux is usually chosen to be the maximum voltage V_max to maximize the hold-up time T_h. Typically, the auxiliary voltage V_aux is regulated at the maximum operating input voltage V_max, i.e., V_aux = V_max. Any suitable circuit can be used to provide the auxiliary voltage V_aux. For example, the auxiliary voltage circuit could be a circuit similar to a housekeeping circuit that provides a voltage to be applied to other circuit components of the power converter and could be as simple as a circuit including an auxiliary inductor winding, a one-diode rectifier, and an LC or C filter. The maximum operating input voltage V_max is the highest voltage allowed across the input terminals of the power converter 101 at which the output voltage V_out stays regulated. In particular, the maximum input voltage rating of the power converter 101 can be used as the maximum operating input voltage V_max.

[0034] It is also possible to connect the hold-up capacitor C_h to the input terminals +V_in, -V_in; however, doing so will reduce the hold-up time T because V_in < V_max. This is especially true when the input voltage V_in is low. Advantages in charging the hold-up capacitor C_h to the maximum voltage V_max include that the hold-up time T_h is independent of the input voltage V_in and that the hold-up time T_h is relatively long when the input voltage V_in is low.

[0035] The operation of the control circuit 102 according to the first preferred embodiment of the present invention is shown in Fig. 2. Under normal operating conditions, i.e., when V_min < Vin≤ V_max, the switch Ql is in the ON state, the switch Q2 is in the OFF state, and the voltage V_h of hold-up capacitor C_h is charged to V_aux, which is typically V_max. When the input power P_in is interrupted, either because of shutdown or some non-normal condition, the input voltage V_in starts to decay. When the input voltage V_in decays below the minimum operating voltage V_min, the control circuit 102 disables sending the under-voltage lockout signal UVLO to the power converter 101 for time T greater than or equal to the hold-up time T_h to ensure that the under- voltage lockout signal UVLO is disabled at least during the hold-up time T_h, turns OFF the switch Ql, and turns ON the switch Q2. By disabling the sending of the under-voltage lockout signal UVLO by the control circuit 102, the UVLO functionality of the power converter 101 is disabled. Disabling the UVLO functionality allows the power converter 101 to provide a voltage output in an input voltage range (i.e., V_ab_S-min≤ V_in≤ V_UV|₀) in which the power converter 101 would not normally provide a voltage output.

[0036] By turning switch Ql OFF, and turning switch Q2 ON, the hold-up capacitor C_h is disconnected from the positive auxiliary terminal +V_aux and connected to the positive input terminal +V_in through the current-limiting resistor Rl. The hold-up capacitor C provides power to the power converter 101 during hold-up time T_h, causing the voltage across the input terminals +V_in, -V_in of the power converter 101 to increase quickly from the minimum operating voltage V_min to approximately V_aux, which is typically the maximum operating input voltage V_max.

[0037] If input power P_in is restored during the hold-up time T , the output voltage V_out can remain regulated because of the control circuit 102 enabling of the sending of the under- voltage lockout signal UVLO after time T has elapsed. If interruption of the input power P_in persists at the end of hold-up time T_h, the power converter 101 shuts down when the control circuit 102 enables sending the under-voltage lockout signal UVLO or when the decaying voltage across the input terminals +V_in, -V_in crosses the absolute minimum operating input voltage Vabs-min- The absolute minimum operating input voltage V_abs-min refers to the lowest voltage allowed for the input voltage V_in and can be determined according to the ratings of the power converter 101. In particular, V_abs-min can be the lowest voltage that allows the power converter 101 to regulate the output voltage V_out- That is, the power converter provides a regulated output for V_abs__min≤ V_in≤ V_uv,₀, V_uv,₀≤ V_in≤ V_min, and V_min≤ V_in≤ V_max.

[0038] The disabling of the sending of the under-voltage lockout signal UVLO to the power converter 101 during the hold-up time T_h eliminates under-shoot of the output voltage V_out that can take place if commutation of the hold-up capacitor C_h to the positive input terminal +V_in takes a relatively long time, such that the input voltage V_in reaches the under-voltage lockout voltage Vuvio of the power converter 101 and allows the control circuit 102 to further extend the hold-up time T_h by using the absolute maximum range for the input voltage V_in, i.e., the range

Of V_abs-min— Vj_n≤ V_max.

[0039] Dynamic control of the under-voltage lockout voltage V_UV|₀ is particularly effective for wide-input-range power converters with multiple sub-ranges and a programmable under- voltage lockout voltage for each sub-range. For example, the power converter can be capable of operating from power supplied by one of two (or more) battery voltages selected by a user- programmable under-voltage lockout voltage. As one particular example, two batteries with nominal voltages 24 V and 48 V can have absolute minimum operating input voltages V_ab_S-min that can be defined by the voltage of the source battery when it is fully discharged, e.g., about 13 V, and the under-voltage lockout voltage for the 48 V battery is set to 30 V. Assuming the 48 V battery is being used when input power P_in is interrupted, the control circuit 102 disables the 30 V under-voltage lockout voltage of the power converter 101, thus allowing the output voltage V_out to stay regulated while input voltage drops down to 13 V for time T greater than or equal to the hold-up time T .

[0040] According to the first preferred embodiment of the present invention, values for the hold-up capacitor C_h and the hold-up time T_h can be determined as follows:

[0041] The capacitance value of the hold-up capacitor C provided by equation (4) is lower than the corresponding value provided by equation (2), and the hold-up time T_h provided by equation (5) is larger than the corresponding time provided by equation (3) by a factor of (V_max ² - V_abs-min²)/(Vnom² - V_uv|₀ ²), assuming that in equations (2) and (3) V_in = V_nom, where V_nom is the nominal input voltage. The hold-up circuit 100 shown in Fig. 1 provides the hold-up time T determined according to equation (5), independent of the initial input voltage V_in. Thus, the hold-up circuit 100, without adding significant complexity, provides a longer hold-up time T_h than is provided by the first conventional technique as described above. Accordingly, the first preferred embodiment of the present invention provides a relatively long hold-up time T_h without requiring a relatively large capacitance value for the hold-up capacitor C_h.

[0042] According to the second preferred embodiment of the present invention, in addition to detection of the input voltage V_in, the control circuit 102 also includes an input voltage slope detector that detects the slope S = dV_in/dt, the slew rate of change in the input voltage V_in.

[0043] The operation of the control circuit 102 according to the second preferred embodiment of the present invention is shown in Fig 3. Under normal operating conditions, that is, when V_min < V_in < V_max, the slope S can be either positive (corresponding to increasing input voltage) or negative (corresponding to decreasing input voltage). However, if the slope S is negative, the absolute value of the slope | S | is preferably below a predetermined slope threshold S_th (corresponding to a slowly decreasing input voltage) for normal operating conditions.

[0044] Under normal operating conditions, the switch Ql is in the ON state, the switch Q2 is in the OFF state, and the voltage V_h of hold-up capacitor C_h is charged to V_aux = V_max. When the absolute value of the slope | S | exceeds a predetermined slope threshold S_th, or when the input voltage V_in decays below the minimum operating voltage V_min, the control circuit 102 operates as described above in the first preferred embodiment of the present invention. That is, the control circuit 102 disables sending the under-voltage lockout signal UVLO to the power converter 101 for time T greater than or equal to the hold-up time T_h, turns OFF the switch Ql, and turns ON the switch Q2.

[0045] By turning switch Ql OFF, and turning switch Q2 ON, the hold-up capacitor C_h is disconnected from the positive auxiliary terminal +V_aux and connected to the positive input terminal +V_in through the current-limiting resistor Rl. The hold-up capacitor C_h provides power to the power converter 101 during hold-up time T , causing the voltage across the input terminals +V_in, -V_in of the power converter 101 to increase quickly from the minimum operating voltage V_min to approximately V_aux, which is typically the maximum operating input voltage V_max.

[0046] If input power P_in is restored during the hold-up time T , the output voltage V_out can remain regulated because of the control circuit 102 enabling of the sending of the under- voltage lockout signal UVLO after time T has elapsed. If interruption of the input power P_in persists at the end of hold-up time T_h, the power converter 101 shuts down when the control circuit 102 enables sending the under-voltage lockout signal UVLO or when the decaying voltage across the input terminals +V_in, -V_in crosses the absolute minimum operating input

VOltage Vabs-min-

[0047] Adding detection of the slope S to the control circuit 102 provides improved detection of a power interruption event so as to allow commutation of the switches Ql, Q2 to begin sooner. Further, the detection of the slope S provides additional extension of the hold-up time T_h or reduction in the capacitance value of the hold-up capacitor C_h by detecting a power interruption before the input voltage V_in reaches V_min. [0048] According to the third preferred embodiment of the present invention, the auxiliary terminal -V_aux is connected to the input terminal +V_in, instead of the input terminal -V_in, as shown by the dashed line in Fig. 1. This arrangement reduces the auxiliary voltage and simplifies implementation of the auxiliary output, including auxiliary terminals +V_aux, -V_aux. The principle of operation in the third preferred embodiment is similar to the first and second preferred embodiments of the present invention.

[0049] According to the third preferred embodiment of the present invention, the voltage V of the hold-up capacitor C is (V_in + V_aux) and the values of the hold-up capacitor C_h and the hold-up time T_h are determined as follows:

2XP₀XT)₁

h^~ x((Vi„+v_aux)²-v_abs__min ²) ^ ^} _ C_hx((Vi_n+V_aux)² -V_abs__min ²)xii

[0050] The capacitance value of the hold-up capacitor C_h provided by equation (6) is lower than the corresponding value provided by equation (2), and the hold-up time T_h provided by equation (7) is larger than the corresponding time provided by equation (3) by a factor of

[( nom + V_aux)² - V_abs__min ²]/(V_nom ² - V_UVio²), assuming that in equations (2), (3), (6) and (7) V_in = V_nom, where V_n0m is the nominal input voltage.

[0051] Similar to the first preferred embodiment of the present invention, the auxiliary voltage V_aux can be constant (regulated), proportional to V_in (non-regulated), or can have any suitable relationship with the input voltage V_in. For example, if at nominal input voltage V_n0m auxiliary voltage V_aux is kept at voltage equal to V_max - V_nom , equations (6), (7) provide the same values for the hold-up capacitor C_h and the hold-up time T_h as equations (4), (5). Thus, the holdup circuit 100, without adding significant complexity, provides a longer hold-up time T_h than is provided by the first conventional technique as described above. Furthermore, the third preferred embodiment of the present invention provides hold-up time operation for low values of the input voltage V_in.

[0052] In the preferred embodiments of the present invention, including the first, second, and third preferred embodiments described above, the switches Ql and Q2 are preferably metal-oxide-semiconductor field-effect transistors (MOSFETs), for example. Fig. 4 illustrates a hold-up circuit 200 according to a preferred embodiment of the present invention where the switches Ql, Q2 are N-channel MOSFETs, for example. The diode D2 shown in Fig. 4 is connected between the drain of the switch Ql and to the positive terminal of the auxiliary output +V_aux. All other components and connections are similar to or the same as those shown in Fig. 1.

[0053] The operation of the hold-up circuit 200 shown in Fig. 4 is the same as or similar to the first, second, and third preferred embodiments. Differences in the operation of the hold-up circuit 200 are described as follows. When the power converter 201 is turned on, the body diode of the switch Q2 conducts to allow the hold-up capacitor C_h to pre-charge to the input voltage V_in through the body diode of switch Q2 and the current-limiting resistor R2. When the switch Ql turns ON, hold-up capacitor C_n is charged to the maximum operating input voltage V_max through diode D2 and the switch Ql, as described above with respect to the first, second, and third preferred embodiments. Diode Dl disconnects the hold-up capacitor C_n from the positive auxiliary terminal +V_aux when the switch Ql is in an OFF state by blocking conduction of the body diode of the switch Ql.

[0054] Alternatively, current limiting during discharging of the hold-up capacitor C_n can be provided by controlling the turn-on slew rate of the switch Q2. Thus, the current-limiting resistor Rl can be shorted or eliminated.

[0055] In accordance with the preferred embodiments of the present invention, the holdup capacitor C_n is connected to the positive auxiliary terminal +V_aux, and not the positive input terminal +V_in, during normal operation of the hold-up circuits 100, 200. Accordingly, the holdup capacitor C_n can be charged to a voltage that is greater than the input voltage V_in, and is preferably charged to the maximum operating input voltage V_max.

[0056] Furthermore, in accordance with the preferred embodiments of the present invention, when input power P_in is interrupted, the control circuits 102, 202 disable sending the under-voltage lockout signal UVLO to the power converters 101, 202 for a period of time T greater than or equal to the hold-up time T_n, disconnect the hold-up capacitor C_n from V_aux, and connect the hold-up capacitor C to inputs of the power converters 101, 202. [0057] Moreover, in accordance with the preferred embodiments of the present invention, the current-limiting resistor Rl, the diode Dl, the current-limiting resistor R2, and the switches Ql and Q2 can be modified, adjusted, or replaced with similar elements or circuitry that provides similar operation.

[0058] A hold-up circuit according to various preferred embodiments of the present invention can be used with a power converter that provides a regulated, a semi-regulated, a quasi-regulated, or a non-regulated output. A hold-up circuit according to various preferred embodiments of the present invention can be integrated into a power converter or can be made as a separate module.

[0059] The control circuit 102, 202 of the hold-up circuit 101, 201 can be a digital or analog integrated circuit that can be programmed to provide the various functions discussed above. For example, the control circuit 102, 202 could be a standard micro-controller, a digital controller, a discrete circuit with comparators and flip-flops, etc.

[0060] While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.

Claims

WHAT IS CLAIMED IS:

1. A hold-up circuit for providing power to a power converter during a power interruption, the hold-up circuit comprising:

a hold-up capacitor arranged to be connected to the power converter; and

a control circuit arranged and programmed to, after a beginning of a power

interruption, disable an under-voltage lockout function of the power converter.

2. A hold-up circuit of claim 1, wherein:

the hold-up capacitor is arranged to be connected to an input terminal of the power converter or to an auxiliary output terminal of the power converter; and

the control circuit is arranged and programmed to:

connect the hold-up capacitor to the auxiliary output terminal to charge the hold-up capacitor; and

after the beginning of the power interruption, connect the hold-up capacitor to the input terminal of the power converter while disabling the under-voltage lockout function of the power converter.

3. A hold-up circuit of claim 1, wherein, when the power interruption ends, the control circuit is arranged and programmed to enable the under-voltage lockout function of the power converter.

4. A hold-up circuit of claim 2, wherein, when the power interruption ends, the control circuit is arranged and programmed to enable the under-voltage lockout function of the power converter and to connect the hold-up capacitor to the auxiliary output terminal of the power converter.

5. A hold-up circuit of claim 1, wherein the control circuit is arranged and programmed to disable the under-voltage lockout function of the power converter at least until a voltage provided by the hold-up capacitor reaches an absolute minimum operating input voltage.

6. A hold-up circuit of claim 1, further comprising a first current-limiting resistor and a diode arranged in parallel.

7. A hold-up circuit of claim 6, further comprising a second current-limiting resistor in series with the diode.

8. A hold-up circuit of claim 7, wherein a resistance value of the second current-limiting resistor is less than a resistance value of the first current-limiting resistor.

9. A hold-up circuit of claim 1, further comprising two switches connected in series between an input terminal and an auxiliary terminal of the power converter.

10. A hold-up circuit of claim 9, further comprising a first current-limiting resistor and a diode arranged in parallel; wherein

a midpoint of the two switches is connected to the first current-limiting resistor and the diode.

11. A hold-up circuit of claim 9, further comprising a diode connected between one of the two switches and an auxiliary terminal of the power converter.

12. A hold-up circuit of claim 1, further comprising an input voltage slope detector arranged to detect a slope S = dV_in/dt of an input voltage; wherein

the control circuit is arranged and programmed to, if the slope is less than zero and if an absolute value of the slope | S | exceeds a predetermined slope threshold S_th, disable the under- voltage lockout function of the power converter.

13. A hold-up circuit of claim 12, wherein the control circuit is arranged and

programmed to disable the under-voltage lockout function of the power converter at least until a voltage provided by the hold-up capacitor reaches an absolute minimum operating input voltage.

14. A hold-up circuit of claim 2, further comprising an input voltage slope detector arranged to detect a slope S = dV_in/dt of an input voltage; wherein

15. A hold-up circuit of claim 14, wherein the control circuit is arranged and

16. A power converter system comprising:

a power converter; and

a hold-up circuit of claim 1 connected to the power converter.

17. A power converter system comprising:

a power converter including:

an input terminal; and

an auxiliary output terminal; and

a hold-up circuit of claim 2 connected to the power converter.

18. A power converter system of claim 17, further comprising:

an additional auxiliary output terminal; and

an auxiliary output capacitor connected between the auxiliary output terminal and the additional auxiliary output terminal.

19. A power converter system of claim 18, further comprising an additional input terminal; wherein

the input terminal and the auxiliary output terminal are positive terminals;

the additional input terminal and the additional auxiliary output terminal are negative terminals; and

the additional input terminal and the additional auxiliary output terminal are connected.

20. A power converter system of claim 18, further comprising an additional input terminal; wherein

the input terminal and the auxiliary output terminal are positive terminals;

the input terminal and the additional auxiliary output terminal are connected.