WO2014098566A1 - An ion sensitive field effect transistor - Google Patents

An ion sensitive field effect transistor Download PDF

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Publication number
WO2014098566A1
WO2014098566A1 PCT/MY2013/000269 MY2013000269W WO2014098566A1 WO 2014098566 A1 WO2014098566 A1 WO 2014098566A1 MY 2013000269 W MY2013000269 W MY 2013000269W WO 2014098566 A1 WO2014098566 A1 WO 2014098566A1
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Prior art keywords
effect transistor
multigate
region
ion sensitive
channel region
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Application number
PCT/MY2013/000269
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French (fr)
Inventor
Mat Hussin MOHD ROFEI
Bien Chia Sheng Daniel
Saidin NASIMAH
Wan Ismail WAN AZLI
Syono MOHD ISMAHADI
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Mimos Bhd
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Mimos Bhd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
    • G01N27/403—Cells and electrode assemblies
    • G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
    • G01N27/4148—Integrated circuits therefor, e.g. fabricated by CMOS processing

Definitions

  • the present invention relates to an ion sensitive field effect transistor (ISFET).
  • ISFET ion sensitive field effect transistor
  • Ion sensitive field effect transistor (ISFET) pH sensor is a silicon based device.
  • a conventional ISFET structure is similar to Metal- Oxide-Semiconductor Field Effect Transistor (MOSFET) but without gate electrode deposited on gate insulator exposing the insulator layer (sensing membrane) to an electrolyte solution.
  • MOSFET Metal- Oxide-Semiconductor Field Effect Transistor
  • the basic idea of an ISFET is to remove the metal plate of an MOSFET and expose the oxide insulator to an electrolyte.
  • This insulator will then interact with the solution and creates an electrolyte-insulator interfacial potential which is directly modulate the channel conductivity between the source and the drain terminal.
  • the amount of current flowing through the channel between the source and the drain is a measure of the amount of inversion charge in the channel which, by charge neutrality of the entire device, the inversion charge must be equal to the amount of charges on the upper side of the insulator layer. It can be seen as a charge sensor device.
  • SNR signal-to-noise ratio
  • the planar membrane has limited exposed area to the ions in the sample to be tested hence limiting the sensitivity and efficiency of the device.
  • Miniaturization of ISFET for integrated micro and nano-sensor system will further reduce the gate size and minimize the sensing area which will degrade the sensor signal.
  • transistor pH sensor is provided with an improved sensor gate configuration.
  • a tantalum oxide-sensing gate is disposed on top of an alumina layer.
  • the tantalum oxide-sensing gate provides advantageous sensitivity, while the alumina barrier layer increases sensor longevity in situations where the sensor is exposed to caustic cleaning processes such as Clean In Place processes.
  • the present invention provides an ion sensitive filed effect transistor comprising: a semiconductor substrate (101); a channel region (103) havingdoped polysilicon layer of at least 5el6 per cubic centimeter for conducting the current,formed over the semiconductor substrate (101); a drain region (105); a source region (107), wherein the source region (107) and the drain region (105) vertically connected to the channel region (103); a gate insulating layer (109); and a sensing membrane layer (111); characterized in that the gate insulating layer (109) and the sensing membrane layer (111) are formed along substantially all of the side walls of the channel region (103) to create a vertical multigate electrodes.
  • the above provision is advantageous as the polysilicon layer is used as an active region predetermined channel for a transistor to build vertical field effect transistor.
  • the present invention provides ISFET with multi-dimensional sensing membrane (111). It is an improvement of the current ISFET design which uses planar structure for the sensing membrane.
  • the built-up of the multi-gate vertical ISFET of the present invention increases the membrane's surface area thus improving the sensitivity of the device.
  • Figure 1 illustrates cross section view of the present invention.
  • Figure 2 illustrates flowchart of a method for producing the present invention.
  • Figure 3 illustrates procedural diagrams of the method for producing the present invention.
  • the present invention relates to field effect transistors particularly to vertical multi- gate ion sensitive field effect transistors and a method of producing them.
  • the present invention provides an ion sensitive filed effect transistor comprising: a semiconductor substrate (101); a channel region (103) having adoped polysilicon layer (104) of at least 5el6 per cubic centimeter for conducting the current,formed over the semiconductor substrate (101); a drain region (105); a source region (107), wherein the source region (107) and the drain region (105) vertically connected to the channel region (103); a gate insulating layer (109); and a sensing membrane layer (111); characterized in that the gate insulating layer (109) and the sensing membrane layer (111) are formed along substantially all of the side walls of the channel region (103) to create a vertical multigate electrodes.
  • the sensing membrane layer (111) further comprising silicon nitride and metal oxides in which the metal oxides further comprising Aluminium Oxide; Tantalum Pentoxide; and Haf
  • the present invention comprises of polysilicon layer (104) implanted with high
  • the transistor is designed in vertical order, which the drain region (105) is created by ion implantation in silicon substrate (101).
  • effect transistor comprising: providing semiconductor substrate (201); forming a drain region (203); forming a channel region (205); forming a source region (207); forming a gate insulating layer on the channel region (209); forming a sensing membrane layer on the gate insulating layer (211); and forming special contact holes to connect source and the channel region together (213).
  • the flowchart of the method is illustrated in Figure 2.
  • Step 1 is n-type ion implantation on silicon substrate (101) to create drain region (105).
  • the dopant ion used is arsenic or phosphorus.
  • Step 2 is polysilicon deposition.
  • Lightly doped p-type polysilicon layer (104) is used for channel region (103).
  • Step 3 is ion implantation on polysilicon surface for source region (107). The same dopant type and dose as drain region (105) is used.
  • Step 4 is polysilicon gate etch to define active or channel region (103) for the ISFET.
  • the channel region (103) can be fabricated by micro or nano-fabrication techniques, which can be by lithographic patterning, pattern transfer or by thin film deposition and etching methods.
  • Step 5 is gate oxidation/gate insulating layer (109) and sensing membrane layer (111) deposition on polysilicon (104) and sidewalk Both of these layers are performed consecutively with typically same dielectric thickness.
  • Membranes which are used as sensor elements themselves or as filters, are key component in many types of sensing devices. There are many types of sensing membrane for FET-based chemical sensor for wide range of sensing applications. The role of a chemical coating in a potentiometric sensor is to make the device selective and sensitive to analytes of interest. As for example in biosensor, enzymes and antibodies based membrane are often used to render a sensor biocompatible or as an inert matrix for active sensor components. But only the inorganic gate materials can be made easily, and the technology is compatible with standard IC technology. For gate oxidation, monocrystalline and poly crystalline silicon surface were oxidized at high temperature, dry process (thermal growing of Si02) to receive target thickness of Si02 layer.
  • a chemosensitive silicon nitride layer is deposited from two gaseous phases in Low Pressure Chemical Vapor Deposition (LPCVD) process.
  • the silicon nitride is formed in the pyrolytic reaction between dichlorosilane and ammonia at high temperature and typically low pressure.
  • Step 6 is when contact holes are created and followed by metallization steps. Special contact for source and polysilicon is created to short the source and channel substrate (PSUB) in single contact hole.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Electrochemistry (AREA)
  • Molecular Biology (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Analytical Chemistry (AREA)
  • Biochemistry (AREA)
  • General Health & Medical Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Immunology (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention relates toanion sensitive filed effect transistor comprising: a semiconductor substrate (101); a channel region (103) having adoped polysilicon layer (104) of at least 5e16 per cubic centimeter for conducting the current, formed over the semiconductor substrate (101); a drain region (105); a source region (107), wherein the source region (107) and the drain region (105) vertically connected to the channel region (103); a gate insulating layer (109); and a sensing membrane layer (111); characterized in that the gate insulating layer (109) and the sensing membrane layer (111) are formed along substantially all of the side walls of the channel region (103) to create a vertical multigate electrodes.

Description

Description
Title of Invention: AN ION SENSITIVE FIELD EFFECT
TRANSISTOR
[ 1 ] FIELD OF INVENTION
[2] The present invention relates to an ion sensitive field effect transistor (ISFET).
[3] BACKGROUND OF THE INVENTION
[4] Silicon-based chemical sensors are quite popular technology nowadays because of their advantages which are simplicity in function, fast response, small size, rigid design, and projected low cost. Additionally, the silicon technology is a good platform for system integration of chemical sensors because of the process compatibility with integrated circuit (IC) technology. Ion sensitive field effect transistor (ISFET) pH sensor is a silicon based device. A conventional ISFET structure is similar to Metal- Oxide-Semiconductor Field Effect Transistor (MOSFET) but without gate electrode deposited on gate insulator exposing the insulator layer (sensing membrane) to an electrolyte solution. The basic idea of an ISFET is to remove the metal plate of an MOSFET and expose the oxide insulator to an electrolyte. This insulator will then interact with the solution and creates an electrolyte-insulator interfacial potential which is directly modulate the channel conductivity between the source and the drain terminal. Basically the amount of current flowing through the channel between the source and the drain is a measure of the amount of inversion charge in the channel which, by charge neutrality of the entire device, the inversion charge must be equal to the amount of charges on the upper side of the insulator layer. It can be seen as a charge sensor device. To ensure high signal-to-noise ratio (SNR), sufficient sensing area must be exposed to the electrolyte. Currently the planar membrane has limited exposed area to the ions in the sample to be tested hence limiting the sensitivity and efficiency of the device. Miniaturization of ISFET for integrated micro and nano-sensor system will further reduce the gate size and minimize the sensing area which will degrade the sensor signal.
[5] One of the examples isEP 1706734which relates toanon sensitive field effect
transistor pH sensor is provided with an improved sensor gate configuration.
Specifically, a tantalum oxide-sensing gate is disposed on top of an alumina layer. The tantalum oxide-sensing gate provides advantageous sensitivity, while the alumina barrier layer increases sensor longevity in situations where the sensor is exposed to caustic cleaning processes such as Clean In Place processes.
[6] Miniaturization of ISFET for integrated micro and nano-sensor system would further reduce the gate size and minimize the sensing area which would also degrade the sensor signal.
[7] Therefore there is a need for an invention which provides solution to the problem.
[8] SUMMARY OF THE INVENTION
[9] According to an aspect of the present invention, the present invention provides an ion sensitive filed effect transistor comprising: a semiconductor substrate (101); a channel region (103) havingdoped polysilicon layer of at least 5el6 per cubic centimeter for conducting the current,formed over the semiconductor substrate (101); a drain region (105); a source region (107), wherein the source region (107) and the drain region (105) vertically connected to the channel region (103); a gate insulating layer (109); and a sensing membrane layer (111); characterized in that the gate insulating layer (109) and the sensing membrane layer (111) are formed along substantially all of the side walls of the channel region (103) to create a vertical multigate electrodes.
[10] The above provision is advantageous as the polysilicon layer is used as an active region predetermined channel for a transistor to build vertical field effect transistor. The present invention provides ISFET with multi-dimensional sensing membrane (111). It is an improvement of the current ISFET design which uses planar structure for the sensing membrane. The built-up of the multi-gate vertical ISFET of the present invention increases the membrane's surface area thus improving the sensitivity of the device.
[11] BRIEF DESCRIPTION OF THE DRAWINGS
[12] Figure 1 illustrates cross section view of the present invention.
[13] Figure 2 illustrates flowchart of a method for producing the present invention.
[14] Figure 3 illustrates procedural diagrams of the method for producing the present invention.
[15] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[16] The present invention relates to field effect transistors particularly to vertical multi- gate ion sensitive field effect transistors and a method of producing them. Referring to Figure 1, generally, the present invention provides an ion sensitive filed effect transistor comprising: a semiconductor substrate (101); a channel region (103) having adoped polysilicon layer (104) of at least 5el6 per cubic centimeter for conducting the current,formed over the semiconductor substrate (101); a drain region (105); a source region (107), wherein the source region (107) and the drain region (105) vertically connected to the channel region (103); a gate insulating layer (109); and a sensing membrane layer (111); characterized in that the gate insulating layer (109) and the sensing membrane layer (111) are formed along substantially all of the side walls of the channel region (103) to create a vertical multigate electrodes. The sensing membrane layer (111) further comprising silicon nitride and metal oxides in which the metal oxides further comprising Aluminium Oxide; Tantalum Pentoxide; and Hafnium Oxide, or the like.
[17] The present invention comprises of polysilicon layer (104) implanted with high
doping n-type or p-type layer on top for source region and light doping with opposite type dopant at the bottom. The transistor is designed in vertical order, which the drain region (105) is created by ion implantation in silicon substrate (101).
[18] Generally, the methodfor manufacturing a multigate electrode ion sensitive filed
effect transistor comprising: providing semiconductor substrate (201); forming a drain region (203); forming a channel region (205); forming a source region (207); forming a gate insulating layer on the channel region (209); forming a sensing membrane layer on the gate insulating layer (211); and forming special contact holes to connect source and the channel region together (213). The flowchart of the method is illustrated in Figure 2.
[19] Detailed explanations on the process flow with diagram is illustrated in Figure 3, in which the process is started with Step 1. Step 1 is n-type ion implantation on silicon substrate (101) to create drain region (105). The dopant ion used is arsenic or phosphorus. Step 2 is polysilicon deposition. Lightly doped p-type polysilicon layer (104) is used for channel region (103). Step 3 is ion implantation on polysilicon surface for source region (107). The same dopant type and dose as drain region (105) is used. Step 4 is polysilicon gate etch to define active or channel region (103) for the ISFET. The channel region (103) can be fabricated by micro or nano-fabrication techniques, which can be by lithographic patterning, pattern transfer or by thin film deposition and etching methods. Step 5 is gate oxidation/gate insulating layer (109) and sensing membrane layer (111) deposition on polysilicon (104) and sidewalk Both of these layers are performed consecutively with typically same dielectric thickness.
Membranes, which are used as sensor elements themselves or as filters, are key component in many types of sensing devices. There are many types of sensing membrane for FET-based chemical sensor for wide range of sensing applications. The role of a chemical coating in a potentiometric sensor is to make the device selective and sensitive to analytes of interest. As for example in biosensor, enzymes and antibodies based membrane are often used to render a sensor biocompatible or as an inert matrix for active sensor components. But only the inorganic gate materials can be made easily, and the technology is compatible with standard IC technology. For gate oxidation, monocrystalline and poly crystalline silicon surface were oxidized at high temperature, dry process (thermal growing of Si02) to receive target thickness of Si02 layer. Afterwards, for pH sensors a chemosensitive silicon nitride layer is deposited from two gaseous phases in Low Pressure Chemical Vapor Deposition (LPCVD) process. The silicon nitride is formed in the pyrolytic reaction between dichlorosilane and ammonia at high temperature and typically low pressure. Step 6 is when contact holes are created and followed by metallization steps. Special contact for source and polysilicon is created to short the source and channel substrate (PSUB) in single contact hole.
Although the invention has been described with reference to particular embodiment, it is to be understood that the embodiment is merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiment that other arrangements may be devised without departing from the scope of the present invention as defined by the appended claims.

Claims

Claims
A multigate electrode ion sensitive filed effect transistor comprising: asemiconductor substrate (101);
a channel region (103) havingdoped polysilicon layer (104) of at least 5e16 per cubic centimeter for conducting the current,formed over the semiconductor substrate (101);
adrain region (105);
asource region (107), wherein the source region (107) and the drain region (105) vertically connected to the channel region (103);
agate insulating layer (109); and
asensing membrane layer (111);
characterizedin that
thegate insulating layer (109) and the sensing membrane layer (111) are formed along substantially all of the side walls of the channel region (103) to create a vertical multigate electrodes.
An ion sensitive filed effect transistor as claimed in Claim 1, wherein the sensing membrane layer (111) further comprising silicon nitride and metal oxides.
An ion sensitive filed effect transistor as claimed in Claim 2, wherein the metal oxide further comprising: Aluminium Oxide; Tantalum Pentoxide; and Hafnium Oxide.
A method for manufacturing a multigate electrode ion sensitive filed effect transistor comprising:
providingsemiconductor substrate (201);
forminga drain region (203);
forminga channel region (205);
forminga source region (207);
forminga gate insulating layer on the channel region (209);
forminga sensing membrane layer on the gate insulating layer (211); and
formingspecial contact holes to connect source and the channel region together (213).
A method for manufacturing a multigate electrode ion sensitive filed effect transistor as claimed in Claim 4, wherein the step of forming a drain region (203) further comprising implanting ion into the semiconductor substrate.
A method for manufacturing a multigate electrode ion sensitive filed effect transistor as claimed in Claim 4, wherein the step of forming a channel region (207) further comprising forming a doped polysilicon electrode on the semiconductor substrate.
A method for manufacturing a multigate electrode ion sensitive filed effect transistor as claimed in Claim 4, wherein the step of forming a source region (207) further comprising implanting ion into the polysilicon electrode surface.
A method for manufacturing a multigate electrode ion sensitive filed effect transistor as claimed in Claim 4, wherein the special contact holes are formed on the polysilicon electrode.
A method for manufacturing a multigate electrode ion sensitive filed effect transistor as claimed in Claim 4 or Claim 6, wherein the channel region is formed by micro or nano-fabrication technique.
A method for manufacturing a multigate electrode ion sensitive filed effect transistor as claimed in Claim 9, wherein the micro or nano- fabrication technique can be of: lithographic patterning, or pattern transfer, or thin film deposition and etching methods.
PCT/MY2013/000269 2012-12-21 2013-12-20 An ion sensitive field effect transistor Ceased WO2014098566A1 (en)

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MYPI2012005558 2012-12-21
MYPI2012005558 2012-12-21

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108107078A (en) * 2017-11-09 2018-06-01 友达光电股份有限公司 Sensing device
CN114076789A (en) * 2021-11-17 2022-02-22 潍柴动力股份有限公司 Ion sensitive thin film transistor for detecting ion activity of object to be detected and detection method
CN114137377A (en) * 2021-10-09 2022-03-04 金波 Target molecule detection transistor sensor and preparation method thereof
CN115501920A (en) * 2022-09-16 2022-12-23 中国人民解放军陆军特色医学中心 Preparation method of nucleic acid amplification detection micro-fluidic chip with enhanced sensitivity of organic electrochemical transistor

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009045091A2 (en) * 2007-10-05 2009-04-09 Mimos Berhad A vertical thin polysilicon substrate isfet
US20100126885A1 (en) * 2008-11-21 2010-05-27 Hiroyuki Iechi Sensor device and method of measuring a solution
WO2012154027A1 (en) * 2011-05-12 2012-11-15 Mimos Bhd. An apparatus for sensor applications and method of manufacturing thereof

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* Cited by examiner, † Cited by third party
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WO2009045091A2 (en) * 2007-10-05 2009-04-09 Mimos Berhad A vertical thin polysilicon substrate isfet
US20100126885A1 (en) * 2008-11-21 2010-05-27 Hiroyuki Iechi Sensor device and method of measuring a solution
WO2012154027A1 (en) * 2011-05-12 2012-11-15 Mimos Bhd. An apparatus for sensor applications and method of manufacturing thereof

Non-Patent Citations (2)

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Title
CHENG-HSIN CHEN ET AL: "A novel vertical MOSFET with bMPI structure for 1T-DRAM application", NEXT-GENERATION ELECTRONICS (ISNE), 2010 INTERNATIONAL SYMPOSIUM ON, IEEE, PISCATAWAY, NJ, USA, 18 November 2010 (2010-11-18), pages 133 - 135, XP031836197, ISBN: 978-1-4244-6693-1 *
HONG-KUN LYU ET AL: "Formation of a Vertical MOSFET for Charge Sensing in a Si Micro-Fluidic Channel Chin-Sung Park and Geunbae Lim", JOURNAL OF THE KOREAN PHYSICAL SOCIETY, 31 January 2004 (2004-01-31), pages 162 - 166, XP055112661, Retrieved from the Internet <URL:http://www.kps.or.kr/home/kor/journal/library/downloadPdf.asp?articleuid=%7B09297AE9-AD67-4D9A-ADBC-907F49219536%7D.> [retrieved on 20140408] *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108107078A (en) * 2017-11-09 2018-06-01 友达光电股份有限公司 Sensing device
CN114137377A (en) * 2021-10-09 2022-03-04 金波 Target molecule detection transistor sensor and preparation method thereof
CN114076789A (en) * 2021-11-17 2022-02-22 潍柴动力股份有限公司 Ion sensitive thin film transistor for detecting ion activity of object to be detected and detection method
CN115501920A (en) * 2022-09-16 2022-12-23 中国人民解放军陆军特色医学中心 Preparation method of nucleic acid amplification detection micro-fluidic chip with enhanced sensitivity of organic electrochemical transistor
CN115501920B (en) * 2022-09-16 2024-04-05 中国人民解放军陆军特色医学中心 Preparation method of nucleic acid amplification detection micro-fluidic chip of organic electrochemical crystal Guan Zengmin

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